WO2015122139A1 - Differential amplifier - Google Patents

Differential amplifier Download PDF

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Publication number
WO2015122139A1
WO2015122139A1 PCT/JP2015/000397 JP2015000397W WO2015122139A1 WO 2015122139 A1 WO2015122139 A1 WO 2015122139A1 JP 2015000397 W JP2015000397 W JP 2015000397W WO 2015122139 A1 WO2015122139 A1 WO 2015122139A1
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Prior art keywords
terminal
input transistor
differential input
differential
energization
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PCT/JP2015/000397
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French (fr)
Japanese (ja)
Inventor
隼人 佐藤
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株式会社デンソー
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Publication of WO2015122139A1 publication Critical patent/WO2015122139A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45085—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45332—Indexing scheme relating to differential amplifiers the AAC comprising one or more capacitors as feedback circuit elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45374—Indexing scheme relating to differential amplifiers the AAC comprising one or more discrete resistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45458—Indexing scheme relating to differential amplifiers the CSC comprising one or more capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45476—Indexing scheme relating to differential amplifiers the CSC comprising a mirror circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45674—Indexing scheme relating to differential amplifiers the LC comprising one current mirror

Definitions

  • This disclosure relates to a differential amplifier.
  • the present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to provide a differential amplifier capable of suppressing generation of an offset voltage due to high frequency noise applied to an input terminal while suppressing an increase in circuit area. is there.
  • the differential amplifier includes a differential pair, a current generation circuit, a first compensation capacitor, and a second compensation capacitor.
  • the differential pair includes a first input terminal, a second input terminal, a first differential input transistor, and a second differential input transistor that form a pair.
  • Each of the first and second differential input transistors has a first energization terminal, a second energization terminal, and a control terminal.
  • the control terminal of the first differential input transistor is connected to the first input terminal, the control terminal of the second differential input transistor is connected to the second input terminal, and
  • the first energization terminal and the first energization terminal of the second differential input transistor are connected.
  • the current generation circuit is connected between the first energization terminal of the first differential input transistor and the first energization terminal of the second differential input transistor and a first power supply line, and is connected to the differential pair. Generate current to flow.
  • the first compensation capacitor is connected between the control terminal of the first differential input transistor and the first energization terminal.
  • the second compensation capacitor is AC-connected to the first energization terminal of the first differential input transistor and the first energization terminal of the second differential input transistor and to the first power supply line or the first power supply line. Are connected to a ground line having the same potential.
  • the above differential amplifier can suppress the generation of offset voltage due to high frequency noise. Further, for example, since it is not necessary to form an inductor, an increase in circuit area can be suppressed.
  • a differential amplifier includes a differential pair, a current generation circuit, and a compensation capacitor.
  • the differential pair includes a first input terminal, a second input terminal, a first differential input transistor, and a second differential input transistor that form a pair.
  • Each of the first and second differential input transistors has a first energization terminal, a second energization terminal, and a control terminal.
  • the control terminal of the first differential input transistor is connected to the first input terminal
  • the control terminal of the second differential input transistor is connected to the second input terminal
  • the first energization terminal and the first energization terminal of the second differential input transistor are connected.
  • the current generation circuit is connected between the first energization terminal of the first differential input transistor and the first energization terminal of the second differential input transistor and a first power supply line, and is connected to the differential pair. Generate current to flow.
  • the compensation capacitor is connected between the control terminal of the first differential input transistor and the first energization terminal.
  • a voltage including AC noise is applied to the first input terminal, the amplitude of AC noise propagating between the control terminal and the first energization terminal of the first differential input transistor, and the second
  • the capacitance value of the compensation capacitor is set so that the difference in amplitude of AC noise propagating between the control terminal and the first energization terminal of the differential input transistor is within a predetermined value.
  • the above differential amplifier can suppress the generation of offset voltage due to high frequency noise. Further, for example, since it is not necessary to form an inductor, an increase in circuit area can be suppressed.
  • FIG. 1 is a configuration diagram of a part of the differential amplifier according to the first embodiment.
  • FIG. 2 is an overall configuration diagram of the differential amplifier.
  • FIG. 3 is an AC equivalent circuit of the differential amplifier.
  • FIG. 4 is an overall configuration diagram of the differential amplifier according to the second embodiment.
  • FIG. 5 is an overall configuration diagram of a differential amplifier according to the third embodiment.
  • FIG. 6 is a configuration diagram of a part of the differential amplifier according to the fourth embodiment.
  • FIG. 7 is a configuration diagram of a source grounding circuit with a source resistor.
  • FIG. 8 is an overall configuration diagram of a differential amplifier according to the fifth embodiment.
  • FIG. 9 is an overall configuration diagram of a differential amplifier according to the sixth embodiment.
  • FIG. 10 is an overall configuration diagram of a differential amplifier according to the seventh embodiment.
  • FIG. 11 is an overall configuration diagram of a differential amplifier according to the eighth embodiment.
  • FIG. 12 is an overall configuration diagram of a differential amplifier according to the ninth embodiment.
  • FIG. 13 is an overall configuration diagram of a differential amplifier according to the tenth embodiment.
  • the differential amplifier 1 includes a differential pair 2, a constant current circuit 3, a first compensation capacitor Ca, a second compensation capacitor Cb, and an active load 4.
  • the differential pair 2 includes a pair of input terminals including a non-inverting input terminal 5 and an inverting input terminal 6, a first differential input transistor M1, and a second differential input transistor M2.
  • the non-inverting input terminal 5 corresponds to the first input terminal
  • the inverting input terminal 6 corresponds to the second input terminal.
  • the transistors M1 and M2 are N-channel MOS transistors, and their sources are connected to each other at a node N1.
  • the gates of the transistors M1 and M2 are connected to the input terminals 5 and 6, respectively. Parasitic capacitances Cgs1 and Cgs2 exist between the gates and sources of the transistors M1 and M2, respectively.
  • the gates, sources, and drains of the transistors M1 and M2 correspond to a control terminal, a first energization terminal, and a second energization terminal, respectively.
  • the constant current circuit 3 is connected between the node N1 and the first power supply line 7 (ground line), and is a current generation circuit that supplies a constant current to the differential pair 2.
  • the constant current circuit 3 has a configuration of a current mirror circuit composed of N-channel type MOS transistors M3 and M4. When a constant current Iref flows into the transistor M4 from a constant current circuit (not shown), the same current Iref also flows through the transistor M3 connected between the node N1 and the first power supply line 7.
  • a parasitic capacitance Ct3 between the drain and source of the transistor M3 is an output parasitic capacitance between both terminals of the constant current circuit 3.
  • the first compensation capacitor Ca is connected between the gate and source of the transistor M1 connected to the non-inverting input terminal 5 to which high frequency noise is applied.
  • the second compensation capacitor Cb is connected between the node N1 and the first power supply line 7.
  • the active load 4 includes P-channel MOS transistors M5 and M6 connected between the second power supply line 8 and the drains of the transistors M1 and M2. The gates of the transistors M5 and M6 and the drain of the transistor M5 are connected to each other.
  • the differentially amplified voltage Vout is output from the output terminal 9 connected to the drains of the transistors M2 and M6.
  • the voltage Vin ⁇ b> 1 is input to the non-inverting input terminal 5, and the voltage Vin ⁇ b> 2 is input to the inverting input terminal 6.
  • the voltage Vin1 is a voltage in which an AC component vrf, which is a high-frequency noise component, is superimposed on a DC component Vdc, which is an input signal.
  • the voltage Vin2 is a constant voltage Vref. That is, high frequency noise is applied to the input terminal 5 on the side to which the first compensation capacitor Ca is connected.
  • the unit capacitance of the gate oxide film of the MOS transistor is defined as Cox
  • the average electron mobility of the channel is defined as ⁇
  • the channel width is defined as W
  • the channel length is defined as L
  • the threshold voltage is defined as Vt.
  • equation (2) is obtained by integrating equation (1).
  • the second term of the equation (2) is a DC offset current due to a high frequency noise component.
  • Equation (3) when the AC component vgs is a sine wave noise having an amplitude Vm, the AC component vgs can be expressed as shown in Equation (3), and further, Equation (4) is established. As a result, the second term of equation (2) is equal to equation (5).
  • FIG. 3 is an AC equivalent circuit from the non-inverting input terminal 5 to the first power supply line 7 for obtaining AC components vgs1, vgs2 of the gate-source voltages of the transistors M1, M2.
  • the AC component vrf exists between the non-inverting input terminal 5 and the first power supply line 7, and the inverting input terminal 6 is grounded to the first power supply line 7.
  • the AC components vgs1 and vgs2 of the gate-source voltages of the transistors M1 and M2 are expressed by Equations (7) and (8), respectively.
  • the equations (7) and (8) can be approximated as equations (9) and (10), respectively.
  • This approximation is more accurate as the compensation capacitors Ca and Cb have larger capacitances than the parasitic capacitances Cgs1, Cgs2, and Ct3.
  • the compensation capacitors Ca and Cb are several pF
  • the parasitic capacitances Cgs1, Cgs2, and Ct3 are several tens of fF.
  • the amplitudes of the high frequency noises propagated between the gates and sources of the transistors M1 and M2 are equal.
  • the magnitudes of the DC offset currents flowing through the transistors M1 and M2 become equal, the DC offset currents cancel each other, and no drain current imbalance occurs.
  • the non-inverting input terminal 5 since the compensation capacitors Ca and Cb having the same capacitance values and the capacitance values larger than the parasitic capacitances Cgs1, Cgs2, and Ct3 are provided, the non-inverting input terminal 5 has high frequency noise. Even if is added, generation of an offset voltage at the output terminal 9 can be suppressed. That is, an effect of increasing noise tolerance can be obtained.
  • the first and second compensation capacitors Ca and Cb need only have capacitance values larger than the parasitic capacitances Cgs1, Cgs2, and Ct3, and can be realized with a relatively small area. An increase in area can be suppressed.
  • the differential amplifier 1 is suitable for an integrated circuit that amplifies a sensor signal.
  • the present embodiment has a voltage follower configuration in which the output terminal 9 of the differential amplifier 1 described above is connected to the inverting input terminal 6 and the output voltage Vout is fed back.
  • the voltage Vin1 input from the non-inverting input terminal 5 is multiplied by 1 and output from the output terminal 9.
  • the output voltage Vout As described in the first embodiment, even when high frequency noise is superimposed on the input voltage Vin1, no offset voltage due to high frequency noise is generated in the output voltage Vout.
  • the differential amplifier 11 does not include the second compensation capacitor Cb of the differential amplifier 1 shown in FIG. 1, but includes a compensation capacitor Cd instead of the first compensation capacitor Ca between the gate and source of the transistor M1. It is different in point.
  • the compensation capacitor Cd also has the same amplitude of noise propagated between the gate and source of the transistors M1 and M2 when high frequency noise is applied to the non-inverting input terminal 5.
  • a capacity value is set. The conditions are as shown in the equation (14).
  • the magnitude of the DC offset current flowing through the transistors M1 and M2 is equalized when high frequency noise is applied to the non-inverting input terminal 5, and the generation of offset voltage can be suppressed by canceling each other. That is, an effect of increasing noise tolerance can be obtained.
  • the parasitic capacitances Cgs1 and Cgs2 are very close values, and the parasitic capacitance is an extremely small value of about several tens of fF. Therefore, the capacitance value of the compensation capacitor Cd is also about several tens of fF. Value. Therefore, the compensation capacitor Cd can be realized with a very small area, and an increase in circuit area can be suppressed as compared with the conventional configuration using an element such as an inductor.
  • the differential amplifier 11 of this embodiment is also suitable for an integrated circuit that amplifies a sensor signal.
  • the differential amplifier 21 shown in FIG. 6 includes source resistors R1 and R2 between the sources of the transistors M1 and M2 and the node N1 with respect to the differential amplifier 1 shown in FIG.
  • the transconductance gm of the transistors M1 and M2 of the common source circuit depends on the input voltage, the relationship between the input and the output is nonlinear.
  • the source resistors R1 and R2 are inserted, the dependence on the transconductance gm is reduced by negative feedback, and the linearity of the input / output characteristics is improved.
  • the gain is lower than that of the differential amplifier 1 without the source resistors R1 and R2.
  • the transconductance Gm is given by equation (17), and the small signal voltage gain Av is given by equation (18).
  • gm is the transconductance of the transistor M1.
  • the differential amplifier 21 of the present embodiment provided with the source resistors R1 and R2 also has the effect of increasing the noise immunity as in the first embodiment.
  • the compensation capacitors Ca and Cb have the same capacitance value and larger than the parasitic capacitances Cgs1, Cgs2, and Ct3.
  • the capacitance values of the first and second compensation capacitors Ca and Cb may be changed as appropriate.
  • the first and second compensation capacitors Ca and Cb may have different capacitance values.
  • the AC components vgs1 and vgs2 of the gate-source voltages of the transistors M1 and M2 can be expressed as shown in the equations (7) and (8), respectively.
  • the difference in the amplitude of the high frequency noise propagated between the gate and source of these transistors M1 and M2 is as shown in the following equation (19).
  • the capacitance values of the first and second compensation capacitors Ca and Cb are preferably set as appropriate so that the ⁇ vgs can be suppressed to a predetermined value or less.
  • the capacitance value of the compensation capacitor Cd may be appropriately changed as long as the offset voltage due to high frequency noise can be suppressed.
  • the AC components vgs1 and vgs2 of the gate-source voltages of the transistors M1 and M2 can be expressed as shown in equations (15) and (16), respectively.
  • the difference in amplitude of the high frequency noise propagated between the gate and source of these transistors M1 and M2 is as shown in the following equation (20).
  • the capacitance value of the compensation capacitor Cd is preferably set as appropriate so that the ⁇ vgs can be suppressed to a predetermined value or less.
  • FIG. 8 shows an explanatory diagram of the fifth embodiment, corresponding to FIG. 2 of the first embodiment.
  • the transistors M1b to M6b of FIG. 8 having the same functions as those of the transistors M1 to M6 of FIG. 2 are indicated by adding the subscript “b” to the corresponding transistors M1 to M6 of FIG.
  • the active load 4 as a load circuit is configured on the first power supply line 7 (ground) side, and the constant current circuit 3 is configured on the second power supply line 8 side. Yes. In the present embodiment, there are almost the same effects as the first embodiment.
  • the form of the voltage follower shown in the second embodiment can also be used.
  • the output terminal 9 of the differential amplifier 101 can be connected to the inverting input terminal 6 and the capacitor CL can be connected instead of the voltage Vref to feed back the output voltage Vout.
  • the form of the common source circuit with the source resistance shown in the fourth embodiment can also be used.
  • FIG. 9 shows an explanatory diagram of the sixth embodiment, corresponding to FIG. 5 of the third embodiment.
  • the transistors M1b to M6b in FIG. 9 having the same functions as the transistors M1 to M6 in FIG. 5 are indicated by adding the subscript “b” to the corresponding transistors M1 to M6 in FIG.
  • the differential amplifier 201 in FIG. 9 uses P-channel MOS transistors M1b and M2b as differential input transistors. Although a detailed description of the circuit configuration of FIG. 9 is omitted, the active load 4 as a load circuit is configured on the first power supply line 7 (ground) side, and the constant current circuit 3 is configured on the second power supply line 8 side. . Also in this embodiment, there exists an effect substantially the same as 3rd Embodiment.
  • the form of the voltage follower shown in the second embodiment can also be used. That is, the output terminal 9 of the differential amplifier 201 can be connected to the inverting input terminal 6 and the capacitor CL can be connected instead of the voltage Vref to feed back the output voltage Vout.
  • the form of the common source circuit with the source resistance shown in the fourth embodiment can also be used.
  • FIG. 10 shows an explanatory diagram of the seventh embodiment, corresponding to FIG. 2 of the first embodiment.
  • Transistors having the same functions as those of the transistors M1 to M6 in FIG. 2 are denoted by reference numerals in FIG. 10 as transistors T1 to T6.
  • a bipolar junction transistor T1 to T6 having a base (control terminal), a collector (second energization terminal), and an emitter (first energization terminal) is used. You may do it.
  • the form of the voltage follower shown in the second embodiment can also be used. That is, the output terminal 9 of the differential amplifier 301 can be connected to the inverting input terminal 6, and the capacitor CL can be connected instead of the voltage Vref to feed back the output voltage Vout. Further, although not shown, a form of a grounded emitter circuit with an emitter resistor can be used so as to show a similar configuration (grounded source circuit) as in the fourth embodiment.
  • FIG. 11 shows an explanatory diagram of the eighth embodiment, corresponding to FIG. 5 of the third embodiment.
  • Transistors having the same functions as those of the transistors M1 to M6 in FIG. 5 are denoted by reference numerals in FIG. 11 as transistors T1 to T6.
  • the configuration of the third embodiment may also be configured using bipolar junction transistors T1 to T6.
  • the form of the voltage follower shown in the second embodiment can also be used.
  • the output terminal 9 of the differential amplifier 401 can be connected to the inverting input terminal 6 and the capacitor CL can be connected instead of the voltage Vref to feed back the output voltage Vout.
  • a configuration of a grounded emitter circuit with an emitter resistor can be used as shown in a similar configuration (grounded source circuit) to the fourth embodiment.
  • FIG. 12 shows an explanatory diagram of the ninth embodiment, corresponding to FIG. 2 of the first embodiment.
  • the transistors M1c to M6c of FIG. 12 having the same functions as those of the transistors M1 to M6 of FIG. 2 are indicated by adding the suffix “c” to the corresponding transistors M1 to M6 of FIG.
  • the load circuit 4c includes, for example, a circuit in which the drains of the differential pair 2 by transistors M1c and M2c are folded (for example, a folded cascode circuit M5c to M5c to which a constant bias b1 is applied). M8c) may be used.
  • active loads M9c to M12c to which constant biases b2 to b3 are applied may be connected in series to the folded cascode circuits M5c to M8c, or resistors may be connected instead of the active loads M9c to M12c. May be.
  • FIG. 13 shows an explanatory diagram of the tenth embodiment, corresponding to FIG. 5 of the third embodiment.
  • the transistors M1c to M6c of FIG. 13 having the same functions as those of the transistors M1 to M6 of FIG. 5 are indicated by adding the subscript “c” to the corresponding transistors M1 to M6 of FIG.
  • the load circuit 4c may use, for example, a circuit (for example, folded cascode circuits M5c to M8c) in which the drains of the differential pair 2 by the transistors M1c and M2c are folded.
  • active loads M9c to M12c to which constant biases b2 to b3 are applied may be connected in series to the folded cascode circuits M5c to M8c, or a resistor is connected instead of the active loads M9c to M12c. May be.
  • the first compensation capacitor Ca and the compensation capacitor Cd may be connected between the gate and source of the transistor M2 connected to the inverting input terminal 6.
  • the differential amplifiers 1 and 11 shown in the first and third embodiments may be configured to feed back the signal output from the differential pair 2 to the input terminal. it can.
  • the second compensation capacitor Cb is provided between the node N1 and the first power supply line 7.
  • the second compensation capacitor Cb is provided between the node N1 and the ground line (a ground line having the same potential as the first power supply line 7). May be.
  • a configuration in which a resistor is provided instead of the constant current circuit 3 and the common sources of the transistors M1 and M2 of the differential pair 2 are connected to the resistor may be employed.
  • a typical circuit configuration according to the present application is illustrated, but the configuration or technical idea of each embodiment can be applied in appropriate combination.
  • a general circuit configuration can be applied in combination, and is not limited to the circuit topology described in the above embodiment.

Abstract

Provided is a differential amplifier wherein: a first compensation capacitor (Ca) is connected between the control terminal of a first differential input transistor (M1, M1b, M1c, T1) and a first current-carrying terminal thereof; and a second compensation capacitor (Cb) is connected between each of the first current-carrying terminal of the first differential input transistor and a first current-carrying terminal of a second differential input transistor (M2, M2b, M2c, T2) and either a first power supply line (7) or a ground line that is at the same AC potential as the first power supply line. The capacitances of the first and second compensation capacitors have been set such that the difference in amplitude between AC noises propagating between the control terminals and first current-carrying terminals of the first and second differential input transistors is within a predetermined value range.

Description

差動増幅器Differential amplifier 関連出願の相互参照Cross-reference of related applications
　本開示は、２０１４年２月１２日に出願された日本出願番号２０１４－２４２９６号および２０１４年１０月１４日出願された日本出願番号２０１４－２０９８８４号に基づくもので、ここにその記載内容を援用する。 This disclosure is based on Japanese Application No. 2014-24296 filed on February 12, 2014 and Japanese Application No. 2014-209984 filed on October 14, 2014, the contents of which are incorporated herein by reference. To do.
　本開示は、差動増幅器に関する。 This disclosure relates to a differential amplifier.
　差動増幅器の入力端子に高周波ノイズが印加されると、入力端子から差動入力トランジスタの寄生容量（ゲート・ソース間容量）および定電流回路を通してグランドにノイズが伝播する。このとき差動対を構成する２つの差動入力トランジスタの電流バランスが崩れ、出力電圧にオフセット電圧が発生する虞がある。 When high-frequency noise is applied to the input terminal of the differential amplifier, noise propagates from the input terminal to the ground through the parasitic capacitance (gate-source capacitance) of the differential input transistor and the constant current circuit. At this time, the current balance between the two differential input transistors constituting the differential pair may be lost, and an offset voltage may be generated in the output voltage.
　この技術的課題に対しては、差動増幅器の入力端子に高周波ノイズを除去するフィルタ回路を設ける構成が考えられる。しかし、フィルタ回路を設けると回路規模が大きくなる。他の構成として、特許文献１に記載されているように、差動入力トランジスタと定電流回路との間に高周波ノイズに対し高インピーダンスとなる素子（例えばインダクタ）を接続し、高周波ノイズがグランドに流れることを防ぐことでオフセット電圧を抑制するものもある。しかし、高周波ノイズに対し高インピーダンスとなる素子（インダクタ）を回路上で形成するには大きな回路面積を必要とする。 For this technical problem, a configuration in which a filter circuit for removing high frequency noise is provided at the input terminal of the differential amplifier is conceivable. However, the provision of a filter circuit increases the circuit scale. As another configuration, as described in Patent Document 1, an element (for example, an inductor) having high impedance against high frequency noise is connected between the differential input transistor and the constant current circuit, and the high frequency noise is connected to the ground. Some of them suppress the offset voltage by preventing the flow. However, a large circuit area is required to form an element (inductor) having high impedance against high-frequency noise on the circuit.
特開平９－２６０９７３号公報Japanese Patent Laid-Open No. 9-260973
　本開示は上記事情に鑑みてなされたもので、その目的は、回路面積の増大を抑えつつ、入力端子に加わる高周波ノイズに起因するオフセット電圧の発生を抑制可能な差動増幅器を提供することにある。 The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to provide a differential amplifier capable of suppressing generation of an offset voltage due to high frequency noise applied to an input terminal while suppressing an increase in circuit area. is there.
　本開示の一態様に係る差動増幅器は、差動対と、電流生成回路と、第１補償コンデンサと、第２補償コンデンサとを備える。前記差動対は、対をなす第１入力端子、第２入力端子と、第１差動入力トランジスタと、第２差動入力トランジスタとを備える。前記第１、第２差動入力トランジスタの各々は、第１通電端子、第２通電端子、および制御端子を有する。前記第１差動入力トランジスタの前記制御端子は前記第１入力端子に接続され、前記第２差動入力トランジスタの前記制御端子は前記第２入力端子に接続され、前記第１差動入力トランジスタの前記第１通電端子と前記第２差動入力トランジスタの前記第１通電端子とが接続される。前記電流生成回路は、前記第１差動入力トランジスタの前記第１通電端子および前記第２差動入力トランジスタの前記第１通電端子と第１電源線との間に接続され、前記差動対に流す電流を生成する。 The differential amplifier according to an aspect of the present disclosure includes a differential pair, a current generation circuit, a first compensation capacitor, and a second compensation capacitor. The differential pair includes a first input terminal, a second input terminal, a first differential input transistor, and a second differential input transistor that form a pair. Each of the first and second differential input transistors has a first energization terminal, a second energization terminal, and a control terminal. The control terminal of the first differential input transistor is connected to the first input terminal, the control terminal of the second differential input transistor is connected to the second input terminal, and The first energization terminal and the first energization terminal of the second differential input transistor are connected. The current generation circuit is connected between the first energization terminal of the first differential input transistor and the first energization terminal of the second differential input transistor and a first power supply line, and is connected to the differential pair. Generate current to flow.
　前記第１補償コンデンサは、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間に接続される。前記第２補償コンデンサは、前記第１差動入力トランジスタの前記第１通電端子および前記第２差動入力トランジスタの前記第１通電端子と、前記第１電源線または前記第１電源線と交流的に同電位となる接地線との間に接続される。前記第１入力端子に交流ノイズを含む電圧が印加された際に、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する交流ノイズの振幅と、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する交流ノイズの振幅の差が所定値以内となるように、前記第１補償コンデンサの容量値および、前記第２補償コンデンサの容量値が設定されている。 The first compensation capacitor is connected between the control terminal of the first differential input transistor and the first energization terminal. The second compensation capacitor is AC-connected to the first energization terminal of the first differential input transistor and the first energization terminal of the second differential input transistor and to the first power supply line or the first power supply line. Are connected to a ground line having the same potential. When a voltage including AC noise is applied to the first input terminal, the amplitude of AC noise propagating between the control terminal and the first energization terminal of the first differential input transistor, and the second The capacitance value of the first compensation capacitor and the second compensation capacitor so that the difference in amplitude of AC noise propagating between the control terminal and the first energization terminal of the differential input transistor is within a predetermined value. The capacity value is set.
　上記差動増幅器は、高周波ノイズに起因するオフセット電圧の発生を抑制できる。また、例えばインダクタを形成する必要がなくなるため、回路面積の増大を抑制できる。 The above differential amplifier can suppress the generation of offset voltage due to high frequency noise. Further, for example, since it is not necessary to form an inductor, an increase in circuit area can be suppressed.
　本開示の別の態様に係る差動増幅器は、差動対と、電流生成回路と、補償コンデンサとを備える。前記差動対は、対をなす第１入力端子、第２入力端子と、第１差動入力トランジスタと、第２差動入力トランジスタとを備える。前記第１、第２差動入力トランジスタの各々は、第１通電端子、第２通電端子、および制御端子を有する。前記第１差動入力トランジスタの前記制御端子は前記第１入力端子に接続され、前記第２差動入力トランジスタの前記制御端子は前記第２入力端子に接続され、前記第１差動入力トランジスタの前記第１通電端子と前記第２差動入力トランジスタの前記第１通電端子とが接続される。前記電流生成回路は、前記第１差動入力トランジスタの前記第１通電端子および前記第２差動入力トランジスタの前記第１通電端子と第１電源線との間に接続され、前記差動対に流す電流を生成する。 A differential amplifier according to another aspect of the present disclosure includes a differential pair, a current generation circuit, and a compensation capacitor. The differential pair includes a first input terminal, a second input terminal, a first differential input transistor, and a second differential input transistor that form a pair. Each of the first and second differential input transistors has a first energization terminal, a second energization terminal, and a control terminal. The control terminal of the first differential input transistor is connected to the first input terminal, the control terminal of the second differential input transistor is connected to the second input terminal, and The first energization terminal and the first energization terminal of the second differential input transistor are connected. The current generation circuit is connected between the first energization terminal of the first differential input transistor and the first energization terminal of the second differential input transistor and a first power supply line, and is connected to the differential pair. Generate current to flow.
　前記補償コンデンサは、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間に接続される。前記第１入力端子に交流ノイズを含む電圧が印加された際に、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する交流ノイズの振幅と、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する交流ノイズの振幅の差が所定値以内となるように、前記補償コンデンサの容量値が設定されている。 The compensation capacitor is connected between the control terminal of the first differential input transistor and the first energization terminal. When a voltage including AC noise is applied to the first input terminal, the amplitude of AC noise propagating between the control terminal and the first energization terminal of the first differential input transistor, and the second The capacitance value of the compensation capacitor is set so that the difference in amplitude of AC noise propagating between the control terminal and the first energization terminal of the differential input transistor is within a predetermined value.
　上記差動増幅器は、高周波ノイズに起因するオフセット電圧の発生を抑制できる。また、例えばインダクタを形成する必要がなくなるため、回路面積の増大を抑制できる。 The above differential amplifier can suppress the generation of offset voltage due to high frequency noise. Further, for example, since it is not necessary to form an inductor, an increase in circuit area can be suppressed.
　本開示における上記あるいは他の目的、構成、利点は、下記の図面を参照しながら、以下の詳細説明から、より明白となる。図面において、
図１は、第１実施形態に係る差動増幅器の一部の構成図である。 図２は、差動増幅器の全体構成図である。 図３は、差動増幅器の交流等価回路である。 図４は、第２実施形態に係る差動増幅器の全体構成図である。 図５は、第３実施形態に係る差動増幅器の全体構成図である。 図６は、第４実施形態に係る差動増幅器の一部の構成図である。 図７は、ソース抵抗付きのソース接地回路の構成図である。 図８は、第５実施形態に係る差動増幅器の全体構成図である。 図９は、第６実施形態に係る差動増幅器の全体構成図である。 図１０は、第７実施形態に係る差動増幅器の全体構成図である。 図１１は、第８実施形態に係る差動増幅器の全体構成図である。 図１２は、第９実施形態に係る差動増幅器の全体構成図である。 図１３は、第１０実施形態に係る差動増幅器の全体構成図である。 The above and other objects, configurations, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the following drawings. In the drawing
FIG. 1 is a configuration diagram of a part of the differential amplifier according to the first embodiment. FIG. 2 is an overall configuration diagram of the differential amplifier. FIG. 3 is an AC equivalent circuit of the differential amplifier. FIG. 4 is an overall configuration diagram of the differential amplifier according to the second embodiment. FIG. 5 is an overall configuration diagram of a differential amplifier according to the third embodiment. FIG. 6 is a configuration diagram of a part of the differential amplifier according to the fourth embodiment. FIG. 7 is a configuration diagram of a source grounding circuit with a source resistor. FIG. 8 is an overall configuration diagram of a differential amplifier according to the fifth embodiment. FIG. 9 is an overall configuration diagram of a differential amplifier according to the sixth embodiment. FIG. 10 is an overall configuration diagram of a differential amplifier according to the seventh embodiment. FIG. 11 is an overall configuration diagram of a differential amplifier according to the eighth embodiment. FIG. 12 is an overall configuration diagram of a differential amplifier according to the ninth embodiment. FIG. 13 is an overall configuration diagram of a differential amplifier according to the tenth embodiment.
　以下、差動増幅器の幾つかの実施形態について図面を参照しながら説明する。各実施形態において実質的に同一又は類似部分には同一又は類似符号を付して必要に応じて説明を省略する。 Hereinafter, some embodiments of the differential amplifier will be described with reference to the drawings. In each embodiment, substantially the same or similar parts are denoted by the same or similar reference numerals, and description thereof will be omitted as necessary.
　（第１実施形態）
　第１実施形態について図１から図３を参照しながら説明する。差動増幅器１は、図１および図２に示すように差動対２、定電流回路３、第１補償コンデンサＣａ、第２補償コンデンサＣｂおよび能動負荷４を備えている。 (First embodiment)
A first embodiment will be described with reference to FIGS. 1 to 3. As shown in FIGS. 1 and 2, the differential amplifier 1 includes a differential pair 2, a constant current circuit 3, a first compensation capacitor Ca, a second compensation capacitor Cb, and an active load 4.
　差動対２は、非反転入力端子５と反転入力端子６とからなる一対の入力端子、第１差動入力トランジスタＭ１および第２差動入力トランジスタＭ２から構成されている。本実施形態において、非反転入力端子５が第１入力端子に相当し、反転入力端子６が第２入力端子に相当する。トランジスタＭ１、Ｍ２はＮチャネル型のＭＯＳトランジスタであって、ソース同士がノードＮ１で接続されている。トランジスタＭ１、Ｍ２のゲートは、それぞれ入力端子５、６に接続されている。トランジスタＭ１、Ｍ２のゲート・ソース間には、それぞれ寄生容量Ｃgs1、Ｃgs2が存在する。トランジスタＭ１、Ｍ２のゲート、ソース、ドレインは、それぞれ制御端子、第１通電端子、第２通電端子に相当する。 The differential pair 2 includes a pair of input terminals including a non-inverting input terminal 5 and an inverting input terminal 6, a first differential input transistor M1, and a second differential input transistor M2. In the present embodiment, the non-inverting input terminal 5 corresponds to the first input terminal, and the inverting input terminal 6 corresponds to the second input terminal. The transistors M1 and M2 are N-channel MOS transistors, and their sources are connected to each other at a node N1. The gates of the transistors M1 and M2 are connected to the input terminals 5 and 6, respectively. Parasitic capacitances Cgs1 and Cgs2 exist between the gates and sources of the transistors M1 and M2, respectively. The gates, sources, and drains of the transistors M1 and M2 correspond to a control terminal, a first energization terminal, and a second energization terminal, respectively.
　定電流回路３は、ノードＮ１と第１電源線７（グランド線）との間に接続されており、差動対２に定電流を流す電流生成回路である。この定電流回路３は、Ｎチャネル型のＭＯＳトランジスタＭ３、Ｍ４からなるカレントミラー回路の構成を備えている。図示しない定電流回路からトランジスタＭ４に定電流Ｉrefが流れ込むことにより、ノードＮ１と第１電源線７との間に接続されたトランジスタＭ３にも同じ電流Ｉrefが流れる。トランジスタＭ３のドレイン・ソース間の寄生容量Ｃt3は、定電流回路３の両端子間の出力寄生容量となる。 The constant current circuit 3 is connected between the node N1 and the first power supply line 7 (ground line), and is a current generation circuit that supplies a constant current to the differential pair 2. The constant current circuit 3 has a configuration of a current mirror circuit composed of N-channel type MOS transistors M3 and M4. When a constant current Iref flows into the transistor M4 from a constant current circuit (not shown), the same current Iref also flows through the transistor M3 connected between the node N1 and the first power supply line 7. A parasitic capacitance Ct3 between the drain and source of the transistor M3 is an output parasitic capacitance between both terminals of the constant current circuit 3.
　第１補償コンデンサＣａは、高周波ノイズが加わる非反転入力端子５に接続されたトランジスタＭ１のゲート・ソース間に接続されている。第２補償コンデンサＣｂは、ノードＮ１と第１電源線７との間に接続されている。能動負荷４は、第２電源線８とトランジスタＭ１、Ｍ２のドレインとの間に接続されたＰチャネル型のＭＯＳトランジスタＭ５、Ｍ６から構成されている。トランジスタＭ５、Ｍ６の各ゲートとトランジスタＭ５のドレインは互いに接続されている。差動増幅された電圧Ｖoutは、トランジスタＭ２、Ｍ６のドレインに接続された出力端子９から出力される。 The first compensation capacitor Ca is connected between the gate and source of the transistor M1 connected to the non-inverting input terminal 5 to which high frequency noise is applied. The second compensation capacitor Cb is connected between the node N1 and the first power supply line 7. The active load 4 includes P-channel MOS transistors M5 and M6 connected between the second power supply line 8 and the drains of the transistors M1 and M2. The gates of the transistors M5 and M6 and the drain of the transistor M5 are connected to each other. The differentially amplified voltage Vout is output from the output terminal 9 connected to the drains of the transistors M2 and M6.
　次に、本実施形態の作用について図３も参照しながら説明する。図２に示すように、非反転入力端子５に電圧Ｖin1が入力されており、反転入力端子６に電圧Ｖin2が入力されている。電圧Ｖin1は、入力信号である直流成分Ｖdcに高周波ノイズ成分である交流成分ｖrfが重畳した電圧である。電圧Ｖin2は一定の電圧Ｖrefである。すなわち、第１補償コンデンサＣａが接続されている側の入力端子５に高周波ノイズが加わる。 Next, the operation of this embodiment will be described with reference to FIG. As shown in FIG. 2, the voltage Vin <b> 1 is input to the non-inverting input terminal 5, and the voltage Vin <b> 2 is input to the inverting input terminal 6. The voltage Vin1 is a voltage in which an AC component vrf, which is a high-frequency noise component, is superimposed on a DC component Vdc, which is an input signal. The voltage Vin2 is a constant voltage Vref. That is, high frequency noise is applied to the input terminal 5 on the side to which the first compensation capacitor Ca is connected.
　はじめにオフセット電圧が生じる理由について説明する。ＭＯＳトランジスタのゲート酸化膜の単位容量をＣox、チャネルの平均電子移動度をμ、チャネル幅をＷ、チャネル長をＬ、しきい値電圧をＶｔと定義する。ゲート・ソース間電圧の直流成分をＶGS、交流成分（高周波ノイズ成分、交流ノイズ相当）をｖgsとすると、ＭＯＳトランジスタのドレイン電流Ｉｄは（１）式のように表せる。 First, the reason why offset voltage is generated will be explained. The unit capacitance of the gate oxide film of the MOS transistor is defined as Cox, the average electron mobility of the channel is defined as μ, the channel width is defined as W, the channel length is defined as L, and the threshold voltage is defined as Vt. When the direct current component of the gate-source voltage is VGS and the alternating current component (corresponding to a high frequency noise component, alternating current noise) is vgs, the drain current Id of the MOS transistor can be expressed by the following equation (1).
Figure JPOXMLDOC01-appb-M000001
 　交流成分によるドレイン電流のオフセットを求めるため、（１）式を積分すると（２）式が得られる。この（２）式の第２項が、高周波ノイズ成分による直流オフセット電流となる。
Figure JPOXMLDOC01-appb-M000001
 In order to obtain the offset of the drain current due to the AC component, equation (2) is obtained by integrating equation (1). The second term of the equation (2) is a DC offset current due to a high frequency noise component.
Figure JPOXMLDOC01-appb-M000002
 　ここで、交流成分ｖgsが振幅Ｖｍを持つ正弦波ノイズとすると、交流成分ｖgsは（３）式のように表すことができ、さらに（４）式が成立する。その結果、（２）式の第２項は（５）式に等しくなる。
Figure JPOXMLDOC01-appb-M000002
 Here, when the AC component vgs is a sine wave noise having an amplitude Vm, the AC component vgs can be expressed as shown in Equation (3), and further, Equation (4) is established. As a result, the second term of equation (2) is equal to equation (5).
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000005
 　すなわち、ＭＯＳトランジスタのゲート・ソース間に高周波ノイズが印加されると、そのＭＯＳトランジスタには（５）式で示す正の直流オフセット電流が流れる。従って、差動対２を構成するトランジスタＭ１、Ｍ２のゲート・ソース間に加わる高周波ノイズの振幅が異なると、（５）式で示す直流オフセット電流が相違してアンバランスとなり、オフセット電圧が発生することが分かる。
Figure JPOXMLDOC01-appb-M000005
 That is, when high-frequency noise is applied between the gate and source of a MOS transistor, a positive DC offset current expressed by the equation (5) flows through the MOS transistor. Therefore, if the amplitude of the high frequency noise applied between the gate and source of the transistors M1 and M2 constituting the differential pair 2 is different, the DC offset current shown in the equation (5) is different and unbalanced, and an offset voltage is generated. I understand that.
　そこで、非反転入力端子５に高周波ノイズが加わったとき、トランジスタＭ１、Ｍ２のゲート・ソース間に伝搬されるノイズの振幅が等しくなる条件を求める。図３は、トランジスタＭ１、Ｍ２のゲート・ソース間電圧の交流成分ｖgs1、ｖgs2を求めるための非反転入力端子５から第１電源線７までの交流等価回路である。交流領域では、非反転入力端子５と第１電源線７との間には交流成分ｖrfだけが存在し、反転入力端子６は第１電源線７に接地された状態となる。 Therefore, when high frequency noise is applied to the non-inverting input terminal 5, a condition is obtained in which the amplitudes of noise propagated between the gates and sources of the transistors M1 and M2 are equal. FIG. 3 is an AC equivalent circuit from the non-inverting input terminal 5 to the first power supply line 7 for obtaining AC components vgs1, vgs2 of the gate-source voltages of the transistors M1, M2. In the AC region, only the AC component vrf exists between the non-inverting input terminal 5 and the first power supply line 7, and the inverting input terminal 6 is grounded to the first power supply line 7.
　ノードＮ１と第１電源線７との間の電圧ｖｔは（６）式となる。 The voltage vt between the node N1 and the first power supply line 7 is expressed by equation (6).
Figure JPOXMLDOC01-appb-M000006
 　トランジスタＭ１、Ｍ２のゲート・ソース間電圧の交流成分ｖgs1、ｖgs2は、それぞれ（７）式、（８）式となる。
Figure JPOXMLDOC01-appb-M000006
 The AC components vgs1 and vgs2 of the gate-source voltages of the transistors M1 and M2 are expressed by Equations (7) and (8), respectively.
Figure JPOXMLDOC01-appb-M000007
Figure JPOXMLDOC01-appb-M000007
Figure JPOXMLDOC01-appb-M000008
 　補償コンデンサＣａ、Ｃｂの容量が寄生容量Ｃgs1、Ｃgs2、Ｃt3よりも大きいとすれば、（７）式、（８）式はそれぞれ（９）式、（１０）式のように近似できる。この近似は、補償コンデンサＣａ、Ｃｂの容量が寄生容量Ｃgs1、Ｃgs2、Ｃt3に比べて大きいほど精度が高まる。一例を示せば、補償コンデンサＣａ、Ｃｂが数ｐＦ、寄生容量Ｃgs1、Ｃgs2、Ｃt3が数十ｆＦである。
Figure JPOXMLDOC01-appb-M000008
 If the capacitances of the compensation capacitors Ca and Cb are larger than the parasitic capacitances Cgs1, Cgs2, and Ct3, the equations (7) and (8) can be approximated as equations (9) and (10), respectively. This approximation is more accurate as the compensation capacitors Ca and Cb have larger capacitances than the parasitic capacitances Cgs1, Cgs2, and Ct3. For example, the compensation capacitors Ca and Cb are several pF, and the parasitic capacitances Cgs1, Cgs2, and Ct3 are several tens of fF.
Figure JPOXMLDOC01-appb-M000009
Figure JPOXMLDOC01-appb-M000009
Figure JPOXMLDOC01-appb-M000010
 　ここで、補償コンデンサＣａ、Ｃｂの容量値が互いに等しい場合、次の（１１）式、（１２）式、（１３）式が得られる。
Figure JPOXMLDOC01-appb-M000010
 Here, when the capacitance values of the compensation capacitors Ca and Cb are equal to each other, the following equations (11), (12), and (13) are obtained.
Figure JPOXMLDOC01-appb-M000011
Figure JPOXMLDOC01-appb-M000011
Figure JPOXMLDOC01-appb-M000012
Figure JPOXMLDOC01-appb-M000012
Figure JPOXMLDOC01-appb-M000013
 　すなわち、トランジスタＭ１、Ｍ２のゲート・ソース間に伝搬される高周波ノイズの振幅は等しくなる。その結果、トランジスタＭ１、Ｍ２に流れる直流オフセット電流の大きさは等しくなり、直流オフセット電流が打ち消し合ってドレイン電流のアンバランスが生じない。
Figure JPOXMLDOC01-appb-M000013
 That is, the amplitudes of the high frequency noises propagated between the gates and sources of the transistors M1 and M2 are equal. As a result, the magnitudes of the DC offset currents flowing through the transistors M1 and M2 become equal, the DC offset currents cancel each other, and no drain current imbalance occurs.
　本実施形態の差動増幅器１によれば、互いに容量値が等しく且つ寄生容量Ｃgs1、Ｃgs2、Ｃt3よりも大きい容量値を持つ補償コンデンサＣａ、Ｃｂを備えたので、非反転入力端子５に高周波ノイズが加わっても、出力端子９におけるオフセット電圧の発生を抑えることができる。すなわち、ノイズ耐量を高める効果が得られる。 According to the differential amplifier 1 of the present embodiment, since the compensation capacitors Ca and Cb having the same capacitance values and the capacitance values larger than the parasitic capacitances Cgs1, Cgs2, and Ct3 are provided, the non-inverting input terminal 5 has high frequency noise. Even if is added, generation of an offset voltage at the output terminal 9 can be suppressed. That is, an effect of increasing noise tolerance can be obtained.
　第１、第２補償コンデンサＣａ、Ｃｂは、寄生容量Ｃgs1、Ｃgs2、Ｃt3よりも大きい容量値とすればよく、比較的小さい面積で実現できるため、インダクタなどの素子を用いる従来構成と比べて回路面積の増大を抑制できる。差動増幅器１は、センサ信号を増幅する集積回路などに好適となる。 The first and second compensation capacitors Ca and Cb need only have capacitance values larger than the parasitic capacitances Cgs1, Cgs2, and Ct3, and can be realized with a relatively small area. An increase in area can be suppressed. The differential amplifier 1 is suitable for an integrated circuit that amplifies a sensor signal.
　（第２実施形態）
　第２実施形態について図４を参照しながら説明する。本実施形態は、上述した差動増幅器１の出力端子９を反転入力端子６に接続し、出力電圧Ｖoutを帰還させるボルテージフォロワの形態を備えている。非反転入力端子５から入力された電圧Ｖin1がゲイン１倍されて出力端子９から出力される。第１実施形態で説明したように、入力電圧Ｖin1に高周波ノイズが重畳しても、出力電圧Ｖoutには高周波ノイズによるオフセット電圧は発生しない。 (Second Embodiment)
A second embodiment will be described with reference to FIG. The present embodiment has a voltage follower configuration in which the output terminal 9 of the differential amplifier 1 described above is connected to the inverting input terminal 6 and the output voltage Vout is fed back. The voltage Vin1 input from the non-inverting input terminal 5 is multiplied by 1 and output from the output terminal 9. As described in the first embodiment, even when high frequency noise is superimposed on the input voltage Vin1, no offset voltage due to high frequency noise is generated in the output voltage Vout.
　（第３実施形態）
　第３実施形態について図５を参照しながら説明する。差動増幅器１１は、図１に示した差動増幅器１の第２補償コンデンサＣｂを備えておらず、トランジスタＭ１のゲート・ソース間に第１補償コンデンサＣａに替えて補償コンデンサＣｄを備えている点において異なる。 (Third embodiment)
A third embodiment will be described with reference to FIG. The differential amplifier 11 does not include the second compensation capacitor Cb of the differential amplifier 1 shown in FIG. 1, but includes a compensation capacitor Cd instead of the first compensation capacitor Ca between the gate and source of the transistor M1. It is different in point.
　補償コンデンサＣｄも、上述した補償コンデンサＣａ、Ｃｂと同様に、非反転入力端子５に高周波ノイズが加わったときにトランジスタＭ１、Ｍ２のゲート・ソース間に伝搬されるノイズの振幅が等しくなるように容量値が設定されている。その条件は、（１４）式に示す通りである。 Similarly to the above-described compensation capacitors Ca and Cb, the compensation capacitor Cd also has the same amplitude of noise propagated between the gate and source of the transistors M1 and M2 when high frequency noise is applied to the non-inverting input terminal 5. A capacity value is set. The conditions are as shown in the equation (14).
Figure JPOXMLDOC01-appb-M000014
 　上述した（７）式、（８）式にＣt3＝０および（１４）式を代入すると、トランジスタＭ１、Ｍ２のゲート・ソース間電圧の交流成分ｖgs1、ｖgs2は、それぞれ（１５）式、（１６）式となる。
Figure JPOXMLDOC01-appb-M000014
 By substituting Ct3 = 0 and (14) into the above equations (7) and (8), the AC components vgs1 and vgs2 of the gate-source voltages of the transistors M1 and M2 are expressed by equations (15) and (16, respectively). ).
Figure JPOXMLDOC01-appb-M000015
Figure JPOXMLDOC01-appb-M000015
Figure JPOXMLDOC01-appb-M000016
 　本実施形態によっても、非反転入力端子５に高周波ノイズが加わることでトランジスタＭ１、Ｍ２に流れる直流オフセット電流の大きさは等しくなり、互いに打ち消し合ってオフセット電圧の発生を抑えることができる。すなわち、ノイズ耐量を高める効果が得られる。
Figure JPOXMLDOC01-appb-M000016
 Also according to the present embodiment, the magnitude of the DC offset current flowing through the transistors M1 and M2 is equalized when high frequency noise is applied to the non-inverting input terminal 5, and the generation of offset voltage can be suppressed by canceling each other. That is, an effect of increasing noise tolerance can be obtained.
　また、（１４）式に示す関係において、寄生容量Ｃgs1とＣgs2とは非常に近い値であり、寄生容量は数十ｆＦ程度の極めて小さい値なので、補償コンデンサＣｄの容量値も数十ｆＦ程度の値となる。従って、補償コンデンサＣｄは非常に小さい面積で実現でき、インダクタなどの素子を用いる従来構成と比べて回路面積の増大を抑制できる。本実施形態の差動増幅器１１も、センサ信号を増幅する集積回路などに好適となる。 Further, in the relationship shown in the equation (14), the parasitic capacitances Cgs1 and Cgs2 are very close values, and the parasitic capacitance is an extremely small value of about several tens of fF. Therefore, the capacitance value of the compensation capacitor Cd is also about several tens of fF. Value. Therefore, the compensation capacitor Cd can be realized with a very small area, and an increase in circuit area can be suppressed as compared with the conventional configuration using an element such as an inductor. The differential amplifier 11 of this embodiment is also suitable for an integrated circuit that amplifies a sensor signal.
　（第４実施形態）
　第４実施形態について図６および図７を参照しながら説明する。図６に示す差動増幅器２１は、図１に示した差動増幅器１に対し、トランジスタＭ１、Ｍ２のソースとノードＮ１との間にソース抵抗Ｒ１、Ｒ２を備えている。 (Fourth embodiment)
A fourth embodiment will be described with reference to FIGS. The differential amplifier 21 shown in FIG. 6 includes source resistors R1 and R2 between the sources of the transistors M1 and M2 and the node N1 with respect to the differential amplifier 1 shown in FIG.
　ソース接地回路のトランジスタＭ１、Ｍ２のトランスコンダクタンスｇｍは入力電圧に依存するため、入力と出力の関係は非線形になる。これに対し、ソース抵抗Ｒ１、Ｒ２を挿入すると、負帰還によりトランスコンダクタンスｇｍへの依存性が減り、入出力特性の線形性が向上する。ただし、ソース抵抗Ｒ１、Ｒ２がない差動増幅器１に比べゲインは低下する。 Since the transconductance gm of the transistors M1 and M2 of the common source circuit depends on the input voltage, the relationship between the input and the output is nonlinear. On the other hand, when the source resistors R1 and R2 are inserted, the dependence on the transconductance gm is reduced by negative feedback, and the linearity of the input / output characteristics is improved. However, the gain is lower than that of the differential amplifier 1 without the source resistors R1 and R2.
　図７に示したソース抵抗付きのソース接地回路の場合、トランスコンダクタンスＧｍは（１７）式となり、小信号電圧利得Ａｖは（１８）式となる。ｇｍは、トランジスタＭ１のトランスコンダクタンスである。 In the case of the common source circuit with a source resistance shown in FIG. 7, the transconductance Gm is given by equation (17), and the small signal voltage gain Av is given by equation (18). gm is the transconductance of the transistor M1.
Figure JPOXMLDOC01-appb-M000017
Figure JPOXMLDOC01-appb-M000017
Figure JPOXMLDOC01-appb-M000018
 　すなわち、トランジスタＭ１のトランスコンダクタンスｇｍにかかわらず、抵抗値によって与えられる線形の特性が得られる。ソース抵抗Ｒ１、Ｒ２を備えた本実施形態の差動増幅器２１も、第１実施形態と同様にノイズ耐量を高める効果を奏する。
Figure JPOXMLDOC01-appb-M000018
 That is, a linear characteristic given by the resistance value is obtained regardless of the transconductance gm of the transistor M1. The differential amplifier 21 of the present embodiment provided with the source resistors R1 and R2 also has the effect of increasing the noise immunity as in the first embodiment.
　（第１、第２、第４実施形態の変形例）
　第１、第２、第４実施形態では、補償コンデンサＣａ、Ｃｂの容量値が互いに等しく且つ寄生容量Ｃgs1、Ｃgs2、Ｃt3よりも大きい形態を示したが、高周波ノイズによるオフセット電圧を抑制できれば、第１、第２補償コンデンサＣａ、Ｃｂの容量値は適宜変更しても良い。例えば、第１、第２補償コンデンサＣａ、Ｃｂを互いに異なる容量値としても良い。トランジスタＭ１、Ｍ２のゲート・ソース間電圧の交流成分ｖgs1、ｖgs2は、前述したように、それぞれ（７）式、（８）式に示すように表すことができる。これらのトランジスタＭ１、Ｍ２のゲート・ソース間に伝播される高周波ノイズの振幅の差は、下記の（１９）式に示す通りである。 (Modification of the first, second and fourth embodiments)
In the first, second, and fourth embodiments, the compensation capacitors Ca and Cb have the same capacitance value and larger than the parasitic capacitances Cgs1, Cgs2, and Ct3. However, if the offset voltage due to high frequency noise can be suppressed, The capacitance values of the first and second compensation capacitors Ca and Cb may be changed as appropriate. For example, the first and second compensation capacitors Ca and Cb may have different capacitance values. As described above, the AC components vgs1 and vgs2 of the gate-source voltages of the transistors M1 and M2 can be expressed as shown in the equations (7) and (8), respectively. The difference in the amplitude of the high frequency noise propagated between the gate and source of these transistors M1 and M2 is as shown in the following equation (19).
Figure JPOXMLDOC01-appb-M000019
 　ここで、このΔｖgsを所定値以下に抑えられれば、高周波ノイズの振幅の差を所定値以下に抑えることができる。したがって、第１、第２補償コンデンサＣａ、Ｃｂの容量値は、このΔｖgsが予め定められる所定値以下に抑えられるように適宜設定されていると良い。これにより、ノイズ耐量を高める効果を奏する。
Figure JPOXMLDOC01-appb-M000019
 Here, if this Δvgs can be suppressed to a predetermined value or less, the difference in amplitude of the high frequency noise can be suppressed to a predetermined value or less. Therefore, the capacitance values of the first and second compensation capacitors Ca and Cb are preferably set as appropriate so that the Δvgs can be suppressed to a predetermined value or less. Thereby, there exists an effect which raises noise tolerance.
　（第３実施形態の変形例）
　第３実施形態においても、高周波ノイズによるオフセット電圧を抑制できれば、補償コンデンサＣｄの容量値は適宜変更しても良い。トランジスタＭ１、Ｍ２のゲート・ソース間電圧の交流成分ｖgs1、ｖgs2は、前述したように、それぞれ（１５）式、（１６）式のように表すことができる。これらのトランジスタＭ１、Ｍ２のゲート・ソース間に伝播される高周波ノイズの振幅の差は、下記の（２０）式に示す通りである。 (Modification of the third embodiment)
Also in the third embodiment, the capacitance value of the compensation capacitor Cd may be appropriately changed as long as the offset voltage due to high frequency noise can be suppressed. As described above, the AC components vgs1 and vgs2 of the gate-source voltages of the transistors M1 and M2 can be expressed as shown in equations (15) and (16), respectively. The difference in amplitude of the high frequency noise propagated between the gate and source of these transistors M1 and M2 is as shown in the following equation (20).
Figure JPOXMLDOC01-appb-M000020
 　ここで、このΔｖgsを所定値以下に抑えられれば、高周波ノイズの振幅の差を所定値以下に抑えることができる。したがって、補償コンデンサＣｄの容量値は、このΔｖgsが予め定められる所定値以下に抑えられるように適宜設定されていると良い。これにより、ノイズ耐量を高める効果を奏する。
Figure JPOXMLDOC01-appb-M000020
 Here, if this Δvgs can be suppressed to a predetermined value or less, the difference in amplitude of the high frequency noise can be suppressed to a predetermined value or less. Therefore, the capacitance value of the compensation capacitor Cd is preferably set as appropriate so that the Δvgs can be suppressed to a predetermined value or less. Thereby, there exists an effect which raises noise tolerance.
　（第５実施形態）
　図８は第５実施形態の説明図を示しており、第１実施形態の図２に対応して示している。図２のトランジスタＭ１～Ｍ６と同一機能を備える図８のトランジスタＭ１ｂ～Ｍ６ｂには、対応する図２のトランジスタＭ１～Ｍ６に添え字「ｂ」を付して示している。 (Fifth embodiment)
FIG. 8 shows an explanatory diagram of the fifth embodiment, corresponding to FIG. 2 of the first embodiment. The transistors M1b to M6b of FIG. 8 having the same functions as those of the transistors M1 to M6 of FIG. 2 are indicated by adding the subscript “b” to the corresponding transistors M1 to M6 of FIG.
　図８の差動増幅器１０１は、差動入力トランジスタとしてＰチャネル型のＭＯＳトランジスタＭ１ｂ、Ｍ２ｂを用いている。図８に示す回路構成の詳細説明は省略するが、負荷回路としての能動負荷４が第１電源線７（グランド）側に構成され、定電流回路３が第２電源線８側に構成されている。本実施形態でも第１実施形態とほぼ同様の作用効果を奏する。 8 uses P-channel MOS transistors M1b and M2b as differential input transistors. Although detailed description of the circuit configuration shown in FIG. 8 is omitted, the active load 4 as a load circuit is configured on the first power supply line 7 (ground) side, and the constant current circuit 3 is configured on the second power supply line 8 side. Yes. In the present embodiment, there are almost the same effects as the first embodiment.
　また、図示しないが、第２実施形態に示したボルテージフォロワの形態を用いることもできる。すなわち、差動増幅器１０１の出力端子９を反転入力端子６に接続し、電圧Ｖrefに代えてコンデンサＣＬを接続し、出力電圧Ｖoutを帰還させることも可能である。また、図示しないが、第４実施形態に示したソース抵抗付きのソース接地回路の形態を用いることもできる。 Although not shown, the form of the voltage follower shown in the second embodiment can also be used. In other words, the output terminal 9 of the differential amplifier 101 can be connected to the inverting input terminal 6 and the capacitor CL can be connected instead of the voltage Vref to feed back the output voltage Vout. Although not shown, the form of the common source circuit with the source resistance shown in the fourth embodiment can also be used.
　（第６実施形態）
　図９は第６実施形態の説明図を示しており、第３実施形態の図５に対応して示している。図５のトランジスタＭ１～Ｍ６と同一機能を備える図９のトランジスタＭ１ｂ～Ｍ６ｂには、対応する図５のトランジスタＭ１～Ｍ６に添え字「ｂ」を付して示している。 (Sixth embodiment)
FIG. 9 shows an explanatory diagram of the sixth embodiment, corresponding to FIG. 5 of the third embodiment. The transistors M1b to M6b in FIG. 9 having the same functions as the transistors M1 to M6 in FIG. 5 are indicated by adding the subscript “b” to the corresponding transistors M1 to M6 in FIG.
　図９の差動増幅器２０１は、差動入力トランジスタとしてＰチャネル型のＭＯＳトランジスタＭ１ｂ、Ｍ２ｂを用いている。図９の回路構成の詳細説明は省略するが、負荷回路としての能動負荷４が第１電源線７（グランド）側に構成され、定電流回路３が第２電源線８側に構成されている。本実施形態においても、第３実施形態とほぼ同様の作用効果を奏する。 The differential amplifier 201 in FIG. 9 uses P-channel MOS transistors M1b and M2b as differential input transistors. Although a detailed description of the circuit configuration of FIG. 9 is omitted, the active load 4 as a load circuit is configured on the first power supply line 7 (ground) side, and the constant current circuit 3 is configured on the second power supply line 8 side. . Also in this embodiment, there exists an effect substantially the same as 3rd Embodiment.
　また、図示しないが、第２実施形態に示したボルテージフォロワの形態を用いることもできる。すなわち、差動増幅器２０１の出力端子９を反転入力端子６に接続し、電圧Ｖrefに代えてコンデンサＣＬを接続し、出力電圧Ｖoutを帰還させることも可能である。また、図示しないが、第４実施形態に示したソース抵抗付きのソース接地回路の形態を用いることもできる。 Although not shown, the form of the voltage follower shown in the second embodiment can also be used. That is, the output terminal 9 of the differential amplifier 201 can be connected to the inverting input terminal 6 and the capacitor CL can be connected instead of the voltage Vref to feed back the output voltage Vout. Although not shown, the form of the common source circuit with the source resistance shown in the fourth embodiment can also be used.
　（第７実施形態）
　図１０は第７実施形態の説明図を示しており、第１実施形態の図２に対応して示している。図２のトランジスタＭ１～Ｍ６と同一機能を備えるトランジスタにはトランジスタＴ１～Ｔ６として図１０に符号を付している。 (Seventh embodiment)
FIG. 10 shows an explanatory diagram of the seventh embodiment, corresponding to FIG. 2 of the first embodiment. Transistors having the same functions as those of the transistors M1 to M6 in FIG. 2 are denoted by reference numerals in FIG. 10 as transistors T1 to T6.
　この図１０の差動増幅器３０１に示すように、ベース（制御端子）、コレクタ（第２通電端子）、エミッタ（第１通電端子）の各端子を備えたバイポーラジャンクショントランジスタＴ１～Ｔ６を用いて構成しても良い。 As shown in the differential amplifier 301 of FIG. 10, a bipolar junction transistor T1 to T6 having a base (control terminal), a collector (second energization terminal), and an emitter (first energization terminal) is used. You may do it.
　また、図示しないが、第２実施形態に示したボルテージフォロワの形態を用いることもできる。すなわち、差動増幅器３０１の出力端子９を反転入力端子６に接続し、電圧Ｖrefに代えてコンデンサＣＬを接続し、出力電圧Ｖoutを帰還させることも可能である。また、図示しないが、第４実施形態に類似構成（ソース接地回路）を示すように、エミッタ抵抗付きのエミッタ接地回路の形態を用いることもできる。 Although not shown, the form of the voltage follower shown in the second embodiment can also be used. That is, the output terminal 9 of the differential amplifier 301 can be connected to the inverting input terminal 6, and the capacitor CL can be connected instead of the voltage Vref to feed back the output voltage Vout. Further, although not shown, a form of a grounded emitter circuit with an emitter resistor can be used so as to show a similar configuration (grounded source circuit) as in the fourth embodiment.
　（第８実施形態）
　図１１は第８実施形態の説明図を示しており、第３実施形態の図５に対応して示している。図５のトランジスタＭ１～Ｍ６と同一機能を備えるトランジスタにはトランジスタＴ１～Ｔ６として図１１に符号を付している。この図１１の差動増幅器４０１に示すように、第３実施形態の構成についても、バイポーラジャンクショントランジスタＴ１～Ｔ６を用いて構成しても良い。 (Eighth embodiment)
FIG. 11 shows an explanatory diagram of the eighth embodiment, corresponding to FIG. 5 of the third embodiment. Transistors having the same functions as those of the transistors M1 to M6 in FIG. 5 are denoted by reference numerals in FIG. 11 as transistors T1 to T6. As shown in the differential amplifier 401 of FIG. 11, the configuration of the third embodiment may also be configured using bipolar junction transistors T1 to T6.
　また、図示しないが、第２実施形態に示したボルテージフォロワの形態を用いることもできる。すなわち、差動増幅器４０１の出力端子９を反転入力端子６に接続し、電圧Ｖrefに代えてコンデンサＣＬを接続し、出力電圧Ｖoutを帰還させることも可能である。また、図示しないが、第４実施形態に類似構成（ソース接地回路）を示したように、エミッタ抵抗付きのエミッタ接地回路の形態を用いることもできる。 Although not shown, the form of the voltage follower shown in the second embodiment can also be used. In other words, the output terminal 9 of the differential amplifier 401 can be connected to the inverting input terminal 6 and the capacitor CL can be connected instead of the voltage Vref to feed back the output voltage Vout. Although not shown in the drawings, a configuration of a grounded emitter circuit with an emitter resistor can be used as shown in a similar configuration (grounded source circuit) to the fourth embodiment.
　（第９実施形態）
　図１２は第９実施形態の説明図を示しており、第１実施形態の図２に対応して示している。図２のトランジスタＭ１～Ｍ６と同一機能を備える図１２のトランジスタＭ１ｃ～Ｍ６ｃには、対応する図２のトランジスタＭ１～Ｍ６に添え字「ｃ」を付して示している。図１２の差動増幅器５０１に示すように、負荷回路４ｃとしては、例えばトランジスタＭ１ｃ、Ｍ２ｃによる差動対２のドレインが折り返された回路（例えば一定バイアスｂ１が印加されたフォールデッドカスコード回路Ｍ５ｃ～Ｍ８ｃ）を用いても良い。また、一定のバイアスｂ２～ｂ３が印加された能動負荷Ｍ９ｃ～Ｍ１２ｃをフォールデッドカスコード回路Ｍ５ｃ～Ｍ８ｃに直列接続して構成しても良いし、この能動負荷Ｍ９ｃ～Ｍ１２ｃに代えて抵抗を接続しても良い。 (Ninth embodiment)
FIG. 12 shows an explanatory diagram of the ninth embodiment, corresponding to FIG. 2 of the first embodiment. The transistors M1c to M6c of FIG. 12 having the same functions as those of the transistors M1 to M6 of FIG. 2 are indicated by adding the suffix “c” to the corresponding transistors M1 to M6 of FIG. As shown in the differential amplifier 501 of FIG. 12, the load circuit 4c includes, for example, a circuit in which the drains of the differential pair 2 by transistors M1c and M2c are folded (for example, a folded cascode circuit M5c to M5c to which a constant bias b1 is applied). M8c) may be used. Further, active loads M9c to M12c to which constant biases b2 to b3 are applied may be connected in series to the folded cascode circuits M5c to M8c, or resistors may be connected instead of the active loads M9c to M12c. May be.
　（第１０実施形態）
　図１３は第１０実施形態の説明図を示しており、第３実施形態の図５に対応して示している。図５のトランジスタＭ１～Ｍ６と同一機能を備える図１３のトランジスタＭ１ｃ～Ｍ６ｃには、対応する図５のトランジスタＭ１～Ｍ６に添え字「ｃ」を付して示している。図１３の差動増幅器６０１に示すように、負荷回路４ｃは、例えばトランジスタＭ１ｃ、Ｍ２ｃによる差動対２のドレインが折り返された回路（例えばフォールデッドカスコード回路Ｍ５ｃ～Ｍ８ｃ）を用いても良い。また、一定のバイアスｂ２～ｂ３が印加された能動負荷Ｍ９ｃ～Ｍ１２ｃをフォールデッドカスコード回路Ｍ５ｃ～Ｍ８ｃに直列接続して構成しても良いし、この能動負荷Ｍ９ｃ～Ｍ１２ｃに代えて抵抗を接続しても良い。 (10th Embodiment)
FIG. 13 shows an explanatory diagram of the tenth embodiment, corresponding to FIG. 5 of the third embodiment. The transistors M1c to M6c of FIG. 13 having the same functions as those of the transistors M1 to M6 of FIG. 5 are indicated by adding the subscript “c” to the corresponding transistors M1 to M6 of FIG. As shown in the differential amplifier 601 of FIG. 13, the load circuit 4c may use, for example, a circuit (for example, folded cascode circuits M5c to M8c) in which the drains of the differential pair 2 by the transistors M1c and M2c are folded. Further, active loads M9c to M12c to which constant biases b2 to b3 are applied may be connected in series to the folded cascode circuits M5c to M8c, or a resistor is connected instead of the active loads M9c to M12c. May be.
　（その他の実施形態）
　以上、本開示の実施形態について説明したが、本開示は上述した実施形態に限定されるものではなく、発明の要旨を逸脱しない範囲内で種々の変形、拡張を行うことができる。 (Other embodiments)
Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications and extensions can be made without departing from the scope of the invention.
　反転入力端子６に高周波ノイズが加わる場合には、第１補償コンデンサＣａおよび補償コンデンサＣｄは、反転入力端子６に接続されたトランジスタＭ２のゲート・ソース間に接続すればよい。第２実施形態に一例を示したように、第１、第３実施形態に示した差動増幅器１、１１について、差動対２から出力される信号を入力端子に帰還させる形態とすることができる。 When high-frequency noise is applied to the inverting input terminal 6, the first compensation capacitor Ca and the compensation capacitor Cd may be connected between the gate and source of the transistor M2 connected to the inverting input terminal 6. As shown in the second embodiment, the differential amplifiers 1 and 11 shown in the first and third embodiments may be configured to feed back the signal output from the differential pair 2 to the input terminal. it can.
　第３実施形態に示した差動増幅器１１にソース抵抗Ｒ１、Ｒ２を加えても、第４実施形態と同様にノイズ耐量を高める効果を奏する。第２補償コンデンサＣｂは、ノードＮ１と第１電源線７との間に設けたが、ノードＮ１と接地線（第１電源線７と交流的に同電位となる接地線）との間に設けてもよい。 Even if the source resistors R1 and R2 are added to the differential amplifier 11 shown in the third embodiment, the effect of increasing noise immunity is obtained as in the fourth embodiment. The second compensation capacitor Cb is provided between the node N1 and the first power supply line 7. However, the second compensation capacitor Cb is provided between the node N1 and the ground line (a ground line having the same potential as the first power supply line 7). May be.
　定電流回路３の代わりに抵抗を設け、差動対２のトランジスタＭ１、Ｍ２のコモンソースが抵抗に接続される構成であってもよい。前述の各実施形態では、本願に係る代表的な回路構成を図示しているが、各実施形態の構成又は技術思想は適宜組み合わせて適用できる。また、一般的な回路構成を組み合わせて適用でき、前述実施形態で説明した回路トポロジに限られるものではない。 A configuration in which a resistor is provided instead of the constant current circuit 3 and the common sources of the transistors M1 and M2 of the differential pair 2 are connected to the resistor may be employed. In each of the above-described embodiments, a typical circuit configuration according to the present application is illustrated, but the configuration or technical idea of each embodiment can be applied in appropriate combination. Further, a general circuit configuration can be applied in combination, and is not limited to the circuit topology described in the above embodiment.

Claims (8)

  1. 　対をなす第１入力端子（５）、第２入力端子（６）と、第１通電端子、第２通電端子、および制御端子を有する第１差動入力トランジスタ（Ｍ１、Ｍ１ｂ、Ｍ１ｃ、Ｔ１）と、第１通電端子、第２通電端子、および制御端子を有する第２差動入力トランジスタ（Ｍ２、Ｍ２ｂ、Ｍ２ｃ、Ｔ２）とを備え、前記第１差動入力トランジスタの前記制御端子は前記第１入力端子に接続され、前記第２差動入力トランジスタの前記制御端子は前記第２入力端子に接続され、前記第１差動入力トランジスタの前記第１通電端子と前記第２差動入力トランジスタの前記第１通電端子とが接続された差動対（２）と、
    　前記第１差動入力トランジスタの前記第１通電端子および前記第２差動入力トランジスタの前記第１通電端子と第１電源線（７）との間に接続され、前記差動対に流す電流を生成する電流生成回路（３）と、
    　前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間に接続された第１補償コンデンサ（Ｃａ）と、
    　前記第１差動入力トランジスタの前記第１通電端子および前記第２差動入力トランジスタの前記第１通電端子と、前記第１電源線または前記第１電源線と交流的に同電位となる接地線との間に接続された第２補償コンデンサ（Ｃｂ）と、を備え、
    　前記第１入力端子に交流ノイズを含む電圧が印加された際に、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する交流ノイズの振幅と、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する交流ノイズの振幅の差が所定値以内となるように、前記第１補償コンデンサの容量値および、前記第２補償コンデンサの容量値が設定されている差動増幅器。     A first differential input transistor (M1, M1b, M1c, T1) having a pair of a first input terminal (5), a second input terminal (6), a first energization terminal, a second energization terminal, and a control terminal And a second differential input transistor (M2, M2b, M2c, T2) having a first energization terminal, a second energization terminal, and a control terminal, the control terminal of the first differential input transistor being the first A first input terminal, the control terminal of the second differential input transistor is connected to the second input terminal, the first energization terminal of the first differential input transistor and the second differential input transistor; A differential pair (2) connected to the first energization terminal;
    A current flowing through the differential pair is connected between the first energization terminal of the first differential input transistor and the first energization terminal of the second differential input transistor and a first power supply line (7). A current generation circuit (3) to generate;
    A first compensation capacitor (Ca) connected between the control terminal of the first differential input transistor and the first energization terminal;
    The first energization terminal of the first differential input transistor and the first energization terminal of the second differential input transistor, and the first power supply line or a ground line that has the same potential as the first power supply line. A second compensation capacitor (Cb) connected between
    When a voltage including AC noise is applied to the first input terminal, the amplitude of AC noise propagating between the control terminal and the first energization terminal of the first differential input transistor, and the second The capacitance value of the first compensation capacitor and the second compensation capacitor so that the difference in amplitude of AC noise propagating between the control terminal and the first energization terminal of the differential input transistor is within a predetermined value. A differential amplifier with a capacitance value of.
  2. 　前記第１補償コンデンサの前記容量値、および前記第２補償コンデンサの前記容量値は、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する前記交流ノイズの前記振幅と、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する前記交流ノイズの前記振幅の差が０となるように設定されている請求項１記載の差動増幅器。 The capacitance value of the first compensation capacitor and the capacitance value of the second compensation capacitor are the values of the AC noise propagating between the control terminal and the first conduction terminal of the first differential input transistor. 2. The difference according to claim 1, wherein the difference between the amplitude and the amplitude of the AC noise propagating between the control terminal and the first energization terminal of the second differential input transistor is set to be zero. Dynamic amplifier.
  3. 　前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する前記交流ノイズの前記振幅と、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間に伝播する前記交流ノイズの前記振幅が同じになるように、前記第１補償コンデンサの前記容量値と、前記第２補償コンデンサの前記容量値は互いに等しく、且つ、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間の寄生容量（Ｃgs1）、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間の寄生容量（Ｃgs2）、および前記電流生成回路の出力寄生容量（Ｃt3）よりも大きい値に設定されている請求項１または２記載の差動増幅器。 The amplitude of the AC noise propagating between the control terminal of the first differential input transistor and the first energization terminal, and the control terminal and the first energization terminal of the second differential input transistor. The capacitance value of the first compensation capacitor and the capacitance value of the second compensation capacitor are equal to each other and the first differential input transistor so that the amplitude of the AC noise propagating therebetween is the same. A parasitic capacitance (Cgs1) between the control terminal and the first energization terminal, a parasitic capacitance (Cgs2) between the control terminal and the first energization terminal of the second differential input transistor, and the current 3. The differential amplifier according to claim 1, wherein the differential amplifier is set to a value larger than an output parasitic capacitance (Ct3) of the generation circuit.
  4. 　対をなす第１入力端子（５）、第２入力端子（６）と、第１通電端子、第２通電端子、および制御端子を有する第１差動入力トランジスタ（Ｍ１、Ｍ１ｂ、Ｍ１ｃ、Ｔ１）と、第１通電端子、第２通電端子、および制御端子を有する第２差動入力トランジスタ（Ｍ２、Ｍ２ｂ、Ｍ２ｃ、Ｔ２）とを備え、前記第１差動入力トランジスタの前記制御端子は前記第１入力端子に接続され、前記第２差動入力トランジスタの前記制御端子は前記第２入力端子に接続され、前記第１差動入力トランジスタの第１通電端子と前記第２差動入力トランジスタの第１通電端子とが接続された差動対（２）と、
    　前記第１差動入力トランジスタの前記第１通電端子および前記第２差動入力トランジスタの前記第１通電端子と第１電源線（７）との間に接続され、前記差動対に流す電流を生成する電流生成回路（３）と、
    　前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間に接続された補償コンデンサ（Ｃｄ）とを備え、
    　前記第１入力端子に交流ノイズを含む電圧が印加された際に、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する交流ノイズの振幅と、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する交流ノイズの振幅の差が所定値以内となるように、前記補償コンデンサ（Ｃｄ）の容量値が設定されている差動増幅器。     A first differential input transistor (M1, M1b, M1c, T1) having a pair of a first input terminal (5), a second input terminal (6), a first energization terminal, a second energization terminal, and a control terminal And a second differential input transistor (M2, M2b, M2c, T2) having a first energization terminal, a second energization terminal, and a control terminal, the control terminal of the first differential input transistor being the first The first differential input transistor, the control terminal of the second differential input transistor is connected to the second input terminal, the first energization terminal of the first differential input transistor and the second differential input transistor of the second differential input transistor. A differential pair (2) connected to one energizing terminal;
    A current flowing through the differential pair is connected between the first energization terminal of the first differential input transistor and the first energization terminal of the second differential input transistor and a first power supply line (7). A current generation circuit (3) to generate;
    A compensation capacitor (Cd) connected between the control terminal of the first differential input transistor and the first energization terminal;
    When a voltage including AC noise is applied to the first input terminal, the amplitude of AC noise propagating between the control terminal and the first energization terminal of the first differential input transistor, and the second Difference in which the capacitance value of the compensation capacitor (Cd) is set so that the difference in amplitude of the AC noise propagating between the control terminal and the first energization terminal of the differential input transistor is within a predetermined value. Dynamic amplifier.
  5. 　前記補償コンデンサの容量値は、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する前記交流ノイズの前記振幅と、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する前記交流ノイズの前記振幅の差が０となるように設定されている請求項４記載の差動増幅器。 The capacitance value of the compensation capacitor includes the amplitude of the AC noise propagating between the control terminal of the first differential input transistor and the first energization terminal, and the control terminal of the second differential input transistor. 5. The differential amplifier according to claim 4, wherein the difference in amplitude of the AC noise propagating between the power supply terminal and the first energization terminal is set to be zero.
  6. 　前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間の寄生容量をＣgs1、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間の寄生容量をＣgs2とし、前記電流生成回路の両端子間の出力寄生容量をＣt3としたとき、前記第１差動入力トランジスタの前記制御端子と前記第１通電端子との間を伝播する前記交流ノイズの前記振幅と、前記第２差動入力トランジスタの前記制御端子と前記第１通電端子との間に伝播する前記交流ノイズの前記振幅が同じになるように、前記補償コンデンサ（Ｃｄ）の容量値はＣgs2＋Ｃt3－Ｃgs1に等しく設定されている請求項４または５記載の差動増幅器。 A parasitic capacitance between the control terminal of the first differential input transistor and the first energization terminal is represented by Cgs1, and a parasitic capacitance between the control terminal of the second differential input transistor and the first energization terminal is represented by Cgs1. The amplitude of the AC noise that propagates between the control terminal of the first differential input transistor and the first energization terminal, where Cgs2 is the output parasitic capacitance between both terminals of the current generation circuit. And the capacitance value of the compensation capacitor (Cd) is Cgs2 + Ct3− so that the amplitude of the AC noise propagating between the control terminal and the first energization terminal of the second differential input transistor is the same. 6. The differential amplifier according to claim 4, wherein the differential amplifier is set equal to Cgs1.
  7. 　前記差動対から出力される信号を前記第２入力端子に帰還させる形態を備えている請求項１から６の何れか一項に記載の差動増幅器。 The differential amplifier according to any one of claims 1 to 6, further comprising a configuration in which a signal output from the differential pair is fed back to the second input terminal.
  8. 　第２電源線（８）と前記第１差動入力トランジスタの前記第２通電端子および前記第２差動入力トランジスタの前記第２通電端子との間に負荷回路（４、４ｃ）をさらに備え、
    　前記電流生成回路は定電流回路から構成されている請求項１から７の何れか一項に記載の差動増幅器。     A load circuit (4, 4c) is further provided between the second power line (8) and the second energization terminal of the first differential input transistor and the second energization terminal of the second differential input transistor;
    The differential amplifier according to claim 1, wherein the current generation circuit includes a constant current circuit.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59182608A (en) * 1983-03-31 1984-10-17 Matsushita Electric Ind Co Ltd Low noise amplifier
JP2003037458A (en) * 2001-07-23 2003-02-07 Nec Corp Differential amplifier circuit
JP2005124175A (en) * 2003-09-24 2005-05-12 Matsushita Electric Ind Co Ltd Amplifier and frequency converter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59182608A (en) * 1983-03-31 1984-10-17 Matsushita Electric Ind Co Ltd Low noise amplifier
JP2003037458A (en) * 2001-07-23 2003-02-07 Nec Corp Differential amplifier circuit
JP2005124175A (en) * 2003-09-24 2005-05-12 Matsushita Electric Ind Co Ltd Amplifier and frequency converter

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