WO2015117659A1 - Procédé de préparation de réseau de points quantiques et de structure hétératique à points quantiques - Google Patents

Procédé de préparation de réseau de points quantiques et de structure hétératique à points quantiques Download PDF

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Publication number
WO2015117659A1
WO2015117659A1 PCT/EP2014/052362 EP2014052362W WO2015117659A1 WO 2015117659 A1 WO2015117659 A1 WO 2015117659A1 EP 2014052362 W EP2014052362 W EP 2014052362W WO 2015117659 A1 WO2015117659 A1 WO 2015117659A1
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quantum dot
silar
substrate surface
process according
qds
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PCT/EP2014/052362
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English (en)
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Sachin KINGE
Enrique CANOVAS DIAZ
Mischa BONN
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Toyota Motor Europe Nv/Sa
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Priority to US15/114,267 priority Critical patent/US9917218B2/en
Priority to PCT/EP2014/052362 priority patent/WO2015117659A1/fr
Priority to JP2016550613A priority patent/JP6463773B2/ja
Priority to CN201480074944.1A priority patent/CN105981149B/zh
Publication of WO2015117659A1 publication Critical patent/WO2015117659A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035209—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures
    • H01L31/035218—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures the quantum structure being quantum dots
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/0256—Selenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02568—Chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02601—Nanoparticles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02628—Liquid deposition using solutions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035236—Superlattices; Multiple quantum well structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1828—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
    • H01L31/1836—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe comprising a growth substrate not being an AIIBVI compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation

Definitions

  • the present invention seeks to provide a new way of preparing quantum dot arrays, which may in preferred embodiments be stacked quantum dot superlattices, and can be used in optoelectronic devices such as solar cells.
  • quantum dots reference is made here to nanometer sized particles of semiconductor material where quantum confinement is present. Depending upon the semiconductor material, the maximum sizes change but are usually below lOOnm. The exact size of the quantum dots may enable the semiconductor band gap to be modulated, which provides potential for increasing photo-electric conversion efficiency with respect to bulk films of semiconductor material in more conventional solar cells and related devices.
  • QDs quantum dots
  • QDS QD solid
  • QD-SL QD superlattice
  • QD-SLs have mostly been grown by epitaxial deposition techniques such as molecular beam epitaxy (MBE) or metal-organic chemical vapour deposition (MOCVD), these being techniques that require low vacuum, high temperature and pristine precursors.
  • Solid state grown QD-SLs show a low defect density with QDs which are perfectly passivated by a bulk barrier material.
  • MBE molecular beam epitaxy
  • MOCVD metal-organic chemical vapour deposition
  • colloidal QDs are most commonly spherical, but rod shapes and others are available.
  • QD synthesis does not take place in situ (on top of a bulk substrate) but in solution.
  • the QDs are applied to the substrate surface by spin coating or dropcasting protocols of molecularly passivated QDs onto a substrate. Due to the poorer surface passivation of the nanocrystals, the colloidal approach suffers from high defect concentration and is prone to photodegradation (through oxidation processes).
  • SILAR successive ion layer adsorption reaction
  • a substrate is alternatively soaked in a cation precursor solution and then an anion precursor solution.
  • the cations may here for example the chosen among Cu, Zn, Sn and In, and the deposited anions are most commonly chalcogenides (sulfides and selenides in particular - tellurides are also possible candidates though not often used).
  • the present invention provides a wet room temperature growth process for QDs on a crystalline substrate by a SILAR (successive ionic layer deposition and reaction) method, and also provides inorganic passivation of QDs through the growth of a thin film on top of the dots (barrier material matching or not the one employed for the substrate).
  • SILAR superior ionic layer deposition and reaction
  • the process can be repeated in order to achieve QD layer stacks acting as QD-SLs.
  • Control on QD size in the superlattice can be advantageously achieved by controlling the growth deposition rate (e.g. by controlling soaking time and/or precursor concentrations) of QDs and barrier material spacer.
  • Multiple QD stacks can be prepared with a view to allowing the active material to have strong absorption- emission properties, favourable for optoelectronic applications.
  • the present invention is directed to a process for preparing a quantum dot array comprising at least the steps of:
  • the quantum dots are passivated by the addition of an inorganic shell or film, most preferably of the same nature as the (crystalline semiconductor) substrate surface used in step (a) of the method of claim 1.
  • the present invention relates to a quantum dot array or a quantum dot superlattice structure obtained by the above-mentioned processes.
  • Figure 1 is a schematic diagram showing the growth of an AB compound by a SILAR method.
  • Figure 2 schematically shows the strain induced nucleation of QDs in a bilayer stack as a function of barrier material thickness.
  • Figure 3 schematically shows formation of tandem structures using SILAR growth on a patterned substrate.
  • Figure 4 shows atomic force microscopy (AFM) images of (top left) a TiO 2 bare substrate, (top right) PbS QDs nucleated on TiO 2 after 2 cycles.
  • AFM atomic force microscopy
  • FIG. 1 is a schematic diagram showing the growth of an AB compound by a SILAR method.
  • SILAR cycle refers to (a) A + ion solution dipping; (b) rinsing-removal of A + ions in excess; (c) B " ion solution dipping; (d) rinsing-removal of B " ions in excess.
  • the nucleation of a QD layer by SILAR follows a protocol analogous to that used for the growth of a thin film (differing only in the amount of material deposited).
  • Control of deposition on the substrate surface to achieve only very small particles (quantum dots) can be achieved by controlling deposition rate (as is done in MBE and MOCVD).
  • Control of dipping time and/or precursor concentrations provide means for controlling material deposition. With a relatively slow rate and with adequate lattice mistmatch between the substrate and deposited layer, only dots will nucleate.
  • a SILAR process for deposition onto an amorphous substrate e.g. glass
  • one SILAR cycle is as follows:
  • PbS Lead sulphide
  • chalcogenide materials of groups I— VI, II— VI, III— VI, V-VI, VIII-VI binary and I-III-VI, II-II-VI, II-III-VI, II-VI-VI and II-V-VI ternary chalcogenides and composites e.g. AgS, Sb 2 S 3 , Bi 3 Se 2 , CoS and CdS, PbSe, PbS, ZnS,ZnSe etc. Tellurides may also be used.
  • any semiconducting (crystalline) material can serve as substrate (and barrier material) in the present invention.
  • materials grown by SILAR could also be used as substrate.
  • Preferred materials grown by SILAR would then include the same ones as those indicated in the above list of preferred materials deposited using a SILAR method as quantum dots in the present invention. In effect, it would be of interest to grow the whole QD solid at room temperature (QD and barrier material). Whether or not it is possible to grow QDs onto such a substrate will depend on lattice match constraints.
  • the anion and cation precursor solutions contain anion / cation concentrations in the range of 0.001 M to 0.1 M, and the time of the exposure of the substrate to each solution is between 1 second and 1 minute, the rinsing steps also taking place over the same timeframe, with typical step times being 10 seconds or 20 seconds. Between 10 and 1000 SILAR cycles may appropriately be used. All the SILAR process can be advantageously carried out at room temperature and no external energy is needed for the growth. By repeating the process, carrying out different cycles, a degree of control over the QD size can be achieved. However the dots will be randomly distributed over the substrate surface and their size distribution will be broad. SILAR QDs will be influenced by several parameters during growth like the number of cycles, duration of dipping, post-annealing recipes, etc.
  • the first layer will typically be characterized by a random distribution of dots over unit area and (depending on growth conditions) some degree of heterogeneity as regards sizes - this is difficult to avoid in practice.
  • the second layer in the stack (cf. Figure 2) it is possible to achieve improved homogeneity of QD size by tuning of barrier thickness (only the bigger buried dots will promote a new dot on top, and hence the QD size distribution becomes narrower).
  • barrier thickness only the bigger buried dots will promote a new dot on top, and hence the QD size distribution becomes narrower.
  • templates are used as the starting substrates. These substrate surfaces are covered with surface structures, patterns created by photo/chemical etching or by soft lithographic techniques. This first template layer will create the ordered array of QDs. In successive layers there is no need for a template but particles will grow in patterns with similar mechanisms as mentioned above.
  • a certain thickness for the active material may in some cases be advantageous.
  • a method is provided for preparing a quantum dot superlattice (QD SL) with a narrow QD size distribution.
  • a three-dimensional QD-SL it is envisaged in the present invention to repeat the SILAR process described above as many times as desired to produce a number of stacked QD layers.
  • a QD-barrier layer is appropriately grown on top of the underlying QD array.
  • QD distribution may be controlled based on QD strain-induced growth.
  • inorganic passivation (of QDs) is used, a first layer with a distribution / array of dots being covered, most preferably, with an inorganic layer made of the same material as the substrate.
  • Figure 2 schematically shows the strain induced nucleation of QDs in a bilayer stack as a function of barrier material thickness.
  • WL stands for "wetting layer”.
  • WL wetting layer
  • the other option is that the dots nucleate directly (without the assistance of a WL) - this is called a Volmer -Webber situation.
  • the strain pattern induced by QD of any size from the first layer will trigger the growth of QDs in the second layer (broad QD size distribution).
  • the middle part of the Figure with an intermediate barrier thickness, only the biggest dots from the first layer will trigger the nucleation of dots in the second layer on particular sites (narrow QD size distribution).
  • the strain pattern of dots in the first layer will not affect the nucleation of dots in the second layer (broad QD size distribution).
  • the vertical self-assembling will also serve to electronically couple QD layer stacks, which will be advantageous for the extraction (i.e. in solar cells) or injection (i.e. LEDs) of charges into the lattice.
  • the choice of potential candidate barrier layers is dependent upon lattice matching of QD/barrier.
  • QD/barrier type II band alignments where there is band offset in two materials - hence one charge carrier is localized in one material and the other is localized in the other material) are expected to be beneficial for PV applications where carriers need to be separated and type I (where both charge carriers are localized to the core) band alignment for emission applications (LED and QD lasers).
  • Type I e.g.
  • layer widths of 10 to 100 nanometers are envisaged to be generally appropriate in order to promote ordering in the second layer of QDs. If the device needs only to have one QD layer in the stack, higher thickness may be appropriate.
  • the barrier thickness should be such as to induce strain in the second deposition phase of SILAR of QD material. Exact preferable values of thickness will depend upon QD material type, and lattice properties. However, appropriately the thickness will be tuned until it induces strain suitable to grow QDs in the next SILAR cycle at preferred locations.
  • each flask was equipped with a rubber septum, a long needle piercing the rubber septum immersing its end into the solution.
  • the long needle was connected with silicone tubings to the argon part of a Schlenk line.
  • a shorter needle was used to pierce the septum, inserting it only enough to go through the septum, but not reaching the surface of the liquid.
  • 405 mg of lead nitrate was dissolved in 60 mL oxygen free methanol by 45 min sonication to give a clear solution.
  • One cycle consisted of 20 s immersion into 0.02 mol/L methanolic Pb(NO 3 )2 solution, 30 s immersion into methanol I rinsing bath, 20 s immersion into 0.02 mol/L methanolic Na 2 S solution and 30 s immersion into methanol II rinsing bath.
  • a final 50 s immersion into 60 mL of methanol III was carried out after the completed SILAR process.
  • Table 1 A summary of the immersion times during a SILAR process is available in Table 1 below. The sample was allowed to dry in inert atmosphere. For batch processing multiple samples another 60 mL of oxygen-free methanol were used as wetting bath before the SILAR cycles instead of using the final rinsing bath methanol III.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Photovoltaic Devices (AREA)
  • Led Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

La présente invention concerne un procédé de préparation d'un réseau de points quantiques (QD) comprenant au moins les étapes consistant à : (a) fournir une surface de substrat semi-conducteur cristallin; (b) déposer des points quantiques sur ladite surface de substrat au moyen d'un procédé d'adsorption et de réaction de couches ioniques successives (SILAR). Lesdites étapes peuvent être répétées afin d'obtenir une structure hétératique à points quantiques.
PCT/EP2014/052362 2014-02-06 2014-02-06 Procédé de préparation de réseau de points quantiques et de structure hétératique à points quantiques WO2015117659A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US15/114,267 US9917218B2 (en) 2014-02-06 2014-02-06 Process for preparing quantum dot array and quantum dot superlattice
PCT/EP2014/052362 WO2015117659A1 (fr) 2014-02-06 2014-02-06 Procédé de préparation de réseau de points quantiques et de structure hétératique à points quantiques
JP2016550613A JP6463773B2 (ja) 2014-02-06 2014-02-06 量子ドットアレイ及び量子ドット超格子の作製方法
CN201480074944.1A CN105981149B (zh) 2014-02-06 2014-02-06 量子点阵列和量子点超晶格的制备方法

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PCT/EP2014/052362 WO2015117659A1 (fr) 2014-02-06 2014-02-06 Procédé de préparation de réseau de points quantiques et de structure hétératique à points quantiques

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CN105981149A (zh) 2016-09-28
CN105981149B (zh) 2019-11-29
US20170162733A1 (en) 2017-06-08

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