WO2015096061A1 - Method for testing junction temperature of semiconductor device - Google Patents

Method for testing junction temperature of semiconductor device Download PDF

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Publication number
WO2015096061A1
WO2015096061A1 PCT/CN2013/090423 CN2013090423W WO2015096061A1 WO 2015096061 A1 WO2015096061 A1 WO 2015096061A1 CN 2013090423 W CN2013090423 W CN 2013090423W WO 2015096061 A1 WO2015096061 A1 WO 2015096061A1
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Prior art keywords
semiconductor device
current
junction temperature
tested
test
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PCT/CN2013/090423
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French (fr)
Chinese (zh)
Inventor
朱阳军
董少华
王任卿
陆江
卢烁今
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中国科学院微电子研究所
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Priority to PCT/CN2013/090423 priority Critical patent/WO2015096061A1/en
Publication of WO2015096061A1 publication Critical patent/WO2015096061A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/01—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using semiconducting elements having PN junctions

Definitions

  • the present invention relates to the field of thermal reliability analysis techniques for semiconductor devices, and more particularly to a junction temperature testing method for a semiconductor device.
  • thermal reliability analysis methods for semiconductor devices are mainly classified into optical methods and standard electrical methods.
  • thermal reliability analysis method of the semiconductor device it is easy to cause misjudgment or missed judgment, and the error rate is high.
  • embodiments of the present invention provide a junction temperature testing method for a semiconductor device to improve the accuracy of reliability analysis of a semiconductor device and reduce the error rate of false positives or missed errors.
  • the embodiment of the present invention provides the following technical solutions:
  • a method for testing a junction temperature of a semiconductor device comprising: pre-acquiring a current-voltage curve of the semiconductor device to be tested at different junction temperatures, obtaining the a current-voltage-junction temperature curve cluster of the semiconductor device to be tested;
  • test current I Passing the test current I to the semiconductor device under test to obtain a voltage Vi of the semiconductor device to be tested under different test currents Ii, wherein i has a value range of 0 N;
  • the effective area of the semiconductor device to be tested is A E
  • the current-voltage-junction temperature curve cluster of the semiconductor device to be tested is used to obtain different A Ej according to the test current and the measured voltage of the semiconductor device to be tested.
  • the junction temperature Tji of the semiconductor device to be tested corresponding to Ii/A Ej -Vi, wherein j has a value range of 1 j M;
  • the junction temperature of the effective area A E is obtained; wherein, i, j, M, and N are all positive integers, and ⁇ 1 and N are not less than 2.
  • the current-voltage curve of the semiconductor device to be tested is collected in advance at different junction temperatures, and the current-voltage-junction temperature curve cluster of the semiconductor device to be tested is obtained:
  • the first semiconductor device is placed in a constant temperature environment, and the current-voltage characteristic curve of the first semiconductor device is collected at different temperatures to obtain a current-voltage-junction temperature curve cluster of the first semiconductor device.
  • the method further includes:
  • Tji junction temperature of the semiconductor device under test Ii / A Ej -Vi corresponds comprising:
  • the semiconductor device to be tested According to the test current of the semiconductor device to be tested, Ii/A Ej values under different A Ej are obtained; in the voltage-junction temperature curve corresponding to Ii/A, the junction temperature Tji corresponding to the measured voltage is determined.
  • the semiconductor device to be tested is subjected to a test current I, and Ii is obtained under different test currents.
  • the voltage Vi of the semiconductor device to be tested includes:
  • n 3.
  • obtaining a minimum floating Tj value includes:
  • obtaining a junction temperature of the semiconductor device to be tested includes:
  • the average value of the junction temperatures under the effective area A E is calculated as the junction temperature of the semiconductor device to be tested.
  • a current-voltage curve of the semiconductor device to be tested is collected in different junction temperatures to obtain a current-voltage-junction temperature curve cluster of the semiconductor device to be tested;
  • the semiconductor device is tested with different test currents Ii to obtain a voltage Vi across the semiconductor device to be tested under different test currents Ii, and further assume that the effective area of the semiconductor device to be tested is A E , according to the semiconductor to be tested.
  • the test current and the measured voltage of the device, using the current-voltage-junction temperature curve cluster of the semiconductor device to be tested obtain the junction temperature Tji of the semiconductor device to be tested corresponding to Ii/A Ej -Vi under different AEj .
  • the test method provided by the embodiment of the present invention not only does not perform the cap opening operation on the semiconductor device to be tested, and has no destructiveness and damage to the semiconductor device to be tested, and can also test the test to be tested.
  • junction temperature of the semiconductor device and the effective area corresponding to the junction temperature can reflect the junction temperature of the semiconductor device to be tested and its distribution state, thereby improving the accuracy of the reliability analysis of the semiconductor device to be tested, and reducing the error.
  • FIG. 1 is a flow chart of a method for testing a junction temperature of a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a flow chart of a temperature-sensitive parameter PN junction forward voltage drop V F -high temperature region of a semiconductor device to be tested according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram showing a relationship between an effective area A E of a semiconductor device to be tested and a forward voltage drop of the PN junction according to an embodiment of the present invention
  • Figure 4 is a schematic diagram of a multi-step constant current repetitive pulse test waveform.
  • the optical method is also called infrared thermal imaging.
  • This method requires photographing the chip inside the semiconductor device, so it is necessary to process the semiconductor device specifically for testing.
  • the capping operation is performed by a chemical method (such as acid etching) to expose the chip inside the semiconductor device.
  • the metal packaged semiconductor device the metal cap on the front surface of the semiconductor device needs to be physically removed, so that the semiconductor Device The internal chip is exposed to obtain the thermal distribution of the chip surface inside the semiconductor device by infrared thermal imaging. It is destructive to the finished semiconductor device and is a destructive detection method. Even some semiconductor devices cannot be obtained even after opening the cap. Its heat distribution. Moreover, many reliability problems of semiconductor devices appear on the package.
  • infrared thermal imaging is not suitable as a conventional semiconductor device measurement method.
  • the standard electrical method for decades, has been using the Delta-V method to calculate the junction temperature, that is, using the forward voltage drop of the PN junction in a semiconductor device as a temperature sensitive parameter, and using a single test current to measure a single temperature value,
  • the quasi-average junction temperature of the entire semiconductor device such as the International Electrotechnical Commission's authoritative standard IEC60747-8:2000, the US military standard MIL-STD-750E and the national military standard GJB 128A-97, etc., due to its non-destructive testing of finished semiconductor devices Characteristics are widely adopted as technical standard methods.
  • the basic method for measuring the junction temperature of the IEC standard is: According to the emission junction of the semiconductor device under test
  • the standard electrical method assumes that when the transistor of the semiconductor device under test dissipates power, its junction temperature distribution is uniform and is the same as the temperature of the calibration transistor, that is, the semiconductor device under test and the calibration transistor. The temperature distribution is the same, and the effective area remains 100%, that is, the semiconductor device under test is in the constant temperature region. It should also be noted that when the semiconductor device under test is in In the constant temperature zone and without self-heating, or when stored at room temperature (including room temperature), the overall temperature of the semiconductor device under test is consistent, with a uniform temperature value, and the junction temperature is equal to the constant temperature zone (including room temperature) The temperature at which the standard electrical method measures the junction temperature is scientific and rigorous.
  • the internal electric field distribution is also non-uniform, resulting in carriers (electrons and holes) in the semiconductor device.
  • the distribution is also different, so that there are some differences in the different regions between the semiconductor device, the carriers, and between the carriers and the crystal lattice.
  • the macroscopic representation is the self-heating effect at the heat source of the semiconductor device, that is, the semiconductor device.
  • the temperature distribution throughout the interior is not uniform, especially when it is operated under high pressure. Therefore, in general, the junction temperature distribution of the semiconductor device under test is uneven when the power is dissipated.
  • the quasi-average junction temperature measured by the standard electrical method cannot reflect the peak junction temperature and junction temperature distribution state of the semiconductor device under test, and it is easy to cause misjudgment or missed judgment in reliability screening and assessment. Therefore, research and exploration of a semiconductor device thermal reliability analysis method can not only have the characteristics of non-destructive and non-destructive detection of standard electrical methods, but also have the characteristics of infrared thermal imaging to characterize the temperature distribution of the semiconductor device under test. It is a research that is very scientific and has great practical value and great economic benefits.
  • an embodiment of the present invention provides a junction temperature testing method for a semiconductor device, including:
  • test current I Passing the test current I to the semiconductor device under test to obtain a voltage Vi of the semiconductor device to be tested under different test currents Ii, wherein i has a value range of 0 N;
  • the effective area is provided a semiconductor device under test as A E, measured according to the test current and test voltage of the semiconductor device, obtained at different A Ej, Ii / A Ej -Vi corresponding to the semiconductor device under test
  • the minimum floating Tj value is obtained, and the effective area A corresponding to the Tj value is recorded as the effective area A E of the semiconductor device to be tested;
  • the junction temperature of the effective area A E is obtained; wherein, i, j, M, and N are all positive integers, and ⁇ 1 and N are not less than 2.
  • a current-voltage curve of the semiconductor device to be tested is collected in different junction temperatures to obtain a current-voltage-junction temperature curve cluster of the semiconductor device to be tested;
  • the semiconductor device is tested with different test currents Ii to obtain a voltage Vi across the semiconductor device to be tested under different test currents Ii, and further assume that the effective area of the semiconductor device to be tested is A E , according to the semiconductor to be tested.
  • the test current and the measured voltage of the device, using the current-voltage-junction temperature curve cluster of the semiconductor device to be tested obtain the junction temperature Tji of the semiconductor device to be tested corresponding to Ii/A Ej -Vi under different AEj .
  • the test method provided by the embodiment of the present invention not only does not perform the cap opening operation on the semiconductor device to be tested, and has no destructiveness and damage to the semiconductor device to be tested, and can also test the test to be tested.
  • the junction temperature of the semiconductor device and the effective area corresponding to the junction temperature can reflect the junction temperature of the semiconductor device to be tested and its distribution state, thereby improving the accuracy of the reliability analysis of the semiconductor device to be tested, and reducing the error. The error rate of the judgment or missed judgment.
  • an embodiment of the present invention provides a junction temperature testing method for a semiconductor device, including: Step 1: pre-collecting a current-voltage curve of the semiconductor device to be tested at different junction temperatures, and obtaining the A current-voltage-junction temperature curve cluster of the semiconductor device is measured.
  • step 1 comprises:
  • Step 101 Select the same batch of semiconductor devices fabricated from the same semiconductor material, the same structure, and the same process as the semiconductor device to be tested as the first semiconductor device.
  • Step 102 The first semiconductor device is placed in a constant temperature environment, and a current-voltage characteristic curve of the first semiconductor device is collected at different temperatures to obtain a current-voltage-junction temperature curve cluster of the first semiconductor device. .
  • the current-voltage-junction temperature characteristic curve that is, the current-voltage-junction temperature curve cluster of the first semiconductor device is a current-voltage-junction temperature characteristic curve cluster of the semiconductor device to be tested.
  • the current-voltage-junction temperature characteristic curve provided by the embodiment of the present invention Clusters allow for diversification of the form of junction temperature distribution. Moreover, the data in the current-voltage-junction temperature characteristic curve cluster is highly accurate, the junction temperature can be accurate to o.rc, and the voltage can be accurate to the order of 10 microvolts, thereby making the current-voltage-junction temperature characteristic Curve clusters have a high degree of confidence.
  • step 1 further includes:
  • Step 103 processing a current-voltage-junction temperature curve cluster of the semiconductor device to be tested, and obtaining a current of the semiconductor device to be tested as a parameter, wherein a voltage of the semiconductor device to be tested is an independent variable, and the to-be-tested
  • the junction temperature of a semiconductor device is a function of a strain.
  • Step 2 Pass the test current I to the semiconductor device under test to obtain the voltage Vi of the semiconductor device to be tested under different test currents Ii, where i has a value range of 0 i N. Where i and N are both positive integers and N is not less than 2.
  • N may be 10. It can also be 20 or other values, which are not limited by the present invention, depending on the specific test requirements.
  • the semiconductor device Since the semiconductor device has a small current overheating effect, that is, the semiconductor device has a non-uniform junction temperature distribution, the smaller the test current is used, the more the current is heated, and the more concentrated the current, the higher the current density. The smaller the effective area of the semiconductor device to be tested is.
  • a transistor is formed by connecting m sub-transistors (referred to as sub-tubes) in parallel, and the temperature distribution in each sub-transistor is uniform, but the temperature of each sub-transistor is different, for the semiconductor The device's small current over-temperature effect is verified.
  • the junction voltage drop of each sub-transistor is equal to the junction voltage drop of the transistor, and the sum of the currents of all the sub-transistors is equal to the total current flowing through the transistor. .
  • q is the electron charge
  • n is the injection coefficient
  • K is the Boltzmann constant
  • ⁇ is the sub Transistor junction temperature
  • the PN junction is generally selected as a parasitic pn junction inside each sub-transistor
  • B is the structural factor of the sub-transistor, for the same device
  • B is Changshu
  • ⁇ is A constant greater than three
  • VgO is the forbidden band width of the transistor semiconductor material.
  • equations (2) and (3) can be rewritten as:
  • the ratio of the sum of the area of all the sub-transistors greater than or equal to ⁇ " to the total area of the transistor is referred to as the effective area of the transistor, denoted as A E , which means: when the junction temperature distribution inside the semiconductor device In the case of unevenness, the area through which most (preferably 99%) current flows accounts for the area of the active area of the transistor.
  • the current ie, the test current
  • the current ratio of the region gradually increases, that is, as the test current decreases, the current inside the semiconductor device tends to be more toward the high temperature region.
  • the effective area of the semiconductor device is smaller, and therefore, the effective area A E of the semiconductor device decreases as the forward voltage drop of the PN junction increases.
  • the test current I is as small as possible while meeting the test requirements.
  • the value of the temperature-sensitive parameter at zero time is an indispensable data for measuring the junction temperature of the semiconductor device to be tested, especially the thermal analysis method has high requirements.
  • the measured PN junction source-drain junction
  • the current shutdown has a tailing phenomenon, and the test current is set up for some time. In this short time, the temperature sensitivity parameter value also changes.
  • the thermal spectrum analysis method requires at least two measurement currents. Therefore, when obtaining the zero-time temperature sensitivity parameter, it is preferable to use a multi-step constant current repetition pulse test. Taking the third-order constant current as an example, the test principle waveform is shown in Figure 4. In Figure 4, t. Indicates the moment when the power is cut off, that is, the zero time. Since the measurement data of the same current at different times is required to be fitted or reversed using the mathematical physical method, it is necessary to repeat the pulse of the step constant current to measure the voltage Vi at the time of the semiconductor device to be tested.
  • step 2 includes:
  • Step 201 pass the test current Ii to the semiconductor device to be tested, and measure the voltage Vij of the semiconductor device to be tested at time tj, where j is equal to 1 n in turn, and n is not less than 2;
  • Step 202 For different time tj The measured Vij is fitted to obtain the electric power corresponding to the test current Ii. Press Vi.
  • n is preferably 3.
  • n 3
  • the test moments corresponding to the current are respectively t u , t 21 , t 31
  • the measured temperature-sensitive parameters and time at the corresponding time are polynomial And, that is, the zero-time temperature-sensitive parameter VI corresponding to the current II is obtained, and similarly, the zero-time temperature-sensitive parameter Vi corresponding to the other measured currents is obtained.
  • Step 3 The effective area of the semiconductor device to be tested is A E , and the current-voltage-junction temperature curve cluster of the semiconductor device to be tested is obtained according to the test current and the measured voltage of the semiconductor device to be tested.
  • the junction temperature Tji of the semiconductor device to be tested corresponding to Ii/A Ej -Vi under different A Ej , wherein j has a value range of 1 j M. Where i, j, and M are all positive integers, and M is not less than 2.
  • the current flowing through the barrier of the semiconductor device having a uniform junction temperature distribution of T is I, and the watershed area is A. . If the barrier temperature distribution is no longer uniform at a certain time, to maintain the flow-through temperature as the barrier current in the T effective area A E ( A E A.) is still I, then the watershed area A 0 ⁇
  • the current density inside increases to ⁇ , and the temperature sensitive parameter voltage at this time is equal to the barrier at the same temperature T, /
  • the watershed area is A.
  • the current is the voltage value corresponding to A E .
  • the MQH algorithm will be described below in conjunction with a specific example.
  • the junction temperature distribution is checked, the passing current is I, and the watershed area is A. . If the effective area is reduced to 1/2 of the original and the junction temperature rises to T, the current density in the transistor is increased by a factor of two. If the current through the transistor is still I, then the temperature is sensitive.
  • the parameter voltage is equal to the voltage value of the transistor when the temperature of the transistor is T in the thermostat. Therefore, it is assumed that the effective area of the semiconductor device to be tested is A E .
  • the MQH algorithm, test current Ii is selected as a reference current, the current sequence respectively expressed as hexyl Gou single standard ⁇ ⁇
  • test current of the semiconductor device to be tested Using the corresponding relationship between the test current of the semiconductor device to be tested and its corresponding voltage measured in step 2, first obtain the test current according to the test current 1 1 under the different A Ej : ⁇ corresponding current density value Ii / A Ej Then, in the voltage-junction temperature curve corresponding to Ii/A Ej , the junction temperature Tji corresponding to the measured voltage 1 ⁇ 4 is determined.
  • the measured data is shown in the following table:
  • the product A Ej is recorded as the effective area A E of the semiconductor device to be tested.
  • test current L Since the test current L is small, it has little effect on the thermal effect of the semiconductor device to be tested. Almost negligible, therefore, at different test currents L, the junction temperature of the semiconductor device under test is close to a fixed value. Therefore, after measuring the Tj values of each group, the minimum floating Tj value is selected from each group of Tj values, and the effective area A Ej corresponding to the Tj value is the effective area corresponding to the high temperature region of the semiconductor device to be tested. .
  • obtaining a minimum floating Tj value according to each group of Tj values includes: calculating a variance of Tji in each group of Tj values, obtaining a Tj value having the smallest variance, and recording the minimum floating Tj value.
  • the floating minimum Tj value may be selected from the array of Tj values by other methods, which is not limited by the present invention.
  • Step 5 The junction temperature of each of the effective area A E, to obtain the junction temperature of the semiconductor device under test; effective area A Ej obtained after the semiconductor device under test, based on the effective area A E at each junction temperature, A junction temperature of the semiconductor device to be tested is obtained.
  • step 5 specifically includes: calculating an average value of each junction temperature of the effective area A E as a junction temperature of the semiconductor device to be tested.
  • the test method provided by the embodiment of the present invention not only does not perform the cap opening operation on the semiconductor device to be tested, and has no destructiveness and damage to the semiconductor device to be tested, and can also test the test to be tested.
  • the junction temperature of the semiconductor device and the effective area corresponding to the junction temperature can reflect the junction temperature of the semiconductor device to be tested and its distribution state, thereby improving the accuracy of the reliability analysis of the semiconductor device to be tested, and reducing the error.

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Abstract

A method for testing the junction temperature of a semiconductor device comprises: collecting beforehand the current-voltage curves of the semiconductor device to be tested at different junction temperatures to obtain a current-voltage-junction temperature curve family of the semiconductor device to be tested; applying a test current I to the semiconductor device to be tested to obtain voltages Vi under different test currents Ii; setting the effective area of the semiconductor device to be tested as AE, and on the basis of the test currents and measured voltages of the semiconductor device to be tested, employing the current-voltage-junction temperature curve family to obtain the junction temperatures Tj of the semiconductor device to be tested corresponding to Ii/AEj-Vi under different AEj; selecting the Tj value with the minimal fluctuation from the various groups of Tj values, and taking the effective area AEj corresponding to the Tj value as the effective area AE of the semiconductor device to be tested; and obtaining the junction temperature of the semiconductor device to be tested according to the junction temperatures under the effective area AE. Thus, the precision of the reliability analysis of the semiconductor device to be tested is raised, and the error rate of erroneous judgment or missing judgment is reduced.

Description

一种半导体器件的结温测试方法  Junction temperature test method for semiconductor device
技术领域 本发明涉及半导体器件热可靠性分析技术领域，尤其涉及一种半导体器件 的结温测试方法。 TECHNICAL FIELD The present invention relates to the field of thermal reliability analysis techniques for semiconductor devices, and more particularly to a junction temperature testing method for a semiconductor device.
背景技术 对于半导体器件而言， 特别是大功率半导体器件 （power semiconductor devices ), 不论是研发设计人员还是工程应用人员， 除关心半导体器件的电学 性能外， 更加注重半导体器件的可靠性与使用寿命。 而半导体器件的可靠性包 括很多方面， 其中， 热可靠性问题一直是半导体器件可靠性中最重要且难解决 的问题， 相关的分析与测试技术的发展十分緩慢。 目前半导体器件的热可靠性分析方法主要分大类， 即光学法和标准电学 法。但是， 利用现有技术中半导体器件的热可靠性分析方法判断半导体器件的 热可靠性时， 容易造成误判或漏判， 错误率较高。 BACKGROUND OF THE INVENTION For semiconductor devices, especially power semiconductor devices, both R&D designers and engineering applications, in addition to the electrical performance of semiconductor devices, pay more attention to the reliability and service life of semiconductor devices. The reliability of semiconductor devices includes many aspects. Among them, the thermal reliability problem has always been the most important and difficult problem in the reliability of semiconductor devices. The development of related analysis and testing techniques is very slow. At present, thermal reliability analysis methods for semiconductor devices are mainly classified into optical methods and standard electrical methods. However, when the thermal reliability of the semiconductor device is judged by the thermal reliability analysis method of the semiconductor device in the prior art, it is easy to cause misjudgment or missed judgment, and the error rate is high.
发明内容 为解决上述技术问题，本发明实施例提供了一种半导体器件的结温测试方 法， 以提高半导体器件可靠性分析的精度， 降低误判或漏判的错误率。 为解决上述问题， 本发明实施例提供了如下技术方案： SUMMARY OF THE INVENTION In order to solve the above problems, embodiments of the present invention provide a junction temperature testing method for a semiconductor device to improve the accuracy of reliability analysis of a semiconductor device and reduce the error rate of false positives or missed errors. In order to solve the above problem, the embodiment of the present invention provides the following technical solutions:
一种半导体器件的结温测试方法， 包括： 预先采集不同结温下， 所述待测半导体器件的电流 -电压曲线， 获得所述 待测半导体器件的电流 -电压 -结温曲线簇； A method for testing a junction temperature of a semiconductor device, comprising: pre-acquiring a current-voltage curve of the semiconductor device to be tested at different junction temperatures, obtaining the a current-voltage-junction temperature curve cluster of the semiconductor device to be tested;
给所述待测半导体器件通以测试电流 I, 获得不同测试电流 Ii下， 所述待 测半导体器件的电压 Vi, 其中， i的取值范围为 0 N;  Passing the test current I to the semiconductor device under test to obtain a voltage Vi of the semiconductor device to be tested under different test currents Ii, wherein i has a value range of 0 N;
设所述待测半导体器件的有效面积为 AE, 根据所述待测半导体器件的测 试电流和测得电压， 利用所述待测半导体器件的电流-电压-结温曲线簇， 获得 不同 AEj下， Ii/AEj-Vi所对应的所述待测半导体器件的结温 Tji, 其中， j的取值 范围为 1 j M; The effective area of the semiconductor device to be tested is A E , and the current-voltage-junction temperature curve cluster of the semiconductor device to be tested is used to obtain different A Ej according to the test current and the measured voltage of the semiconductor device to be tested. Next, the junction temperature Tji of the semiconductor device to be tested corresponding to Ii/A Ej -Vi, wherein j has a value range of 1 j M;
从各组 Tj值中选取浮动最小的 Tj值， 并将 Tj值所对应的有效面积 A 记为所述待测半导体器件的有效面积 AE; Selecting the minimum floating Tj value from each group of Tj values, and recording the effective area A corresponding to the Tj value as the effective area A E of the semiconductor device to be tested;
根据该有效面积 AE下各结温， 得到所述待测半导体器件的结温； 其中， i、 j、 M、 N均为正整数， 且^1、 N均不小于 2。 According to the junction temperature of the effective area A E , the junction temperature of the semiconductor device to be tested is obtained; wherein, i, j, M, and N are all positive integers, and ^1 and N are not less than 2.
优选的， 预先采集不同结温下， 所述待测半导体器件的电流 -电压曲线， 获得所述待测半导体器件的电流 -电压 -结温曲线簇包括：  Preferably, the current-voltage curve of the semiconductor device to be tested is collected in advance at different junction temperatures, and the current-voltage-junction temperature curve cluster of the semiconductor device to be tested is obtained:
选取与所述待测半导体器件用相同半导体材料、相同结构和相同工艺制造 的同批次半导体器件为第一半导体器件；  Selecting the same batch of semiconductor devices fabricated from the same semiconductor material, the same structure, and the same process as the semiconductor device to be tested as the first semiconductor device;
将第一半导体器件放在恒温环境中， 采集不同温度下， 所述第一半导体器 件的电流-电压特性曲线， 获得所述第一半导体器件的电流 -电压 -结温曲线簇。  The first semiconductor device is placed in a constant temperature environment, and the current-voltage characteristic curve of the first semiconductor device is collected at different temperatures to obtain a current-voltage-junction temperature curve cluster of the first semiconductor device.
优选的， 还包括：  Preferably, the method further includes:
根据所述待测半导体器件的电流-电压-结温曲线簇， 获得以所述待测半导 体器件电流为参量， 所述待测半导体器件电压为自变量， 所述待测半导体器件 的结温为应变量的函数曲线。  Obtaining, according to the current-voltage-junction temperature curve cluster of the semiconductor device to be tested, a current of the semiconductor device to be tested as a parameter, the voltage of the semiconductor device to be tested is an independent variable, and a junction temperature of the semiconductor device to be tested is The function curve of the dependent variable.
优选的， 根据所述待测半导体器件的测试电流和测得电压， 获得不同入 下， Ii/AEj-Vi所对应的所述待测半导体器件的结温 Tji包括： Preferably, according to the test current and a measured voltage of said semiconductor device under test, to obtain the different, Tji junction temperature of the semiconductor device under test Ii / A Ej -Vi corresponds comprising:
根据所述待测半导体器件的测试电流， 获得不同 AEj下的 Ii/AEj值； 在 Ii/A 对应的电压-结温曲线中， 确定所述测得电压所对应的结温 Tji。 优选的， 给所述待测半导体器件通以测试电流 I, 获得不同测试电流下 Ii, 所述待测半导体器件的电压 Vi包括： According to the test current of the semiconductor device to be tested, Ii/A Ej values under different A Ej are obtained; in the voltage-junction temperature curve corresponding to Ii/A, the junction temperature Tji corresponding to the measured voltage is determined. Preferably, the semiconductor device to be tested is subjected to a test current I, and Ii is obtained under different test currents. The voltage Vi of the semiconductor device to be tested includes:
给所述待测半导体器件通以测试电流 Ii,测量 tj时刻所述待测半导体器件 的电压 Vij , 其中， j依次等于 1 n, 且 n不小于 2; 对不同时刻 tj测得的 Vij进行拟合， 得到测试电流 Ii对应的电压 Vi。  Passing the test current Ii to the semiconductor device to be tested, and measuring the voltage Vij of the semiconductor device to be tested at time tj, wherein j is equal to 1 n in turn, and n is not less than 2; and Vij measured at different time tj is simulated In combination, a voltage Vi corresponding to the test current Ii is obtained.
优选的， n为 3。  Preferably, n is 3.
优选的， 根据各组 Tj值， 获得浮动最小的 Tj值包括：  Preferably, according to each group of Tj values, obtaining a minimum floating Tj value includes:
计算各组 Tj值中 Tji的方差， 获得方差最小的 Tj值， 记为浮动最小的 Tj 值。  Calculate the variance of Tji in each group of Tj values, and obtain the Tj value with the smallest variance, which is recorded as the minimum floating Tj value.
优选的， 根据该有效面积 AE下各结温， 得到所述待测半导体器件的结温 包括： Preferably, according to the junction temperatures of the effective area A E , obtaining a junction temperature of the semiconductor device to be tested includes:
计算该有效面积 AE下各结温的平均值作为所述待测半导体器件的结温。 与现有技术相比， 上述技术方案具有以下优点： The average value of the junction temperatures under the effective area A E is calculated as the junction temperature of the semiconductor device to be tested. Compared with the prior art, the above technical solution has the following advantages:
本发明实施例所提供的技术方案，预先采集不同结温下， 所述待测半导体 器件的电流- 电压曲线， 获得待测半导体器件的电流-电压-结温的曲线簇； 然 后给所述待测半导体器件通以不同的测试电流 Ii, 获得不同测试电流 Ii下， 所 述待测半导体器件两端的电压 Vi, 再假设所述待测半导体器件的有效面积为 AE, 根据所述待测半导体器件的测试电流和测得电压， 利用所述待测半导体 器件的电流-电压-结温曲线簇， 获得不同 AEj下， Ii/AEj-Vi所对应的所述待测 半导体器件的结温 Tji。 According to the technical solution provided by the embodiment of the present invention, a current-voltage curve of the semiconductor device to be tested is collected in different junction temperatures to obtain a current-voltage-junction temperature curve cluster of the semiconductor device to be tested; The semiconductor device is tested with different test currents Ii to obtain a voltage Vi across the semiconductor device to be tested under different test currents Ii, and further assume that the effective area of the semiconductor device to be tested is A E , according to the semiconductor to be tested The test current and the measured voltage of the device, using the current-voltage-junction temperature curve cluster of the semiconductor device to be tested, obtain the junction temperature Tji of the semiconductor device to be tested corresponding to Ii/A Ej -Vi under different AEj .
由于测试电流的电流值很小， 对所述待测半导体器件的热效应影响很小， 故当对所述待测半导体器件通以不同的测试电流 Ii时，其结温的变化较小。所 以， 从各组测试电流测得的 Tj值中选取出浮动最小的一组 Tj值， 这组 Tj值 的平均值认为是实际结温， 该 Tj值所对应的有效面积 AEj记为所述待测半导 体器件的有效面积 AE。 由此可见， 本发明实施例所提供的测试方法， 不仅不用对所述待测半导体 器件进行开帽操作， 对所述待测半导体器件没有破坏性和损伤， 而且还可以测 试出所述待测半导体器件的结温以及该结温所对应的有效面积，即可以反映所 述待测半导体器件的结温及其分布状态，从而提高了所述待测半导体器件可靠 性分析的精度， 降低了误判或漏判的错误率。 附图说明 Since the current value of the test current is small, the thermal effect on the semiconductor device to be tested has little effect, so when the test current Ii is applied to the semiconductor device to be tested, the change in junction temperature is small. Therefore, a set of Tj values with the smallest float is selected from the Tj values measured by the test currents of each group, and the average value of the Tj values is considered to be the actual junction temperature, and the effective area AEj corresponding to the Tj value is recorded as the Measure the effective area AE of the semiconductor device. It can be seen that the test method provided by the embodiment of the present invention not only does not perform the cap opening operation on the semiconductor device to be tested, and has no destructiveness and damage to the semiconductor device to be tested, and can also test the test to be tested. The junction temperature of the semiconductor device and the effective area corresponding to the junction temperature can reflect the junction temperature of the semiconductor device to be tested and its distribution state, thereby improving the accuracy of the reliability analysis of the semiconductor device to be tested, and reducing the error. The error rate of the judgment or missed judgment. DRAWINGS
图 1为本发明实施例所提供的半导体器件结温测试方法的流程图； 图 2为本发明实施例所提供的待测半导体器件的温敏参数 PN结正向压降 VF-高温区 （Th=423.15K ) 与低温区 （1 =381.1510 电流比值之间的曲线关系 示意图； 1 is a flow chart of a method for testing a junction temperature of a semiconductor device according to an embodiment of the present invention; FIG. 2 is a flow chart of a temperature-sensitive parameter PN junction forward voltage drop V F -high temperature region of a semiconductor device to be tested according to an embodiment of the present invention; Schematic diagram of the relationship between T h =423.15K) and the low temperature region (1 = 381.1510 current ratio;
图 3为本发明实施例所提供的待测半导体器件的有效面积 AE与所述 PN 结正向压降之间的曲线关系示意图； 3 is a schematic diagram showing a relationship between an effective area A E of a semiconductor device to be tested and a forward voltage drop of the PN junction according to an embodiment of the present invention;
图 4为多阶梯恒流重复脉冲测试波形示意图。 具体实施方式 正如背景技术部分所述，利用现有技术中半导体器件的热可靠性分析方法 判断半导体器件的热可靠性时， 容易造成误判或漏判， 错误率较高。  Figure 4 is a schematic diagram of a multi-step constant current repetitive pulse test waveform. BEST MODE FOR CARRYING OUT THE INVENTION As described in the background section, when the thermal reliability of a semiconductor device is judged by the thermal reliability analysis method of the semiconductor device of the prior art, it is easy to cause misjudgment or missed judgment, and the error rate is high.
发明人研究发现， 光学法又称红外热成像法， 这种测试方法需要对半导体 器件内部的芯片进行拍照， 故需要专门对半导体器件进行加工后才能进行测 试， 例如对于塑料封装的半导体器件， 需要使用化学的方法（如酸腐蚀）对其 进行开帽操作，使得半导体器件内部的芯片棵露出来，对于金属封装的半导体 器件， 需要将半导体器件正面的金属盖板通过物理方法取掉，使得半导体器件 内部的芯片棵露出来，才能利用红外热成像法获取半导体器件内部芯片表面的 热分布， 对于成品半导体器件具有破坏性， 属于破坏性检测手段， 甚至有些半 导体器件即使对其开帽后也无法获取其热分布。 而且， 半导体器件的可靠性问 题很多是出现在封装上，当被测半导体器件的可靠性问题是由封装的原因引起 时， 则开帽后测得的测试结果不足以说明问题，会对实际存在的可靠性问题造 成误判或者漏判，因此，红外热成像法不适合作为常规的半导体器件测量方法。 The inventor has found that the optical method is also called infrared thermal imaging. This method requires photographing the chip inside the semiconductor device, so it is necessary to process the semiconductor device specifically for testing. For example, for a plastic packaged semiconductor device, The capping operation is performed by a chemical method (such as acid etching) to expose the chip inside the semiconductor device. For the metal packaged semiconductor device, the metal cap on the front surface of the semiconductor device needs to be physically removed, so that the semiconductor Device The internal chip is exposed to obtain the thermal distribution of the chip surface inside the semiconductor device by infrared thermal imaging. It is destructive to the finished semiconductor device and is a destructive detection method. Even some semiconductor devices cannot be obtained even after opening the cap. Its heat distribution. Moreover, many reliability problems of semiconductor devices appear on the package. When the reliability problem of the semiconductor device under test is caused by the cause of the package, the test result measured after opening the cap is insufficient to explain the problem and will actually exist. The reliability problem causes misjudgment or missed judgment. Therefore, infrared thermal imaging is not suitable as a conventional semiconductor device measurement method.
而标准电学法， 几十年来一直都是使用 Delta-V法计算结温， 即采用半导 体器件中 PN结的正向压降作为温敏参数， 并且使用单一的测试电流测量出单 一的温度值，作为整个半导体器件的准平均结温，如国际电工委员会的权威标 准 IEC60747-8:2000, 美军标 MIL-STD-750E以及国军标 GJB 128A-97等等， 由于其对成品半导体器件的无损测试特性， 被广泛采用为技术标准方法。  The standard electrical method, for decades, has been using the Delta-V method to calculate the junction temperature, that is, using the forward voltage drop of the PN junction in a semiconductor device as a temperature sensitive parameter, and using a single test current to measure a single temperature value, As the quasi-average junction temperature of the entire semiconductor device, such as the International Electrotechnical Commission's authoritative standard IEC60747-8:2000, the US military standard MIL-STD-750E and the national military standard GJB 128A-97, etc., due to its non-destructive testing of finished semiconductor devices Characteristics are widely adopted as technical standard methods.
具体的， IEC标准测量结温的基本方法是： 根据被测半导体器件的发射结 Specifically, the basic method for measuring the junction temperature of the IEC standard is: According to the emission junction of the semiconductor device under test
(或集电结 )在恒定测量电流 /m时的温敏参数的温度特性，在对被测半导体器 件进行通电自加热的测试中，规定有一个特定的小于加热电流的测量电流， 测 量温敏参数 α在加热前后的变化量 , 然后用温敏参数 α在加热前后的变化 量 去除以温敏参数 α , 计算出集电结的结温变化 Δη , 最后再加上加热前集 电结的初始温服 Γ。， 即可得到被测半导体器件的准平均结温 7；, 即 (Or collector junction) at a constant measuring current / m, the temperature characteristics of the temperature-sensitive parameters, there is less than a specific heating current to measure the current in a semiconductor device under test is energized self-heating, the predetermined, measurement temperature sensitive The amount of change of the parameter α before and after heating, and then the temperature-sensitive parameter α is removed by the temperature-sensitive parameter α before and after heating, and the junction temperature change Δη of the collector junction is calculated, and finally the initial of the collector node before heating is added. Warm clothes. , to obtain the quasi-average junction temperature of the semiconductor device under test 7;
AV  AV
τ - AT + T - ~— + T  τ - AT + T - ~- + T
a  a
需要说明的是，标准电学法假设：当被测半导体器件的晶体管耗散功率时， 其结温分布是均匀的， 并且和校准晶体管的温度相同， 即所述被测半导体器件 与所述校准晶体管的温度分布相同， 且有效面积保持 100%不变， 也即相当于 所述被测半导体器件处于恒温区内。还需要说明的是， 当被测半导体器件处于 恒温区中且自身没有通电自加热的情况下，或者在常温（包括室温）下储存时， 被测半导体器件整体温度均勾一致， 具有一个统一的温度值， 其结温等于恒温 区（包括室温）的温度， 此时， 标准电学方法所测量的结温的物理意义是科学 的、 严格的。 但是， 由于半导体器件内部各处的掺杂浓度是不均匀的，且半导体器件在 耗散功率时，其内部的电场分布也是不均匀的，导致半导体器件内部载流子（电 子和空穴）的分布也不相同， 从而使得半导体器件内部， 载流子之间、 载流子 和晶格之间热交换时， 不同区域存在一些差异，宏观上表现为半导体器件热源 处的自热效应， 即半导体器件内部各处的温度分布不均匀，特别是被施加高压 下工作时， 这种现象更为明显， 因此， 一般情况下， 被测半导体器件在耗散功 率时， 其结温分布都是不均匀的，从而导致标准电学法测得的准平均结温无法 反应被测半导体器件的峰值结温和结温分布状态，在可靠性筛选和考核时容易 造成误判或者漏判的情况。 因此，研究探索一种的半导体器件热可靠性的分析方法， 可以既具有标准 电学法的非破坏性和无损伤探测的特点，又具有红外热成像法能够表征被测半 导体器件温度分布的特点，是非常有科学意义且具有极大实用价值及巨大经济 效益的一项研究。 It should be noted that the standard electrical method assumes that when the transistor of the semiconductor device under test dissipates power, its junction temperature distribution is uniform and is the same as the temperature of the calibration transistor, that is, the semiconductor device under test and the calibration transistor. The temperature distribution is the same, and the effective area remains 100%, that is, the semiconductor device under test is in the constant temperature region. It should also be noted that when the semiconductor device under test is in In the constant temperature zone and without self-heating, or when stored at room temperature (including room temperature), the overall temperature of the semiconductor device under test is consistent, with a uniform temperature value, and the junction temperature is equal to the constant temperature zone (including room temperature) The temperature at which the standard electrical method measures the junction temperature is scientific and rigorous. However, since the doping concentration throughout the semiconductor device is not uniform, and the semiconductor device is dissipating power, the internal electric field distribution is also non-uniform, resulting in carriers (electrons and holes) in the semiconductor device. The distribution is also different, so that there are some differences in the different regions between the semiconductor device, the carriers, and between the carriers and the crystal lattice. The macroscopic representation is the self-heating effect at the heat source of the semiconductor device, that is, the semiconductor device. The temperature distribution throughout the interior is not uniform, especially when it is operated under high pressure. Therefore, in general, the junction temperature distribution of the semiconductor device under test is uneven when the power is dissipated. Therefore, the quasi-average junction temperature measured by the standard electrical method cannot reflect the peak junction temperature and junction temperature distribution state of the semiconductor device under test, and it is easy to cause misjudgment or missed judgment in reliability screening and assessment. Therefore, research and exploration of a semiconductor device thermal reliability analysis method can not only have the characteristics of non-destructive and non-destructive detection of standard electrical methods, but also have the characteristics of infrared thermal imaging to characterize the temperature distribution of the semiconductor device under test. It is a research that is very scientific and has great practical value and great economic benefits.
基于上述研究的基石出上，本发明实施例提供了一种半导体器件的结温测试 方法， 包括：  Based on the above research, an embodiment of the present invention provides a junction temperature testing method for a semiconductor device, including:
预先采集不同结温下， 所述待测半导体器件的电流 -电压曲线， 获得所述 待测半导体器件的电流 -电压 -结温曲线簇；  Collecting a current-voltage curve of the semiconductor device to be tested at different junction temperatures to obtain a current-voltage-junction temperature curve cluster of the semiconductor device to be tested;
给所述待测半导体器件通以测试电流 I, 获得不同测试电流 Ii下， 所述待 测半导体器件的电压 Vi, 其中， i的取值范围为 0 N; 设所述待测半导体器件的有效面积为 AE, 根据所述待测半导体器件的测 试电流和测得电压， 获得不同 AEj下， Ii/AEj-Vi所对应的所述待测半导体器件 的结温 Tji, 其中， j的取值范围为 l j M; Passing the test current I to the semiconductor device under test to obtain a voltage Vi of the semiconductor device to be tested under different test currents Ii, wherein i has a value range of 0 N; The effective area is provided a semiconductor device under test as A E, measured according to the test current and test voltage of the semiconductor device, obtained at different A Ej, Ii / A Ej -Vi corresponding to the semiconductor device under test The junction temperature Tji, where j has a value range of lj M;
根据各组 Tj值， 获得浮动最小的 Tj值， 并将 Tj值所对应的有效面积 A 记为所述待测半导体器件的有效面积 AE; According to the Tj value of each group, the minimum floating Tj value is obtained, and the effective area A corresponding to the Tj value is recorded as the effective area A E of the semiconductor device to be tested;
根据该有效面积 AE下各结温， 得到所述待测半导体器件的结温； 其中， i、 j、 M、 N均为正整数， 且^1、 N均不小于 2。 According to the junction temperature of the effective area A E , the junction temperature of the semiconductor device to be tested is obtained; wherein, i, j, M, and N are all positive integers, and ^1 and N are not less than 2.
本发明实施例所提供的技术方案，预先采集不同结温下， 所述待测半导体 器件的电流- 电压曲线， 获得待测半导体器件的电流-电压-结温的曲线簇； 然 后给所述待测半导体器件通以不同的测试电流 Ii, 获得不同测试电流 Ii下， 所 述待测半导体器件两端的电压 Vi, 再假设所述待测半导体器件的有效面积为 AE, 根据所述待测半导体器件的测试电流和测得电压， 利用所述待测半导体 器件的电流-电压-结温曲线簇， 获得不同 AEj下， Ii/AEj-Vi所对应的所述待测 半导体器件的结温 Tji。 According to the technical solution provided by the embodiment of the present invention, a current-voltage curve of the semiconductor device to be tested is collected in different junction temperatures to obtain a current-voltage-junction temperature curve cluster of the semiconductor device to be tested; The semiconductor device is tested with different test currents Ii to obtain a voltage Vi across the semiconductor device to be tested under different test currents Ii, and further assume that the effective area of the semiconductor device to be tested is A E , according to the semiconductor to be tested The test current and the measured voltage of the device, using the current-voltage-junction temperature curve cluster of the semiconductor device to be tested, obtain the junction temperature Tji of the semiconductor device to be tested corresponding to Ii/A Ej -Vi under different AEj .
由于测试电流的电流值很小， 对所述待测半导体器件的热效应影响很小， 故当对所述待测半导体器件通以不同的测试电流 Ii时，其结温的变化较小。所 以， 从各组测试电流测得的 Tj值中选取出浮动最小的一组 Tj值， 这组 Tj值 的平均值认为是实际结温， 该 Tj值所对应的有效面积 AEj记为所述待测半导 体器件的有效面积 AE。 由此可见， 本发明实施例所提供的测试方法， 不仅不用对所述待测半导体 器件进行开帽操作， 对所述待测半导体器件没有破坏性和损伤， 而且还可以测 试出所述待测半导体器件的结温以及该结温所对应的有效面积，即可以反映所 述待测半导体器件的结温及其分布状态，从而提高了所述待测半导体器件可靠 性分析的精度， 降低了误判或漏判的错误率。 为使本发明的上述目的、特征和优点能够更为明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。下面以所述待测半导体器件为 MOSFET 器件为例对本发明实施例所提供的半导体器件的结温测试方法进行详细描述， 但本发明所提供的测试方法并不仅限于 MOSFET器件。 Since the current value of the test current is small, the thermal effect on the semiconductor device to be tested has little effect, so when the test current Ii is applied to the semiconductor device to be tested, the change in junction temperature is small. Therefore, a set of Tj values with the smallest float is selected from the Tj values measured by the test currents of each group, and the average value of the Tj values is considered to be the actual junction temperature, and the effective area AEj corresponding to the Tj value is recorded as the Measure the effective area AE of the semiconductor device. It can be seen that the test method provided by the embodiment of the present invention not only does not perform the cap opening operation on the semiconductor device to be tested, and has no destructiveness and damage to the semiconductor device to be tested, and can also test the test to be tested. The junction temperature of the semiconductor device and the effective area corresponding to the junction temperature can reflect the junction temperature of the semiconductor device to be tested and its distribution state, thereby improving the accuracy of the reliability analysis of the semiconductor device to be tested, and reducing the error. The error rate of the judgment or missed judgment. The above described objects, features, and advantages of the present invention will be more apparent from the aspects of the invention. The method for testing the junction temperature of the semiconductor device provided by the embodiment of the present invention is described in detail below by taking the semiconductor device to be tested as a MOSFET device as an example. However, the test method provided by the present invention is not limited to the MOSFET device.
在以下描述中阐述了具体细节以便于充分理解本发明。但是本发明能够以 多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明 内涵的情况下做类似推广。 因此本发明不受下面公开的具体实施的限制。  Specific details are set forth in the following description in order to provide a thorough understanding of the invention. However, the present invention can be implemented in a variety of other ways than those described herein, and those skilled in the art can make similar promotion without departing from the spirit of the invention. The invention is therefore not limited by the specific embodiments disclosed below.
如图 1所示，本发明实施例提供了一种半导体器件的结温测试方法，包括： 步骤 1 : 预先采集不同结温下， 所述待测半导体器件的电流 -电压曲线， 获 得所述待测半导体器件的电流 -电压 -结温曲线簇。 As shown in FIG. 1 , an embodiment of the present invention provides a junction temperature testing method for a semiconductor device, including: Step 1: pre-collecting a current-voltage curve of the semiconductor device to be tested at different junction temperatures, and obtaining the A current-voltage-junction temperature curve cluster of the semiconductor device is measured.
在本发明的一个实施例中， 步骤 1包括：  In an embodiment of the invention, step 1 comprises:
步骤 101 : 选取与所述待测半导体器件用相同半导体材料、 相同结构和相 同工艺制造的同批次半导体器件为第一半导体器件。  Step 101: Select the same batch of semiconductor devices fabricated from the same semiconductor material, the same structure, and the same process as the semiconductor device to be tested as the first semiconductor device.
步骤 102: 将所述第一半导体器件放在恒温环境中， 采集不同温度下， 所 述第一半导体器件的电流-电压特性曲线， 获得所述第一半导体器件的电流-电 压-结温曲线簇。  Step 102: The first semiconductor device is placed in a constant temperature environment, and a current-voltage characteristic curve of the first semiconductor device is collected at different temperatures to obtain a current-voltage-junction temperature curve cluster of the first semiconductor device. .
由于所述第一半导体器件与所述待测半导体器件为用相同半导体材料、相 同结构和相同工艺制造的同批半导体器件， 因此， 所述待测半导体器件与所述 第一半导体器件具有相同的电流-电压-结温特性曲线， 即所述第一半导体器件 的电流 -电压 -结温曲线簇即为所述待测半导体器件的电流-电压-结温特性曲线 簇。  Since the first semiconductor device and the semiconductor device to be tested are the same batch of semiconductor devices fabricated by the same semiconductor material, the same structure, and the same process, the semiconductor device to be tested has the same same as the first semiconductor device. The current-voltage-junction temperature characteristic curve, that is, the current-voltage-junction temperature curve cluster of the first semiconductor device is a current-voltage-junction temperature characteristic curve cluster of the semiconductor device to be tested.
结温任何分布的微分元， 原理上都可以从所述电流-电压-结温特性曲线簇 中找到一个对应的点， 因此， 本发明实施例所提供的电流-电压-结温特性曲线 簇允许结温分布形式的多样化。 而且， 所述电流-电压-结温特性曲线簇中的数 据精度很高， 结温可以精确到 o.rc , 电压可以精确到 10微伏量级， 从而使得 所述电流-电压-结温特性曲线簇具有较高的可信度。 Any distribution of differential junction temperature, in principle, can find a corresponding point from the current-voltage-junction temperature characteristic curve cluster. Therefore, the current-voltage-junction temperature characteristic curve provided by the embodiment of the present invention Clusters allow for diversification of the form of junction temperature distribution. Moreover, the data in the current-voltage-junction temperature characteristic curve cluster is highly accurate, the junction temperature can be accurate to o.rc, and the voltage can be accurate to the order of 10 microvolts, thereby making the current-voltage-junction temperature characteristic Curve clusters have a high degree of confidence.
在本发明的另一个实施例中， 步骤 1还包括：  In another embodiment of the present invention, step 1 further includes:
步骤 103: 对所述待测半导体器件的电流-电压-结温曲线簇进行处理， 获 得以所述待测半导体器件电流为参量， 所述待测半导体器件的电压为自变量， 所述待测半导体器件的结温为应变量的函数曲线。  Step 103: processing a current-voltage-junction temperature curve cluster of the semiconductor device to be tested, and obtaining a current of the semiconductor device to be tested as a parameter, wherein a voltage of the semiconductor device to be tested is an independent variable, and the to-be-tested The junction temperature of a semiconductor device is a function of a strain.
步骤 2: 给所述待测半导体器件通以测试电流 I, 获得不同测试电流 Ii下， 所述待测半导体器件的电压 Vi, 其中， i的取值范围为 0 i N。 其中， i、 N 均为正整数， 且 N不小于 2。  Step 2: Pass the test current I to the semiconductor device under test to obtain the voltage Vi of the semiconductor device to be tested under different test currents Ii, where i has a value range of 0 i N. Where i and N are both positive integers and N is not less than 2.
需要说明的是， 为了提高所述测试结果的准确性， N越大越好， 但为了降 低数据统计的计算量， N越小越好， 故在本发明的一个实施例中， N 可以为 10, 也可以为 20或其他数值， 本发明对此并不做限定， 视具体的测试需求而 定。  It should be noted that, in order to improve the accuracy of the test result, the larger the N, the better, but in order to reduce the calculation amount of the data statistics, the smaller the N, the better, so in one embodiment of the present invention, N may be 10. It can also be 20 or other values, which are not limited by the present invention, depending on the specific test requirements.
由于半导体器件具有小电流过趋热效应，即所述半导体器件在结温分布不 均匀的情况下， 使用的测试电流越小， 电流的趋热性越明显， 电流越集中， 电 流密度越大， 所述待测半导体器件的有效面积越小。  Since the semiconductor device has a small current overheating effect, that is, the semiconductor device has a non-uniform junction temperature distribution, the smaller the test current is used, the more the current is heated, and the more concentrated the current, the higher the current density. The smaller the effective area of the semiconductor device to be tested is.
下面以晶体管并联模型为例， 即一个晶体管由 m个子晶体管（简称子管） 并联而成，每个子晶体管内的温度分布都是均匀的，但各个子晶体管的温度各 不相同， 对所述半导体器件的小电流过趋热效应进行验证。  Taking the transistor parallel model as an example, a transistor is formed by connecting m sub-transistors (referred to as sub-tubes) in parallel, and the temperature distribution in each sub-transistor is uniform, but the temperature of each sub-transistor is different, for the semiconductor The device's small current over-temperature effect is verified.
由于所述晶体管在工作时， m个子晶体管是并联的，那么每个子晶体管的 结压降均等于所述晶体管的结压降，而所有子晶体管的电流之和等于流经所述 晶体管的总电流。  Since the m sub-transistors are in parallel when the transistor is in operation, the junction voltage drop of each sub-transistor is equal to the junction voltage drop of the transistor, and the sum of the currents of all the sub-transistors is equal to the total current flowing through the transistor. .
任选两个子晶体管， 设它们的温度分别为 Th和 Tl 其中
Figure imgf000011_0001
T 根据肖 克莱（shockley ) 方程： 9 。 gVF Optional two sub-transistors, set their temperatures to T h and T l respectively
Figure imgf000011_0001
T according to the Shockley equation: 9 . gV F
JF = BTre nKT {enKT -1) J F = BT r e nKT {e nKT -1)
( 1 ) 得到流过这两个子晶体管的电流密度分别为：  (1) The current densities flowing through the two sub-transistors are:
J Th) = sh(e"KTh -l) = BT e-^(e"KT^— 1) (2) JT h ) = sh (e" KTh -l) = BT e-^(e" KT ^— 1) (2)
JFi(7i) = Jsl(e"KTl — 1) = BT{ re-^{enKTi 其中， q为电子电荷， n为注入系数， K为玻尔兹曼常熟， Τ为所述子晶 体管 ΡΝ结温度，对于 MOSFET器件来说， 所述 PN结一般选取的是各子晶体 管内部寄生的 pn结， B为所述子晶体管的结构因子， 对于同一器件来说， B 为常熟， γ为一个大于 3的常数， VgO为所述晶体管半导体材料的禁带宽度。 J Fi (7i) = J sl (e" KTl — 1) = BT { r e-^{e nKTi where q is the electron charge, n is the injection coefficient, K is the Boltzmann constant, and Τ is the sub Transistor junction temperature, for MOSFET devices, the PN junction is generally selected as a parasitic pn junction inside each sub-transistor, B is the structural factor of the sub-transistor, for the same device, B is Changshu, γ is A constant greater than three, VgO is the forbidden band width of the transistor semiconductor material.
在温度不是很高的情况下， 反向漏电可以忽略不计， 则 （2)式和（3)式 可以改写为：  In the case where the temperature is not very high, the reverse leakage is negligible, then equations (2) and (3) can be rewritten as:
(4)
Figure imgf000012_0001
根据（4) 式和（5) 式可得流过高温子晶体管 Th和低温子晶体管 T的电 流密度的比值为： (4)
Figure imgf000012_0001
The ratio of the current densities flowing through the high temperature sub-transistor T h and the low-temperature sub-transistor T according to equations (4) and (5) is:
Figure imgf000012_0002
(6)。 丄―丄
Figure imgf000012_0002
(6).丄―丄
由于式（6) 中 V <VgO,
Figure imgf000012_0003
J τh 由 （6) 式可见， 随着 VF的减小,
Figure imgf000012_0004
增大， 因而 ( 而 vF的减小意味着 流经所述晶体管的总电流 IF减小， 即随着测试电流 ¾的减小， 流经高温子晶 体管 Th的电流密度和流经低温子晶体管 τ 的电流密度的比值是成指数增大 的， 也即所述晶体管内部测试电流的分布更加不均匀。 Since V <VgO in equation (6),
Figure imgf000012_0003
J τh is seen by (6), as V F decreases,
Figure imgf000012_0004
Increase, thus (and the decrease in v F means The total current I F flowing through the transistor decreases, i.e., as the decrease in the test current ¾ of high temperature flowing through the transistor current density ratio of the current density flowing through the low temperature of the transistor T h τ is increased exponentially That is, the distribution of the test current inside the transistor is more uneven.
下面继续以晶体管为例， 对有效面积 AE的概念进行介绍。 选取 100只子 晶体管， 温度从 443.15K开始降温， 每次测量降低 1K。 设有一个子晶体管的 温度为 η ,所有大于或等于这个温度的子晶体管的电流之和与总电流的比值记 为 ^ 则结合式（5 ) 可以得到： Let's continue with the transistor as an example to introduce the concept of effective area A E . Select 100 sub-transistors, the temperature starts to cool down from 443.15K, and each measurement is reduced by 1K. The temperature of a sub-transistor is η, and the ratio of the sum of the currents of the sub-transistors greater than or equal to this temperature to the total current is recorded as ^, then the combination of equations (5) can be obtained:
Figure imgf000013_0001
Figure imgf000013_0001
当/ r =99%时表明 99%的电流都在结温高于或等于 Tj的子晶体管内流过， 而结温低于 Tj的子晶体管所流过的电流只占总电流的 1%, 可以忽略。 这样就 把所有大于或等于 τ」的子晶体管的面积之和与所述晶体管的总面积的比值称 为所述晶体管的有效面积， 记为 AE, 其意义为： 当半导体器件内部结温分布 不均匀时， 绝大多数（优选为 99% )的电流流过的面积占所述晶体管有源区面 积、的比例。 When / r =99%, it means that 99% of the current flows in the sub-transistor whose junction temperature is higher than or equal to Tj, and the current flowing through the sub-transistor whose junction temperature is lower than Tj accounts for only 1% of the total current. can be omitted. Thus, the ratio of the sum of the area of all the sub-transistors greater than or equal to τ" to the total area of the transistor is referred to as the effective area of the transistor, denoted as A E , which means: when the junction temperature distribution inside the semiconductor device In the case of unevenness, the area through which most (preferably 99%) current flows accounts for the area of the active area of the transistor.
以上从理论上证明了： 随着测试电流的减小， 所述半导体器件内部的电流 会更加趋向高温区。 下面结合实验数据进行验证。  The above theoretically proves that as the test current decreases, the current inside the semiconductor device tends to be more toward the high temperature region. The following is combined with experimental data for verification.
如图 2 所示， 图 2 中示出了温敏参数 PN 结正向压降 VF-高温区 ( Th=423.15K )与低温区 （丁尸381.1510 电流比值之间的曲线关系， 其中， 横 坐标表示所述晶体管温敏参数 PN 结正向压降 VF , 纵坐标表示高温区 ( Th=423.15K )与低温区 （T尸 381.15K ) 的电流比值。 从图 2中可以看出， 随 着温敏参数 PN结正向压降 V 增大， 纵坐标表示高温区 （Th=423.15K )与 低温区 (丁尸381.15K ) 的电流比值逐渐减小， 而流经 PN结的电流 (即测试电 流）与 PN结的正向压降成正比， 因此， 随着测试电流的减小， 高温区与低温 区的电流比值逐渐增大， 即随着测试电流的减小， 所述半导体器件内部的电流 会更加趋向高温区。 而所述半导体器件内部的电流越趋向高温区， 所述半导体 器件的有效面积越小， 因此， 所述半导体器件的有效面积 AE随着所述 PN结 正向压降的增大而减小， 如图 3所示。 As shown in Figure 2, Figure 2 shows the relationship between the temperature-sensitive parameter PN junction forward voltage drop V F - high temperature region ( T h = 423.15K ) and the low temperature region ( Ding dynasty 381.1510 current ratio value, where The abscissa indicates the forward voltage drop V F of the PN junction of the transistor temperature sensitive parameter, and the ordinate indicates the current ratio of the high temperature region (T h = 423.15K ) to the low temperature region (T 381.15K ). As can be seen from Figure 2 As the temperature-sensitive parameter PN junction forward voltage drop V increases, the ordinate indicates that the current ratio between the high temperature region (T h = 423.15K) and the low temperature region (Ding 381.15K) gradually decreases, while flowing through the PN junction The current (ie, the test current) is proportional to the forward voltage drop of the PN junction, so as the test current decreases, the high temperature region and low temperature The current ratio of the region gradually increases, that is, as the test current decreases, the current inside the semiconductor device tends to be more toward the high temperature region. Whereas the current inside the semiconductor device tends to a high temperature region, the effective area of the semiconductor device is smaller, and therefore, the effective area A E of the semiconductor device decreases as the forward voltage drop of the PN junction increases. , As shown in Figure 3.
由此可见， 随着测试电流的减小， 高温区与低温区的电流比值逐渐增大， 所述半导体器件内部的电流会更加趋向高温区， 所述半导体器件的有效面积 AE越小。 It can be seen that as the test current decreases, the current ratio between the high temperature region and the low temperature region gradually increases, and the current inside the semiconductor device tends to be higher toward the high temperature region, and the effective area A E of the semiconductor device is smaller.
因此， 在本发明的一个优选实施例中， 所述测试电流 I在满足测试要求的 前提下越小越好。  Therefore, in a preferred embodiment of the invention, the test current I is as small as possible while meeting the test requirements.
需要说明的是，零时刻温敏参数的值是测量待测半导体器件结温必不可少 的数据，尤其是热普分析法对其有较高的要求。一般半导体器件在施加功率时， 被测 PN结（源漏结）一直反偏， 所以断掉功率后理论上无需延迟， 越快测量 越好。 但是， 对于 MOSFET器件， 其电流的关断存在拖尾现象， 测试电流的 建立也需要一些时间， 而在这很短的时间里， 温敏参数值也会有变化。  It should be noted that the value of the temperature-sensitive parameter at zero time is an indispensable data for measuring the junction temperature of the semiconductor device to be tested, especially the thermal analysis method has high requirements. Generally, when a semiconductor device is applied with power, the measured PN junction (source-drain junction) is always reverse biased, so theoretically no delay is required after the power is turned off, and the faster the measurement, the better. However, for MOSFET devices, the current shutdown has a tailing phenomenon, and the test current is set up for some time. In this short time, the temperature sensitivity parameter value also changes.
而且， 热谱分析方法要求至少有两个以上的测量电流， 因此， 在获取零时 刻温敏参数的时候， 优选采用多阶梯恒流重复脉冲测试。 以 3阶恒流为例， 测 试原理波形如图 4所示。 图 4中 t。表示断掉功率的时刻， 即零时刻。 由于需要 同一电流在不同时刻的测量数据才可以使用数学物理方法进行拟合或者反推， 因此， 需要对阶梯恒流进行重复脉冲， 以测得所述待测半导体器件零时刻的电 压 Vi。  Moreover, the thermal spectrum analysis method requires at least two measurement currents. Therefore, when obtaining the zero-time temperature sensitivity parameter, it is preferable to use a multi-step constant current repetition pulse test. Taking the third-order constant current as an example, the test principle waveform is shown in Figure 4. In Figure 4, t. Indicates the moment when the power is cut off, that is, the zero time. Since the measurement data of the same current at different times is required to be fitted or reversed using the mathematical physical method, it is necessary to repeat the pulse of the step constant current to measure the voltage Vi at the time of the semiconductor device to be tested.
故， 当所述待测半导体器件为 MOSFET器件时， 在本发明的一个实施例 中， 步骤 2包括：  Therefore, when the semiconductor device to be tested is a MOSFET device, in an embodiment of the present invention, step 2 includes:
步骤 201 : 给所述待测半导体器件通以测试电流 Ii, 测量 tj时刻所述待测 半导体器件的电压 Vij , 其中， j依次等于 1 n, 且 n不小于 2; 步骤 202: 对不同时刻 tj测得的 Vij进行拟合， 得到测试电流 Ii对应的电 压 Vi。 Step 201: pass the test current Ii to the semiconductor device to be tested, and measure the voltage Vij of the semiconductor device to be tested at time tj, where j is equal to 1 n in turn, and n is not less than 2; Step 202: For different time tj The measured Vij is fitted to obtain the electric power corresponding to the test current Ii. Press Vi.
还需要说明的是， 重复脉冲的次数既不是越多越好也不是越少越好，如果 重复脉冲的次数过多，会导致由于降温太多而偏离零时刻太远，如果重复脉冲 的次数过少， 会由于拟合数据过少， 而对拟合函数的精度和结果造成影响。 在 本发明的一个实施例中， n优选为 3。  It should also be noted that the number of repetitions of the pulse is neither as high as possible, nor as little as possible. If the number of repetitions of the pulse is too large, it will cause too much deviation from zero due to too much temperature drop. Less, because of too little fitting data, it affects the accuracy and results of the fitting function. In one embodiment of the invention, n is preferably 3.
当 n为 3时，对于图 4中重复脉冲下的阶梯恒流测量， 电流 对应的测试 时刻分别是 tu、 t21、 t31 ,将测得的对应时刻的温敏参数与时间进行多项式拟和， 即得到电流 II对应的零时刻温敏参数 VI , 同理， 拟和得到其他测量电流所对 应的零时刻温敏参数 Vi。 When n is 3, for the step constant current measurement under the repeated pulse in FIG. 4, the test moments corresponding to the current are respectively t u , t 21 , t 31 , and the measured temperature-sensitive parameters and time at the corresponding time are polynomial And, that is, the zero-time temperature-sensitive parameter VI corresponding to the current II is obtained, and similarly, the zero-time temperature-sensitive parameter Vi corresponding to the other measured currents is obtained.
步骤 3: 设所述待测半导体器件的有效面积为 AE, 根据所述待测半导体 器件的测试电流和测得电压， 利用所述待测半导体器件的电流-电压-结温曲线 簇，获得不同 AEj下， Ii/AEj-Vi所对应的所述待测半导体器件的结温 Tji, 其中， j的取值范围为 1 j M。 其中， i、 j、 M均为正整数， 且 M不小于 2。 Step 3: The effective area of the semiconductor device to be tested is A E , and the current-voltage-junction temperature curve cluster of the semiconductor device to be tested is obtained according to the test current and the measured voltage of the semiconductor device to be tested. The junction temperature Tji of the semiconductor device to be tested corresponding to Ii/A Ej -Vi under different A Ej , wherein j has a value range of 1 j M. Where i, j, and M are all positive integers, and M is not less than 2.
根据 MQH算法可知： 已知流过结温分布均匀为 T的半导体器件势垒的电 流为 I, 流域面积为 A。。 如果在某时刻该势垒温度分布不再均匀， 若要维持流 过温度为 T有效面积 AE ( AE A。） 内的势垒电流仍为 I , 那么该流域面积 A0 丄 According to the MQH algorithm, it is known that the current flowing through the barrier of the semiconductor device having a uniform junction temperature distribution of T is I, and the watershed area is A. . If the barrier temperature distribution is no longer uniform at a certain time, to maintain the flow-through temperature as the barrier current in the T effective area A E ( A E A.) is still I, then the watershed area A 0丄
内的电流密度增加为 ^， 此时的温敏参数电压等于该势垒在相同温度 T下， / The current density inside increases to ^, and the temperature sensitive parameter voltage at this time is equal to the barrier at the same temperature T, /
流域面积为 A。的情况下， 电流为 AE 所对应的电压值。 下面结合一具体实例对 MQH算法进行描述。对于处在恒温装置里的晶体 管， 结温分布均勾， 通过电流为 I, 流域面积为 A。。 如果有效面积缩小为原来 的 1/2, 结温上升为 T时， 则该晶体管内的电流密度增大到原来的 2倍， 若此 时仍然维持通过晶体管的电流为 I, 则此时温敏参数电压等于该晶体管在恒温 装置里温度为 T时， 电流为 21所对应的电压值。 因此，设所述待测半导体器件的有效面积为 AE。在本发明的一个实施例中， M为 100,即所述待测半导体器件的有效面积 AE的序列为 AE=( 100%, 99%, 1% )共一百个元素， 分别记为 ΑΕ1 , ΑΕ2, ... , ΑΕ1。。， 根据 MQH算法， 选定测 试电流 Ii作为基准电流，分别得到电流序列 苟单标己为 ΒΛ表示 The watershed area is A. In the case, the current is the voltage value corresponding to A E . The MQH algorithm will be described below in conjunction with a specific example. For the transistor in the thermostat, the junction temperature distribution is checked, the passing current is I, and the watershed area is A. . If the effective area is reduced to 1/2 of the original and the junction temperature rises to T, the current density in the transistor is increased by a factor of two. If the current through the transistor is still I, then the temperature is sensitive. The parameter voltage is equal to the voltage value of the transistor when the temperature of the transistor is T in the thermostat. Therefore, it is assumed that the effective area of the semiconductor device to be tested is A E . In an embodiment of the invention, M is 100, that is, the sequence of the effective area A E of the semiconductor device to be tested is A E = (100%, 99%, 1%), a total of one hundred elements, respectively denoted as Α Ε1 , Α Ε 2 , ... , Α Ε1 . . The MQH algorithm, test current Ii is selected as a reference current, the current sequence respectively expressed as hexyl Gou single standard Β Λ
A A A £100 以测试电流 Ii作为基准电流的序列， 即 Βη = ( AAA £100 takes the test current Ii as the sequence of the reference current, ie Β η = (
A £100  A £100
利用步骤 2 中测得的所述待测半导体器件的测试电流及其相应电压的对 应关系， 先根据测试电流 11 获得不同 AEj下所述测试电流：^对应的电流密度 值 Ii/AEj, 然后， 再在 Ii/AEj对应的电压-结温曲线中， 确定所述测得电压 ¼所 对应的结温 Tji。 Using the corresponding relationship between the test current of the semiconductor device to be tested and its corresponding voltage measured in step 2, first obtain the test current according to the test current 1 1 under the different A Ej : ^ corresponding current density value Ii / A Ej Then, in the voltage-junction temperature curve corresponding to Ii/A Ej , the junction temperature Tji corresponding to the measured voltage 1⁄4 is determined.
需要说明的是，在本发明的一个实施例中，Μ为 100, ΑΕ=( 100%, 99%,It should be noted that in one embodiment of the invention, Μ is 100, Α Ε = (100%, 99%,
1% ), 在本发明的另一个实施例中， Μ还可以为 50或其他数字， 相应的 ΑΕ=1%), in another embodiment of the present invention, Μ may also be 50 or other numbers, corresponding Α Ε =
( 100%, 98%, 2% )或 （99%, 97%, 1% )或其他序列等， 本发明 对此并不做限定， 具体视情况而定。 (100%, 98%, 2%) or (99%, 97%, 1%) or other sequences, etc., the invention is not limited thereto, as the case may be.
以 Ν为 5 , Μ为 100为例， 则所测得的数据如下表所示：  Taking Ν as 5 and Μ as 100 as an example, the measured data is shown in the following table:
Figure imgf000016_0001
积 AEj记为所述待测半导体器件的有效面积 AE。
Figure imgf000016_0001
The product A Ej is recorded as the effective area A E of the semiconductor device to be tested.
由于所述测试电流 L很小， 其对所述待测半导体器件的热效应影响很小， 几乎可以忽略不计， 因此， 在不同的测试电流 L下， 所述待测半导体器件的结 温接近定值。 所以， 在测得各组 Tj值后， 从各组 Tj值中选取浮动最小的 Tj 值，该 Tj值所对应的有效面积 AEj即为所述待测半导体器件的高温区所对应的 有效面积。 Since the test current L is small, it has little effect on the thermal effect of the semiconductor device to be tested. Almost negligible, therefore, at different test currents L, the junction temperature of the semiconductor device under test is close to a fixed value. Therefore, after measuring the Tj values of each group, the minimum floating Tj value is selected from each group of Tj values, and the effective area A Ej corresponding to the Tj value is the effective area corresponding to the high temperature region of the semiconductor device to be tested. .
在本发明的一个实施例中， 根据各组 Tj值， 获得浮动最小的 Tj值包括： 计算各组 Tj值中 Tji的方差， 获得方差最小的 Tj值， 记为浮动最小的 Tj值。 在本发明的其他实施例中， 还可以通过其他方法从各组 Tj值中陣选出浮动最 小的 Tj值， 本发明对此并不做限定。  In an embodiment of the present invention, obtaining a minimum floating Tj value according to each group of Tj values includes: calculating a variance of Tji in each group of Tj values, obtaining a Tj value having the smallest variance, and recording the minimum floating Tj value. In other embodiments of the present invention, the floating minimum Tj value may be selected from the array of Tj values by other methods, which is not limited by the present invention.
步骤 5: 根据该有效面积 AE下各结温， 得到所述待测半导体器件的结温； 获得所述待测半导体器件的有效面积 AEj后， 根据该有效面积 AE下各结 温， 得到所述待测半导体器件的结温。 在本发明的一个实施例中， 步骤 5具体 包括：计算该有效面积 AE下各结温的平均值作为所述待测半导体器件的结温。 Step 5: The junction temperature of each of the effective area A E, to obtain the junction temperature of the semiconductor device under test; effective area A Ej obtained after the semiconductor device under test, based on the effective area A E at each junction temperature, A junction temperature of the semiconductor device to be tested is obtained. In an embodiment of the present invention, step 5 specifically includes: calculating an average value of each junction temperature of the effective area A E as a junction temperature of the semiconductor device to be tested.
由此可见， 本发明实施例所提供的测试方法， 不仅不用对所述待测半导体 器件进行开帽操作， 对所述待测半导体器件没有破坏性和损伤， 而且还可以测 试出所述待测半导体器件的结温以及该结温所对应的有效面积，即可以反映所 述待测半导体器件的结温及其分布状态，从而提高了所述待测半导体器件可靠 性分析的精度， 降低了误判或漏判的错误率。  It can be seen that the test method provided by the embodiment of the present invention not only does not perform the cap opening operation on the semiconductor device to be tested, and has no destructiveness and damage to the semiconductor device to be tested, and can also test the test to be tested. The junction temperature of the semiconductor device and the effective area corresponding to the junction temperature can reflect the junction temperature of the semiconductor device to be tested and its distribution state, thereby improving the accuracy of the reliability analysis of the semiconductor device to be tested, and reducing the error. The error rate of the judgment or missed judgment.
本说明书中各个部分采用递进的方式描述，每个部分重点说明的都是与其 他部分的不同之处， 各个部分之间相同相似部分互相参见即可。 The various parts of this manual are described in a progressive manner. Each part focuses on the differences between the other parts. The same similar parts between the parts can be referred to each other.
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本 发明。 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见 的， 本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在 其它实施例中实现。 因此， 本发明将不会被限制于本文所示的实施例， 而是要 符合与本文所公开的原理和新颖特点相一致的最宽的范围。 The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be practiced without departing from the spirit or scope of the invention. Implemented in other embodiments. Therefore, the present invention is not to be limited to the embodiment shown herein, but is to be accorded the broadest scope of the principles and novel features disclosed herein.

Claims

权 利 要 求 Rights request
1、 一种半导体器件的结温测试方法， 其特征在于， 包括： 1. A junction temperature testing method for semiconductor devices, characterized by including:
预先采集不同结温下， 所述待测半导体器件的电流 -电压曲线， 获得所述 待测半导体器件的电流 -电压 -结温曲线簇； Pre-collect the current-voltage curves of the semiconductor device under test at different junction temperatures to obtain the current-voltage-junction temperature curve cluster of the semiconductor device under test;
给所述待测半导体器件通以测试电流 I, 获得不同测试电流 Ii下， 所述待 测半导体器件的电压 Vi, 其中， i的取值范围为 0 N; Pass the test current I to the semiconductor device under test to obtain the voltage Vi of the semiconductor device under test under different test currents Ii, where the value range of i is 0 N;
设所述待测半导体器件的有效面积为 AE, 根据所述待测半导体器件的测 试电流和测得电压， 利用所述待测半导体器件的电流-电压-结温曲线簇， 获得 不同 AEj下， Ii/AEj-Vi所对应的所述待测半导体器件的结温 Tji, 其中， j的取值 范围为 1 j M; Assume that the effective area of the semiconductor device under test is AE . According to the test current and measured voltage of the semiconductor device under test, use the current-voltage-junction temperature curve cluster of the semiconductor device under test to obtain different AEj Below, the junction temperature Tji of the semiconductor device under test corresponding to Ii/A Ej -Vi, where the value range of j is 1 j M;
从各组 Tj值中选取浮动最小的 Tj值， 并将 Tj值所对应的有效面积 A 记为所述待测半导体器件的有效面积 AE; Select the Tj value with the smallest floating value from each group of Tj values, and record the effective area A corresponding to the Tj value as the effective area A E of the semiconductor device under test;
根据该有效面积 AE下各结温， 得到所述待测半导体器件的结温； 其中， i、 j、 M、 N均为正整数， 且^1、 N均不小于 2。 According to each junction temperature under the effective area A E , the junction temperature of the semiconductor device to be tested is obtained; where i, j, M, and N are all positive integers, and neither ^1 nor N is less than 2.
2、 根据权利要求 1所述的测试方法， 其特征在于， 预先采集不同结温下， 所述待测半导体器件的电流-电压曲线， 获得所述待测半导体器件的电流 -电压 -结温曲线簇包括： 2. The testing method according to claim 1, characterized in that, the current-voltage curve of the semiconductor device to be tested is collected in advance at different junction temperatures, and the current-voltage-junction temperature curve of the semiconductor device to be tested is obtained. Clusters include:
选取与所述待测半导体器件用相同半导体材料、相同结构和相同工艺制造 的同批次半导体器件为第一半导体器件； Select the same batch of semiconductor devices manufactured with the same semiconductor material, the same structure and the same process as the semiconductor device to be tested as the first semiconductor device;
将第一半导体器件放在恒温环境中， 采集不同温度下， 所述第一半导体器 件的电流-电压特性曲线， 获得所述第一半导体器件的电流 -电压 -结温曲线簇。 Place the first semiconductor device in a constant temperature environment, collect the current-voltage characteristic curves of the first semiconductor device at different temperatures, and obtain the current-voltage-junction temperature curve cluster of the first semiconductor device.
3、 根据权利要求 1所述的测试方法， 其特征在于， 还包括： 3. The test method according to claim 1, further comprising:
根据所述待测半导体器件的电流-电压-结温曲线簇， 获得以所述待测半导 体器件电流为参量， 所述待测半导体器件电压为自变量， 所述待测半导体器件 的结温为应变量的函数曲线。 According to the current-voltage-junction temperature curve cluster of the semiconductor device under test, it is obtained that the current of the semiconductor device under test is a parameter, the voltage of the semiconductor device under test is an independent variable, and the junction temperature of the semiconductor device under test is Function curve of strain quantity.
4、 根据权利要求 3所述的测试方法， 其特征在于， 根据所述待测半导体 器件的测试电流和测得电压， 获得不同 AEj下， Ii/AEj-Vi所对应的所述待测半 导体器件的结温 Tji包括： 4. The testing method according to claim 3, characterized in that, according to the test current and the measured voltage of the semiconductor device to be tested, the to-be-tested value corresponding to Ii/A Ej -Vi is obtained under different A Ej . The junction temperature Tji of semiconductor devices includes:
根据所述待测半导体器件的测试电流， 获得不同 AEj下的 Ii/AEj值； 在 Ii/AEj对应的电压-结温曲线中， 确定所述测得电压所对应的结温 Tji。 According to the test current of the semiconductor device under test, obtain the Ii/A Ej value under different A Ej ; in the voltage-junction temperature curve corresponding to Ii/A Ej , determine the junction temperature Tji corresponding to the measured voltage .
5、 根据权利要求 1所述的测试方法， 其特征在于， 给所述待测半导体器 件通以测试电流 I, 获得不同测试电流下 Ii, 所述待测半导体器件的电压 Vi 包括： 5. The testing method according to claim 1, characterized in that, a test current I is passed to the semiconductor device under test to obtain Ii under different test currents, and the voltage Vi of the semiconductor device under test includes:
给所述待测半导体器件通以测试电流 Ii,测量 tj时刻所述待测半导体器件 的电压 Vij , 其中， j依次等于 1 n, 且 n不小于 2; Pass the test current Ii to the semiconductor device under test, and measure the voltage Vij of the semiconductor device under test at time tj, where j is equal to 1 n in turn, and n is not less than 2;
对不同时刻 tj测得的 Vij进行拟合， 得到测试电流 Ii对应的电压 Vi。 Fit the Vij measured at different times tj to obtain the voltage Vi corresponding to the test current Ii.
6、 根据权利要求 5所述的测试方法， 其特征在于， n为 3。 6. The test method according to claim 5, characterized in that n is 3.
7、 根据权利要求 1所述的测试方法， 其特征在于， 根据各组 Tj值， 获得 浮动最小的 Tj值包括： 7. The test method according to claim 1, characterized in that, according to each group of Tj values, obtaining the smallest floating Tj value includes:
计算各组 Tj值中 Tji的方差， 获得方差最小的 Tj值， 记为浮动最小的 Tj 值。 Calculate the variance of Tji in each group of Tj values, and obtain the Tj value with the smallest variance, which is recorded as the Tj value with the smallest floating value.
8、 根据权利要求 1 所述的测试方法， 其特征在于， 根据该有效面积 AE 下各结温， 得到所述待测半导体器件的结温包括： 8. The testing method according to claim 1, characterized in that, according to each junction temperature under the effective area A E , obtaining the junction temperature of the semiconductor device to be tested includes:
计算该有效面积 AE下各结温的平均值作为所述待测半导体器件的结温。 Calculate the average value of each junction temperature under the effective area A E as the junction temperature of the semiconductor device under test.
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