WO2015056426A1 - Data-storage control device - Google Patents

Data-storage control device Download PDF

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Publication number
WO2015056426A1
WO2015056426A1 PCT/JP2014/005117 JP2014005117W WO2015056426A1 WO 2015056426 A1 WO2015056426 A1 WO 2015056426A1 JP 2014005117 W JP2014005117 W JP 2014005117W WO 2015056426 A1 WO2015056426 A1 WO 2015056426A1
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WO
WIPO (PCT)
Prior art keywords
voltage
memory card
power supply
input terminal
terminal
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PCT/JP2014/005117
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French (fr)
Japanese (ja)
Inventor
貴雄 國井
貴巨 長谷川
渡邉　聡
林　宏樹
Original Assignee
株式会社デンソー
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Publication of WO2015056426A1 publication Critical patent/WO2015056426A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2015—Redundant power supplies

Definitions

  • the present disclosure relates to a data storage control device that stores data in a memory card.
  • a backup power source provided with a large-capacity capacitor (hereinafter referred to as a backup capacitor) when power supply is cut off is known (for example, see Patent Document 1). reference).
  • the memory card When the memory card is installed in the vehicle, a situation occurs where the voltage of the in-vehicle battery is not stable due to cranking or the like. In such a situation, there is a possibility that the host device does not stop outputting the clock signal immediately after the power supply from the in-vehicle battery is cut off. If the output of the clock signal is not stopped immediately after the power supply is cut off, the memory card may not be able to finish the normal termination process during the backup time.
  • the present disclosure has been made in view of such problems, and an object thereof is to provide a data storage control device capable of avoiding destruction of data stored in a memory card.
  • the data storage control device includes a control device, a power interruption determination unit, a clock signal stop unit, and a backup power source.
  • the control device operates by receiving power supply from the outside and controls the memory card by outputting at least a clock signal to a memory card that operates in synchronization with a clock signal input from the outside.
  • the power interruption determination unit determines whether or not a predetermined power interruption determination condition indicating that power supply from at least the main power supply that supplies power to the memory card and the control device is cut off is satisfied.
  • the clock signal stop unit stops the output of the clock signal by the control device when the power interruption determination unit determines that the power interruption determination condition is satisfied.
  • the backup power supply continuously supplies power to the memory card after the power supply from the main power supply is interrupted until at least the preset backup time has elapsed.
  • the clock signal stop unit stops the output of the clock signal by the control device.
  • the memory card executes the process when the power supply from the main power supply is cut off when the input of the clock signal is stopped, the memory card has a time for executing this process. As a result, it is possible to secure a backup time in which power is supplied from the backup power supply, and to avoid the destruction of data stored in the memory card.
  • FIG. 3 is a circuit diagram showing a configuration of a memory card power supply circuit 7 of the data storage control device 1.
  • FIG. 3 is a timing chart showing the operation of the data storage control device 1.
  • 3 is a first timing chart showing operations of a shutdown signal control unit 24 and a shutdown signal output unit 25 of the data storage control device 1.
  • 6 is a second timing chart showing operations of the shutdown signal control unit 24 and the shutdown signal output unit 25.
  • 10 is a third timing chart showing the operations of the shutdown signal control unit 24 and the shutdown signal output unit 25.
  • FIG. 10 is a fourth timing chart showing operations of the shutdown signal control unit 24 and the shutdown signal output unit 25.
  • a data storage control device 1 to which the present disclosure is applied is mounted on a vehicle, and as shown in FIG. 1, a regulator 2, a main microcomputer 3, a sub-microcomputer 4, a memory card 5, a card slot 6, a memory card power supply circuit 7, A power supply interruption detection circuit 8 is provided.
  • the regulator 2 receives a power supply voltage from a battery (not shown) mounted on the vehicle via a main relay (not shown), and from this power supply voltage, a drive voltage (this embodiment) for operating the data storage control device 1 In the form, 5V, 3.3V, etc.) are generated and output.
  • a drive voltage this embodiment
  • the voltage supplied from the battery to the data storage control device 1 via the main relay is referred to as + B voltage.
  • the main microcomputer 3 executes various processes for controlling the control target (memory card 5 in this embodiment).
  • the sub-microcomputer 4 executes various processes for controlling the controlled object (the regulator 2 in this embodiment). Note that the main microcomputer 3 and the sub-microcomputer 4 are connected to each other so that data communication is possible.
  • the memory card 5 includes a card body formed in a rectangular plate shape, a data rewritable nonvolatile memory, and a card controller that controls writing and reading of data to and from the nonvolatile memory.
  • the memory card 5 is configured by housing a nonvolatile memory and a card controller in the card body.
  • the memory card 5 is an SD card (registered trademark) in this embodiment.
  • the card slot 6 has a mounting portion for mounting the memory card 5 in a removable manner. Furthermore, the card slot 6 includes a power supply terminal, a clock terminal, a command terminal, a data terminal, and a card detection terminal.
  • the power supply terminal is for inputting a voltage for operating the memory card 5 (hereinafter referred to as a card operating voltage VDD) from the memory card power supply circuit 7.
  • a card operating voltage VDD a voltage for operating the memory card 5
  • the clock terminal is for inputting a clock signal for operating the memory card 5 from the main microcomputer 3.
  • the memory card 5 is configured to perform internal measures for avoiding data destruction until the backup time (for example, 250 ms in the present embodiment) elapses after the clock signal input stops.
  • the command terminal is for inputting / outputting a command signal for controlling the memory card 5 to / from the main microcomputer 3.
  • the data terminal is for inputting / outputting data signals to / from the memory card 5 to / from the main microcomputer 3.
  • the card detection terminal is for outputting a card detection signal indicating whether or not the memory card 5 is inserted in the card slot 6.
  • the card detection signal of the present embodiment is a signal that is at a low level when the memory card 5 is inserted in the card slot 6 and is at a high level when the memory card 5 is not inserted.
  • the memory card power supply circuit 7 receives the drive voltage from the regulator 2, and generates and outputs a card operating voltage VDD (for example, 3.3 V in the present embodiment) from the drive voltage.
  • VDD card operating voltage
  • the power supply interruption detection circuit 8 receives the + B voltage, detects whether or not the + B voltage instantaneous interruption has occurred, and detects that the + B voltage instantaneous interruption has been detected. Is output to the sub-microcomputer 4. Note that the instantaneous power interruption detection circuit 8 of the present embodiment determines that an instantaneous interruption of the + B voltage has occurred when the + B voltage is equal to or less than a preset instantaneous interruption determination value (for example, 4.5 V).
  • a preset instantaneous interruption determination value for example, 4.5 V.
  • the main microcomputer 3 when the sub-microcomputer 4 inputs the instantaneous power interruption detection signal from the power supply interruption detection circuit 8, the main microcomputer 3 is turned off and the main microcomputer 3 is forcibly shut down. As a result, the main microcomputer 3 stops outputting the clock signal.
  • the memory card power supply circuit 7 includes a 5V voltage input terminal 11, a 3.3V voltage input terminal 12, a ground terminal 13, a main control signal input terminal 14, a sub control signal input terminal 15, and a card detection input terminal. 16, a card voltage output terminal 17, and an ON notification output terminal 18.
  • 5V drive voltage of 5V is input from the regulator 2 to the 5V voltage input terminal 11.
  • a 3.3 V drive voltage is input from the regulator 2 to the 3.3 V voltage input terminal 12.
  • the ground terminal 13 is connected to the ground.
  • the main-side card control signal for controlling the output of the card operating voltage VDD is input from the main microcomputer 3 to the main control signal input terminal 14.
  • the sub-control signal input terminal 15 receives a sub-side card control signal for controlling the output of the card operating voltage VDD from the sub-microcomputer 4.
  • a card detection signal is input from the card slot 6 to the card detection input terminal 16.
  • the memory card power supply circuit 7 includes a capacitor charging IC 21, a backup capacitor 22, a DC / DC converter 23, a shutdown signal control unit 24, a shutdown signal output unit 25, and a power-on determination unit 26.
  • the capacitor charging IC 21 has a voltage input terminal Vin and a voltage output terminal Vout.
  • the capacitor charging IC 21 inputs a driving voltage of 5 V to the voltage input terminal Vin, and generates a charging voltage (for example, 4 V in the present embodiment) for charging the backup capacitor 22 from the driving voltage, This charging voltage is output from the voltage output terminal Vout.
  • the backup capacitor 22 is a backup power supply for the memory card 5, and the memory card power supply circuit 7 supplies the card operating voltage VDD for at least the backup time (for example, 250 ms in this embodiment) after the supply of the + B voltage is stopped. Capacitance that can be set.
  • the positive electrode of the backup capacitor 22 is connected to the voltage output terminal Vout of the capacitor charging IC 21, and the negative electrode of the backup capacitor 22 is grounded.
  • the DC / DC converter 23 has a voltage input terminal Vin, a voltage output terminal Vout, and a shutdown terminal SHDN.
  • the DC / DC converter 23 inputs the charging voltage from the capacitor charging IC 21 to the voltage input terminal Vin, generates a card operating voltage VDD from the charging voltage, and uses the card operating voltage VDD as a voltage output terminal. Output from Vout.
  • the DC / DC converter 23 outputs the card operating voltage VDD when the shutdown signal input to the shutdown terminal SHDN is at a high level, while the card operating voltage VDD is output when the shutdown signal is at a low level. Stop output.
  • the shutdown signal control unit 24 includes a transistor 31, resistors 32, 33, 34, 35, 36, 37 and diodes 38, 39.
  • the transistor 31 is an NPN type transistor, and has a collector, a base, and an emitter.
  • the collector of the transistor 31 is connected to the 3.3V voltage input terminal 12 through the resistor 32.
  • the base of the transistor 31 is connected to the main control signal input terminal 14 via the resistor 33.
  • the emitter of the transistor 31 is connected to the ground terminal 13.
  • the resistor 34 has one end connected to the base of the transistor 31 and the other end grounded.
  • the resistor 35 has one end connected to the main control signal input terminal 14 and the other end connected to one end of the resistor 36.
  • the other end of the resistor 36 is connected to the shutdown signal output unit 25.
  • the resistor 37 has one end connected to the voltage output terminal Vout of the DC / DC converter 23 and the other end connected to the shutdown signal output unit 25.
  • the diode 38 has an anode connected to a connection point between the resistor 32 and the collector of the transistor 31 and a cathode connected to the sub-control signal input terminal 15.
  • the diode 39 has an anode connected to a connection point between the resistor 35 and the resistor 36, and a cathode connected to the sub control signal input terminal 15.
  • the shutdown signal output unit 25 includes an OR circuit 41, a transistor 42, resistors 43 and 44, and diodes 45 and 46.
  • the OR circuit 41 has a first input terminal, a second input terminal, an output terminal, and a power supply voltage terminal.
  • the OR circuit 41 performs an OR operation on signals input to the first input terminal and the second input terminal, and indicates the operation result.
  • the signal is output from the output terminal.
  • the first input terminal is connected to the voltage output terminal Vout of the DC / DC converter 23 via the resistor 37 of the shutdown signal control unit 24.
  • the second input terminal is connected to the collector of the transistor 31 in the shutdown signal control unit 24.
  • the output terminal is connected to the shutdown terminal SHDN of the DC / DC converter 23 via the resistor 43.
  • the transistor 42 is an NPN type transistor and has a collector, a base, and an emitter.
  • the collector of the transistor 42 is connected to the shutdown terminal SHDN of the DC / DC converter 23.
  • the base of the transistor 42 is connected to the main control signal input terminal 14 via the resistors 35 and 36 of the shutdown signal control unit 24.
  • the emitter of the transistor 42 is connected to the ground terminal 13.
  • the resistor 44 has one end connected to the base of the transistor 42 and the other end grounded. Then, when the main-side card control signal from the main microcomputer 3 is at a high level, the resistors 35, 36, 36, 36, A resistance value of 44 is set.
  • the diode 45 has an anode connected to the voltage output terminal Vout of the DC / DC converter 23 and a cathode connected to the power supply voltage terminal of the OR circuit 41.
  • the diode 46 has an anode connected to the voltage output terminal Vout of the capacitor charging IC 21 and a cathode connected to the power supply voltage terminal of the OR circuit 41.
  • the power-on determination unit 26 includes a negative OR circuit 51, transistors 52 and 53, and resistors 54, 55, 56, 57, 58, and 59.
  • the negative OR circuit 51 has a first input terminal, a second input terminal, an output terminal, and a power supply voltage terminal, performs a negative OR operation on signals input to the first input terminal and the second input terminal, and obtains an operation result. Is output from the output terminal.
  • the first input terminal is connected to the collector of the transistor 52.
  • the second input terminal is connected to the card detection input terminal 16.
  • the output terminal is connected to the base of the transistor 53 via the resistor 54.
  • the transistor 52 is an NPN type transistor, and has a collector, a base, and an emitter.
  • the collector of the transistor 52 is connected to the 3.3V voltage input terminal 12 through the resistor 55.
  • the base of the transistor 52 is connected to the voltage output terminal Vout of the capacitor charging IC 21 via the resistor 56.
  • the emitter of the transistor 52 is connected to the ground terminal 13.
  • the resistor 57 has one end connected to the base of the transistor 52 and the other end grounded.
  • the voltage of the backup capacitor 22 is equal to or higher than the backup possible voltage (eg, 1.3 V in this embodiment)
  • the divided voltage of the resistor 57 by the resistors 56 and 57 is set higher than the ON voltage of the transistor 52.
  • the resistance values of the resistors 56 and 57 are set.
  • the backup-capable voltage is a voltage at which the backup capacitor 22 can accumulate a charge amount for the backup time.
  • the transistor 53 is an NPN type transistor, and has a collector, a base, and an emitter.
  • the collector of the transistor 53 is connected to the ON notification output terminal 18 and is connected to the main microcomputer 3.
  • the transistor 53 is provided so as to match the input voltage on the main microcomputer 3 side, and the ON notification output terminal 18 needs to be pulled up by the input voltage of the microcomputer (not shown).
  • the base of the transistor 53 is connected to the output terminal of the NOR circuit 51 through the resistor 54.
  • the emitter of the transistor 53 is connected to the ground terminal 13.
  • the resistor 58 has one end connected to the base of the transistor 53 and the other end grounded.
  • the resistance values of the resistors 54 and 58 are set so that the divided voltage of the resistor 58 by the resistors 54 and 58 is higher than the ON voltage of the transistor 53. Is set.
  • the resistor 59 has one end connected to the 3.3V voltage input terminal 12 and the other end connected to the card detection input terminal 16.
  • the transistor 52 when the voltage of the backup capacitor 22 rises due to the charging of the backup capacitor 22, the transistor 52 is turned on, and the first input terminal of the negative OR circuit 51 is at the low level. It becomes. Further, when the card detection input terminal 16 is at a low level, the second input terminal of the NOR circuit 51 is at a low level.
  • the output terminal of the NOR circuit 51 becomes high level when the backup capacitor 22 is charged and the memory card 5 is inserted in the card slot 6, and becomes low level in other cases. .
  • the transistor 53 When the output terminal of the negative OR circuit 51 is at a high level, the transistor 53 is turned on and the on notification output terminal 18 is at a low level.
  • the regulator 2 starts to operate, and a drive voltage of 5 V is output from the regulator 2. Is done. As a result, a drive voltage of 5 V is input to the voltage input terminal Vin of the capacitor charging IC 21 and the capacitor charging IC 21 starts operating. As a result, the voltage at the voltage output terminal Vout of the capacitor charging IC 21 becomes the charging voltage (4 V in this embodiment), and the voltage of the backup capacitor 22 and the voltage of the voltage input terminal Vin of the DC / DC converter 23 are reduced. The voltage gradually increases until the charging voltage (4 V) is reached.
  • the memory card power supply circuit 7 sets the voltage of the ON notification output terminal 18 to a low level, thereby reducing the low level.
  • An ON-enabled notification is output (see arrow AL1).
  • the main microcomputer 3 is turned on when a drive voltage of 5 V is supplied from the regulator 2. Thereafter, in the main microcomputer 3, the port setting is completed at time t02 during initialization, and the main control signal input terminal 14 is logically fixed to the high level (see arrow AL2). Thereafter, at time t03, the sub microcomputer 4 sets the sub control signal input terminal 15 to the high level.
  • the sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level after 250 ms or more has elapsed since the main microcomputer 3 was turned on. This is because a power holding time of 250 ms is required when the clocks from the main microcomputer 3 are stopped due to a hard reset of the main microcomputer 3, and the power holding time of 250 ms is protected in any state.
  • the main microcomputer 3 sets the main control signal input terminal 14 to the low level.
  • the shutdown terminal SHDN of the DC / DC converter 23 becomes high level
  • the DC / DC converter 23 starts to operate
  • the card operating voltage VDD is output from the voltage output terminal Vout of the DC / DC converter 23.
  • the main microcomputer 3 sets the main control signal input terminal 14 to a low level after a discharge time (for example, 10 ms in the present embodiment) has elapsed since the sub control signal input terminal 15 has become a high level.
  • This discharge time is a time required for reliably dropping the voltage of the power supply (DC / DC converter 23) of the memory card 5.
  • the main microcomputer 3 when the ON notification output terminal 18 is at the high level when the charging period ends, the main microcomputer 3 does not set the main control signal input terminal 14 to the low level. Thereby, the operation of the DC / DC converter 23 is prohibited and the memory card 5 can be prevented from being turned on.
  • the DC / DC converter 23 outputs the card operating voltage VDD from the voltage output terminal Vout for at least 250 ms (refer to the backup period (time t05 to t06) in the figure).
  • the voltage of the backup capacitor 22 becomes lower than the operable voltage of the DC / DC converter 23, the power supply to the OR circuit 41 is stopped, and the shutdown terminal SHDN of the DC / DC converter 23 becomes low level.
  • the output of the card operating voltage VDD from the DC / DC converter 23 is stopped at time t06.
  • the charging period starts, and the operation is performed up to time t08 in the same manner as the charging period from time t01 to time t02.
  • the operation shifts to normal operation, and the same operation as normal operation from time t04 to time t05 is performed.
  • the delayed ACC is a process executed after the ACC power supply is turned off in order to terminate the main microcomputer 3 safely.
  • the main microcomputer 3 sets the main control signal input terminal 14 to the high level.
  • the shutdown terminal SHDN of the DC / DC converter 23 becomes low level, and the output of the card operating voltage VDD from the DC / DC converter 23 is stopped.
  • the sub-microcomputer 4 sets the sub-control signal input terminal 15 to the low level at time t11 when the discharge time (for example, 10 ms in the present embodiment) has elapsed since the output stop of the DC / DC converter 23. Thereafter, at time t12, the main microcomputer 3 is turned off (see arrow AL3), and the system is shut down.
  • the discharge time for example, 10 ms in the present embodiment
  • FIG. 4 is a timing chart showing the operations of the shutdown signal control unit 24 and the shutdown signal output unit 25 when the ACC power supply is turned on in a state where the voltage of the backup capacitor 22 is 0V.
  • the main microcomputer 3 is turned on (see arrow AL21), and the main control signal input terminal 14 is logically fixed to the high level. Accordingly, an on-voltage is applied to the base of the transistor 31, and the transistor 31 is turned on. Since the sub control signal input terminal 15 is at a low level before the transistor 31 is turned on, the voltage level of the second input terminal of the OR circuit 41 does not change before and after the transistor 31 is turned on. , Remain at low level.
  • the sub control signal input terminal 15 at this time is at a low level, the on-voltage is not applied to the base of the transistor 42, and the transistor 42 is in the off state.
  • the sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level at time t24.
  • the sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level after 250 ms or more has elapsed since the main microcomputer 3 was turned on.
  • the main microcomputer 3 sets the main control signal input terminal 14 to low level. As a result, the transistor 31 is turned off, and the second input terminal of the OR circuit 41 becomes high level. For this reason, the output terminal of the OR circuit 41 becomes high level. Further, when the transistor 42 is turned off, the shutdown terminal SHDN of the DC / DC converter 23 becomes high level, and the DC / DC converter 23 starts to operate. As a result, the first input terminal of the OR circuit 41 becomes high level.
  • FIG. 5 is a timing chart showing the operation of the shutdown signal control unit 24 and the shutdown signal output unit 25 when an instantaneous interruption of the + B voltage occurs.
  • the power supply interruption detection circuit 8 outputs an instantaneous interruption detection signal to the sub-microcomputer 4. Then, when the instantaneous interruption detection signal is input, the sub microcomputer 4 sets the sub control signal input terminal 15 to the low level. As a result, the second input terminal of the OR circuit 41 becomes low level.
  • the main microcomputer 3 is reset (see arrow AL31), so that the main control signal input terminal 14 becomes high level. Accordingly, an on-voltage is applied to the base of the transistor 31, and the transistor 31 is turned on. Further, at time t33, the main microcomputer 3 is turned off (see arrow AL32), the voltage level of the main control signal input terminal 14 becomes indefinite, and the transistor 31 is turned off.
  • the drive voltages of 5V and 3.3V start to decrease.
  • the voltage of the voltage output terminal Vout of the capacitor charging IC 21 decreases due to the decrease of the driving voltage of 5 V, and the voltage input terminal Vin of the DC / DC converter 23 and the power supply voltage of the OR circuit 41 follow this.
  • the terminal voltage drops.
  • the card operating voltage VDD (3.3 V) is input from the DC / DC converter 23 to the power supply voltage terminal of the OR circuit 41 through the diode 45.
  • the voltage drop at the power supply voltage terminal of the OR circuit 41 is temporarily stopped when the card operation voltage VDD (3.3 V) is reached, and the voltage at the power supply voltage terminal of the OR circuit 41 is reduced to the card operation voltage VDD. Held at (3.3V).
  • FIG. 6 is a timing chart showing operations of the shutdown signal control unit 24 and the shutdown signal output unit 25 when the ACC power supply is turned off.
  • the system shifts to delayed ACC.
  • the main microcomputer 3 sets the main control signal input terminal 14 to the high level.
  • the sub control signal input terminal 15 is at a high level, an on-voltage is applied to the bases of the transistors 31 and 42, and the transistors 31 and 42 are turned on.
  • the second input terminal of the OR circuit 41 and the shutdown terminal SHDN of the DC / DC converter 23 change from the high level to the low level.
  • the shutdown terminal SHDN of the DC / DC converter 23 becomes low level, the output of the card operating voltage VDD from the DC / DC converter 23 is stopped.
  • the sub microcomputer 4 sets the sub control signal input terminal 15 to the low level. Thereafter, at time t43, the main microcomputer 3 is turned off.
  • FIG. 7 is a timing chart showing operations of the shutdown signal control unit 24 and the shutdown signal output unit 25 when the main microcomputer 3 is reset.
  • the sub microcomputer 4 changes the sub control signal input terminal 15 from the high level to the low level.
  • the second input terminal of the OR circuit 41 changes from the high level to the low level.
  • the main microcomputer 3 is reset (see arrow AL51), so that the main control signal input terminal 14 becomes high level. Accordingly, the transistor 31 is turned on.
  • the sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level at time t53.
  • the sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level after 250 ms or more has elapsed since the main microcomputer 3 was turned on. Thereby, the transistor 42 is turned on, and the shutdown terminal SHDN of the DC / DC converter 23 is changed from the high level to the low level.
  • the shutdown terminal SHDN of the DC / DC converter 23 becomes low level, the output of the card operating voltage VDD from the DC / DC converter 23 is stopped.
  • the main microcomputer 3 sets the main control signal input terminal 14 to low level at time t54 when the discharge time has elapsed since the sub control signal input terminal 15 became high level. Thereby, the transistors 31 and 42 are turned off. First, when the transistor 31 is turned off, the second input terminal of the OR circuit 41 is changed from low level to high level, and thereby the output terminal of the OR circuit 41 is changed from low level to high level. Further, when the transistor 42 is turned off, the shutdown terminal SHDN of the DC / DC converter 23 is changed from the low level to the high level. As a result, the output of the card operating voltage VDD from the DC / DC converter 23 is resumed.
  • the data storage control device 1 configured as described above includes a main microcomputer 3, a power supply interruption detection circuit 8, a sub-microcomputer 4, and a backup capacitor 22.
  • the main microcomputer 3 operates with power supplied from the outside and controls the memory card 5 by outputting at least a clock signal to the memory card 5 operating in synchronization with a clock signal input from the outside.
  • the power supply interruption detection circuit 8 determines that the + B voltage instantaneous interruption has occurred when the + B voltage is equal to or less than a predetermined instantaneous interruption determination value (for example, 4.5 V).
  • the sub-microcomputer 4 turns off the main microcomputer 3 and forcibly shuts down the main microcomputer 3 when the power supply interruption detection circuit 8 determines that an instantaneous interruption of the + B voltage has occurred.
  • the output of the clock signal by is stopped.
  • the backup capacitor 22 continuously supplies power to the memory card 5 after the + B voltage is cut off until at least a preset backup time (for example, 250 ms) elapses.
  • the sub-microcomputer 4 stops the output of the clock signal from the main microcomputer 3 when the power supply interruption detection circuit 8 determines that the + B voltage instantaneous interruption has occurred.
  • the memory card 5 executes the process when the + B voltage is cut off when the input of the clock signal is stopped, the memory card 5 sets the time for executing this process as A backup time during which power is supplied by the backup capacitor 22 can be secured, and destruction of data stored in the memory card 5 can be avoided.
  • the main microcomputer 3 corresponds to the control device
  • the + B voltage corresponds to the main power supply
  • the power supply interruption detection circuit 8 corresponds to the interruption determination part
  • the sub microcomputer 4 corresponds to the clock signal stop part
  • the backup capacitor 22 corresponds to the backup power supply.
  • this indication is not limited to the above-mentioned embodiment, and can take various forms, as long as it belongs to the technical scope of this indication.
  • an SD card is used as a memory card.
  • the present invention is not limited to the SD card, and when the power supply is cut off, destruction of already stored data is avoided. Any storage medium provided with a function for performing the processing for this purpose may be used.
  • the main microcomputer 3 when the instantaneous interruption detection signal is input to the sub-microcomputer 4, the main microcomputer 3 is turned off and the main microcomputer 3 is forcibly shut down.
  • the method of stopping the output of the clock signal by the main microcomputer 3 is not limited to this.
  • a signal stop signal may be output to the main microcomputer 3.

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Abstract

By outputting at least a clock signal to a memory card (5) that operates on power supplied from the outside and is synchronized on a clock signal inputted from the outside, a primary microcomputer (3) in this data-storage control device (1) controls said memory card (5). If a +B voltage is less than or equal to a momentary-interruption threshold, a momentary-power-supply-interruption detection circuit (8) determines that a momentary interruption has occurred in said +B voltage. If it is determined that a momentary interruption has occurred in the +B voltage, a secondary microcomputer (4) forcibly shuts down the primary microcomputer (3) by cutting the supply of power thereto, thereby stopping the primary microcomputer (3) from outputting the abovementioned clock signal. A backup capacitor (22) continuously supplies power to the memory card (5) until at least a backup period has elapsed since the +B voltage cut out. This makes it possible to avoid corruption of data stored in the memory card.

Description

データ記憶制御装置Data storage controller 関連出願の相互参照Cross-reference of related applications
　本出願は、２０１３年月１０月１８日に出願された日本出願番号２０１３－２１７３９３号に基づくもので、ここにその記載内容を援用する。 This application is based on Japanese Patent Application No. 2013-217393 filed on October 18, 2013, the contents of which are incorporated herein by reference.
　本開示は、メモリカードにデータを記憶するデータ記憶制御装置に関する。 The present disclosure relates to a data storage control device that stores data in a memory card.
　データ書き換え可能な不揮発性メモリを搭載するメモリカードへのアクセス（データ読込、データ書込、データ消去）中に突然、メモリカードへの電源供給が断たれると、上記メモリカードに既に記憶されているデータまで破壊されるおそれがある。なお、ユーザアクセス時以外にもメモリカード内部のコントローラ制御によっては上記現象が発生する可能性がある。このようなデータ破壊を抑制するために、電源供給が断たれたときのバックアップ電源として大容量のコンデンサ（以下、バックアップ用コンデンサという）を設けたものが知られている（例えば、特許文献１を参照）。 If the power supply to the memory card is suddenly interrupted while accessing a memory card equipped with a rewritable nonvolatile memory (data reading, data writing, data erasing), the data is already stored in the memory card. The existing data may be destroyed. In addition to the time of user access, the above phenomenon may occur depending on controller control inside the memory card. In order to suppress such data destruction, a backup power source provided with a large-capacity capacitor (hereinafter referred to as a backup capacitor) when power supply is cut off is known (for example, see Patent Document 1). reference).
　バックアップ用コンデンサを設けることにより、メモリカードへの電源供給が断たれた場合であっても、バックアップ用コンデンサに充電されている電荷量に応じたバックアップ時間継続してメモリカードへ電源を供給することができる。そして、このバックアップ時間中に、メモリカード自身が正常終了処理を実行することで、メモリカードに既に記憶されているデータの破壊を回避することができる。 By providing a backup capacitor, even if the power supply to the memory card is cut off, power is supplied to the memory card continuously for the backup time corresponding to the amount of charge stored in the backup capacitor. Can do. And during this backup time, the memory card itself performs normal termination processing, so that it is possible to avoid destruction of data already stored in the memory card.
特開平８－２４９２４４号公報JP-A-8-249244
　しかし、メモリカード自身が正常終了処理を開始するための条件を、「メモリカードへのアクセスを制御するホスト機器からのクロック信号の入力が停止すること」とした場合に、以下の問題が発生することが懸念される。 However, the following problem occurs when the condition for the memory card itself to start the normal termination process is "stop the input of the clock signal from the host device that controls access to the memory card". There is concern.
　メモリカードが車両に搭載されている場合には、車載バッテリの電圧がクランキング等により安定しない状況が発生する。このような状況では、車載バッテリからの電源供給が断たれた直後にホスト機器がクロック信号の出力を停止しない可能性がある。そして、電源供給が断たれた直後にクロック信号の出力を停止しなかった場合には、メモリカードが上記正常終了処理を上記バックアップ時間中に終了させることができなくなるおそれがある。 When the memory card is installed in the vehicle, a situation occurs where the voltage of the in-vehicle battery is not stable due to cranking or the like. In such a situation, there is a possibility that the host device does not stop outputting the clock signal immediately after the power supply from the in-vehicle battery is cut off. If the output of the clock signal is not stopped immediately after the power supply is cut off, the memory card may not be able to finish the normal termination process during the backup time.
　本開示は、こうした問題に鑑みてなされたものであり、メモリカードに記憶されているデータの破壊を回避することができるデータ記憶制御装置を提供することを目的とする。 The present disclosure has been made in view of such problems, and an object thereof is to provide a data storage control device capable of avoiding destruction of data stored in a memory card.
　本開示の一態様によれば、データ記憶制御装置は、制御装置と、電断判断部と、クロック信号停止部と、バックアップ電源とを備える。 According to one aspect of the present disclosure, the data storage control device includes a control device, a power interruption determination unit, a clock signal stop unit, and a backup power source.
　制御装置は、外部から電源供給を受けて動作するとともに外部から入力するクロック信号に同期して動作するメモリカードへ、少なくともクロック信号を出力することによりメモリカードを制御する。 The control device operates by receiving power supply from the outside and controls the memory card by outputting at least a clock signal to a memory card that operates in synchronization with a clock signal input from the outside.
　また電断判断部は、少なくともメモリカードと制御装置への電源供給を行う主電源からの電源供給が断たれることを示す予め設定された電断判断条件が成立したか否かを判断する。そしてクロック信号停止部は、電断判断条件が成立したと電断判断部が判断した場合に、制御装置によるクロック信号の出力を停止させる。 The power interruption determination unit determines whether or not a predetermined power interruption determination condition indicating that power supply from at least the main power supply that supplies power to the memory card and the control device is cut off is satisfied. The clock signal stop unit stops the output of the clock signal by the control device when the power interruption determination unit determines that the power interruption determination condition is satisfied.
　またバックアップ電源は、主電源からの電源供給が断たれてから、少なくとも予め設定されたバックアップ時間が経過するまで継続してメモリカードへ電源を供給する。 Also, the backup power supply continuously supplies power to the memory card after the power supply from the main power supply is interrupted until at least the preset backup time has elapsed.
　このように構成されたデータ記憶制御装置では、電断判断部が、主電源からの電源供給が断たれると判断した場合に、クロック信号停止部が、制御装置によるクロック信号の出力を停止させる。 In the data storage control device configured as described above, when the power interruption determination unit determines that the power supply from the main power supply is cut off, the clock signal stop unit stops the output of the clock signal by the control device. .
　これにより、メモリカードが、クロック信号の入力が停止したことを契機として、主電源からの電源供給が断たれたときの処理を実行する場合において、メモリカードは、この処理を実行するための時間として、バックアップ電源により電源が供給されるバックアップ時間を確保することができ、メモリカードに記憶されているデータの破壊を回避することができる。 As a result, when the memory card executes the process when the power supply from the main power supply is cut off when the input of the clock signal is stopped, the memory card has a time for executing this process. As a result, it is possible to secure a backup time in which power is supplied from the backup power supply, and to avoid the destruction of data stored in the memory card.
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。
本開示の一実施形態にかかるデータ記憶制御装置１の構成を示すブロック図である。 データ記憶制御装置１のメモリカード電源回路７の構成を示す回路図である。 データ記憶制御装置１の動作を示すタイミングチャートである。 データ記憶制御装置１のシャットダウン信号制御部２４およびシャットダウン信号出力部２５の動作を示す第１のタイミングチャートである。 シャットダウン信号制御部２４およびシャットダウン信号出力部２５の動作を示す第２のタイミングチャートである。 シャットダウン信号制御部２４およびシャットダウン信号出力部２５の動作を示す第３のタイミングチャートである。 シャットダウン信号制御部２４およびシャットダウン信号出力部２５の動作を示す第４のタイミングチャートである。 The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings.
It is a block diagram showing the composition of data storage control device 1 concerning one embodiment of this indication. 3 is a circuit diagram showing a configuration of a memory card power supply circuit 7 of the data storage control device 1. FIG. 3 is a timing chart showing the operation of the data storage control device 1. 3 is a first timing chart showing operations of a shutdown signal control unit 24 and a shutdown signal output unit 25 of the data storage control device 1. 6 is a second timing chart showing operations of the shutdown signal control unit 24 and the shutdown signal output unit 25. 10 is a third timing chart showing the operations of the shutdown signal control unit 24 and the shutdown signal output unit 25. FIG. FIG. 10 is a fourth timing chart showing operations of the shutdown signal control unit 24 and the shutdown signal output unit 25. FIG.
　以下に本開示の実施形態について図面とともに説明する。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.
　本開示が適用されたデータ記憶制御装置１は、車両に搭載され、図１に示すように、レギュレータ２とメインマイコン３とサブマイコン４とメモリカード５とカードスロット６とメモリカード電源回路７と電源瞬断検出回路８を備える。 A data storage control device 1 to which the present disclosure is applied is mounted on a vehicle, and as shown in FIG. 1, a regulator 2, a main microcomputer 3, a sub-microcomputer 4, a memory card 5, a card slot 6, a memory card power supply circuit 7, A power supply interruption detection circuit 8 is provided.
　レギュレータ２は、車両に搭載されたバッテリ（不図示）からメインリレー（不図示）を介して電源電圧を入力し、この電源電圧から、データ記憶制御装置１が動作するための駆動電圧（本実施形態では５Ｖ、３．３Ｖ等）を生成して出力する。以下、バッテリからメインリレーを介してデータ記憶制御装置１に供給される電圧を＋Ｂ電圧という。 The regulator 2 receives a power supply voltage from a battery (not shown) mounted on the vehicle via a main relay (not shown), and from this power supply voltage, a drive voltage (this embodiment) for operating the data storage control device 1 In the form, 5V, 3.3V, etc.) are generated and output. Hereinafter, the voltage supplied from the battery to the data storage control device 1 via the main relay is referred to as + B voltage.
　メインマイコン３は、制御対象（本実施形態ではメモリカード５）を制御するための各種処理を実行する。サブマイコン４は、制御対象（本実施形態ではレギュレータ２）を制御するための各種処理を実行する。なお、メインマイコン３とサブマイコン４は、互いにデータ通信可能に接続されている。 The main microcomputer 3 executes various processes for controlling the control target (memory card 5 in this embodiment). The sub-microcomputer 4 executes various processes for controlling the controlled object (the regulator 2 in this embodiment). Note that the main microcomputer 3 and the sub-microcomputer 4 are connected to each other so that data communication is possible.
　メモリカード５は、矩形板状に形成されているカード本体と、データ書き換え可能な不揮発性メモリと、不揮発性メモリに対するデータの書き込みと読み出しを制御するカードコントローラとを備えている。そしてメモリカード５は、カード本体内に不揮発性メモリとカードコントローラを収納して構成されている。なおメモリカード５は、本実施形態ではＳＤカード（登録商標）である。 The memory card 5 includes a card body formed in a rectangular plate shape, a data rewritable nonvolatile memory, and a card controller that controls writing and reading of data to and from the nonvolatile memory. The memory card 5 is configured by housing a nonvolatile memory and a card controller in the card body. The memory card 5 is an SD card (registered trademark) in this embodiment.
　カードスロット６は、メモリカード５を着脱可能に装着する装着部を備えている。さらにカードスロット６は、電源端子、クロック端子、コマンド端子、データ端子およびカード検出端子を備える。 The card slot 6 has a mounting portion for mounting the memory card 5 in a removable manner. Furthermore, the card slot 6 includes a power supply terminal, a clock terminal, a command terminal, a data terminal, and a card detection terminal.
　電源端子は、メモリカード５を動作させるための電圧（以下、カード動作電圧ＶＤＤという）をメモリカード電源回路７から入力するためのものである。 The power supply terminal is for inputting a voltage for operating the memory card 5 (hereinafter referred to as a card operating voltage VDD) from the memory card power supply circuit 7.
　クロック端子は、メモリカード５を動作させるためのクロック信号をメインマイコン３から入力するためのものである。なおメモリカード５は、クロック信号の入力が停止すると、その時点からバックアップ時間（本実施形態では例えば２５０ｍｓ）が経過するまでに、データ破壊回避のための内部処置を行うように構成されている。 The clock terminal is for inputting a clock signal for operating the memory card 5 from the main microcomputer 3. Note that the memory card 5 is configured to perform internal measures for avoiding data destruction until the backup time (for example, 250 ms in the present embodiment) elapses after the clock signal input stops.
　コマンド端子は、メインマイコン３との間で、メモリカード５を制御するためのコマンド信号を入出力するためのものである。データ端子は、メインマイコン３との間で、メモリカード５に対するデータの書き込みと読み出しのためのデータ信号を入出力するためのものである。 The command terminal is for inputting / outputting a command signal for controlling the memory card 5 to / from the main microcomputer 3. The data terminal is for inputting / outputting data signals to / from the memory card 5 to / from the main microcomputer 3.
　カード検出端子は、メモリカード５がカードスロット６に装着されているか否かを示すカード検出信号を出力するためのものである。本実施形態のカード検出信号は、メモリカード５がカードスロット６に装着されているときにローレベルとなり、装着されていないときにハイレベルとなる信号である。 The card detection terminal is for outputting a card detection signal indicating whether or not the memory card 5 is inserted in the card slot 6. The card detection signal of the present embodiment is a signal that is at a low level when the memory card 5 is inserted in the card slot 6 and is at a high level when the memory card 5 is not inserted.
　メモリカード電源回路７は、レギュレータ２から駆動電圧を入力して、この駆動電圧から、カード動作電圧ＶＤＤ（本実施形態では例えば３．３Ｖ）を生成して出力する。 The memory card power supply circuit 7 receives the drive voltage from the regulator 2, and generates and outputs a card operating voltage VDD (for example, 3.3 V in the present embodiment) from the drive voltage.
　電源瞬断検出回路８は、＋Ｂ電圧を入力して、＋Ｂ電圧の瞬断が発生したか否かを検出し、＋Ｂ電圧の瞬断を検出した場合に、＋Ｂ電圧の瞬断を検出した旨を示す瞬断検出信号をサブマイコン４へ出力する。なお、本実施形態の電源瞬断検出回路８は、＋Ｂ電圧が予め設定された瞬断判定値（例えば４．５Ｖ）以下である場合に、＋Ｂ電圧の瞬断が発生したと判断する。 The power supply interruption detection circuit 8 receives the + B voltage, detects whether or not the + B voltage instantaneous interruption has occurred, and detects that the + B voltage instantaneous interruption has been detected. Is output to the sub-microcomputer 4. Note that the instantaneous power interruption detection circuit 8 of the present embodiment determines that an instantaneous interruption of the + B voltage has occurred when the + B voltage is equal to or less than a preset instantaneous interruption determination value (for example, 4.5 V).
　またサブマイコン４は、電源瞬断検出回路８から瞬断検出信号を入力すると、メインマイコン３の電源を切ってメインマイコン３を強制的にシャットダウンさせる。これによりメインマイコン３は、クロック信号の出力を停止する。 Further, when the sub-microcomputer 4 inputs the instantaneous power interruption detection signal from the power supply interruption detection circuit 8, the main microcomputer 3 is turned off and the main microcomputer 3 is forcibly shut down. As a result, the main microcomputer 3 stops outputting the clock signal.
　メモリカード電源回路７は、図２に示すように、５Ｖ電圧入力端子１１と３．３Ｖ電圧入力端子１２と接地端子１３とメイン制御信号入力端子１４とサブ制御信号入力端子１５とカード検出入力端子１６とカード電圧出力端子１７とオン通知出力端子１８を備える。 As shown in FIG. 2, the memory card power supply circuit 7 includes a 5V voltage input terminal 11, a 3.3V voltage input terminal 12, a ground terminal 13, a main control signal input terminal 14, a sub control signal input terminal 15, and a card detection input terminal. 16, a card voltage output terminal 17, and an ON notification output terminal 18.
　５Ｖ電圧入力端子１１には、レギュレータ２から５Ｖの駆動電圧が入力する。３．３Ｖ電圧入力端子１２には、レギュレータ２から３．３Ｖの駆動電圧が入力する。接地端子１３はグランドに接続される。 5V drive voltage of 5V is input from the regulator 2 to the 5V voltage input terminal 11. A 3.3 V drive voltage is input from the regulator 2 to the 3.3 V voltage input terminal 12. The ground terminal 13 is connected to the ground.
　メイン制御信号入力端子１４には、メインマイコン３から、カード動作電圧ＶＤＤの出力を制御するためのメイン側カード制御信号が入力する。サブ制御信号入力端子１５には、サブマイコン４から、カード動作電圧ＶＤＤの出力を制御するためのサブ側カード制御信号が入力する。カード検出入力端子１６には、カードスロット６からカード検出信号が入力する。 The main-side card control signal for controlling the output of the card operating voltage VDD is input from the main microcomputer 3 to the main control signal input terminal 14. The sub-control signal input terminal 15 receives a sub-side card control signal for controlling the output of the card operating voltage VDD from the sub-microcomputer 4. A card detection signal is input from the card slot 6 to the card detection input terminal 16.
　またメモリカード電源回路７は、コンデンサ充電用ＩＣ２１とバックアップ用コンデンサ２２とＤＣ／ＤＣコンバータ２３とシャットダウン信号制御部２４とシャットダウン信号出力部２５と電源オン判定部２６を備える。 The memory card power supply circuit 7 includes a capacitor charging IC 21, a backup capacitor 22, a DC / DC converter 23, a shutdown signal control unit 24, a shutdown signal output unit 25, and a power-on determination unit 26.
　コンデンサ充電用ＩＣ２１は、電圧入力端子Ｖｉｎと電圧出力端子Ｖｏｕｔを有している。そしてコンデンサ充電用ＩＣ２１は、５Ｖの駆動電圧を電圧入力端子Ｖｉｎに入力して、この駆動電圧から、バックアップ用コンデンサ２２を充電するための充電用電圧（本実施形態では例えば４Ｖ）を生成し、この充電用電圧を電圧出力端子Ｖｏｕｔから出力する。 The capacitor charging IC 21 has a voltage input terminal Vin and a voltage output terminal Vout. The capacitor charging IC 21 inputs a driving voltage of 5 V to the voltage input terminal Vin, and generates a charging voltage (for example, 4 V in the present embodiment) for charging the backup capacitor 22 from the driving voltage, This charging voltage is output from the voltage output terminal Vout.
　バックアップ用コンデンサ２２は、メモリカード５のバックアップ電源であり、＋Ｂ電圧の供給停止から、少なくとも上記バックアップ時間（本実施形態では例えば２５０ｍｓ）継続してメモリカード電源回路７がカード動作電圧ＶＤＤを供給することができる静電容量に設定されている。そして、バックアップ用コンデンサ２２の正極がコンデンサ充電用ＩＣ２１の電圧出力端子Ｖｏｕｔに接続されるとともに、バックアップ用コンデンサ２２の負極が接地される。 The backup capacitor 22 is a backup power supply for the memory card 5, and the memory card power supply circuit 7 supplies the card operating voltage VDD for at least the backup time (for example, 250 ms in this embodiment) after the supply of the + B voltage is stopped. Capacitance that can be set. The positive electrode of the backup capacitor 22 is connected to the voltage output terminal Vout of the capacitor charging IC 21, and the negative electrode of the backup capacitor 22 is grounded.
　ＤＣ／ＤＣコンバータ２３は、電圧入力端子Ｖｉｎと電圧出力端子Ｖｏｕｔとシャットダウン端子ＳＨＤＮを有している。そしてＤＣ／ＤＣコンバータ２３は、コンデンサ充電用ＩＣ２１からの充電用電圧を電圧入力端子Ｖｉｎに入力して、この充電用電圧から、カード動作電圧ＶＤＤを生成し、このカード動作電圧ＶＤＤを電圧出力端子Ｖｏｕｔから出力する。またＤＣ／ＤＣコンバータ２３は、シャットダウン端子ＳＨＤＮに入力するシャットダウン信号がハイレベルである場合には、カード動作電圧ＶＤＤを出力する一方、シャットダウン信号がローレベルである場合には、カード動作電圧ＶＤＤの出力を停止する。 The DC / DC converter 23 has a voltage input terminal Vin, a voltage output terminal Vout, and a shutdown terminal SHDN. The DC / DC converter 23 inputs the charging voltage from the capacitor charging IC 21 to the voltage input terminal Vin, generates a card operating voltage VDD from the charging voltage, and uses the card operating voltage VDD as a voltage output terminal. Output from Vout. The DC / DC converter 23 outputs the card operating voltage VDD when the shutdown signal input to the shutdown terminal SHDN is at a high level, while the card operating voltage VDD is output when the shutdown signal is at a low level. Stop output.
　シャットダウン信号制御部２４は、トランジスタ３１と抵抗３２，３３，３４，３５，３６，３７とダイオード３８，３９を備える。 The shutdown signal control unit 24 includes a transistor 31, resistors 32, 33, 34, 35, 36, 37 and diodes 38, 39.
　トランジスタ３１は、ＮＰＮ型のトランジスタであり、コレクタ、ベースおよびエミッタを有する。トランジスタ３１のコレクタは、抵抗３２を介して３．３Ｖ電圧入力端子１２に接続される。トランジスタ３１のベースは、抵抗３３を介してメイン制御信号入力端子１４に接続される。トランジスタ３１のエミッタは接地端子１３に接続される。なお抵抗３４は、一端がトランジスタ３１のベースに接続され、他端が接地される。そして、メインマイコン３からのメイン側カード制御信号がハイレベルである場合において、抵抗３３，３４による抵抗３４の分圧電圧がトランジスタ３１のオン電圧より高くなるように、抵抗３３，３４の抵抗値が設定されている。 The transistor 31 is an NPN type transistor, and has a collector, a base, and an emitter. The collector of the transistor 31 is connected to the 3.3V voltage input terminal 12 through the resistor 32. The base of the transistor 31 is connected to the main control signal input terminal 14 via the resistor 33. The emitter of the transistor 31 is connected to the ground terminal 13. The resistor 34 has one end connected to the base of the transistor 31 and the other end grounded. When the main card control signal from the main microcomputer 3 is at a high level, the resistance values of the resistors 33 and 34 are set so that the divided voltage of the resistor 34 by the resistors 33 and 34 is higher than the ON voltage of the transistor 31. Is set.
　抵抗３５は、一端がメイン制御信号入力端子１４に接続されるとともに、他端が抵抗３６の一端に接続される。そして、抵抗３６の他端はシャットダウン信号出力部２５に接続される。抵抗３７は、一端がＤＣ／ＤＣコンバータ２３の電圧出力端子Ｖｏｕｔに接続されるとともに、他端がシャットダウン信号出力部２５に接続される。 The resistor 35 has one end connected to the main control signal input terminal 14 and the other end connected to one end of the resistor 36. The other end of the resistor 36 is connected to the shutdown signal output unit 25. The resistor 37 has one end connected to the voltage output terminal Vout of the DC / DC converter 23 and the other end connected to the shutdown signal output unit 25.
　ダイオード３８は、アノードが抵抗３２とトランジスタ３１のコレクタとの接続点に接続されるとともに、カソードがサブ制御信号入力端子１５に接続される。ダイオード３９は、アノードが抵抗３５と抵抗３６との接続点に接続されるとともに、カソードがサブ制御信号入力端子１５に接続される。 The diode 38 has an anode connected to a connection point between the resistor 32 and the collector of the transistor 31 and a cathode connected to the sub-control signal input terminal 15. The diode 39 has an anode connected to a connection point between the resistor 35 and the resistor 36, and a cathode connected to the sub control signal input terminal 15.
　シャットダウン信号出力部２５は、論理和回路４１とトランジスタ４２と抵抗４３，４４とダイオード４５，４６を備える。 The shutdown signal output unit 25 includes an OR circuit 41, a transistor 42, resistors 43 and 44, and diodes 45 and 46.
　論理和回路４１は、第１入力端子と第２入力端子と出力端子と電源電圧端子を有し、第１入力端子と第２入力端子に入力した信号の論理和演算を行い、演算結果を示す信号を出力端子から出力する。第１入力端子は、シャットダウン信号制御部２４の抵抗３７を介してＤＣ／ＤＣコンバータ２３の電圧出力端子Ｖｏｕｔに接続される。第２入力端子は、シャットダウン信号制御部２４におけるトランジスタ３１のコレクタに接続される。出力端子は、抵抗４３を介してＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮに接続される。 The OR circuit 41 has a first input terminal, a second input terminal, an output terminal, and a power supply voltage terminal. The OR circuit 41 performs an OR operation on signals input to the first input terminal and the second input terminal, and indicates the operation result. The signal is output from the output terminal. The first input terminal is connected to the voltage output terminal Vout of the DC / DC converter 23 via the resistor 37 of the shutdown signal control unit 24. The second input terminal is connected to the collector of the transistor 31 in the shutdown signal control unit 24. The output terminal is connected to the shutdown terminal SHDN of the DC / DC converter 23 via the resistor 43.
　トランジスタ４２は、ＮＰＮ型のトランジスタであり、コレクタ、ベースおよびエミッタを有する。トランジスタ４２のコレクタは、ＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮに接続される。トランジスタ４２のベースは、シャットダウン信号制御部２４の抵抗３５，３６を介してメイン制御信号入力端子１４に接続される。トランジスタ４２のエミッタは接地端子１３に接続される。なお抵抗４４は、一端がトランジスタ４２のベースに接続され、他端が接地される。そして、メインマイコン３からのメイン側カード制御信号がハイレベルである場合において、抵抗３５，３６，４４による抵抗４４の分圧電圧がトランジスタ４２のオン電圧より高くなるように、抵抗３５，３６，４４の抵抗値が設定されている。 The transistor 42 is an NPN type transistor and has a collector, a base, and an emitter. The collector of the transistor 42 is connected to the shutdown terminal SHDN of the DC / DC converter 23. The base of the transistor 42 is connected to the main control signal input terminal 14 via the resistors 35 and 36 of the shutdown signal control unit 24. The emitter of the transistor 42 is connected to the ground terminal 13. The resistor 44 has one end connected to the base of the transistor 42 and the other end grounded. Then, when the main-side card control signal from the main microcomputer 3 is at a high level, the resistors 35, 36, 36, 36, A resistance value of 44 is set.
　ダイオード４５は、アノードがＤＣ／ＤＣコンバータ２３の電圧出力端子Ｖｏｕｔに接続されるとともに、カソードが論理和回路４１の電源電圧端子にされる。ダイオード４６は、アノードがコンデンサ充電用ＩＣ２１の電圧出力端子Ｖｏｕｔに接続されるとともに、カソードが論理和回路４１の電源電圧端子にされる。 The diode 45 has an anode connected to the voltage output terminal Vout of the DC / DC converter 23 and a cathode connected to the power supply voltage terminal of the OR circuit 41. The diode 46 has an anode connected to the voltage output terminal Vout of the capacitor charging IC 21 and a cathode connected to the power supply voltage terminal of the OR circuit 41.
　電源オン判定部２６は、否定論理和回路５１とトランジスタ５２，５３と抵抗５４，５５，５６，５７，５８，５９を備える。 The power-on determination unit 26 includes a negative OR circuit 51, transistors 52 and 53, and resistors 54, 55, 56, 57, 58, and 59.
　否定論理和回路５１は、第１入力端子と第２入力端子と出力端子と電源電圧端子を有し、第１入力端子と第２入力端子に入力した信号の否定論理和演算を行い、演算結果を示す信号を出力端子から出力する。第１入力端子は、トランジスタ５２のコレクタに接続される。第２入力端子は、カード検出入力端子１６に接続される。出力端子は、抵抗５４を介してトランジスタ５３のベースに接続される。 The negative OR circuit 51 has a first input terminal, a second input terminal, an output terminal, and a power supply voltage terminal, performs a negative OR operation on signals input to the first input terminal and the second input terminal, and obtains an operation result. Is output from the output terminal. The first input terminal is connected to the collector of the transistor 52. The second input terminal is connected to the card detection input terminal 16. The output terminal is connected to the base of the transistor 53 via the resistor 54.
　トランジスタ５２は、ＮＰＮ型のトランジスタであり、コレクタ、ベースおよびエミッタを有する。トランジスタ５２のコレクタは、抵抗５５を介して３．３Ｖ電圧入力端子１２に接続される。トランジスタ５２のベースは、抵抗５６を介してコンデンサ充電用ＩＣ２１の電圧出力端子Ｖｏｕｔに接続される。トランジスタ５２のエミッタは接地端子１３に接続される。なお抵抗５７は、一端がトランジスタ５２のベースに接続され、他端が接地される。そして、バックアップ用コンデンサ２２の電圧がバックアップ可能電圧（本実施形態では例えば１．３Ｖ）以上である場合において、抵抗５６，５７による抵抗５７の分圧電圧がトランジスタ５２のオン電圧より高くなるように、抵抗５６，５７の抵抗値が設定されている。なおバックアップ可能電圧は、バックアップ用コンデンサ２２がバックアップ時間分の電荷量を蓄積することができる電圧である。 The transistor 52 is an NPN type transistor, and has a collector, a base, and an emitter. The collector of the transistor 52 is connected to the 3.3V voltage input terminal 12 through the resistor 55. The base of the transistor 52 is connected to the voltage output terminal Vout of the capacitor charging IC 21 via the resistor 56. The emitter of the transistor 52 is connected to the ground terminal 13. The resistor 57 has one end connected to the base of the transistor 52 and the other end grounded. When the voltage of the backup capacitor 22 is equal to or higher than the backup possible voltage (eg, 1.3 V in this embodiment), the divided voltage of the resistor 57 by the resistors 56 and 57 is set higher than the ON voltage of the transistor 52. The resistance values of the resistors 56 and 57 are set. The backup-capable voltage is a voltage at which the backup capacitor 22 can accumulate a charge amount for the backup time.
　トランジスタ５３は、ＮＰＮ型のトランジスタであり、コレクタ、ベースおよびエミッタを有する。トランジスタ５３のコレクタは、オン通知出力端子１８に接続され、メインマイコン３に接続されている。なお、トランジスタ５３はメインマイコン３側の入力電圧に合わせられるように設けており、オン通知出力端子１８はマイコンの入力電圧でプルアップされている必要がある（図示せず）。トランジスタ５３のベースは、抵抗５４を介して否定論理和回路５１の出力端子に接続される。トランジスタ５３のエミッタは接地端子１３に接続される。なお抵抗５８は、一端がトランジスタ５３のベースに接続され、他端が接地される。そして、否定論理和回路５１からの出力信号がハイレベルである場合において、抵抗５４，５８による抵抗５８の分圧電圧がトランジスタ５３のオン電圧より高くなるように、抵抗５４，５８の抵抗値が設定されている。 The transistor 53 is an NPN type transistor, and has a collector, a base, and an emitter. The collector of the transistor 53 is connected to the ON notification output terminal 18 and is connected to the main microcomputer 3. The transistor 53 is provided so as to match the input voltage on the main microcomputer 3 side, and the ON notification output terminal 18 needs to be pulled up by the input voltage of the microcomputer (not shown). The base of the transistor 53 is connected to the output terminal of the NOR circuit 51 through the resistor 54. The emitter of the transistor 53 is connected to the ground terminal 13. The resistor 58 has one end connected to the base of the transistor 53 and the other end grounded. When the output signal from the NOR circuit 51 is at a high level, the resistance values of the resistors 54 and 58 are set so that the divided voltage of the resistor 58 by the resistors 54 and 58 is higher than the ON voltage of the transistor 53. Is set.
　抵抗５９は、一端が３．３Ｖ電圧入力端子１２に接続されるとともに、他端がカード検出入力端子１６に接続される。 The resistor 59 has one end connected to the 3.3V voltage input terminal 12 and the other end connected to the card detection input terminal 16.
　このように構成された電源オン判定部２６では、バックアップ用コンデンサ２２の充電によりバックアップ用コンデンサ２２の電圧が上昇すると、トランジスタ５２がオン状態となり、否定論理和回路５１の第１入力端子がローレベルとなる。また、カード検出入力端子１６がローレベルである場合に、否定論理和回路５１の第２入力端子がローレベルとなる。 In the power-on determination unit 26 configured as described above, when the voltage of the backup capacitor 22 rises due to the charging of the backup capacitor 22, the transistor 52 is turned on, and the first input terminal of the negative OR circuit 51 is at the low level. It becomes. Further, when the card detection input terminal 16 is at a low level, the second input terminal of the NOR circuit 51 is at a low level.
　すなわち、否定論理和回路５１の出力端子は、バックアップ用コンデンサ２２が充電されており且つメモリカード５がカードスロット６に装着されている場合にハイレベルになり、それ以外の場合にローレベルになる。 That is, the output terminal of the NOR circuit 51 becomes high level when the backup capacitor 22 is charged and the memory card 5 is inserted in the card slot 6, and becomes low level in other cases. .
　そして、否定論理和回路５１の出力端子がハイレベルのときに、トランジスタ５３がオン状態となり、オン通知出力端子１８がローレベルになる。 When the output terminal of the negative OR circuit 51 is at a high level, the transistor 53 is turned on and the on notification output terminal 18 is at a low level.
　次に、このように構成されたデータ記憶制御装置１の動作の具体例を説明する。 Next, a specific example of the operation of the data storage control device 1 configured as described above will be described.
　図３に示すように、まず、時刻ｔ０１でデータ記憶制御装置１の電源がオンになると（時刻ｔ０１における＋Ｂ電圧を参照）、レギュレータ２が動作を開始し、レギュレータ２から５Ｖの駆動電圧が出力される。これにより、コンデンサ充電用ＩＣ２１の電圧入力端子Ｖｉｎに５Ｖの駆動電圧が入力し、コンデンサ充電用ＩＣ２１が動作を開始する。これにより、コンデンサ充電用ＩＣ２１の電圧出力端子Ｖｏｕｔの電圧が、充電用電圧（本実施形態では４Ｖ）になり、バックアップ用コンデンサ２２の電圧と、ＤＣ／ＤＣコンバータ２３の電圧入力端子Ｖｉｎの電圧が、充電用電圧（４Ｖ）になるまで徐々に上昇する。 As shown in FIG. 3, first, when the power of the data storage control device 1 is turned on at time t01 (see the + B voltage at time t01), the regulator 2 starts to operate, and a drive voltage of 5 V is output from the regulator 2. Is done. As a result, a drive voltage of 5 V is input to the voltage input terminal Vin of the capacitor charging IC 21 and the capacitor charging IC 21 starts operating. As a result, the voltage at the voltage output terminal Vout of the capacitor charging IC 21 becomes the charging voltage (4 V in this embodiment), and the voltage of the backup capacitor 22 and the voltage of the voltage input terminal Vin of the DC / DC converter 23 are reduced. The voltage gradually increases until the charging voltage (4 V) is reached.
　また、バックアップ用コンデンサ２２の電圧がバックアップ可能電圧（本実施形態では例えば１．３Ｖ）になると、メモリカード電源回路７は、オン通知出力端子１８の電圧をローレベルにすることにより、ローレベルのオン可能通知を出力する（矢印ＡＬ１を参照）。メインマイコン３は、レギュレータ２から５Ｖの駆動電圧の供給されることにより電源がオンになる。その後、メインマイコン３では、初期化中の時刻ｔ０２でポート設定が終了し、メイン制御信号入力端子１４がハイレベルに論理固定される（矢印ＡＬ２を参照）。その後、時刻ｔ０３で、サブマイコン４は、サブ制御信号入力端子１５をハイレベルにする。なおサブマイコン４は、メインマイコン３の電源がオンになってから２５０ｍｓ以上経過した後に、サブ制御信号入力端子１５をハイレベルにする。これは、メインマイコン３のハードリセット時などでメインマイコン３からのクロック類が止まった場合に２５０ｍｓの電源保持時間が必要となり、いかなる状態でも２５０ｍｓの電源保持時間を守るためである。 In addition, when the voltage of the backup capacitor 22 becomes a backupable voltage (eg, 1.3 V in this embodiment), the memory card power supply circuit 7 sets the voltage of the ON notification output terminal 18 to a low level, thereby reducing the low level. An ON-enabled notification is output (see arrow AL1). The main microcomputer 3 is turned on when a drive voltage of 5 V is supplied from the regulator 2. Thereafter, in the main microcomputer 3, the port setting is completed at time t02 during initialization, and the main control signal input terminal 14 is logically fixed to the high level (see arrow AL2). Thereafter, at time t03, the sub microcomputer 4 sets the sub control signal input terminal 15 to the high level. The sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level after 250 ms or more has elapsed since the main microcomputer 3 was turned on. This is because a power holding time of 250 ms is required when the clocks from the main microcomputer 3 are stopped due to a hard reset of the main microcomputer 3, and the power holding time of 250 ms is protected in any state.
　時刻ｔ０４で充電期間が終わり、このときに、オン通知出力端子１８がローレベルである場合に、メインマイコン３は、メイン制御信号入力端子１４をローレベルにする。これにより、ＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがハイレベルになり、ＤＣ／ＤＣコンバータ２３が動作を開始し、ＤＣ／ＤＣコンバータ２３の電圧出力端子Ｖｏｕｔからカード動作電圧ＶＤＤを出力する。なおメインマイコン３は、サブ制御信号入力端子１５がハイレベルになってから放電時間（本実施形態では例えば１０ｍｓ）経過した後に、メイン制御信号入力端子１４をローレベルにする。この放電時間は、メモリカード５の電源（ＤＣ／ＤＣコンバータ２３）の電圧を確実に落としておくために必要とする時間である。一方、充電期間が終わったときにオン通知出力端子１８がハイレベルである場合には、メインマイコン３は、メイン制御信号入力端子１４をローレベルにしない。これにより、ＤＣ／ＤＣコンバータ２３の動作が禁止され、メモリカード５の電源が入らないようにできる。 When the charging period ends at time t04 and the ON notification output terminal 18 is at the low level at this time, the main microcomputer 3 sets the main control signal input terminal 14 to the low level. As a result, the shutdown terminal SHDN of the DC / DC converter 23 becomes high level, the DC / DC converter 23 starts to operate, and the card operating voltage VDD is output from the voltage output terminal Vout of the DC / DC converter 23. The main microcomputer 3 sets the main control signal input terminal 14 to a low level after a discharge time (for example, 10 ms in the present embodiment) has elapsed since the sub control signal input terminal 15 has become a high level. This discharge time is a time required for reliably dropping the voltage of the power supply (DC / DC converter 23) of the memory card 5. On the other hand, when the ON notification output terminal 18 is at the high level when the charging period ends, the main microcomputer 3 does not set the main control signal input terminal 14 to the low level. Thereby, the operation of the DC / DC converter 23 is prohibited and the memory card 5 can be prevented from being turned on.
　時刻ｔ０５で、例えば＋Ｂ電圧の瞬断により、５Ｖ駆動電圧の供給が停止すると、バックアップ用コンデンサ２２からＤＣ／ＤＣコンバータ２３へ電源が供給される。これにより、少なくとも２５０ｍｓの間（図中のバックアップ期間（時刻ｔ０５～ｔ０６）を参照）、ＤＣ／ＤＣコンバータ２３は電圧出力端子Ｖｏｕｔからカード動作電圧ＶＤＤを出力する。 At time t05, for example, when the supply of 5V drive voltage is stopped due to an instantaneous interruption of the + B voltage, power is supplied from the backup capacitor 22 to the DC / DC converter 23. Thus, the DC / DC converter 23 outputs the card operating voltage VDD from the voltage output terminal Vout for at least 250 ms (refer to the backup period (time t05 to t06) in the figure).
　その後、バックアップ用コンデンサ２２の電圧がＤＣ／ＤＣコンバータ２３の動作可能電圧より低くなったり、論理和回路４１への電源供給が停止してＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがローレベルになったりすることにより、時刻ｔ０６で、ＤＣ／ＤＣコンバータ２３からのカード動作電圧ＶＤＤの出力が停止する。 Thereafter, the voltage of the backup capacitor 22 becomes lower than the operable voltage of the DC / DC converter 23, the power supply to the OR circuit 41 is stopped, and the shutdown terminal SHDN of the DC / DC converter 23 becomes low level. Thus, the output of the card operating voltage VDD from the DC / DC converter 23 is stopped at time t06.
　その後、時刻ｔ０７で＋Ｂ電圧が回復すると、充電期間となり、時刻ｔ０８まで、時刻ｔ０１から時刻ｔ０２までの充電期間と同様に動作する。次に時刻ｔ０８で、通常動作に移行し、時刻ｔ０４から時刻ｔ０５までの通常動作と同様に動作する。 After that, when the + B voltage recovers at time t07, the charging period starts, and the operation is performed up to time t08 in the same manner as the charging period from time t01 to time t02. Next, at time t08, the operation shifts to normal operation, and the same operation as normal operation from time t04 to time t05 is performed.
　その後、時刻ｔ０９で、ＡＣＣ電源がオフになると、ディレイドＡＣＣに移行する。ディレイドＡＣＣは、メインマイコン３を安全に終了させるために、ＡＣＣ電源のオフ後に実行する処理である。そして、時刻ｔ１０でディレイドＡＣＣが完了すると、メインマイコン３は、メイン制御信号入力端子１４をハイレベルにする。これにより、ＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがローレベルになり、ＤＣ／ＤＣコンバータ２３からのカード動作電圧ＶＤＤの出力が停止する。 After that, when the ACC power is turned off at time t09, the operation shifts to the delayed ACC. The delayed ACC is a process executed after the ACC power supply is turned off in order to terminate the main microcomputer 3 safely. When the delayed ACC is completed at time t10, the main microcomputer 3 sets the main control signal input terminal 14 to the high level. As a result, the shutdown terminal SHDN of the DC / DC converter 23 becomes low level, and the output of the card operating voltage VDD from the DC / DC converter 23 is stopped.
　ＤＣ／ＤＣコンバータ２３の出力停止から放電時間（本実施形態では例えば１０ｍｓ）が経過した時刻ｔ１１で、サブマイコン４は、サブ制御信号入力端子１５をローレベルにする。その後、時刻ｔ１２で、メインマイコン３の電源をオフにし（矢印ＡＬ３を参照）、システムシャットダウンを行う。 The sub-microcomputer 4 sets the sub-control signal input terminal 15 to the low level at time t11 when the discharge time (for example, 10 ms in the present embodiment) has elapsed since the output stop of the DC / DC converter 23. Thereafter, at time t12, the main microcomputer 3 is turned off (see arrow AL3), and the system is shut down.
　次に、シャットダウン信号制御部２４およびシャットダウン信号出力部２５の動作の具体例を説明する。 Next, specific examples of operations of the shutdown signal control unit 24 and the shutdown signal output unit 25 will be described.
　図４は、バックアップ用コンデンサ２２の電圧が０Ｖである状態でＡＣＣ電源がオンになる場合のシャットダウン信号制御部２４およびシャットダウン信号出力部２５の動作を示すタイミングチャートである。 FIG. 4 is a timing chart showing the operations of the shutdown signal control unit 24 and the shutdown signal output unit 25 when the ACC power supply is turned on in a state where the voltage of the backup capacitor 22 is 0V.
　図４に示すように、ＡＣＣ電源がオンになると、＋Ｂ電圧がデータ記憶制御装置１に入力することにより（時刻ｔ２１における＋Ｂ電圧を参照）、レギュレータ２が動作を開始し、レギュレータ２から５Ｖと３．３Ｖの駆動電圧が出力される（時刻ｔ２２における５Ｖ駆動電圧および３．３Ｖ駆動電圧を参照）。これにより、コンデンサ充電用ＩＣ２１の電圧入力端子Ｖｉｎに５Ｖの駆動電圧が入力し、コンデンサ充電用ＩＣ２１が動作を開始する。これにより、バックアップ用コンデンサ２２の電圧と、ＤＣ／ＤＣコンバータ２３の電圧入力端子Ｖｉｎの電圧が、充電用電圧（４Ｖ）になるまで徐々に上昇する。 As shown in FIG. 4, when the ACC power supply is turned on, the + B voltage is input to the data storage control device 1 (see the + B voltage at time t21), whereby the regulator 2 starts to operate, A drive voltage of 3.3V is output (see 5V drive voltage and 3.3V drive voltage at time t22). As a result, a drive voltage of 5 V is input to the voltage input terminal Vin of the capacitor charging IC 21 and the capacitor charging IC 21 starts operating. Thereby, the voltage of the backup capacitor 22 and the voltage of the voltage input terminal Vin of the DC / DC converter 23 are gradually increased until the voltage for charging (4 V) is reached.
　その後、時刻ｔ２３でメインマイコン３の電源がオンになり（矢印ＡＬ２１を参照）、メイン制御信号入力端子１４がハイレベルに論理固定される。これにより、トランジスタ３１のベースにオン電圧が印加され、トランジスタ３１がオン状態となる。なお、トランジスタ３１がオン状態となる前にサブ制御信号入力端子１５がローレベルであるため、トランジスタ３１がオン状態となる前後で、論理和回路４１の第２入力端子の電圧レベルは変化せず、ローレベルのままである。 Thereafter, at time t23, the main microcomputer 3 is turned on (see arrow AL21), and the main control signal input terminal 14 is logically fixed to the high level. Accordingly, an on-voltage is applied to the base of the transistor 31, and the transistor 31 is turned on. Since the sub control signal input terminal 15 is at a low level before the transistor 31 is turned on, the voltage level of the second input terminal of the OR circuit 41 does not change before and after the transistor 31 is turned on. , Remain at low level.
　また、このときのサブ制御信号入力端子１５はローレベルであるため、トランジスタ４２のベースにはオン電圧が印加されず、トランジスタ４２はオフ状態である。 Further, since the sub control signal input terminal 15 at this time is at a low level, the on-voltage is not applied to the base of the transistor 42, and the transistor 42 is in the off state.
　その後、メインマイコン３の初期化が完了すると（矢印ＡＬ２２を参照）、時刻ｔ２４で、サブマイコン４は、サブ制御信号入力端子１５をハイレベルにする。なおサブマイコン４は、メインマイコン３の電源がオンになってから２５０ｍｓ以上経過した後に、サブ制御信号入力端子１５をハイレベルにする。 Thereafter, when initialization of the main microcomputer 3 is completed (see arrow AL22), the sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level at time t24. The sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level after 250 ms or more has elapsed since the main microcomputer 3 was turned on.
　そして、サブ制御信号入力端子１５をハイレベルにすることにより、トランジスタ４２のベースにオン電圧が印加され、トランジスタ４２がオン状態となる。 Then, by setting the sub control signal input terminal 15 to the high level, an on voltage is applied to the base of the transistor 42, and the transistor 42 is turned on.
　次に、サブ制御信号入力端子１５がハイレベルになってから放電時間（１０ｍｓ）が経過した時刻ｔ２５で、メインマイコン３は、メイン制御信号入力端子１４をローレベルにする。これにより、トランジスタ３１がオフ状態となり、論理和回路４１の第２入力端子がハイレベルになる。このため、論理和回路４１の出力端子がハイレベルになる。さらに、トランジスタ４２がオフ状態となることにより、ＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがハイレベルになり、ＤＣ／ＤＣコンバータ２３が動作を開始する。これにより、論理和回路４１の第１入力端子がハイレベルになる。 Next, at time t25 when the discharge time (10 ms) has elapsed after the sub control signal input terminal 15 becomes high level, the main microcomputer 3 sets the main control signal input terminal 14 to low level. As a result, the transistor 31 is turned off, and the second input terminal of the OR circuit 41 becomes high level. For this reason, the output terminal of the OR circuit 41 becomes high level. Further, when the transistor 42 is turned off, the shutdown terminal SHDN of the DC / DC converter 23 becomes high level, and the DC / DC converter 23 starts to operate. As a result, the first input terminal of the OR circuit 41 becomes high level.
　図５は、＋Ｂ電圧の瞬断が発生する場合のシャットダウン信号制御部２４およびシャットダウン信号出力部２５の動作を示すタイミングチャートである。 FIG. 5 is a timing chart showing the operation of the shutdown signal control unit 24 and the shutdown signal output unit 25 when an instantaneous interruption of the + B voltage occurs.
　図５に示すように、時刻ｔ３１で、＋Ｂ電圧の瞬断が発生すると、電源瞬断検出回路８はサブマイコン４へ瞬断検出信号を出力する。そしてサブマイコン４は、瞬断検出信号が入力すると、サブ制御信号入力端子１５をローレベルにする。これにより、論理和回路４１の第２入力端子がローレベルになる。 As shown in FIG. 5, when + B voltage instantaneous interruption occurs at time t31, the power supply interruption detection circuit 8 outputs an instantaneous interruption detection signal to the sub-microcomputer 4. Then, when the instantaneous interruption detection signal is input, the sub microcomputer 4 sets the sub control signal input terminal 15 to the low level. As a result, the second input terminal of the OR circuit 41 becomes low level.
　その後、時刻ｔ３２で、メインマイコン３がリセットされることで（矢印ＡＬ３１を参照）、メイン制御信号入力端子１４がハイレベルになる。これにより、トランジスタ３１のベースにオン電圧が印加され、トランジスタ３１がオン状態となる。さらに、時刻ｔ３３で、メインマイコン３の電源がオフになることで（矢印ＡＬ３２を参照）、メイン制御信号入力端子１４の電圧レベルが不定になり、トランジスタ３１がオフ状態となる。 Thereafter, at time t32, the main microcomputer 3 is reset (see arrow AL31), so that the main control signal input terminal 14 becomes high level. Accordingly, an on-voltage is applied to the base of the transistor 31, and the transistor 31 is turned on. Further, at time t33, the main microcomputer 3 is turned off (see arrow AL32), the voltage level of the main control signal input terminal 14 becomes indefinite, and the transistor 31 is turned off.
　その後、時刻ｔ３４で、５Ｖと３．３Ｖの駆動電圧が低下し始める。ここで、５Ｖの駆動電圧の低下により、コンデンサ充電用ＩＣ２１の電圧出力端子Ｖｏｕｔの電圧が低下し、これに追従して、ＤＣ／ＤＣコンバータ２３の電圧入力端子Ｖｉｎと論理和回路４１の電源電圧端子の電圧が低下する。但し、論理和回路４１の電源電圧端子には、ダイオード４５を介してＤＣ／ＤＣコンバータ２３からカード動作電圧ＶＤＤ（３．３Ｖ）が入力する。このため、論理和回路４１の電源電圧端子における電圧低下は、カード動作電圧ＶＤＤ（３．３Ｖ）になった時点で一旦終了し、論理和回路４１の電源電圧端子の電圧は、カード動作電圧ＶＤＤ（３．３Ｖ）に保持される。 After that, at time t34, the drive voltages of 5V and 3.3V start to decrease. Here, the voltage of the voltage output terminal Vout of the capacitor charging IC 21 decreases due to the decrease of the driving voltage of 5 V, and the voltage input terminal Vin of the DC / DC converter 23 and the power supply voltage of the OR circuit 41 follow this. The terminal voltage drops. However, the card operating voltage VDD (3.3 V) is input from the DC / DC converter 23 to the power supply voltage terminal of the OR circuit 41 through the diode 45. For this reason, the voltage drop at the power supply voltage terminal of the OR circuit 41 is temporarily stopped when the card operation voltage VDD (3.3 V) is reached, and the voltage at the power supply voltage terminal of the OR circuit 41 is reduced to the card operation voltage VDD. Held at (3.3V).
　そして時刻ｔ３５で、ＤＣ／ＤＣコンバータ２３の電圧入力端子Ｖｉｎの電圧が、ＤＣ／ＤＣコンバータ２３の動作可能電圧を下回ると、ＤＣ／ＤＣコンバータ２３からのカード動作電圧ＶＤＤの出力が停止される。このため、論理和回路４１の第１入力端子と電源電圧端子の電圧がカード動作電圧ＶＤＤ（３．３Ｖ）から低下し始め、ＤＣ／ＤＣコンバータ２３の放電時間で０Ｖになる。これにより、論理和回路４１の出力端子がハイレベルからローレベルになり、これに追従して、ＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがハイレベルからローレベルになる。 At time t35, when the voltage at the voltage input terminal Vin of the DC / DC converter 23 falls below the operable voltage of the DC / DC converter 23, the output of the card operating voltage VDD from the DC / DC converter 23 is stopped. For this reason, the voltage of the first input terminal and the power supply voltage terminal of the OR circuit 41 starts to decrease from the card operating voltage VDD (3.3 V), and becomes 0 V in the discharge time of the DC / DC converter 23. As a result, the output terminal of the OR circuit 41 changes from the high level to the low level, and following this, the shutdown terminal SHDN of the DC / DC converter 23 changes from the high level to the low level.
　図６は、ＡＣＣ電源をオフにした場合のシャットダウン信号制御部２４およびシャットダウン信号出力部２５の動作を示すタイミングチャートである。 FIG. 6 is a timing chart showing operations of the shutdown signal control unit 24 and the shutdown signal output unit 25 when the ACC power supply is turned off.
　ＡＣＣ電源がオフになると、ディレイドＡＣＣに移行する。そして、図６に示すように、時刻ｔ４１でディレイドＡＣＣが完了すると（矢印ＡＬ４１を参照）、メインマイコン３は、メイン制御信号入力端子１４をハイレベルにする。このときにサブ制御信号入力端子１５がハイレベルであるため、トランジスタ３１，４２のベースにオン電圧が印加され、トランジスタ３１，４２がオン状態となる。これにより、論理和回路４１の第２入力端子とＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがハイレベルからローレベルになる。そして、ＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがローレベルになることにより、ＤＣ／ＤＣコンバータ２３からのカード動作電圧ＶＤＤの出力が停止する。 ∙ When the ACC power is turned off, the system shifts to delayed ACC. As shown in FIG. 6, when the delayed ACC is completed at time t41 (see arrow AL41), the main microcomputer 3 sets the main control signal input terminal 14 to the high level. At this time, since the sub control signal input terminal 15 is at a high level, an on-voltage is applied to the bases of the transistors 31 and 42, and the transistors 31 and 42 are turned on. As a result, the second input terminal of the OR circuit 41 and the shutdown terminal SHDN of the DC / DC converter 23 change from the high level to the low level. Then, when the shutdown terminal SHDN of the DC / DC converter 23 becomes low level, the output of the card operating voltage VDD from the DC / DC converter 23 is stopped.
　さらに、ＤＣ／ＤＣコンバータ２３の出力停止から放電時間が経過した時刻ｔ４２で、サブマイコン４は、サブ制御信号入力端子１５をローレベルにする。その後、時刻ｔ４３で、メインマイコン３の電源をオフにする。 Furthermore, at time t42 when the discharge time has elapsed since the output of the DC / DC converter 23 is stopped, the sub microcomputer 4 sets the sub control signal input terminal 15 to the low level. Thereafter, at time t43, the main microcomputer 3 is turned off.
　図７は、メインマイコン３がリセットされる場合のシャットダウン信号制御部２４およびシャットダウン信号出力部２５の動作を示すタイミングチャートである。 FIG. 7 is a timing chart showing operations of the shutdown signal control unit 24 and the shutdown signal output unit 25 when the main microcomputer 3 is reset.
　図７に示すように、メインマイコン３が暴走してリセットをかける前の時刻ｔ５１で、サブマイコン４は、サブ制御信号入力端子１５をハイレベルからローレベルにする。これにより、論理和回路４１の第２入力端子がハイレベルからローレベルになる。 As shown in FIG. 7, at time t51 before the main microcomputer 3 runs out of control and resets, the sub microcomputer 4 changes the sub control signal input terminal 15 from the high level to the low level. As a result, the second input terminal of the OR circuit 41 changes from the high level to the low level.
　その後、時刻ｔ５２で、メインマイコン３がリセットされることで（矢印ＡＬ５１を参照）、メイン制御信号入力端子１４がハイレベルになる。これにより、トランジスタ３１がオン状態となる。 Thereafter, at time t52, the main microcomputer 3 is reset (see arrow AL51), so that the main control signal input terminal 14 becomes high level. Accordingly, the transistor 31 is turned on.
　その後、メインマイコン３の初期化が完了すると（矢印ＡＬ５２を参照）、時刻ｔ５３で、サブマイコン４は、サブ制御信号入力端子１５をハイレベルにする。なおサブマイコン４は、メインマイコン３の電源がオンになってから２５０ｍｓ以上経過した後に、サブ制御信号入力端子１５をハイレベルにする。これにより、トランジスタ４２がオン状態となり、ＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがハイレベルからローレベルになる。ＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがローレベルになることにより、ＤＣ／ＤＣコンバータ２３からのカード動作電圧ＶＤＤの出力が停止する。 Thereafter, when the initialization of the main microcomputer 3 is completed (see arrow AL52), the sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level at time t53. The sub-microcomputer 4 sets the sub-control signal input terminal 15 to the high level after 250 ms or more has elapsed since the main microcomputer 3 was turned on. Thereby, the transistor 42 is turned on, and the shutdown terminal SHDN of the DC / DC converter 23 is changed from the high level to the low level. When the shutdown terminal SHDN of the DC / DC converter 23 becomes low level, the output of the card operating voltage VDD from the DC / DC converter 23 is stopped.
　サブ制御信号入力端子１５がハイレベルになってから放電時間が経過した時刻ｔ５４で、メインマイコン３は、メイン制御信号入力端子１４をローレベルにする。これにより、トランジスタ３１，４２がオフ状態となる。まず、トランジスタ３１がオフ状態となることにより、論理和回路４１の第２入力端子がローレベルからハイレベルになり、これにより、論理和回路４１の出力端子がローレベルからハイレベルになる。また、トランジスタ４２がオフ状態となることにより、ＤＣ／ＤＣコンバータ２３のシャットダウン端子ＳＨＤＮがローレベルからハイレベルになる。これにより、ＤＣ／ＤＣコンバータ２３からのカード動作電圧ＶＤＤの出力が再開される。 The main microcomputer 3 sets the main control signal input terminal 14 to low level at time t54 when the discharge time has elapsed since the sub control signal input terminal 15 became high level. Thereby, the transistors 31 and 42 are turned off. First, when the transistor 31 is turned off, the second input terminal of the OR circuit 41 is changed from low level to high level, and thereby the output terminal of the OR circuit 41 is changed from low level to high level. Further, when the transistor 42 is turned off, the shutdown terminal SHDN of the DC / DC converter 23 is changed from the low level to the high level. As a result, the output of the card operating voltage VDD from the DC / DC converter 23 is resumed.
　このように構成されたデータ記憶制御装置１は、メインマイコン３と、電源瞬断検出回路８と、サブマイコン４と、バックアップ用コンデンサ２２とを備える。 The data storage control device 1 configured as described above includes a main microcomputer 3, a power supply interruption detection circuit 8, a sub-microcomputer 4, and a backup capacitor 22.
　メインマイコン３は、外部から電源供給を受けて動作するとともに外部から入力するクロック信号に同期して動作するメモリカード５へ、少なくともクロック信号を出力することによりメモリカード５を制御する。 The main microcomputer 3 operates with power supplied from the outside and controls the memory card 5 by outputting at least a clock signal to the memory card 5 operating in synchronization with a clock signal input from the outside.
　また電源瞬断検出回路８は、＋Ｂ電圧が予め設定された瞬断判定値（例えば４．５Ｖ）以下である場合に、＋Ｂ電圧の瞬断が発生したと判断する。そしてサブマイコン４は、＋Ｂ電圧の瞬断が発生したと電源瞬断検出回路８が判断した場合に、メインマイコン３の電源を切ってメインマイコン３を強制的にシャットダウンさせることにより、メインマイコン３によるクロック信号の出力を停止させる。 The power supply interruption detection circuit 8 determines that the + B voltage instantaneous interruption has occurred when the + B voltage is equal to or less than a predetermined instantaneous interruption determination value (for example, 4.5 V). The sub-microcomputer 4 turns off the main microcomputer 3 and forcibly shuts down the main microcomputer 3 when the power supply interruption detection circuit 8 determines that an instantaneous interruption of the + B voltage has occurred. The output of the clock signal by is stopped.
　またバックアップ用コンデンサ２２は、＋Ｂ電圧が断たれてから、少なくとも予め設定されたバックアップ時間（例えば２５０ｍｓ）が経過するまで継続してメモリカード５へ電源を供給する。 Further, the backup capacitor 22 continuously supplies power to the memory card 5 after the + B voltage is cut off until at least a preset backup time (for example, 250 ms) elapses.
　このように構成されたデータ記憶制御装置１では、電源瞬断検出回路８が、＋Ｂ電圧の瞬断が発生したと判断した場合に、サブマイコン４が、メインマイコン３によるクロック信号の出力を停止させる。 In the data storage control device 1 configured as described above, the sub-microcomputer 4 stops the output of the clock signal from the main microcomputer 3 when the power supply interruption detection circuit 8 determines that the + B voltage instantaneous interruption has occurred. Let
　これにより、メモリカード５が、クロック信号の入力が停止したことを契機として、＋Ｂ電圧が断たれたときの処理を実行する場合において、メモリカード５は、この処理を実行するための時間として、バックアップ用コンデンサ２２により電源が供給されるバックアップ時間を確保することができ、メモリカード５に記憶されているデータの破壊を回避することができる。 As a result, when the memory card 5 executes the process when the + B voltage is cut off when the input of the clock signal is stopped, the memory card 5 sets the time for executing this process as A backup time during which power is supplied by the backup capacitor 22 can be secured, and destruction of data stored in the memory card 5 can be avoided.
　以上説明した実施形態において、メインマイコン３は制御装置、＋Ｂ電圧は主電源、電源瞬断検出回路８は電断判断部、サブマイコン４はクロック信号停止部、バックアップ用コンデンサ２２はバックアップ電源に相当する。 In the embodiment described above, the main microcomputer 3 corresponds to the control device, the + B voltage corresponds to the main power supply, the power supply interruption detection circuit 8 corresponds to the interruption determination part, the sub microcomputer 4 corresponds to the clock signal stop part, and the backup capacitor 22 corresponds to the backup power supply. To do.
　以上、本開示の一実施形態について説明したが、本開示は上記実施形態に限定されるものではなく、本開示の技術的範囲に属する限り種々の形態を採ることができる。 As mentioned above, although one embodiment of this indication was explained, this indication is not limited to the above-mentioned embodiment, and can take various forms, as long as it belongs to the technical scope of this indication.
　例えば上記実施形態では、メモリカードとしてＳＤカードを用いたものを示したが、ＳＤカードに限定されるものではなく、電源供給が断たれたときに、既に記憶されているデータの破壊を回避するための処理を行う機能を備えた記憶媒体であればよい。 For example, in the above-described embodiment, an SD card is used as a memory card. However, the present invention is not limited to the SD card, and when the power supply is cut off, destruction of already stored data is avoided. Any storage medium provided with a function for performing the processing for this purpose may be used.
　また上記実施形態では、サブマイコン４に瞬断検出信号が入力すると、メインマイコン３の電源を切ってメインマイコン３を強制的にシャットダウンさせるものを示した。しかし、メインマイコン３によるクロック信号の出力を停止させる方法はこれに限定されるものではなく、例えば、サブマイコン４に瞬断検出信号が入力すると、クロック信号の出力を停止することを指示するクロック信号停止信号をメインマイコン３へ出力するようにしてもよい。 In the above-described embodiment, when the instantaneous interruption detection signal is input to the sub-microcomputer 4, the main microcomputer 3 is turned off and the main microcomputer 3 is forcibly shut down. However, the method of stopping the output of the clock signal by the main microcomputer 3 is not limited to this. For example, when the instantaneous interruption detection signal is input to the sub-microcomputer 4, a clock that instructs to stop the output of the clock signal. A signal stop signal may be output to the main microcomputer 3.

Claims (1)

  1. 　外部から電源供給を受けて動作するとともに外部から入力するクロック信号に同期して動作するメモリカード（５）へ、少なくとも前記クロック信号を出力することにより前記メモリカードを制御する制御装置（３）と、
    　少なくとも前記メモリカードと前記制御装置への電源供給を行う主電源からの電源供給が断たれることを示す予め設定された電断判断条件が成立したか否かを判断する電断判断部（８）と、
    　前記電断判断条件が成立したと電断判断部が判断した場合に、前記制御装置による前記クロック信号の出力を停止させるクロック信号停止部（４）と、
    　前記主電源からの電源供給が断たれてから、少なくとも予め設定されたバックアップ時間が経過するまで継続して前記メモリカードへ電源を供給するバックアップ電源（２２）と、を備えるデータ記憶制御装置。     A control device (3) for controlling the memory card by outputting at least the clock signal to a memory card (5) which operates by receiving power supply from outside and operates in synchronization with a clock signal input from the outside; ,
    A power interruption determination unit (8) that determines whether or not a predetermined power interruption determination condition indicating that power supply from a main power supply that supplies power to at least the memory card and the control device is cut off is satisfied. )When,
    A clock signal stop unit (4) for stopping the output of the clock signal by the control device when the power interruption determination unit determines that the power interruption determination condition is satisfied;
    A data storage control device comprising: a backup power supply (22) that supplies power to the memory card continuously after at least a preset backup time elapses after power supply from the main power supply is cut off.
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