WO2015051633A1

WO2015051633A1 - Power failure processing method and system for storage system

Info

Publication number: WO2015051633A1
Application number: PCT/CN2014/076712
Authority: WO
Inventors: 胡章雄
Original assignee: 华为技术有限公司
Priority date: 2013-10-10
Filing date: 2014-05-04
Publication date: 2015-04-16
Also published as: CN103678178B; CN103678178A; WO2015051633A9

Abstract

Disclosed are a power failure processing method and system for a storage system. The storage system comprises a primary power source, a backup power source, a first controller, a second controller, and a storage device, the first controller comprising a first buffer, and the second controller comprising a second buffer. The method comprises: when the primary power source is powered off, the first controller executing an operation of writing data of the first buffer into the storage device by using the backup power source, and the second controller executing an operation of writing data of the second buffer into the storage device by using the backup power source; when all data of the first buffer has been written into the storage device but data of the second buffer has not all been written into the storage device, the first controller sending a first turn-off signal to the backup power source, so that the first controller implements a power-off operation; and when the primary power source restores power supply, the first controller initiating a power-on operation by using the primary power source. Also disclosed is a storage system. The method can improve a restoration capability and reliability of a storage system.

Description

Power-down processing method and system for storage system

The present invention relates to the field of electronic technologies, and in particular, to a power-down processing method and system for a storage system. Background technique

When a power failure event occurs in the main power supply of the storage system, the data cached by the primary controller and the secondary controller in the dual control system needs to be saved through the power-down processing flow. In the specific implementation, in the case of main power failure, the backup power supply (Battery Backup Unit

The first controller performs an operation of writing the first cached data to the memory by using the backup power source when the main power source is powered down, and the second controller executes the An operation of writing the second cached data into the memory;

When the first cached data has been all written to the memory, and the second cached data has not been written to the memory, the first controller sends the first to the backup power source Turning off the signal to cause the first controller to complete the power-off operation;

When the main power source resumes power supply, the first controller initiates a power-on operation by using the main power source. In a first possible implementation manner of the first aspect, the method further includes:

When the data of the second cache is all written into the memory, the second controller sends a second shutdown signal to the backup power source, so that the second controller completes the power-off operation;

The second controller initiates a power-on operation by using the main power source.

In conjunction with the first possible implementation of the first aspect, in a second possible implementation of the first aspect, the method further includes:

The backup power source ends the power supply operation according to the first off signal and the second off signal.

With the second possible implementation of the first aspect, in a third possible implementation manner of the first aspect, the standby power supply ends the power supply operation according to the first off signal and the second off signal, including:

After the rising edge of the first off signal occurs, if a rising edge of the second off signal is detected, the standby power supply ends the power supply operation; or

After the falling edge of the first off signal occurs, if it is detected that the second off signal has a falling edge, the standby power supply ends the power supply operation.

With the second possible implementation of the first aspect, in a fourth possible implementation manner of the first aspect, the standby power supply ends the power supply operation according to the first off signal and the second off signal, including:

After the first off signal exhibits a transition from a high level to a high impedance state, if it is detected that the second off signal has a transition from a high level to a high impedance state, the standby power supply ends the power supply operation. ; or

After the first off signal exhibits a transition from a low level to a high impedance state, if it is detected that the second off signal exhibits a transition from a low level to a high impedance state, the standby power supply ends the power supply operation .

Correspondingly, the second aspect of the embodiments of the present invention further provides a storage system, where the storage system package The main power supply, the backup power supply, the first controller, the second controller, and the memory, the first controller includes a first cache, and the second controller includes a second cache, wherein:

The first controller is configured to perform an operation of writing the first cached data into the memory by using the backup power source when the main power source is powered off;

The second controller is configured to perform an operation of writing the data of the second cache to the memory by using the backup power source when the main power source is powered off;

The first controller is further configured to: when the data of the first cache has been all written into the memory, and the data of the second cache has not been completely written into the memory, to the standby The power source sends a first shutdown signal to complete the power-off operation of the first controller. When the main power source resumes power supply, the power source is further used to initiate a power-on operation by using the main power source.

In a first possible implementation manner of the second aspect, when the data of the second cache is all written into the memory, the second controller is further configured to send a second shutdown signal to the backup power source, Completing the power-off operation of the second controller; and also for initiating a power-on operation by using the main power source.

In conjunction with the first possible implementation of the second aspect, in a second possible implementation of the second aspect, the backup power source is further configured to end according to the first off signal and the second off signal Power supply operation.

With reference to the second possible implementation of the second aspect, in a third possible implementation manner of the second aspect, the backup power supply is specifically configured to: when detecting a rising edge of the first shutdown signal, Detecting that a rising edge of the second off signal occurs, ending the power supply operation; or

After detecting the falling edge of the first off signal, if it is detected that the second off signal has a falling edge, the power supply operation is ended.

With reference to the second possible implementation of the second aspect, in a fourth possible implementation manner of the second aspect, the backup power source is specifically configured to detect when the first off signal occurs from a high level to After the high-impedance transition, if it is detected that the second off signal exhibits a transition from a high level to a high impedance state, the standby power supply ends the power supply operation; or

After detecting that the first off signal has a transition from a low level to a high impedance state, if it is detected that the second off signal has a transition from a low level to a high impedance state, the standby power supply ends. Power supply operation.

According to the embodiment of the present invention, in the storage system, when the main power source is powered off, the first controller and the second controller can use the backup power source to perform data backup of the cache data, and complete the power-off operation after the data backup ends. When a controller completes the power-off operation before the second controller, when the main power supply resumes power supply The first controller first uses the main power source to initiate a power-on operation, so that the storage system can be restored to the normal working state in time. The method in the embodiment of the present invention can improve the recovery capability and reliability of the storage system. DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a flowchart of a power-down processing method of a storage system according to an embodiment of the present invention; FIG. 2 is a flowchart of a power-down processing method of a storage system according to another embodiment of the present invention; A schematic structural diagram of a storage system in an embodiment;

4 is a schematic structural diagram of a controller according to an embodiment of the present invention;

FIG. 5 is a flowchart showing the operation of a storage system according to an embodiment of the present invention; FIG.

6 is a schematic structural diagram of a storage system according to another embodiment of the present invention;

7 is a schematic structural diagram of a storage system according to still another embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a storage system according to still another embodiment of the present invention. detailed description

BRIEF DESCRIPTION OF THE DRAWINGS The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative work are within the scope of the present invention.

1 is a flow chart of a power-down processing method of a storage system in an embodiment of the present invention. This method can be applied to a storage system with two controllers. The storage system used in the embodiment of the present invention includes a main power source, a backup power source, a first controller, a second controller, and a memory, wherein the first controller includes a first cache, and the second controller includes a second cache. In a practical application, in a state in which the storage system is in normal operation, the first controller and the second controller work under the power supply support of the main power source, and the backup power source does not supply power to the first controller and the second controller. In the embodiment of the present invention, if the main power of the storage system is abnormally powered down, the method shown in FIG. 1 may be used for processing. As shown in FIG. 1, the processing flow of this embodiment includes the following steps: Step S110, when the main power source is powered off, the first controller performs an operation of writing the first cached data into the memory by using the standby power source, and the second controller performs the operation of writing the second cached data into the memory by using the standby power source. .

In practical applications, when the main power supply is powered off, the storage system starts the power-down processing flow, and the backup power supply starts to supply power to the first controller and the second controller, and supports the first controller to write the first cached data of the first controller. In the memory, and the second controller is configured to write the data of the second cache of the second controller to the memory, and correspondingly, the storage system used in the embodiment of the present invention is configured to save the data of the first cache and the second cache. The data memory can also be powered by the backup power supply to complete the data backup and save work.

In the storage system adopted by the embodiment of the present invention, the memory for storing the first cached data and the second cached data is a non-volatile storage medium, such as FLASH, to ensure the security of the written data.

Step S111, when the first cached data has all been written into the memory, and the second cached data has not been completely written into the memory, the first controller sends a first shutdown signal to the standby power source, so that the first controller Complete the power-off operation. The first controller that completes the power-off operation is in a non-working state.

In the embodiment of the present invention, after the first controller writes the data of the first cache to the memory, the first controller is directly sent to the backup power source without performing polling of the second controller, and the power-off operation is completed. Therefore, after the second controller writes the data of the second cache to the memory, the second controller does not need to poll the first controller, and the second shutdown signal can be directly sent to the backup power source to complete the power-off operation.

When the first cached data has all been written to the memory, and the second cached data has not been completely written to the memory, the first controller may send the first shutdown signal to the backup power source prior to the second controller, and Complete the power-off operation.

In a specific implementation, the first controller sends the first shutdown signal to the backup power source in the following manner: In the first manner, the first controller in the storage system can be configured to connect the first controller to the backup power source when the first controller receives the main power supply. Maintaining a high level, when the main power supply is powered off, the first controller does not write the first cached data to the memory, the serial port of the first controller becomes a low level, and the serial port is output through the first controller. The first off signal maintains a falling edge. When the first controller writes the first cached data to the memory, the serial port of the first controller changes from a low level to a high level, and accordingly, the first off The signal has a rising edge.

In the second mode, when the first controller in the storage system receives the main power supply, the serial port connected to the standby power source of the first controller is kept low, and when the main power supply is powered off, the first controller does not use the first cache. When all the data is written into the memory, the serial port of the first controller becomes high, and the first off signal outputted by the serial port of the first controller maintains a rising edge, when the first controller will first cache When the data is all written into the memory, the serial port of the first controller changes from a high level to a low level, and accordingly, a falling edge occurs on the first off signal.

In the third manner, when the first controller in the storage system receives the main power supply, the output signal of the serial port connected to the first controller and the standby power source is a high-resistance signal. When the main power supply is powered off, the first controller does not When a buffered data is all written into the memory, the signal output by the serial port of the first controller changes from a high impedance state to a high level. At this time, the first shutdown signal outputted by the serial port of the first controller is high. Level, when the first controller writes all the data of the first cache to the memory, the first off signal of the serial port output of the first controller changes from a high level to a high impedance state.

In the fourth method, when the first controller in the storage system receives the main power supply, the output signal of the serial port connected to the first controller and the standby power source is a high-resistance signal. When the main power supply is powered off, the first controller does not When a buffered data is all written into the memory, the signal output by the serial port of the first controller is changed from a high impedance state to a low level. At this time, the first shutdown signal outputted by the serial port of the first controller is low. Level, when the first controller writes all the data of the first cache to the memory, the first off signal of the serial port output of the first controller changes from a low level to a high impedance state.

Step S112: When the main power source resumes power supply, the first controller initiates a power-on operation by using the main power source. In a specific implementation, after the first controller performs the power-off operation, the main power source can be powered when the main power source resumes power supply, and the power-on operation is initiated by the main power source.

In the embodiment of the present invention, if the first controller performs the power-off operation before the second controller in step S111, the first controller may also initiate the power through the main power before the second controller in step S112. Power on operation. The first controller that preferentially initiates the power-on operation can restore the storage system to normal operation.

In the power-down processing method of the storage system of the embodiment of the present invention, when the main power source is powered off, the first controller and the second controller use the backup power source to write the respective cached data into the memory, when the first cached data is all When the memory is written to the memory, and the data of the second cache is not all written to the memory, the first controller sends a first shutdown signal to the backup power source, and completes the power-off operation before the second controller, and when the main power source resumes power supply The first controller first initiates a power-on operation by using the main power source to restore the storage system to a normal working state in time. According to the embodiment of the present invention, any controller that completes the power-off operation of the two controllers can be initiated by using the main power source. The power-on operation restores the storage system to normal operation in a timely manner, improving the recovery capability and reliability of the storage system. An embodiment of the present invention provides a power-down processing method for a storage system. When the primary power source is restored, any controller that first performs a power-off operation in the power-down processing flow of the first controller and the second controller may utilize the master. The power supply initiates a power-on operation, and the storage system is restored to normal operation in time; wherein, after the storage system resumes normal operation, the second controller may continue to write the second cached data to the memory to ensure that the cached data is safe and reliable; The backup power supply of the embodiment of the invention is controlled by the first controller and the second controller, and the power supply operation control of the standby power source is implemented according to the first shutdown signal sent by the first controller and the second shutdown signal sent by the second controller; The method of the embodiment of the invention ensures that the cached data in the storage system is safe and reliable, and can restore the normal working of the system in time, thereby improving the recovery capability and reliability of the storage system. 2 is a flow chart of a power down processing method of a memory system in another embodiment of the present invention. As shown in FIG. 2, the processing flow of this embodiment includes the following steps:

Step S210, when the main power source is powered off, the first controller performs an operation of writing the first cached data into the memory by using the standby power source, and the second controller performs the operation of writing the second cached data into the memory by using the standby power source. .

Step S211, when the first cached data has all been written into the memory, and the second cached data has not been completely written into the memory, the first controller sends a first shutdown signal to the standby power source to enable the first controller. Complete the power-off operation.

Step S212: When the main power source resumes power supply, the first controller initiates a power-on operation by using the main power source. Step S213: When all the data of the second cache is written into the memory, the second controller sends a second shutdown signal to the backup power source, so that the second controller completes the power-off operation. In a specific implementation, after the step S212, the storage system resumes normal operation, in this step, the second controller continues to write the second cached data into the memory, and after all the second cached data is written into the memory, to the standby The power supply sends a second shutdown signal to complete the power-off operation.

The second shutdown signal is of the same type as the first shutdown signal generated by the first controller in step S211. In a specific implementation, the second controller may send the second shutdown signal to the backup power source in the following manner:

In the first method, when the second controller in the storage system receives the main power supply, the serial port connected to the standby power source of the second controller is kept at a high level, and when the main power supply is powered off, the second controller has not yet the second cache. When the data is all written into the memory, the serial port of the second controller becomes a low level, and the second off signal output by the serial port of the second controller maintains a falling edge, when the second controller will be the second cache When the data is all written into the memory, the serial port of the second controller changes from a low level to a high level, and accordingly, a rising edge occurs on the second off signal.

In the second mode, when the second controller in the storage system receives the main power supply, the serial port connected to the backup power source of the second controller is kept low, and when the main power supply is powered off, the second controller has not yet the second cache. When the data is all written into the memory, the serial port of the second controller becomes a high level, and the second off signal output by the serial port of the second controller maintains a rising edge, and when the second controller sets the second cached data When all is written to the memory, the serial port of the second controller changes from a high level to a low level, and accordingly, a falling edge occurs on the second off signal.

In the third mode, when the second controller in the storage system receives the main power supply, the output signal of the serial port connected to the backup power source is a high-resistance signal, and when the main power supply is powered off, the second controller does not When the data of the second cache is all written into the memory, the signal output by the serial port of the second controller is changed from a high impedance state to a low level. At this time, the second shutdown signal outputted by the serial port of the second controller is Low level, when the second controller writes all the data of the second cache into the memory, the second off signal output by the serial port of the second controller changes from a low level to a high impedance state.

In the fourth method, when the second controller in the storage system receives the main power supply, the output signal of the serial port connected to the standby power source is a high-resistance signal, and when the main power supply is powered off, the second controller has not yet When the data of the second cache is all written into the memory, the signal output by the serial port of the second controller changes from a high impedance state to a high level. At this time, the second shutdown signal outputted by the serial port of the second controller is A high level, when the second controller writes all the data of the second cache to the memory, the second off signal output by the serial port of the second controller changes from a high level to a high impedance state.

Step S214: The second controller initiates a power-on operation by using the main power source. In a specific implementation, after the second controller performs the power-off operation, the power-on operation can be initiated by the main power source to restore the normal operation of the second controller.

Further, in the storage system used in the embodiment of the present invention, the backup power source controls the power supply operation according to the first shutdown signal and the second shutdown signal, wherein the first shutdown signal is that the first controller writes the first cached data. After the memory is sent, the second shutdown signal is sent by the second controller after the second cached data is all written into the memory.

Correspondingly, according to the types of the first off signal and the second off signal, the embodiment of the present invention provides the following shutdown schemes for the backup power source:

Solution 1. After the rising edge of the first off signal occurs, if a rising edge of the second off signal is detected, the standby power supply ends the power supply operation. In a specific implementation, the backup power source is connected to the first controller and the second controller, and receives a first shutdown signal from the first controller and a second shutdown signal from the second controller through the line. After the main power supply is powered off, when the first cached data has all been written into the memory, and the second buffered data has not been completely written into the memory, the standby power source can detect that the first off signal first has a rising edge, and can be set. The standby power supply ends the power supply operation when detecting that the first off signal and the second off signal are both rising edges, and then, when the second buffered data is all written into the memory, the standby power source can detect that the second off signal also appears The rising edge, at this time, the standby power supply ends the power supply operation.

Solution 2: After the falling edge of the first off signal occurs, if the falling edge of the second off signal is detected, the standby power supply ends the power supply operation.

In a specific implementation, the backup power source is connected to the first controller and the second controller, and receives a first off signal from the first controller and a second off signal from the second controller through the line. After the main power supply is powered off, when the first buffered data has been completely written into the memory, and the second buffered data has not been completely written into the memory, the standby power source can detect that the first off signal first has a falling edge, and can be set. The standby power supply ends the power supply operation when detecting that the first off signal and the second off signal are both falling edges, and then, when the second buffered data is all written into the memory, the standby power source can detect that the second off signal also appears The falling edge, at this time, the standby power supply ends the power supply operation.

Solution 3: After the first off signal has a transition from a high level to a high impedance state, if a transition from a high level to a high impedance state occurs when the second off signal is detected, the standby power supply ends the power supply operation.

In a specific implementation, the backup power source is connected to the first controller and the second controller, and receives a first off signal from the first controller and a second off signal from the second controller through the line. After the main power supply is powered off, when the first buffered data has been completely written into the memory, and the second buffered data has not been completely written into the memory, the standby power source can detect that the first off signal first appears from the high level to In the high-impedance state transition, the standby power supply can be set to end the power supply operation after detecting that the first off signal and the second off signal both jump to the high impedance state, then when the second cached data is completely written into the memory The standby power source can detect that the second off signal also has a transition from a high level to a high impedance state. At this time, the standby power supply ends the power supply operation.

In the fourth scheme, when the first off signal transitions from the low level to the high impedance state, if the second off signal detects a transition from the low level to the high impedance state, the standby power supply ends the power supply operation.

In a specific implementation, the backup power source is connected to the first controller and the second controller, and receives a first shutdown signal from the first controller and a second shutdown signal from the second controller through the line. Main battery After the source is powered off, when the first cached data has been completely written into the memory, and the second cached data has not been completely written into the memory, the standby power supply can detect that the first off signal first appears from low to high. The transition of the resistance state can be set to the standby power supply to terminate the power supply operation after detecting that the first off signal and the second off signal both jump to the high impedance state, then when the second cached data is all written into the memory, The standby power supply can detect that the second shutdown signal also exhibits a transition from a low level to a high impedance state, at which time the standby power supply ends the power supply operation.

The method described in the foregoing method 1 to method 4 can be implemented by a hardware device, such as a component and a related circuit, and can also be implemented by software control. In the embodiment of the present invention, the power supply operation of the standby power supply is implemented by using the above method 1 to method 4. The implementation is not limited.

In addition to the above method 1 to method 4, there may be more methods for ending the power supply operation according to the first off signal and the second off signal. The embodiment of the present invention is not limited to the methods provided in the first method to the fourth method.

In the storage system used in the embodiment of the present invention, the memory for storing the first cached data and the second cached data is a non-volatile storage medium, such as a read-only memory (ROM). Programmable Read-only Memory (PROM) EAROM EEPROM (Erasable Programmable Read-Only Memory) Electrically Erasable Programmable Read-Only Memory, EEPROM Flash Memory, etc., to ensure the security of written data.

Further, more than two controllers may be used in the storage system according to actual usage requirements. When the main power supply in the storage system is powered off, the multiple controllers can perform the power-down processing method provided by the embodiment of the present invention to perform cache data backup and system recovery work in the same manner, and accordingly, when the backup power supply is subjected to multiple control When the device is controlled, the signal processing method can be set according to the actual situation to end the power supply operation.

An embodiment of the present invention provides a power-down processing method for a storage system. When the primary power source is restored, any controller that first performs a power-off operation in the power-down processing flow of the first controller and the second controller may utilize the master. The power supply initiates a power-on operation, and the storage system is restored to normal operation in time; wherein, after the storage system resumes normal operation, the second controller may continue to write the second cached data to the memory to ensure that the cached data is safe and reliable; The backup power supply of the embodiment of the invention is simultaneously controlled by the first controller and the second controller, according to the first shutdown signal sent by the first controller and the second shutdown sent by the second controller. The signal implements the power supply operation control of the standby power supply. The method of the embodiment of the invention ensures that the cached data in the storage system is safe and reliable, and can restore the normal operation of the system in time, thereby improving the recovery capability and reliability of the storage system. FIG. 3 is a schematic structural diagram of a storage system according to an embodiment of the present invention. As shown in the figure, the storage system in the embodiment of the present invention may at least include: a main power source 31, a first controller 32, a second controller 33, a backup power source 34, and a memory 35, wherein:

The first controller 32, when the main power source 31 is powered down, is used to perform an operation of writing the first cached data of the first controller 32 to the memory 35 using the backup power source 34.

The second controller 33, when the main power source 31 is powered down, is for performing an operation of writing the data of the second cache of the second controller 33 to the memory 35 by the backup power source 34.

The first controller 32 is further configured to send the first shutdown signal to the backup power source 34 when the first cached data has been written to the memory 35 and the second cached data has not been written to the memory 35. The power-off operation of the first controller 32; when the main power source 31 resumes power supply, is also used to initiate a power-on operation by using the main power source 31.

Further optionally, the first controller 32 sends the first shutdown signal to the backup power source 34 in the following manner:

In the first mode, when the first controller 32 in the storage system receives power from the main power source 31, the serial port connected to the backup power source 34 of the first controller 32 maintains a high level. When the main power source 31 is powered off, the first controller 32 does not. When all the data of the first cache is written into the memory 35, the serial port of the first controller 32 becomes a low level, and the first off signal output by the serial port of the first controller 32 is a falling edge, when the first control When the data of the first cache 32 is written into the memory 35, the serial port of the first controller 32 changes from a low level to a high level, and accordingly, a rising edge occurs on the first off signal. For example, the first off signal can be output through a pin serial port of the first controller 32 shown in FIG.

In the second mode, when the first controller 32 in the storage system receives power from the main power source 31, the serial port connected to the backup power source 34 of the first controller 32 is kept at a low level, and when the main power source 31 is powered off, the first controller 32 is not When the first cached data is all written into the memory 35, the serial port of the first controller 32 becomes a high level, and the first off signal output by the serial port of the first controller 32 maintains a rising edge when the first control When the data of the first cache 32 is written to the memory 35, the serial port of the first controller 32 changes from a high level to a low level, and accordingly, a falling edge occurs on the first off signal. For example, Figure 6 A pin serial port of the first controller 32 shown outputs a first off signal.

In the third mode, when the first controller 32 in the storage system receives power from the main power source 31, the signal output from the serial port connected to the backup power source 34 by the first controller 32 is a high-resistance signal, and when the main power source 31 is powered off, the first When the controller 32 does not write all the data of the first cache to the memory 35, the signal output by the serial port of the first controller 32 changes from a high impedance state to a low level. At this time, the first controller 32 passes the The first off signal outputted by the serial port is low. When the first controller 32 writes the first cached data to the memory 35, the first off signal output by the serial port of the first controller 32 is low-level. Becomes a high impedance state. For example, the first off signal can be output through a pin serial port of the first controller 32 shown in FIG.

In the fourth mode, when the first controller 32 in the storage system receives power from the main power source 31, the signal output by the serial port connected to the backup power source 34 by the first controller 32 is a high-resistance signal, and when the main power source 31 is powered off, the first When the controller 32 does not write all the data of the first cache to the memory 35, the signal output by the serial port of the first controller 32 changes from a high impedance state to a high level. At this time, the first controller 32 passes the The first off signal outputted by the serial port is at a high level. When the first controller 32 writes the first cached data to the memory 35, the first off signal output by the serial port of the first controller 32 is jumped from a high level. Becomes a high impedance state. For example, the first off signal can be output through a pin serial port of the first controller 32 shown in FIG.

In a specific implementation, the first controller 32 that completes the power-off operation is in a non-operating state. After the main power source 31 resumes power supply, the first controller 32 initiates a power-on operation by using the main power source 31, and the storage system of the embodiment of the present invention can be restored. The normal work.

Further, optionally, after the storage system resumes normal operation, the second controller 33 in the storage system further continues to write the second cached data into the memory 35 to ensure complete and reliable cache data, wherein: the second controller 33, When the data of the second cache is all written into the memory 35, it is also used to send a second shutdown signal to the backup power source 34 to complete the power-off operation of the second controller 33; and is also used to initiate a power-on operation by using the main power source 31.

Further optionally, the second controller 33 sends the second shutdown signal to the backup power source 34 in the following manner:

In the first mode, when the second controller 33 in the storage system receives power from the main power source 31, the serial port connected to the backup power source 34 of the second controller 33 maintains a high level. When the main power source 31 is powered off, the second controller 33 does not. When all the data of the second cache is written into the memory 35, the serial port of the second controller 33 becomes a low level, and the second off signal output by the serial port of the second controller 33 maintains a falling edge, when the second control When the data of the second cache is all written into the memory 35, the serial port of the second controller 33 is The low level goes high, and accordingly, the second off signal has a rising edge. For example, the second off signal can be output through a pin serial port of the second controller 33 shown in FIG.

In the second mode, when the second controller 33 in the storage system receives power from the main power source 31, the serial port connected to the backup power source 34 of the second controller 33 is kept at a low level, and when the main power source 31 is powered off, the second controller 33 is not When all the data of the second cache is written into the memory 35, the serial port of the second controller 33 becomes a high level, and the second off signal output by the serial port of the second controller 33 maintains a rising edge, when the second control When the data of the second cache is all written into the memory 35, the serial port of the second controller 33 changes from a high level to a low level, and accordingly, a falling edge occurs on the second off signal. For example, the second off signal can be output through a pin serial port of the second controller 33 shown in FIG.

In the third mode, when the second controller 33 in the storage system receives power from the main power source 31, the signal output from the serial port connected to the backup power source 34 by the second controller 33 is a high-resistance signal, and when the main power source 31 is powered off, the second When the controller 33 does not write all the data of the second cache to the memory 35, the signal output by the serial port of the second controller 33 is changed from the high impedance state to the low level. At this time, the second controller 33 The second off signal outputted by the serial port is low level. When the second controller 33 writes the second cached data to the memory 35, the second off signal output by the serial port of the second controller 33 is low-level. Becomes a high impedance state. For example, the second off signal can be output through a pin serial port of the second controller 33 shown in FIG.

In the fourth mode, when the second controller 33 in the storage system receives power from the main power source 31, the signal output from the serial port connected to the backup power source 34 by the second controller 33 is a high-resistance signal, when the main power source 31 is powered off, the second When the controller 33 does not write all the data of the second cache to the memory 35, the signal output by the serial port of the second controller 33 is changed from the high impedance state to the high level. At this time, the second controller 33 The second off signal outputted by the serial port is at a high level. When the second controller 33 writes the data of the second cache to the memory 35, the second off signal output by the serial port of the second controller 33 is jumped from a high level. Becomes a high impedance state. For example, the second off signal can be output through a pin serial port of the second controller 33 shown in FIG.

The standby power source 33 is configured to receive the first shutdown signal sent by the first controller 32, and is further configured to receive the second shutdown signal sent by the second controller 33, and further configured to end the power supply according to the first shutdown signal and the second shutdown signal. operating.

Further optionally, the backup power supply 34 can implement the end of the backup power supply 34 in the following four ways:

In the first mode, after the standby power source 34 detects that the rising edge of the first off signal occurs, if the rising edge of the second off signal is detected, the power supply operation is ended. 6 is an implementation of the power supply operation of the backup power source 34, wherein the backup power source 34 establishes a connection with the first controller 32 and the second controller 33, respectively, through the first transistor Q1 of the first controller 32. The collector cl1 performs signal sampling, detects a first off signal (first BBU_OFF_10) outputted by the serial port of the first controller 32 chip, and performs signal sampling through the collector c2 of the second transistor Q2 of the second controller 33, and detects the first The second controller 33 outputs the second off signal of the chip serial port (the second BBU_OFF_10 I, after the first cached data is all written into the memory 35, the first off signal outputted by the first controller 32 chip serial port changes to a rising edge, the first After the data of the second buffer is all written into the memory 35, the second off signal outputted by the serial port of the second controller 33 is changed to a rising edge, and the implementation can be defined as the logical detection of the first off signal and the second off signal. the way:

When the first cached data is all written to the memory 35, and the second cached data is not all written to the memory 35, the backup power supply 34 will obtain the sampling signal 1 through the collector c1, which is a high level. And it is considered that the first off signal sent by the serial port of the first controller 32 chip is detected as a rising edge, and the standby power source 34 obtains the sampling signal 2 through the collector c2, and the sampling signal 2 is at a low level, and the second is considered as a second. The second off signal sent by the serial port of the controller 33 chip is not changed to a rising edge, and the power supply cannot be ended at present; when the data of the second buffer is all written into the memory 35, the sampling signal 2 obtained by the backup power source 34 through the collector c2 is high. Level, at this time, it is considered that the second off signal sent by the serial port of the chip of the second controller 33 is changed to a rising edge, and it is judged that the power supply operation can be ended according to the change of the first off signal and the second off signal, and the power supply operation is ended. .

Reference may be made to Table 1, wherein BBU_OFF_10 is a logical operation result after the backup power source 34 simultaneously detects the first off signal (first BBU_OFF_10) and the second off signal (second BBU_OFF_10): the first off signal appears to store the first off Signal appears

After the main power supply is powered off, the rising edge, ―off, normal operation, rising

Closed signal appears on the rising edge Usually, the rising edge of the first off signal is present. When the sampling signal 2 obtained by the backup power source 34 through the collector c2 changes from a high level to a low level, it represents a rising edge of the second off signal, and when the first off signal has a rising edge, When the second off signal has a rising edge, BBU_OFF_10 will change from low level to high level, and the power supply operation of the standby power source 34 can be ended.

In the second mode, the backup power supply 34 is further configured to detect that the rising edge of the first closing signal occurs, and if the rising edge of the second closing signal is detected, the power supply operation is ended.

FIG. 6 may be another implementation of ending the power supply operation of the backup power source 34, wherein the backup power source establishes a connection with the first controller 32 and the second controller 33, respectively, through the first transistor Q1 in the first controller 32. The collector electrode cl samples the signal, detects the first off signal (first BBU_OFF_10) outputted by the serial port of the first controller 32 chip, and performs signal sampling through the collector c2 of the second transistor Q2 in the second controller 33. The second controller 33 outputs a second off signal of the chip serial port (the second BBU_OFF_10 I, after the first cached data is all written into the memory 35, the first off signal output by the first controller 32 chip serial port is changed to a falling edge, After the second buffered data is all written into the memory 35, the second off signal outputted by the second controller 33 chip serial port is changed to a falling edge, and the implementation can be defined as the first off signal and the second off signal. Detection method:

When the first cached data is all written to the memory 35, and the second cached data is not all written to the memory 35, the backup power supply 34 will obtain the sampling signal 3 through the collector c1, which is a low level. And it is considered that the first off signal sent by the serial port of the first controller 32 chip is detected as a falling edge, and the standby power source 34 obtains the sampling signal 4 through the collector c2, and the sampling signal 4 is at a high level, and the second is considered as a second. The second off signal sent by the serial port of the chip of the controller 33 is not changed to a falling edge, and the power supply cannot be ended at present; when the data of the second buffer is all written into the memory 35, the sampling signal 4 obtained by the backup power source 34 through the collector c2 is low. Level, at this time, it is considered that the second off signal sent by the serial port of the chip of the second controller 33 is changed to a falling edge, and it is judged that the power supply operation can be ended according to the change of the first off signal and the second off signal, and the power supply operation is ended. .

Referring to Table 2, wherein BBU_OFF_10 is the logical operation result after the standby power supply 34 simultaneously detects the first off signal (the first BBU_OFF_10) and the second off signal (the second BBU_OFF_10): the first off signal appears first in the storage system Shutdown signal appears

Main power supply is powered down. After falling edge, the second off is normal operation.

Closed signal appears on the falling edge ΐ

ZU9L0/n0ZSLJ/∑Jd CC9TS0/S10Z OAV Then, according to the change of the first off signal and the second off signal, it is determined that the power supply operation can be ended currently, and the power supply operation is ended.

Refer to Table 3, where BBU_OFF_10 is the logical operation result after the standby power supply 34 simultaneously detects the first off signal (first BBU_OFF_10) and the second off signal (second BBU_OFF_10): First off signal hopping storage is off After the signal transitions to a high impedance state, the second main power supply is powered down.

Normal operation to high-impedance state off signal transition to high impedance state

When the first cached data is all written into the memory 35, and the second cached data is not all written to the memory 35, the backup power source 34 obtains the sampling signal 7 through the first controller 32 chip serial port and the node 3 of the pull-down resistor R3. The sampling signal 7 is at a low level, and it is considered that the first off signal sent by the serial port of the first controller 32 chip is detected to jump to a high impedance state, and at the same time, the backup power source 34 passes through the serial port and the pull-down resistor of the second controller 33 chip. The node 4 of R4 obtains the sampling signal 8, which is low level, and considers that the second off signal sent by the serial port of the chip of the second controller 33 is detected to not jump to the high impedance state, and the power supply cannot be ended at present; When the data of the second buffer is all written into the memory 35, the backup power source 34 obtains the sampling signal 8 through the serial port of the chip of the second controller 33 and the node 4 of the pull-down resistor R4, and the sampling signal 8 is at a low level, and the second control is considered at this time. The second off signal sent by the serial port of the chip 33 jumps to a high impedance state, and it is judged that the power supply can be ended according to the change of the first off signal and the second off signal. Operate and end the power supply operation.

Reference may be made to Table 4, wherein BBU_OFF_10 is the logical operation result after the standby power supply 34 simultaneously detects the first off signal (the first BBU_OFF_10) and the second off signal (the second BBU_OFF_10): the first off signal hopping is stored off. After the signal transitions to a high impedance state, the second main power supply is powered down.

In the storage system provided by the embodiment of the present invention, each execution part of the backup power source 34 may be a hardware device, such as a component and a related circuit, and may also be a software device integrated in a computer or a chip. The implementation is not limited.

The configuration of the backup power supply 34 used in the storage system of the present invention may be not limited to the foregoing four modules, and there may be more internal structural devices for implementing the power supply operation according to the first shutdown signal and the second shutdown signal. The embodiments of the present invention are not limited to the structural devices provided in the embodiments.

The memory 35 used in the storage system provided by the embodiment of the present invention is a non-volatile storage medium, such as a read-only memory (ROM), a programmable read-only memory (PROM), and an electrically rewritable memory. Read-Only Memory (Electrically Alterable Read-Only Memory), Erasable Programmable Read-Only Memory (EP), Electrically Erasable Programmable Read-Only Memory (EEPROM) Memory), etc., to ensure the security of the written data.

Further, more than two controllers may be used in the storage system provided by the embodiments of the present invention, according to actual usage requirements. When the main power source 31 in the storage system is powered down, multiple controllers in the system can perform cache data backup and system recovery work in the same manner. Accordingly, when the backup power source 35 is controlled by multiple controllers, The situation sets the signal processing method to end the power supply operation.

In the storage system provided by the embodiment of the present invention, when the main power source is restored, any one of the first controller and the second controller that performs the power-off operation in the power-down processing method may initiate the power-on operation by using the main power source. In the storage system of the embodiment of the present invention, the second controller can continue to write the data of the second cache to the memory to ensure that the cached data is safe and reliable. The standby power source is controlled by the first controller and the second controller, and the power supply operation control of the standby power source is implemented according to the first shutdown signal sent by the first controller and the second shutdown signal sent by the second controller. The storage system ensures that the cached data is safe and reliable, and can resume normal work in time, improving recovery and reliability. The flowchart shown in FIG. 5 may be used together. The flowchart shows the steps of the storage system performing the power-down processing method in the embodiment of the present invention, which may include:

In step S510, the main power source 31 is powered off. Wherein, the power failure of the main power source 31 may be a failure of the main power source 31 and a line fault. When a power failure event occurs, the backup power source 34 performs a power-down processing flow on the storage system. Part of the process is powered.

In step S511, the first controller 32 writes the first cached data into the memory 35.

In step S512, the second controller 33 writes the second cached data into the memory 35.

Step S513, whether the first cached data is all written into the memory 35. If it is determined that the first controller 32 has written all the data of the first cache into the memory 35, the process proceeds to step S515; if it is determined that the first controller 32 has not been written, the process returns to step S513.

Step S514, whether the second cached data is all written into the memory 35. If it is determined that the second controller 33 has been written, the process proceeds to step S518; if it is determined that the second controller 33 has not been written, the process returns to step S512.

In step S515, the first controller 32 sends a first off signal to the backup power source 34.

Step S516, the first controller 32 completes the power-off operation.

Step S517, the first controller 32 initiates a power-on operation. If the step is performed in step S5110, the power-on operation initiated by the first controller 32 in this step may be used to restore the normal operation of the storage system.

In step S518, the second controller 33 sends a second shutdown signal to the backup power source 34.

In step S519, the second controller 33 completes the power-off operation.

In step S5110, the second controller 33 initiates a power-on operation. If the step is performed in step S517, the power-on operation initiated by the second controller 33 in this step can be used to restore the normal operation of the storage system.

Step S5111, determining whether the backup power source 34 is turned off according to the first off signal and the second off signal. If it is determined that the backup power source 34 needs to end the power supply according to the first off signal and the second off signal, proceeding to step S5111; if it is determined according to the first off signal and the second off signal that the backup power source 34 is temporarily unable to end the power supply, Go back to step S511. For the method of determining whether the backup power source 34 needs to end the power supply, refer to the method provided in the foregoing embodiment.

In step S5112, the backup power source 34 is turned off.

Step S5113, the end.

In the storage system provided by the embodiment of the present invention, when the main power source is restored, any one of the first controller and the second controller that performs the power-off operation in the power-down processing method may initiate the power-on operation by using the main power source. The recovery of the normal operation is performed in a timely manner; wherein, after the storage system is restored to the normal operation, the second controller may continue to write the data of the second cache to the memory to ensure that the cached data is safe and reliable; in the storage system of the embodiment of the present invention, The backup power source is simultaneously controlled by the first controller and the second controller, and is implemented according to the first shutdown signal sent by the first controller and the second shutdown signal sent by the second controller. The power supply operation control of the power supply; the storage system of the embodiment of the invention ensures that the cached data is safe and reliable, and can resume normal work in time, improving the recovery capability and reliability.

4 is a schematic structural diagram of a controller according to an embodiment of the present invention. The controller shown in the figure may be any one of the first controller and the second controller in the foregoing steps. The processor 41 includes a processor 42, a transmitter 42, a memory 43, a receiver 44, a communication interface 45, and a bus 46. The processor 41, the transmitter 42, the memory 43, the receiver 44, and the communication interface 45 can be connected and communicated via the bus 46.

The processor 41 is configured to perform an operation of writing data buffered by the memory 42 to the external memory by using the standby power source when the main power source is powered off. It is also used to initiate a power-on operation with the main power source when the main power supply is restored. The processor 41 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), etc., and the memory 43 may include a random access memory (RAM), a read only memory. (read-only memory, ROM) and other entities with storage functions.

The transmitter 42 is configured to send a shutdown signal to the backup power source to enable the controller to complete the power-off operation.

The memory 43 is for storing data.

a receiver 44, configured to receive power from the main power source;

The communication interface 45 is configured to communicate with an external device, for example, the communication with the backup power source. The controller of the embodiment of the present invention can write the cached data into the external storage when the main power supply is powered off. After the cached data is completely written into the external memory, the backup power supply is shut down and the power-off operation is performed. When the main power supply is restored, the main power supply can be used to initiate the power-on operation, and the normal operation of the storage system can be restored in time. When the controller of the embodiment of the invention exists in the storage system in multiple forms, the controller can initiate the power-on operation by using the main power source after performing the next point operation, and the controller of the embodiment of the invention improves the recovery capability of the storage system. And reliability.

Through the description of the above embodiments, those skilled in the art can clearly understand that the present invention can be implemented in hardware, firmware implementation, or a combination thereof. When implemented in software, the functions described above may be stored in or transmitted as one or more instructions or code on a computer readable medium. Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage medium may be any available media that can be accessed by a computer. By way of example and not limitation, computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure. The desired program code and any other medium that can be accessed by the computer. Also. Any connection may suitably be a computer readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwaves are included in the fixing of the associated media. As used herein, a disk and a disc include a compact disc (a CD disc, a disc, a digital versatile disc (a DVD floppy disk and a Blu-ray disc. The combination above should also be included in the scope of protection of the computer readable medium). within.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and the equivalent changes made by the claims of the present invention are still within the scope of the present invention.

Claims

Rights request

1. A power-down processing method for a storage system, characterized in that the storage system includes a main power supply, a backup power supply, a first controller, a second controller and a memory, and the first controller includes a first cache, The second controller includes a second cache, and the method includes:

When the main power supply fails, the first controller uses the backup power supply to perform an operation of writing the first cached data into the memory, and the second controller uses the backup power supply to perform an operation of writing the first cached data to the memory. The operation of writing the second cached data into the memory;

When all of the first cached data has been written into the memory and all of the second cached data has not been written into the memory, the first controller sends a first message to the backup power supply. Turn off the signal so that the first controller completes the power-off operation;

When the main power supply resumes power supply, the first controller uses the main power supply to initiate a power-on operation.

2. The method according to claim 1, further comprising:

When all the second cached data is written into the memory, the second controller sends a second shutdown signal to the backup power supply, so that the second controller completes the power-off operation;

The second controller uses the main power supply to initiate a power-on operation.

3. The method according to claim 2, further comprising:

The backup power supply ends the power supply operation according to the first shutdown signal and the second shutdown signal.

4. The method according to claim 3, wherein the backup power supply ending the power supply operation according to the first shutdown signal and the second shutdown signal includes:

When the rising edge of the first shutdown signal appears, if a rising edge of the second shutdown signal is detected, the backup power supply ends the power supply operation; or

After the first shutdown signal has a falling edge, if a falling edge of the second shutdown signal is detected, the backup power supply ends the power supply operation.

5. The method according to claim 3, wherein the backup power supply ending the power supply operation according to the first shutdown signal and the second shutdown signal includes:

When the first shutdown signal transitions from a high level to a high resistance state, and if it is detected that the second shutdown signal transitions from a high level to a high resistance state, the backup power supply ends the power supply operation. ;or

When the first shutdown signal transitions from a low level to a high impedance state, if the second shutdown signal is detected The shutdown signal transitions from a low level to a high impedance state, and the backup power supply ends the power supply operation.

6. A storage system, characterized in that the storage system includes a main power supply, a backup power supply, a first controller, a second controller and a memory, the first controller includes a first cache, the second control unit The server includes a second cache, which:

The first controller is configured to use the backup power supply to write the first cached data into the memory when the main power supply is powered off;

The second controller is configured to use the backup power supply to write the second cached data into the memory when the main power supply is powered off;

The first controller is also configured to send data to the standby when all the first cached data has been written into the memory, but all the second cached data has not been written into the memory. The power supply sends a first shutdown signal to complete the power-off operation of the first controller; when the main power supply resumes power supply, it is also used to initiate a power-on operation using the main power supply.

7. The storage system according to claim 6, wherein when all the data in the second cache is written into the memory, the second controller is further configured to send a second shutdown message to the backup power supply. The signal is used to complete the power-off operation of the second controller; and is also used to initiate the power-on operation using the main power supply.

8. The storage system according to claim 7, characterized in that:

The backup power supply is also used to end the power supply operation according to the first shutdown signal and the second shutdown signal.

9. The storage system according to claim 8, characterized in that:

The backup power supply is specifically used to end the power supply operation when a rising edge of the first shutdown signal is detected and a rising edge of the second shutdown signal is detected; or

When a falling edge of the first shutdown signal is detected and a falling edge of the second shutdown signal is detected, the power supply operation is terminated.

10. The storage system according to claim 8, characterized in that:

The backup power supply is specifically used to detect that the first shutdown signal transitions from a high level to a high resistance state, and if it detects that the second shutdown signal transitions from a high level to a high resistance state. jump, the backup power supply ends the power supply operation; or

When it is detected that the first shutdown signal transitions from a low level to a high resistance state, and if it is detected that the second shutdown signal transitions from a low level to a high resistance state, the backup power supply ends. Power supply operation.