WO2015044529A1 - Assembly level encapsulation layer with multifunctional purpose, and method of producing the same - Google Patents

Assembly level encapsulation layer with multifunctional purpose, and method of producing the same Download PDF

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Publication number
WO2015044529A1
WO2015044529A1 PCT/FI2014/050741 FI2014050741W WO2015044529A1 WO 2015044529 A1 WO2015044529 A1 WO 2015044529A1 FI 2014050741 W FI2014050741 W FI 2014050741W WO 2015044529 A1 WO2015044529 A1 WO 2015044529A1
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Prior art keywords
layer
substrate
solid state
chips
protective layer
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PCT/FI2014/050741
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French (fr)
Inventor
Juha Rantala
Pekka KATILA
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Lumichip Oy
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Publication of WO2015044529A1 publication Critical patent/WO2015044529A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/048—Encapsulation of modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention generally relates to the field of electronic packaging and in particular to the packaging of optoelectronic components, modules and devices, e.g. Light Emitting Devices (LED), ultra-violet LEDs, white light LEDs, Superluminescent LEDs (SLED), Laser Diodes (LD), semiconductor photo detectors or photovoltaic devices. More particularly, embodiments of the present invention include multifunctional ultra-thin protective layers used for assembly level encapsulation (ALE), and having applications e.g. in LED light engine modules.
  • ALE assembly level encapsulation
  • Hermetic sealing is a good choice to improve reliability of electronic and optoelectronic components and prevent their premature end-of-life. Without hermetic protection to external stresses the background defects can develop and cause a premature failure originating typically from chip attach, wire bonding, wire bonding joints, chip's metal-semiconductor contact, or chip's top surface passivation. Hermetic sealing can substantially increase the mean time to failure as typical failure mechanisms are related to moisture leaking into the package and corroding the contacts or active areas e.g. the facets of the laser diodes.
  • External stress is caused for example by oxygen, water vapor, corrosive gases, ions and chemically active radical groups attacking the package surfaces.
  • External stress can cause e.g. mechanical deformation through absorption and desorption of humidity, change in electrical circuitry, galvanic corrosion, de lamination, and oxidation of metal surfaces.
  • humidity can chemically attack aluminum based top electrode contact pads, breaking the electrical connection between the wire bonding and the contact pad.
  • Semiconductor dies have normally a top surface layer, typically a thin nitride or oxide thin film that passivates the die electrically but also acts as a first buffer against corrosion due to environment.
  • a top surface layer typically a thin nitride or oxide thin film that passivates the die electrically but also acts as a first buffer against corrosion due to environment.
  • passivation thin films are grown on wafer level prior the die singulation step. After dies are separated, the dies' vertical sidewalls become exposed to air and corrosive oxygen, and harmful compounds in the air.
  • chip's top surface passivation layers are open on the electrical contact pads, exposing these areas directly to stress from environment.
  • US 2007/0215998 discloses a LED package where a LED is attached to a substrate.
  • a protective layer disposed by plasma chemical vapor deposition surrounds the chip (the LED), the upper side of the substrate and electrically conductive humps.
  • the protective layer consists of several sub-layers which have different refractive index.
  • Dl does not disclose any protective layer consisting of sub-layers with different electrical conductivity.
  • US 2012/0326178 concerns an optoelectronic component comprising a semiconductor protected by a sealing material applied by atomic layer deposition.
  • the encapsulation is introduced at assembly level to provide an optically transparent hermetical sealing layer and electrically insulating layer on all surfaces of the said component.
  • the encapsulation which is in direct contact with the surface of the component, provides a zero cavity structure.
  • an optoelectronic component comprising; a substrate, at least one light emitter device mounted on the substrate, and electrical contacts, with all surfaces coated with the protective layer.
  • the substrate material can be ceramic, but is not limited to, e.g. Alumina (AI 2 O 3 ) or Aluminum Nitride (A1N).
  • the substrate can be semiconductor material, but is not limited to, e.g. Silicon.
  • the substrate material can be a typical printed circuit board material, but is not limited to, e.g. FR4, FR5, or epoxy laminate material.
  • the protective layer can be a material layer deposited with ALD or other similar means.
  • the protective layer can be a multi-layer coating formed of two or more materials, such as AI 2 O 3 and Si02.
  • the protective layer's function is to provide hermetic sealing of all surfaces.
  • the protective layer is deposited with a conformal coating process so that vertical sidewalls, edges, and shadowed areas are covered.
  • the protective layer is formed at least on the front surface of the said component. According to certain embodiments the protective layer could be deposited on all surfaces of the component including the back side of the substrate and substrate's vertical sidewalls.
  • the protective layer could be deposited on top of mechanical package and transparent covering.
  • the protective layer is physically in contact with the active optical chips, and electrical parts, so that no cavity is formed between component and protective layer.
  • Embodiments of the present invention aim to solve issues associated with multichip modules and their hermetic sealing in a cost effective way.
  • a common problem in packaging is that the layouts and dimensions of the units or chips to be packaged are changing due to rapid technical advancement and process changes, as in the field of LED technology.
  • a flexible packaging approach is thus required that can accommodate frequently changing units without being modified despite changes in the actual LED processing or LED chips.
  • An approach that is cost effective and, for example, which does not apply fixed mask sets is desired.
  • the Atomic Layer Deposition (ALD) technique is well suited for this task.
  • the ALD method can be applied on any 3D geometry and packaging material.
  • ALD offers wide selection of materials to choose most suitable to form the said protective layer.
  • the flexibility of the present invention has a substantial advantage over other packaging methods such as WLP.
  • Figure 1 shows schematic cross-section of optoelectronic component with a substrate, a semiconductor die with electrical contact pad layer on top of surface of the die, die attach layer, electrical conductive layer on top surface of the substrate, and a wire bond to form electrical contact between the die and the electrical conductive layers.
  • Figure 2 shows schematic cross-section of optoelectronic component with a substrate, a semiconductor die with electrical contact pad layer on top of surface of the die, die attach layer, electrical conductive layer on top surface of the substrate, a wire bonding to form electrical contact between the die and the electrical conductive layers, and a protective layer covering the component surface excluding the back side of the substrate.
  • Figure 3 shows assembly flow for a typical component comprising a step to form the said protective layer.
  • the present invention discloses means to provide a protective layer after or during the assembly phase to improve the component's reliability.
  • the protective layer is deposited after the basic assembly steps have been completed including the die separation, die attachment to substrate and wire bonding steps.
  • the protective layer is made as a final step of the assembly, or just prior a mechanical enclosure is done. After the protective layer has been deposited, only the contact areas or the soldering pads for a printed circuit board assembly are left un-protected.
  • Such protective layers are ultra-thin optically transparent, conformal and uniform in nature. They provide a moisture resistance and improved electrical insulation with a typical application in LED light engine modules.
  • LED package comprising of a semiconductor die made of III-V semiconductor material mounted with conductive adhesive on an alumina substrate having on its top surface electrically conductive tracks made of silver alloy, and copper wire bonding to form electrical contacts between the semiconductor die and the electrical layer of the substrate.
  • the assembled component can be coated with a protective layer formed of two dielectric materials of 10 nm of AI 2 O 3 and 5 nm of Si0 2 and these sub-layers could be deposited post-assembly e.g. with an atomic layer deposition method.
  • a protection layer would be optically transparent and innocuous.
  • the thickness of the protection layer can be optimized for the transmission at the said wavelength in interest. For example one quarter wavelength thick anti-reflection coating for an emission wavelength of 405 nm would be (405 nm/4/1.8) ⁇ 59 nm.
  • a method of making a solid state light emitting and/or light detecting device comprises the steps of:
  • the protective layer comprises at least one material selected from the group of oxide materials consisting of A1 2 0 3 , Ti0 2 , ZnO, Hf0 2 , HfSiO, Si0 2 , MgO, Ta 2 0 5 , Zr0 2 .
  • the protective layer comprises at least one material selected from the group of nitride materials consisting of A1N, HfN, SiNx, Si 3 N 4 , TaN, Ti .
  • the protective layer consists of electrically conductive material of Indium Tin Oxide.
  • the protective layer manufacturing with the atomic layer deposition can take place at relatively low temperature.
  • a high quality A1 2 0 3 layer can be grown at 120 to 150 °C.
  • Low temperatures are often preferred as typical electronic packaging materials can withstand only 150 °C.
  • a plasma-assisted ALD can be used for depositing low- temperature silicon dioxide as a top sub-layer at temperature of 150 °C.
  • a low temperature thermal ALD process can be used for depositing a high quality silicon dioxide.
  • the substrate or module has typically electrical contact pads used to make the connections to an external circuitry in the printed circuit board assembly phase. Such electrical contact pads on the substrate can be selectively protected during the deposition of the protective layer with e.g. a Kapton tape, which can be removed after the deposition of the protective layer.
  • a hermetically sealed optoelectronic component comprising; a substrate, at least one optoelectronic chip bonded, soldered or glued on the substrate, an electrically conductive track on the substrate, and a wire bonding making electrical connection from the said chip to electrical conductive track on the top surface of the substrate,.
  • optoelectronic components are Light Emitting Diode (LED) components, Laser Diode (LD) components, Superluminescent LEDs (SLED), and other non-emitting types of components such as semiconductor detectors or imaging arrays.
  • LED Light Emitting Diode
  • LD Laser Diode
  • SLED Superluminescent LEDs
  • Light emitter components according to the present invention should not be limited to those emitting visible light but also include other forms of electromagnetic radiation. Further examples of light emitter components include those which comprises an In-, Ga-, A1-, and/or N- containing compound, for instance an InGaN or AlGaN diode.
  • the present invention comprises a component formed of a substrate, semiconductor chip(s), electrical contact wire(s), electrical contact layer(s), electrically conductive track(s), and a protective layer, which is a conformal layer forming a uniform coating on the said component's surface.
  • the protective layer is further hermetic and optically transparent.
  • the protective layer comprises sub-layers of two or more different materials, wherein one sub- layer is electrically conductive in order to avoid charge accumulation in the coating. None of the above-mentioned references discloses any component or solid state device based on such a component, where the component has a protective layer in which one sublayer is electrically conductive in order to avoid charge accumulation in the coating.
  • the protective coating acts also as a functional layer to improve optical performance e.g. it can act as an anti-reflection coating, or provide optimized transmission of the electromagnetic radiation in certain wavelength in interest.
  • the protective layer functions as an optical layer providing means to create selective or custom reflection or transmission bands at a wavelength in interest.
  • a protective layer could be formed of several alternating high refractive index and low refractive index materials.
  • the said protection layer provides means to optimize e.g. sensor sensitivity for a specified wavelength range.
  • Carbonization of materials within the component package can lead to accumulation of materials on top of the active surfaces, possibly causing undesired conductive paths causing leakage currents and short-circuit failures.
  • electrical contacts are made with wire bonding, which have non-insulated metal surfaces.
  • the conductive paths on top surface of the substrates are non-insulated. Both of these are susceptible to leakage currents and short-circuit type failures. If protection layer material is dielectric the said passivation layer acts as electrical insulation layer formed on all electrical conductors prohibiting unwanted current paths and thus improves electrical performance and reliability.
  • the protective layer has a sheet resistance lower than 1000 ohm, or preferably, lower than 100 ohm, or even more preferably lower than 10 ohm.
  • the said protective layer that forms conformal coating around wire bonding would enable use of other materials than Au and leading to a more economical component.
  • Humidity absorbed on the component's surface can cause leakage currents and even cause short circuits.
  • a dielectric protective layer forming uniform insulation layer on all surfaces protects device from such electrical failures.
  • dielectric protective layer acting would prevent galvanic corrosion mechanism to erode metallic surfaces.
  • a conformal passivation layer manufactured post module assembly provides convenient way to passivate all package surfaces susceptible to degradation under corrosive environment. In case of porous package surfaces it is likely that humidity absorbed causes deformation and stress leading to early failure.
  • a conformal passivation layer provides means to prevent absorption of humidity inside porous surfaces.
  • the protective layer can be made hydrophobic to further increase the resistance to humidity.
  • the protective layer typically has a water vapor transmission rate lower than lxl 0 "2 g/m 2 /day, or preferably lower than lxlO 3 g/m 2 /day, as measured at 25 °C, and at 50% relative humidity.
  • the protective layer typically has an oxygen transmission rate lower than lxl 0 "2 cm 3 /m 2 /atm/day, or preferably lower than lxlO "3 cm3/m 2 /atm/day.
  • the said protective layer comprise conductive sub-layers to enable electrical functions.
  • an Indium Tin Oxide (ITO) sub-layer could be used as part of the protective layer. Barrier against oxidation
  • the protection layer covers the package surfaces coated with reflective thin films comprising Ag or Al based alloys. These alloys are susceptible to tarnishing and easily lose their reflectivity due to oxidation if applied without appropriate protective layer.
  • the said protective layer shields such reflector layers from oxidation and lengthens the life-time of the LED.
  • the said protective layer can be manufactured with a wide range of standard deposition methods applied in the semiconductor industry. Such standard methods include for example atomic layer deposition, plasma enhanced chemical vapor deposition, and sputtering. As it is often a requirement to have a conformal layer to protect shadowed areas, the ALD is the most preferred manufacturing method. A thermal, plasma-assisted or spatial ALD can be used for manufacturing the layers, or any combination of those.
  • the structure of the said protective layer is such that it can be processed with a one loading step providing economical solution for the encapsulation.
  • Figure 1 shows an example of an optoelectronic component 100.
  • the component has a substrate 101 having one chip 105 mounted on the substrate.
  • the chip is solder or adhesive mounted on the substrate.
  • a thin material layer 102 of solder or adhesive is between chip and substrate.
  • the chip and substrate both have electrical contact layers 104,110 on top surfaces.
  • the chip is electrically connected from a chip's bonding pad 107 with a wire bonding 108 to the substrate's electrical contact pad 110.
  • Figure 2 shows an example of an optoelectronic component 200 with a protective conformal coating layer 211 forming uniform and homogeneous hermetical seal covering all surfaces of the component.
  • the other components 201 to 210 are analogous to the ones mentioned above in connection to optoelectronic component 100.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A component formed of a substrate (201), semiconductor chip(s) (205), such as an optoelectronic component (200), for example a light emitting diode, electrical contact wire(s) (208), electrical contact layer(s) (204, 210), electrically conductive track(s), and a protective layer (211). The protective layer (211) is optically transparent, it has a thickness is preferably below 100 nm and it is made with the atomic layer deposition method. Embodiments of the present invention solve issues associated with multichip modules and their hermetic sealing.

Description

ASSEMBLY LEVEL ENCAPSULATION LAYER WITH MULTIFUNCTIONAL PURPOSE, AND METHOD OF PRODUCING THE SAME
FIELD OF INVENTION
The present invention generally relates to the field of electronic packaging and in particular to the packaging of optoelectronic components, modules and devices, e.g. Light Emitting Devices (LED), ultra-violet LEDs, white light LEDs, Superluminescent LEDs (SLED), Laser Diodes (LD), semiconductor photo detectors or photovoltaic devices. More particularly, embodiments of the present invention include multifunctional ultra-thin protective layers used for assembly level encapsulation (ALE), and having applications e.g. in LED light engine modules.
BACKGROUND OF THE INVENTION
Electronic or optoelectronic components must be protected from environment to prevent detrimental effects due to humidity, oxygen and corrosion due to ions and non-neutral substances. Different failure modes terminate component's functionality abruptly or by gradually degrading performance. The root causes of the failure modes can be roughly divided into internal and external ones. Internal ones refer to e.g. material defects, electromigration, material diffusion inside semiconductor devices, and e.g. design related failures. External ones are induced by environmental stresses that alone cause failures or trigger internal ones to develop up-to a point of failure.
With properly designed and manufactured packaging it is possible to reduce the effect of environment and enhance the component's reliability. Hermetic sealing is a good choice to improve reliability of electronic and optoelectronic components and prevent their premature end-of-life. Without hermetic protection to external stresses the background defects can develop and cause a premature failure originating typically from chip attach, wire bonding, wire bonding joints, chip's metal-semiconductor contact, or chip's top surface passivation. Hermetic sealing can substantially increase the mean time to failure as typical failure mechanisms are related to moisture leaking into the package and corroding the contacts or active areas e.g. the facets of the laser diodes.
External stress is caused for example by oxygen, water vapor, corrosive gases, ions and chemically active radical groups attacking the package surfaces. External stress can cause e.g. mechanical deformation through absorption and desorption of humidity, change in electrical circuitry, galvanic corrosion, de lamination, and oxidation of metal surfaces. For example humidity can chemically attack aluminum based top electrode contact pads, breaking the electrical connection between the wire bonding and the contact pad.
Semiconductor dies have normally a top surface layer, typically a thin nitride or oxide thin film that passivates the die electrically but also acts as a first buffer against corrosion due to environment. However, such passivation thin films are grown on wafer level prior the die singulation step. After dies are separated, the dies' vertical sidewalls become exposed to air and corrosive oxygen, and harmful compounds in the air. Furthermore, such chip's top surface passivation layers are open on the electrical contact pads, exposing these areas directly to stress from environment.
US 2007/0215998 discloses a LED package where a LED is attached to a substrate. A protective layer, disposed by plasma chemical vapor deposition surrounds the chip (the LED), the upper side of the substrate and electrically conductive humps. The protective layer consists of several sub-layers which have different refractive index. However, Dl does not disclose any protective layer consisting of sub-layers with different electrical conductivity.
US 2012/0326178 concerns an optoelectronic component comprising a semiconductor protected by a sealing material applied by atomic layer deposition.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an encapsulated optoelectronic component. The encapsulation is introduced at assembly level to provide an optically transparent hermetical sealing layer and electrically insulating layer on all surfaces of the said component. The encapsulation, which is in direct contact with the surface of the component, provides a zero cavity structure.
It is an aspect of certain embodiments to provide an optoelectronic component comprising; a substrate, at least one light emitter device mounted on the substrate, and electrical contacts, with all surfaces coated with the protective layer. The substrate material can be ceramic, but is not limited to, e.g. Alumina (AI2O3) or Aluminum Nitride (A1N). The substrate can be semiconductor material, but is not limited to, e.g. Silicon. The substrate material can be a typical printed circuit board material, but is not limited to, e.g. FR4, FR5, or epoxy laminate material.
The protective layer can be a material layer deposited with ALD or other similar means. The protective layer can be a multi-layer coating formed of two or more materials, such as AI2O3 and Si02.
The protective layer's function is to provide hermetic sealing of all surfaces. The protective layer is deposited with a conformal coating process so that vertical sidewalls, edges, and shadowed areas are covered. The protective layer is formed at least on the front surface of the said component. According to certain embodiments the protective layer could be deposited on all surfaces of the component including the back side of the substrate and substrate's vertical sidewalls.
According to certain embodiments the protective layer could be deposited on top of mechanical package and transparent covering.
The protective layer is physically in contact with the active optical chips, and electrical parts, so that no cavity is formed between component and protective layer.
Embodiments of the present invention aim to solve issues associated with multichip modules and their hermetic sealing in a cost effective way. A common problem in packaging is that the layouts and dimensions of the units or chips to be packaged are changing due to rapid technical advancement and process changes, as in the field of LED technology. A flexible packaging approach is thus required that can accommodate frequently changing units without being modified despite changes in the actual LED processing or LED chips. An approach that is cost effective and, for example, which does not apply fixed mask sets is desired. The Atomic Layer Deposition (ALD) technique is well suited for this task. The ALD method can be applied on any 3D geometry and packaging material. ALD offers wide selection of materials to choose most suitable to form the said protective layer. The flexibility of the present invention has a substantial advantage over other packaging methods such as WLP.
It is a further object of the present invention to provide a method for manufacturing a hermetically sealed optoelectronic component according to the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows schematic cross-section of optoelectronic component with a substrate, a semiconductor die with electrical contact pad layer on top of surface of the die, die attach layer, electrical conductive layer on top surface of the substrate, and a wire bond to form electrical contact between the die and the electrical conductive layers.
Figure 2 shows schematic cross-section of optoelectronic component with a substrate, a semiconductor die with electrical contact pad layer on top of surface of the die, die attach layer, electrical conductive layer on top surface of the substrate, a wire bonding to form electrical contact between the die and the electrical conductive layers, and a protective layer covering the component surface excluding the back side of the substrate.
Figure 3 shows assembly flow for a typical component comprising a step to form the said protective layer. EMBODIMENTS
In the present context, the following terms are interchangeably used:
- "die" and "chip"; and - "protection layer", "encapsulation", "coating" and "barrier layer".
The verbs "to comprise" and "to include" are used in this document as open limitations that neither exclude nor require the existence of also un-recited features. The features recited in dependent claims are mutually freely combinable unless otherwise explicitly stated. Furthermore, it is to be understood that the use of "a" or "an", i.e. a singular form, throughout this document does not exclude a plurality.
The present invention discloses means to provide a protective layer after or during the assembly phase to improve the component's reliability. In order to protect all surfaces susceptible to environmental stresses, the protective layer is deposited after the basic assembly steps have been completed including the die separation, die attachment to substrate and wire bonding steps. The protective layer is made as a final step of the assembly, or just prior a mechanical enclosure is done. After the protective layer has been deposited, only the contact areas or the soldering pads for a printed circuit board assembly are left un-protected.
Such protective layers are ultra-thin optically transparent, conformal and uniform in nature. They provide a moisture resistance and improved electrical insulation with a typical application in LED light engine modules.
Referring to Figure 3 :
For example in case of a LED package comprising of a semiconductor die made of III-V semiconductor material mounted with conductive adhesive on an alumina substrate having on its top surface electrically conductive tracks made of silver alloy, and copper wire bonding to form electrical contacts between the semiconductor die and the electrical layer of the substrate.
After the die attach and wire bonding the assembled component can be coated with a protective layer formed of two dielectric materials of 10 nm of AI2O3 and 5 nm of Si02 and these sub-layers could be deposited post-assembly e.g. with an atomic layer deposition method. Such a protection layer would be optically transparent and innocuous. The thickness of the protection layer can be optimized for the transmission at the said wavelength in interest. For example one quarter wavelength thick anti-reflection coating for an emission wavelength of 405 nm would be (405 nm/4/1.8) ~ 59 nm.
According to one embodiment of the present invention, a method of making a solid state light emitting and/or light detecting device, comprises the steps of:
- providing a first substrate;
- providing on the first substrate a plurality of solid state light emitting and/or light detecting chips;
- wire bonding the solid state chips to the first substrate;
- providing a conformal sealing layer to the solid state chips, wire bonds and any exposed first substrate between the solid state chips;
- providing a second substrate that is transmissive to the wavelength of light to be emitted and/or detected by the solid state chips; and
- providing a sealing layer between the first and second substrates and bonding the first and second substrates together so as to seal the solid state chips therebetween.
In one embodiment, the protective layer comprises at least one material selected from the group of oxide materials consisting of A1203, Ti02, ZnO, Hf02, HfSiO, Si02, MgO, Ta205, Zr02.
In another embodiment, the protective layer comprises at least one material selected from the group of nitride materials consisting of A1N, HfN, SiNx, Si3N4, TaN, Ti .
In a third embodiment, the protective layer consists of electrically conductive material of Indium Tin Oxide.
The protective layer manufacturing with the atomic layer deposition can take place at relatively low temperature. A high quality A1203 layer can be grown at 120 to 150 °C. Low temperatures are often preferred as typical electronic packaging materials can withstand only 150 °C. A plasma-assisted ALD can be used for depositing low- temperature silicon dioxide as a top sub-layer at temperature of 150 °C. Alternatively, it has been also proposed to use a low temperature thermal ALD process can be used for depositing a high quality silicon dioxide.
As the protection layer deposition takes place after the assembly i.e. the semiconductor die has been attached to the substrate and electrical connections have been made by wire bonding, all surfaces including die attach layer and wire bonding become protected as well and improve the reliability of the component. The substrate or module has typically electrical contact pads used to make the connections to an external circuitry in the printed circuit board assembly phase. Such electrical contact pads on the substrate can be selectively protected during the deposition of the protective layer with e.g. a Kapton tape, which can be removed after the deposition of the protective layer.
Described herein is a hermetically sealed optoelectronic component. According to an embodiment, there are optoelectronic components comprising; a substrate, at least one optoelectronic chip bonded, soldered or glued on the substrate, an electrically conductive track on the substrate, and a wire bonding making electrical connection from the said chip to electrical conductive track on the top surface of the substrate,.
Examples of optoelectronic components are Light Emitting Diode (LED) components, Laser Diode (LD) components, Superluminescent LEDs (SLED), and other non-emitting types of components such as semiconductor detectors or imaging arrays. Light emitter components according to the present invention should not be limited to those emitting visible light but also include other forms of electromagnetic radiation. Further examples of light emitter components include those which comprises an In-, Ga-, A1-, and/or N- containing compound, for instance an InGaN or AlGaN diode.
In one embodiment, the present invention comprises a component formed of a substrate, semiconductor chip(s), electrical contact wire(s), electrical contact layer(s), electrically conductive track(s), and a protective layer, which is a conformal layer forming a uniform coating on the said component's surface. The protective layer is further hermetic and optically transparent. Preferably the protective layer comprises sub-layers of two or more different materials, wherein one sub- layer is electrically conductive in order to avoid charge accumulation in the coating. None of the above-mentioned references discloses any component or solid state device based on such a component, where the component has a protective layer in which one sublayer is electrically conductive in order to avoid charge accumulation in the coating.
Optical performance
In some embodiments of the present invention, the protective coating acts also as a functional layer to improve optical performance e.g. it can act as an anti-reflection coating, or provide optimized transmission of the electromagnetic radiation in certain wavelength in interest.
In another embodiment the protective layer functions as an optical layer providing means to create selective or custom reflection or transmission bands at a wavelength in interest. Such a protective layer could be formed of several alternating high refractive index and low refractive index materials. Thus the said protection layer provides means to optimize e.g. sensor sensitivity for a specified wavelength range.
Electrical insulation
Carbonization of materials within the component package can lead to accumulation of materials on top of the active surfaces, possibly causing undesired conductive paths causing leakage currents and short-circuit failures. Typically electrical contacts are made with wire bonding, which have non-insulated metal surfaces. Also the conductive paths on top surface of the substrates are non-insulated. Both of these are susceptible to leakage currents and short-circuit type failures. If protection layer material is dielectric the said passivation layer acts as electrical insulation layer formed on all electrical conductors prohibiting unwanted current paths and thus improves electrical performance and reliability.
In one embodiment, the protective layer has a sheet resistance lower than 1000 ohm, or preferably, lower than 100 ohm, or even more preferably lower than 10 ohm. The said protective layer that forms conformal coating around wire bonding would enable use of other materials than Au and leading to a more economical component.
Humidity absorbed on the component's surface can cause leakage currents and even cause short circuits. Thus a dielectric protective layer forming uniform insulation layer on all surfaces protects device from such electrical failures.
Furthermore the said dielectric protective layer acting would prevent galvanic corrosion mechanism to erode metallic surfaces.
A conformal passivation layer manufactured post module assembly provides convenient way to passivate all package surfaces susceptible to degradation under corrosive environment. In case of porous package surfaces it is likely that humidity absorbed causes deformation and stress leading to early failure. A conformal passivation layer provides means to prevent absorption of humidity inside porous surfaces.
In some embodiment of this invention the protective layer can be made hydrophobic to further increase the resistance to humidity. The protective layer typically has a water vapor transmission rate lower than lxl 0"2 g/m2/day, or preferably lower than lxlO 3 g/m2/day, as measured at 25 °C, and at 50% relative humidity.
The protective layer typically has an oxygen transmission rate lower than lxl 0"2 cm3/m2/atm/day, or preferably lower than lxlO"3 cm3/m2/atm/day.
It is foreseen that in some applications it is beneficial to have the said protective layer comprise conductive sub-layers to enable electrical functions. For example to avoid charge accumulation in the coating, an Indium Tin Oxide (ITO) sub-layer could be used as part of the protective layer. Barrier against oxidation
Typically used materials Ag, Al, Cu suffer oxidation. Commonly used reflector materials in LED packages are Ag or Ag based alloys. In another embodiment of the disclosed invention the protection layer covers the package surfaces coated with reflective thin films comprising Ag or Al based alloys. These alloys are susceptible to tarnishing and easily lose their reflectivity due to oxidation if applied without appropriate protective layer. The said protective layer shields such reflector layers from oxidation and lengthens the life-time of the LED.
Manufacturing
The said protective layer can be manufactured with a wide range of standard deposition methods applied in the semiconductor industry. Such standard methods include for example atomic layer deposition, plasma enhanced chemical vapor deposition, and sputtering. As it is often a requirement to have a conformal layer to protect shadowed areas, the ALD is the most preferred manufacturing method. A thermal, plasma-assisted or spatial ALD can be used for manufacturing the layers, or any combination of those. The structure of the said protective layer is such that it can be processed with a one loading step providing economical solution for the encapsulation.
Turning now to Figures 1 and 2:
Figure 1 shows an example of an optoelectronic component 100. The component has a substrate 101 having one chip 105 mounted on the substrate. The chip is solder or adhesive mounted on the substrate. A thin material layer 102 of solder or adhesive is between chip and substrate. The chip and substrate both have electrical contact layers 104,110 on top surfaces. The chip is electrically connected from a chip's bonding pad 107 with a wire bonding 108 to the substrate's electrical contact pad 110.
Figure 2 shows an example of an optoelectronic component 200 with a protective conformal coating layer 211 forming uniform and homogeneous hermetical seal covering all surfaces of the component. The other components 201 to 210 are analogous to the ones mentioned above in connection to optoelectronic component 100.
REFERENCE SIGNS LIST
101 substrate
102 solder/adhesive material layer on top of electrical contact layer on substrate's surface
103 chip vertical edge
104 electrical contact layer on top surface of the chip
105 chip
106 top surface of the chip
107 wire bonding bump on top of electrical contact layer on chip's top surface
108 bonding wire
109 wire bonding bump on top of electrical contact layer on substrate's surface
110 electrical contact layer on substrate's surface
201 substrate
202 contact material layer on top of electrical contact layer on substrate's top surface
203 chip vertical edge
204 electrical contact layer on top surface of the chip
205 chip
206 top surface of the chip
207 wire bonding bump on top of electrical contact layer on chip's top surface
208 bonding wire
209 wire bonding bump on top of electrical contact layer on substrate's surface
210 electrical contact layer on substrate's top surface
211 conformal protection layer
301 Wafer Cutting - Die Singulation
302 Die Attachment to Substrate
303 Electrical Contact Making - Wire Bonding
304 Protective Layer Deposition
305 Mechanical Protection
LIST OF REFERENCES
US 2007/0215998
US 2012/0326178

Claims

1. A component formed of
- a substrate,
semiconductor chip(s),
- electrical contact wire(s), electrical contact layer(s),
electrically conductive track(s), and
a protective layer.
2. A component according to claim 1, wherein the said protective layer
- is a conformal layer forming a uniform coating on the said component's surface,
- is hermetic,
- is optically transparent, and/or
- comprises sub-layers of two or more different materials.
3. A component according to any of the preceding claims, wherein the said protective layer's thickness is preferably below 100 nm, or below 20 nm, or below 5 nm.
4. A component according to any of the preceding claims, wherein the said protective layer is made with a method selected from the group comprising the atomic layer deposition method, the chemical vapor deposition method, plasma enhanced chemical vapor deposition method, physical vapor deposition, electron sputtering, ion beam sputtering, magnetron reactive sputtering and a combination thereof.
5. A component according to any of the preceding claims, wherein the said protective layer comprises at least one material selected from the group of oxide materials consisting of AI2O3, T1O2, ZnO, Hf02, HfSiO, S1O2, MgO, Ta205, Zr02, and/or comprises at least one material selected from the group of nitride materials consisting of A1N, HfN, SiNx, S13N4, TaN, TiN.
6. A component according to any of claims 1 to 4, wherein the said protective layer comprises or consists of electrically conductive material(s) of Indium Tin Oxide.
7. A component according to any of the preceding claims, wherein the said protective layer has water vapor transmission rate lower than lxl 0"2 g/m2/day, or preferably lower than lxlO"3 g/m2/day, as measured at 25 °C, and at 50% relative humidity.
8. A component according to any of the preceding claims, wherein the said protective layer has oxygen transmission rate lower than lxl 0"2 cm3/m2/atm/day, or preferably lower than lxlO"3 cm3/m2/atm/day
9. A component according to any of the preceding claims, wherein the said protective layer forms uniform electrically non-conductive top layer.
10. A component according to any of claims 1 to 9, wherein the said protective layer is electrically conductive, preferably having sheet resistance lower than 1000 ohm, or preferably lower than 100 ohm, or preferable lower than 10 ohm.
11. A component according to any of the preceding claims, wherein the said protective layer has optical transmission higher than 80 % and preferably higher than 85 %.
12. A component according to any of the preceding claims, wherein the said protective layer is transparent for the required electromagnetic wavelengths for the said component.
13. A component according to any of the preceding claims, wherein the refractive index profile of the said protective layer is optimized for light output extraction from the surface of the said component.
14. A component according to any of the preceding claims, wherein the said protective layer forms an anti-reflection coating for the required wavelength range of the said component said anti-reflection coating preferably having a thickness of one quarter wavelength.
15. A component according to any of the preceding claims, wherein the said
semiconductor die is an optoelectronic component, preferably emitting electromagnetic radiation, for example a light emitting diode.
16. A component according to any of claims 1 to 14, wherein the said component detects electromagnetic radiation e.g. a photodiode or a light sensitive sensor array.
17. A component according to any of the preceding claims, formed of
- a substrate,
- semiconductor chip(s),
- electrical contact wire(s), electrical contact layer(s),
- electrically conductive track(s), and
- a protective layer, which
o is a conformal layer forming a uniform coating on the said component's surface,
o is hermetic,
o is optically transparent, and
o comprises sub-layers of two or more different materials, wherein one sublayer is electrically conductive in order to avoid charge accumulation in the coating.
18. A method of making a solid state light emitting and/or light detecting device, in particular based on the use of a component according to any of the claims 1 to 17, comprising:
- providing a first substrate;
- providing on the first substrate a plurality of solid state light emitting and/or light detecting chips;
- wire bonding the solid state chips to the first substrate;
- providing a conformal sealing layer to the solid state chips, wire bonds and any exposed first substrate between the solid state chips;
- providing a second substrate that is transmissive to the wavelength of light to be emitted and/or detected by the solid state chips; and
- providing a sealing layer between the first and second substrates and bonding the first and second substrates together so as to seal the solid state chips therebetween, said sealing layer being an atomic layer deposition (ALD) layer preferably comprising A1203, SiNOx, Zr02, Hf02, (Ba,Sr)Ti03, Hf3N4, Zr3N4, HfOxNy and ZrOxNy and/or Ta2Os, in particular the ALD layer is A1203 or Si Ox or an organic layer, preferably a silicone or epoxy layer.
19. The method of claim 18, further comprising depositing a silicon nitride, oxide or oxynitride layer prior to the ALD layer for coating the solid state chips, wire bonds and any exposed first substrate between the solid state chips, with the ALD layer having a thickness of from 5 to 50 nm deposited thereafter.
20. The method of any of claims 18 or 19, wherein the sealing layer is a metal or ceramic layer, preferably an oxide, nitride or oxynitride of a metal or metalloid, or the sealing layer is a glass frit layer.
21. The method of any of claims 18 to 20, further comprising bonding a second substrate to the first substrate for sealing the light emitting or light detecting chips therebetween, wherein the second substrate is a glass, quartz or sapphire substrate, and preferably the second substrate is a substantially planar substrate.
22. The method of any of claims 18 to 21, wherein the second substrate comprises material selected from the group of an organic polymeric material, a hybrid organic- inorganic polymeric material, a phosphor and combinations thereof.
23. The method of any of claims 18 to 22, wherein the solid state chips comprise both light emitting and light detecting chips, preferably LED chips.
24. The method of any of claims 18 to 23, wherein the conformal layer is a hermetic layer, preferably further comprising, a self-assembled monolayer.
25. The method of any of claims 18 to 24, wherein the ALD layer comprises an nitride, oxide, or oxynitride of aluminum, silicon, zirconium, titanium and/or hafnium.
26. The method of any of claims 18 to 25, further comprising depositing a silicon nitride, oxide or oxynitride layer after the ALD layer for further coating the solid state chips, wire bonds and any exposed first substrate between the solid state chips.
27. The method of any of claims 17 to 25, wherein the ALD layer is an oxide layer preferably comprising CaO, ZnO, Er203, SC203, La203, Hf02, Ta205, Si02, VxOy, Ga203, Y203, Ti02, CuO, Nb205, Yb203, A1203, MgO and/or Zr02or a nitride layer, preferably comprising A1N, TiNx TaNx, and/or TiAIN or an oxynitride layer, preferably comprising Si Ox, HfOxNy and/or ZrOxNy.
28. A solid state device, comprising:
- a first substrate;
- on the first substrate a plurality of solid state light emitting and/or light detecting chips, such as light emitting diodes, which are electrically connected to the first substrate; and
- a conformal sealing layer, which is optionally a hermetic layer and optionally
further comprises a self-assembled monolayer, disposed on the solid state chips, wire bonds and any exposed first substrate between the solid state chips, said sealing layer optionally being an organic layer, preferably a silicone or epoxy layer, or an atomic layer deposition (ALD) layer, preferably having a thickness of from 5 to 50 nm, preferably comprising an nitride, for example a nitride layer comprising A1N, TiNx TaNx, and/or TiAIN, an oxide, for example an oxide layer comprising CaO, ZnO, Er203, Sc203, La203, Hf02, Ta205, Si02, VxOY, Ga203, Y203, Ti02, CuO, Nb205, Yb203, A1203, MgO and/or Zr02, or oxynitride, particularly preferably comprising A1203, SiNOX, Zr02, Hf02, (Ba,Sr)Ti03, Hf3N4, Zr3N4, HfOxNy and ZrOxNy or Ta205, in particular A1203 or SiNOX ,
optionally further comprising a self-assembled monolayer, and/or a metal or ceramic layer, such as an oxide, nitride or oxynitride of a metal or metalloid, or the sealing layer is a glass frit layer, said sealing layer optionally having a water vapor transmission rate lower than lxlO 2 g/m2/day, as measured at 25 °C, and at 50% relative humidity,
further optionally having oxygen transmission rate lower than lxlO 2
cm3/ m2/ atm/ day,
preferably further optionally having sheet resistance lower than 1000 ohm, or preferably lower than 100 ohm, particularly further optionally having optical transmission higher than 80%, in particular higher than 85%,
said sealing layer optionally being provided at a thickness so as to act as an anti- reflection coating at a wavelength of light at which the light emitting or light detecting chips operate.
29. The device of claim 28, wherein a second substrate is provided to connect directly or indirectly to the first substrate for sealing the light emitting or light detecting devices therebetween, and preferably the second substrate is a substantially planar glass, quartz or sapphire substrate, optionally comprising an organic or hybrid organic-inorganic polymeric material, and/or comprising a phosphor, preferably comprising multiple phosphors that emit light at different wavelengths.
30. The device of any of claims 28 to 29, wherein the solid state chips comprise both light emitting and light detecting chips, preferably LED chips.
31. The device of any of claims 28 to 30, further comprising a silicon nitride, oxide or oxynitride layer deposited after the ALD layer for further coating the solid state chips, wire bonds and any exposed first substrate between the solid state chips.
32. The device of any of claims 28 to 31, further comprising:
- a second substrate bonded to the first substrate that is transmissive to the wavelength of light to be emitted and/or detected by the solid state chips.
33. The device of any of claims 28 to 32 further comprising:
- a sealing layer between the first and second substrates for bonding the first and second substrates together so as to seal the solid state chips therebetween, wherein the sealing layer is optionally a glass frit layer, or a metal solder layer, and optionally further comprising an organic polymeric coating on top of the sealing layer, wherein the organic coating comprises at least one phosphorescence material and/or is an epoxy coating or a silicone coating.
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