CN101459210A - Encapsulation structure for photoelectric element and manufacturing process thereof - Google Patents
Encapsulation structure for photoelectric element and manufacturing process thereof Download PDFInfo
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- CN101459210A CN101459210A CNA200710199880XA CN200710199880A CN101459210A CN 101459210 A CN101459210 A CN 101459210A CN A200710199880X A CNA200710199880X A CN A200710199880XA CN 200710199880 A CN200710199880 A CN 200710199880A CN 101459210 A CN101459210 A CN 101459210A
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Abstract
The invention provides a package structure of a photoelectric element and a manufacturing method thereof. The package structure comprises a silicon substrate with a first surface and a second surface, a first insulation layer, a reflective layer, a second insulation layer, a first conductive layer, a second conductive layer and a crystalline grain, wherein the first surface is opposite to the second surface, the first surface is equipped with a reflecting cavity, the second surface is equipped with at least two electrode interlayer holes communicated with the reflecting cavity, the outside of the each electrode interlayer hole is equipped with a groove, the first insulation layer encloses the first and second surfaces of the silicon substrate and the groove, the reflective layer is arranged on the surface of the reflecting cavity and is covered by the second insulation layer, the first conductive layer is arranged on the surface of the first and second insulation layers, the second conductive layer is arranged on the second surface to connect to the first conductive layer, the crystalline grain fixed in the reflecting cavity is connected to the first conductive layer.
Description
Technical field
The present invention relates to a kind of photoelectric element-packaging structure and manufacture method thereof, relate in particular at light-emitting diode (LED) and go up encapsulating structure and the manufacture method thereof of using silicon substrate.
Background technology
Because light-emitting diode (light emitting diode in the photoelectric cell; LED) have that volume is little, luminous efficiency is high and an advantage such as the life-span is long, therefore be considered to the best light source of green energy conservation illumination of future generation.The fashion trend of the fast-developing and full-color screen of LCD in addition, make white light emitting diode except being applied to purposes such as indicator light and large display screen, also be applied in the vast consumption electronic products, for example: mobile phone and PDA(Personal Digital Assistant).
The research and development of at present relevant light-emitting diode focus on luminous efficiency and radiating rate.In luminous efficiency, can improve respectively in extension stage, crystal grain fabrication stage or at encapsulated phase.And improved at encapsulated phase about the heat radiation aspect, the improvement by encapsulating structure or material strengthens radiating efficiency.
The encapsulation of light-emitting diode has many modes at present, wherein uses the light-emitting diode of reflector effectively to increase the luminous efficiency of element by promoting reflectivity.Simultaneously, if reflector has preferable design, can effectively promote the radiating efficiency of light-emitting diode equally.Improved in this respect at present technology has United States Patent (USP) the 6th, 562, and No. 643, the 6th, 268, No. 660 and U.S. Patent Publication No. 2004/0218390.In addition, No. the 6th, 531,328, a kind of prior art such as United States Patent (USP) are disclosed, mainly are to use the base material of silicon substrate 80 as encapsulation.Use the manufacturing process of MEMS (micro electro mechanical system) (MEMS) to make reflector 81 on silicon substrate 80, its structure as shown in Figure 1.One insulating barrier 82 and a metal level 83 coat silicon substrate 80 successively, and wherein metal level 83 is simultaneously as electrode 831 and 832.Light-emitting diode 84 is connected electrically in the reflector 81 in the routing mode, and uses epoxy resin 85 to cover and protect the light-emitting diode 84 that is positioned at reflector 81.Be formed with chadless (semi-through holes) 86 on each reflector 81 both sides, however the purposes of this United States Patent (USP) and undeclared this chadless 86.
Form the procedure of processing of structure as shown in Figure 1, shown in Reference numeral S91～S96 among Fig. 2, comprise: a silicon substrate is provided earlier, and the mode with Wet-type etching forms reflector on silicon substrate then.Then, form the interlayer hole of electrode in the mode of dry-etching at the another side of silicon substrate.Afterwards, form one deck silicon oxide layer with thermal oxidation method or nitrogenize mode or silicon nitride layer coats this silicon substrate.Then, form a conductor layer in the mode of electroplating and coat this silicon substrate.At last, on described reflector, form metallic reflector in the mode of laser treatment and at another surface forming electrode of silicon substrate.
Yet such design has some shortcomings.At first, reflector metal and electrode are to belong to commaterial, do not have a kind of metal to satisfy simultaneously at present to have good reflectivity and applicable to follow-up welding processing.Moreover for the light-emitting diode of different wave length, different metals has different reflectivity, this means that the material of electrode also can change thereupon.The material of preferable electrode is based on scolding tin, but scolding tin and be not suitable for the reflectorized material of visible light.Good reflecting material, for example: gold (Au), silver (Ag), palladium (Pd), platinum (Pt), and be not suitable as the material of electrode.
In addition, dry ecthing is adopted in the etching of bottom interlayer hole, and the elastic space of the following process of the profile after its etching (profile) is lower.Moreover, need to use the laser treatment reflective metal layer, so processing cost is higher.
The applicant is in application for a patent for invention (the TaiWan, China number of patent application: 096105415), improved most of problem of aforementioned prior art of previous proposition.Yet the employed silicon substrate resistivity of this application needs greater than 800 Ω cm, otherwise short circuit is caused in the side that will spread to silicon substrate because of the scolding tin that overflows from electrode.The cost of high resistivity silicon substrate is much larger than the cost of low-resistivity silicon substrate, but the encapsulating structure that this application proposes can't be applied to the low-resistivity silicon substrate.
In sum, press on the market a kind of reliable and process easy high power light electric device or light-emitting diode so that can improve the various shortcomings of above-mentioned existing light-emitting diode.
Summary of the invention
The invention provides a kind of photoelectric element-packaging structure and manufacture method thereof, can use silicon substrate as the substrate of encapsulation strengthening radiating efficiency, and can use ripe micro electronmechanical technology to realize.
The invention provides a kind of photoelectric element-packaging structure and manufacture method thereof, the electrode outside at each photoelectric cell is provided with groove, this groove is coated with insulating barrier, can avoid scolding tin to overflow electrode and spreads on the silicon substrate of side, does not therefore have short circuit and takes place.
The invention provides a kind of photoelectric element-packaging structure and manufacture method thereof of low material cost, but the cheap low-resistivity silicon substrate of use cost is realized encapsulating structure, that is therefore the manufacturing cost of this kind photoelectric cell can reduce significantly.
The invention provides and a kind ofly can select the photoelectric cell of different materials at reflective metal layer and electrode, wherein reflective metal layer can be selected and can not influence the electrode Material Selection at the wavelength of particular light ray, thereby can select the optimization material respectively.
The present invention can use wet etching to form the electrode interlayer hole of bottom, and (process window) is comparatively abundant for follow-up processing space.
The invention provides a kind of photoelectric cell that utilizes the dielectric protection layer reflective metal layer, avoid metal level to produce oxidation, sulfuration or produce reaction with other chemical substance.And the thickness of this insulating barrier can be adjusted into particular light ray is carried out useful interference.
For achieving the above object, the present invention proposes a kind of photoelectric element-packaging structure, and it comprises: the silicon substrate with a first surface and a second surface; This first surface is relative with this second surface, and this first surface has a reflection cavity, and this second surface has at least two electrode interlayer holes that are connected with this reflection cavity, and respectively is provided with a groove in the described electrode interlayer hole outside; One first insulating barrier coats this first surface, this second surface and this groove of this silicon substrate; In addition, this reflection cavity surface is located in a reflector, and one second insulating barrier covers this reflector; One first conductive layer is located at this second insulating barrier and this first surface of insulating layer, and one second conductive layer is located at this second surface and is connected with this first conductive layer; One crystal grain is fixed in this reflection cavity, and is electrically connected to this first conductive layer.
This first insulating barrier is preferably silica, and this second insulating barrier is preferably silicon dioxide, silicon nitride or silicon oxynitride again.
This reflector is preferably aluminium, silver, gold, tin, copper or platinum, its thickness between 300A ° (Ethylmercurichlorendimide) to 20, between 000A °.
This first conductive layer is preferably and extends to this first insulating barrier, and is connected with this second conductive layer, and the two is welding material, for example: silver, nickel/gold, titanium/gold, titanium/nickel/gold, titanium/copper/nickel/gold, titanium tungsten/copper/nickel/gold or chromium/copper/nickel/gold.
The present invention also comprises the adhesive layer of inserting in this reflection cavity.
This crystal grain is electrically connected with this first conductive layer by a plurality of projections, or is electrically connected with this first conductive layer by a plurality of plain conductors.
The present invention also proposes a kind of photoelectric element-packaging structure, it comprises: the silicon substrate with a first surface and a second surface, this first surface is relative with this second surface, and this first surface has a reflection cavity, this second surface has at least two electrode interlayer holes that are connected with this reflection cavity, and respectively is formed with a groove in the described electrode interlayer hole outside; One first insulating barrier coats this first surface, this second surface and this groove of this silicon substrate; In addition, a metal level is located in this reflection cavity, and comprises an echo area and conduction region, and one second insulating barrier covers this echo area; One electrode layer is located at this second surface, and is connected with the conduction region of this metal level; One crystal grain is fixed in this reflection cavity, and is electrically connected on this conduction region.
This metal level is preferably aluminium, silver, gold, tin, copper or platinum.This electrode layer is connected with this conduction region in this metal level, and the two is welding material, for example: silver, nickel/gold, titanium/gold, titanium/nickel/gold, titanium/copper/nickel/gold, titanium tungsten/copper/nickel/gold or chromium/copper/nickel/gold.
The present invention also provides a kind of manufacture method of photoelectric cell: a silicon substrate is provided, and forms at least one reflection cavity in a first surface of this silicon substrate; Afterwards, form a plurality of electrode interlayer holes at a second surface of this silicon substrate, described electrode interlayer hole penetrates this silicon substrate to this reflection cavity, and respectively is provided with a groove in the described electrode interlayer hole outside, and wherein this second surface is relative with this first surface; Form one first insulating barrier then to coat this silicon substrate and this groove; Then, on this reflection cavity, cover a reflector, and on this reflector, form one second insulating barrier; Moreover, on this second insulating barrier, form one first conductive layer, and form one second conductive layer under this second surface and in this two electrodes interlayer hole, wherein this second conductive layer is connected with this first conductive layer; Fix a crystal grain in this reflection cavity, and be electrically connected to this first conductive layer.
This first insulating barrier is preferably by the formed silicon oxide layer of thermal oxidation method, and this second insulating barrier is preferably by the formed silicon dioxide of vapour deposition, silicon nitride or silicon oxynitride layer.
This first conductive layer and this second conductive layer are preferably by plating, evaporation or chemical plating and form, and this first conductive layer is connected with this second conductive layer.
This crystal grain is preferably in the flip chip mode and is fixed in this reflection cavity, or is electrically connected with this first conductive layer by the routing mode.
The present invention also comprises adhesive layer is inserted step in this reflection cavity and this electrode interlayer hole.
The present invention provides a kind of manufacture method of photoelectric cell in addition: a silicon substrate is provided, and forms at least one reflection cavity in a first surface of this silicon substrate; Afterwards, form a plurality of electrode interlayer holes at a second surface of this silicon substrate, described electrode interlayer hole penetrates this silicon substrate to this reflection cavity, and respectively is provided with a groove in described each electrode interlayer hole outside, and wherein this second surface is relative with this first surface; Form one first insulating barrier then to coat this silicon substrate and this groove; Then, cover a metal level on this reflection cavity, wherein this metal level comprises echo area and conduction region, and forms one second insulating barrier on this echo area; Moreover under this second surface and be positioned at this two electrodes interlayer hole and form an electrode layer, wherein this electrode layer is connected with this conduction region; At this reflection cavity internal fixation one crystal grain, and be electrically connected on this conduction region.
This metal level and this electrode layer are preferably by plating, evaporation or chemical plating and form.
The present invention provides a kind of encapsulating structure of solid-state light emitting element in addition, comprise: one has the silicon substrate of a first surface and a second surface, one first insulating barrier, a reflector, that coats this silicon substrate is positioned at second insulating barrier on this reflector, one as two electronic padses and first conductive layer of isolating electrically with this reflector, and one second conductive layer; This first surface is relative with this second surface, and this first surface has a reflection cavity thereon, and this second surface has two electrode interlayer holes, and described electrode interlayer hole sees through this second surface to this reflection cavity; This reflector is positioned on this reflection cavity; This first conductive layer is positioned on this two electrodes interlayer hole, and this first conductive layer is isolated electrically as two electronic padses and with this reflector; This second conductive layer is positioned under this second surface and is positioned at described two electrode interlayer holes.
This first conductive layer and this second conductive layer are welding material.In addition, this second conductive layer is electrically connected with this first conductive layer.
This first conductive layer and this second conductive layer are by the use etching method or (lift-off) method of peeling off forms design transfer.
Description of drawings
Fig. 1 is the encapsulating structure schematic diagram of existing light-emitting diode;
Fig. 2 shows the process chart that forms as the package structure for LED among Fig. 1;
Fig. 3 (a)～3 (n) is the step of manufacturing schematic diagram of photoelectric cell of the present invention;
Fig. 4 (a)～4 (c) is the step of manufacturing schematic diagram of another embodiment of the present invention photoelectric cell;
Fig. 5 is the schematic diagram of another embodiment of the present invention photoelectric element-packaging structure;
Fig. 6 is the schematic diagram of another embodiment of the present invention photoelectric element-packaging structure;
Fig. 7 (a)～7 (i) is the step of manufacturing schematic diagram of another embodiment of the present invention photoelectric cell; And
Fig. 8 is the schematic diagram of another embodiment of the present invention photoelectric element-packaging structure.
Wherein, description of reference numerals is as follows:
11 silicon substrates, 12,13 dielectric materials layers
14,15 photoresist layers, 16 reflection cavity
17,18 electrode interlayer holes 19,19 ' groove
32,32 ' adhesive layer, 34 projections
35 plain conductors, 39 adhesive tapes
71 silicon substrates, 76 reflection cavities
77,78 electrode interlayer holes, 79 grooves
80 silicon substrates, 81 reflectors
82 insulating barriers, 83 metal levels
84 light-emitting diodes, 85 epoxy resin
86 chadlesses
The 11A cup 11B of portion base portion
21A, the 21B first insulating barrier 22A, 22B reflector
23A, the 23B second insulating barrier 31A, 31B crystal grain
33A, 33B photoelectric cell 22A ' reflector
111 first surfaces, 112 second surfaces
121,122 conductive layers, 131,132 electrodes
121 ', 122 ' conductive layer, 131,132 electrodes
711 first surfaces, 712 second surfaces
721 first insulating barriers, 722 reflector
723 second insulating barriers, 741,742 front electrodes
751,752 backplates, 831,832 electrodes
Embodiment
Fig. 3 (a)～3 (n) is the step of manufacturing schematic diagram of photoelectric cell of the present invention.Shown in Fig. 3 (a), a silicon substrate 11 has a first surface 111 and a second surface 112, and first surface 111 is upper surfaces in the drawings, and second surface 112 is lower surfaces.Silicon substrate 11 can be the silicon wafer of high resistivities such as five inches, six inches, eight inches or 12 inches, and its resistivity is less than 200 Ω cm, and can use＜100 the silicon wafer of crystal surface (crystal orientation surface).In addition, silicon atom can be distinguished into monocrystalline silicon, polysilicon and amorphous silicon again according to different crystallization modes.The advantage of using silicon substrate 11 is that heat radiation is good, and can carry out ripe semiconductor machining or micro electronmechanical processes.
Shown in Fig. 3 (b), on silicon substrate 11, be covered with dielectric materials layer (dielectric layer) 12 and 13 (or insulating barriers), this step can utilize the mode of plasma auxiliary chemical vapor deposition (PECVD) to deposit.The dielectric material that dielectric materials layer 12 and 13 selection can be the agent of anti-silicon anisotropic etching gets final product, and the agent of anti-silicon anisotropic etching is a highly basic, for example: potassium hydroxide (KOH; Potassiumhydroxide), TMAH (Tetramethyl ammonium hydroxide), EDP (Ethylenediaminepyrocatochol) or N
2H
4Deng. Dielectric materials layer 12 and 13 can use silicon nitride (silicon nitride; Si
3N
4), silicon dioxide and silicon oxynitride etc.In the present embodiment, dielectric materials layer 12 and 13 is to use silicon nitride.Then implement the next step shown in Fig. 3 (c), on dielectric materials layer 12 and 13, be covered with photoresist (photoresist) layer 14 and 15 of patterning respectively.
Shown in Fig. 3 (d), the dielectric materials layer 12 and 13 that will not cover photoresist layer 14 and 15 parts is removed with etching mode, and then removes photoresist layer 14 and 15.The first surface 111 that so just can will not cover dielectric materials layer 12 forms reflection cavity (reflectiveopening) 16 with etching mode, and the degree of depth of described reflection cavity arrives the top side location of groove 19, shown in Fig. 3 (e).And the second surface 112 that will not cover dielectric materials layer 13 again forms electrode interlayer hole 17 and 18 with etching mode, and forms groove 19.
Shown in Fig. 3 (e)～3 (f), remove remaining dielectric materials layer 12 and 13, and silicon substrate 11 originally can be divided into base portion 11B and the 11A of cup portion.If dielectric materials layer 12 and 13 is a silicon nitride, then can use phosphoric acid (phosphoric acid) to divest through heating.Around base portion 11B and the 11A of cup portion, form first insulating barrier 21A and the 21B respectively, in the present embodiment for selecting to use silicon dioxide (SiO
2) as first insulating barrier 21A and the 21B.Base portion 11B and the 11A of cup portion were exposed in high temperature and the oxygen containing environment after a period of time, can form one deck and silicon tack on the surface of the silicon materials of base portion 11B, the 11A of cup portion and groove 19 well and satisfactory second insulator 21A and the 21B of dielectric property, for example: silicon dioxide.
Below two chemical equations the oxidation reaction of silicon in oxygen or steam described:
1. dry type oxidation (dry oxidation)
Si (solid)+O
2(gas) → SiO
2(solid)
2. wet oxidation (wet oxidation)
Si (solid)+2H
2O (gas) → SiO
2(solid)+2H
2(gas)
In the present embodiment, the first insulator 21A and 21B are the thermal oxides that the mode with wet oxidation forms, and the technological temperature of reaction is between 900 ℃ to 1100 ℃.Because of the time of required reaction shorter, formed thickness between 30A ° to 10, between 000A °.
Shown in Fig. 3 (h)～3 (i), reflector 22A and 22B in the difference coating of the surface of the first insulator 21A and 21B, this step can utilize physical gas phase deposition technology (PVD) to deposit.Above reflector 22A and 22B, cover second insulating barrier 23A and the 23B then, can utilize the mode of plasma auxiliary chemical vapor deposition (PECVD) to deposit a passivation layer (passivation) with as this second insulating barrier 23A and 23B, for example: silicon dioxide, silicon nitride or silicon oxynitride (Silicon-Oxy-Nitride; SiO
xN
y), its main function is to form or protective layer, can prevent that the metal among reflector 22A and the 22B is oxidized.
Silicon oxynitride is a kind of dielectric material of a kind of character between silicon dioxide and silicon nitride, and its characteristic is that the size of stress is littler than silicon nitride, and more better than silicon dioxide to the blocking capability of steam and impurity, so be common protective layer material.Though silica can deposit in the mode of low-pressure chemical vapor deposition (LPCVD), and the environment that is higher than more than 850 ℃ in temperature forms.But for the technological temperature that makes the silicon oxynitride of using as overcoat can be lower than 400 ℃ (to avoid influencing the metal level that has formed on silicon substrate), in the depositing operation of existing silicon oxynitride, all be to carry out in the mode of plasma auxiliary chemical vapor deposition.
Shown in Fig. 3 (j)～3 (k), form conductive layer 121 and 122 again, wherein conductive layer 121 and 122 is located at the surface of the second insulating barrier 23A and 23B respectively, or extends to the surface of the first insulating barrier 21A and 21B.Conductive layer 121 and 122 materials can be chosen as welding material, and look the difference of follow-up packaging technology and the material selecting to be fit to, for example: silver (Ag), nickel/gold (Ni/Au), titanium/gold (Ti/Au), titanium/nickel/gold (Ti/Ni/Au), titanium/copper/nickel/gold (Ti/Cu/Ni/Au), titanium tungsten/copper/nickel/gold (TiW/Cu/Ni/Au) or chromium/copper/nickel/gold (Cr/Cu/Ni/Au) etc.Conductive layer 121 and 122 design transfer can utilize photolithography technology (promptly forming design transfer with etching mode) or the mode of stripping technology forms, and the generation type of conductive layer 121 and 122 can be used plating, evaporation or chemical plating.
The purpose of reflector 22A and 22B mainly is the brightness that is used for increasing photoelectric cell.The material of reflector 22A and 22B can be selected and conductive layer 121 and 122 identical or different materials, if reflector 22A and 22B select and conductive layer 121 and 122 identical materials, can use Al/Ni/Au.If instead reflector 22A and 22B select and conductive layer 121 and 122 different materials, then can be to use aluminium (Al), silver (Ag), gold (Au), tin (Sn), copper (Cu) or platinum metals such as (Pt), select required material according to the difference of wavelength of light, and the thickness of reflector 22A and 22B between 300A ° to 20, between 000A °.
On the first insulating barrier 21A of Lower Half and 21B, form back electrode 131 and 132, wherein electrode 131 is electrically connected conductive layer 121, and electrode 132 is electrically connected conductive layer 122, described electrode 131 and 132 material can be chosen as welding material, or the general good material of conductivity all can, for example: Ag, Ni/Au, Ti/Au, Ti/Ni/Au, Ti/Cu/Ni/Au, TiW/Cu/Ni/Au, Cr/Cu/Ni/Au etc., electrode 131 and 132 design transfer can utilize photolithography technology (promptly utilizing etching mode to form design transfer) or the mode of stripping technology forms, and the generation type of electrode 131 and 132 can be used plating, evaporation or chemical plating.
Shown in Fig. 3 (l), the crystal grain 31A of optoelectronic semiconductor is fixed on the conductive layer 122 in this reflection cavity 16, and be electrically connected on conductive layer 121 and 122, that is be electrically connected by plain conductor 35 and conductive layer 121 and 122 by the mode that routing engages (wire bonding).
Shown in Fig. 3 (m)～3 (n), can with adhesive tape 39 electrode interlayer hole 17 and 18 be touched earlier, in reflection cavity 16, electrode interlayer hole 17 and 18, form adhesive layer 32.After treating that adhesive layer 32 solidifies, again adhesive tape 39 is removed.Except using adhesive tape 39, also can use other sealing barrier material to spill in the adhesive layer 32 self-electrode interlayer holes 17 avoiding, for example: light sheet or mould etc.At last, cutting base portion 11B is to form the photoelectric cell 33A of independent monomer.There is at least one groove 19 both sides of this photoelectric cell 33A, and groove 19 lays respectively at the outside of electrode interlayer hole 17 and 18.When photoelectric cell 33A was welded and fixed to a circuit board, this groove 19 that is coated with the first insulating barrier 21A can avoid scolding tin to overflow and spread to the side of the 11A of cup portion (silicon substrate), did not therefore have short circuit and took place.That is groove 19 can hold unnecessary scolding tin, thereby scolding tin can not spread to the cup portion 11A side that is not coated with insulating barrier.Especially the silicon substrate that uses low-resistivity overflows scolding tin and causes photoelectric cell 33A problem of short-circuit the most serious during as the material of base portion 11B and the 11A of cup portion, and the present invention can solve this problem of short-circuit fully.
Prior art shown in Figure 1, the outside of chadless 86 still has silicon substrate to expose, therefore as the scolding tin that overflows be not contained in fully in the chadless 86, then scolding tin will direct spreading to the silicon substrate that is not coated with insulating barrier and cause short circuit.Review the present invention,, thereby can not spread to the cup portion 11A side that is not coated with insulating barrier because groove 19 can hold unnecessary scolding tin.In addition, both structures also differ bigger.
Except the mode that routing engages, also can adopt the mode of flip chip (flip-chip) that crystal grain 31B is fixed and be electrically connected, shown in Fig. 4 (a) with conductive layer 121 and 122.Be positioned at the groove 19 in the electrode interlayer hole outside ' among the figure for a plurality of.Then, shown in Fig. 4 (b)～4 (c), with adhesive tape 39 the electrode interlayer hole is touched earlier, in reflection cavity and described electrode interlayer hole, form adhesive layer 32.After treating that adhesive layer 32 solidifies, again adhesive tape 39 is removed.At last, cutting base portion 11B is to form the photoelectric cell 33B of independent monomer, and wherein crystal grain 31B is electrically connected with conductive layer 121 and 122 by projection 34.
Previous embodiment is that conductive layer 121,122 and reflector 22A, 22B deposition when the different step is adhered to, yet also can in same deposition step, form, as Fig. 5 and shown in Figure 6, wherein Fig. 5 shows that routing engages the encapsulating structure of pattern, and Fig. 6 shows that flip chip engages the encapsulating structure of pattern.Conductive layer 121 among Fig. 5 and Fig. 6 ', 122 ' be in same deposition step, to form with reflector 22A ', that is their selected materials are also identical.
The present invention also provides a kind of encapsulating structure and manufacture method thereof of solid-state light emitting element, shown in Fig. 7 (a)～7 (i).One silicon substrate 71 has a first surface 711 and a second surface 712, and first surface 711 is upper surfaces in the drawings, and second surface 712 is lower surfaces.Silicon substrate 71 can be the wafer of five inches, six inches, eight inches or 12 inches etc.Silicon substrate 71 can use＜100 crystal surface.Using the several important advantages of silicon substrate is exactly good heat dissipation, and can carry out ripe micro electronmechanical processes.
Shown in Fig. 7 (b), on the first surface 711 of silicon substrate 71, form a reflection cavity 76 in the mode of wet etching, and form groove 79 respectively at the second surface 712 and reflection cavity 76 outsides.The etching solvent of the wet etching of silicon substrate 71 can be potassium hydroxide (KOH).Comprise photolithography technology in this step, just utilize etching technique to realize design transfer, the step that comprises has photoresist coating, soft baking photoresist, exposure, development, hard baking, etching silicon base material and removes photoresist.With reflection cavity 76 and groove 79 that the mode of wet etching forms, its etched profile (profile) is adjustable, and this is because the tropism that waits of wet etching causes.
Shown in Fig. 7 (c), continue on the second surface 712 of silicon substrate 71, to form electrode interlayer hole 77 and 78 in the mode of wet etching. Electrode interlayer hole 77 and 78 can be two, or more than two, and particularly the light-emitting component of Shi Yonging surpasses two and may have four or six electrode interlayer holes 77 and 78 when above.Owing to use wet etching to form the electrode interlayer hole, electrode interlayer hole 77 and 78 opening are bigger, and be comparatively well-to-do for follow-up processing space.Same, this step comprises photolithography technology.
Shown in Fig. 7 (d), form one and coat the silicon oxide layer of silicon substrate 71 as first insulating barrier 721.The mode that silicon oxide layer forms can be thermal oxidation method or chemical vapour deposition technique, and preferred thermal oxidation method, because the silica that forms with thermal oxidation method, its structure is comparatively fine and close.In the present invention, can use dry type or wet type thermal oxidation method.In addition, can also use silicon nitride as first insulating barrier 721.
Shown in Fig. 7 (e), form a reflector 722 in reflection cavity 76.The material in reflector 722 can be silver, aluminium, gold or tin, and wherein the wavelength of employed light is depended in the selection of material.The generation type in reflector 722 can be used plating (electroplating), vapour deposition method (evaporating), or the electron beam epitaxy forms.Because 722 in reflector is formed on the first surface 711 of silicon substrate 71, processing conditions is simpler.In addition, can also utilize etch process that reflector 722 parts beyond the reflection cavity 76 are removed in addition behind the formation reflector 722, and this step is selectable step.
Shown in Fig. 7 (f), form one second insulating barrier 723 and cover reflector 722.Second insulating barrier 723 can be silica or silicon nitride, can be formed by chemical vapour deposition technique.Wherein silica can use plasma gain chemical vapour deposition technique, and silicon nitride can use Low Pressure Chemical Vapor Deposition.The thickness of deposition can be adjusted into for particular beam and has useful interference.Reflector 722 is to coat protection by second insulating barrier 723; can avoid reflective metals oxidation, sulfuration or with other chemical reaction; wherein particularly to select metallic aluminium or tin situation, because the oxidation especially easily of these two kinds of metals as reflective metals.
Shown in Fig. 7 (g), form a first metal layer as front electrode 741 and 742. Front electrode 741 and 742 material be chosen as welding material, its selection determined by follow-up packaging technology, for example: routing encapsulation or flip chip encapsulation because front electrode mainly is to weld with light-emitting component. Front electrode 741 and 742 generation type can be used and electroplate or the mode of evaporation etc. Front electrode 741 and 742 pattern can use and above-mentioned utilize etching method or stripping technology forms design transfer.The formed design transfer of stripping technology and etch process is similar, but order is different.The step of stripping technology is to form the photoresist layer earlier, is exposure imaging then, and at this moment metal level just is formed on the photoresist layer, the metal level that is positioned on the photoresist can be removed together when the photoresist layer removes afterwards.Stripping technology need not reduce by a step at the metal level etching.No matter be to utilize etching method or utilization to peel off method to carry out design transfer, all more traditional laser technology of its cost is cheap, and is ripe technology.
Because there is second insulating barrier 723, front electrode 741 and 742 and reflector 722 electric insulations.This can be avoided because of electric leakage element being produced infringement.
Shown in Fig. 7 (h), form one second metal level as backplate 751 and 752.Backplate 751 and 752 material may be selected to be welding material or general electrode material.Backplate 751 and 752 generation type are identical with the generation type of front electrode 741 and 742, and the mode of design transfer can be identical with the generation type of front electrode 741 and 742 or inequality.Backplate 751 and 752 need be filled up electrode interlayer hole 77 and 78 and be electrically connected with front electrode 741 and 742.
Shown in Fig. 7 (i), after the crystal grain 31A routing encapsulation with light-emitting diode, the adhesive layer 32 that re-uses epoxy resin covers.Adhesive layer 32 can the doping fluorescent powder, and fluorescent material can be yttrium-aluminium-garnet (YAG) family or silicate families.The main body chemical formula of this silicate families is A
2SiO
4, wherein A is for being selected from strontium, calcium, barium, magnesium (Mg), zinc (Zn) and the cadmium (Cd) one at least.The mode that adhesive layer 32 is enclosed can be the mode of revolving die (transfer molding) or the injection of some glue.
As shown in Figure 8, use epoxy resin adhesive layer 32 to cover the crystal grain 31B flip chip encapsulation back of light-emitting diode.Same, adhesive layer 32 can the doping fluorescent powder, and fluorescent material can be yttrium-aluminium-garnet family or silicate families.And adhesive layer 32 covers the mode that the mode of enclosing can be revolving die or the injection of some glue.
Technology contents of the present invention and technical characterstic are described as above, yet the personnel that are familiar with this technology still may be based on enlightenment of the present invention and descriptions and made various replacement and the modifications that do not break away from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the described content of embodiment, and should comprise various do not break away from replacement of the present invention and modifications, and is contained by following claim.
Claims (23)
1, a kind of photoelectric element-packaging structure comprises:
One silicon substrate, it has a first surface and a second surface, and wherein this first surface has a reflection cavity, and a plurality of electrode interlayer holes that this second surface has and this reflection cavity is communicated with, and respectively is provided with at least one groove in the described electrode interlayer hole outside;
One first insulating barrier, it coats this first surface, this second surface and this groove;
One reflector, it is located in this reflection cavity;
One second insulating barrier, it is located on this reflector;
One first conductive layer, it is located at this second surface of insulating layer;
One second conductive layer, it is located at this first surface of insulating layer, and is positioned at described electrode interlayer hole, and wherein this first conductive layer extends to this first insulating barrier, and is connected with this second conductive layer; And
One crystal grain, it is fixed in this reflection cavity, and is electrically connected on this first conductive layer.
2, a kind of photoelectric element-packaging structure comprises:
One silicon substrate, it has a first surface and a second surface, and wherein this first surface has a reflection cavity, and a plurality of electrode interlayer holes that this second surface has and this reflection cavity is communicated with, and respectively is provided with at least one groove in the described electrode interlayer hole outside;
One first insulating barrier, it coats this first surface, this second surface and this groove;
One metal level, it is located in this reflection cavity, and comprises echo area and conduction region;
One second insulating barrier, it is located on this echo area;
One electrode layer, it is located at this first surface of insulating layer, and is positioned at described electrode interlayer hole, and wherein this electrode layer is connected with this conduction region in this metal level; And
One crystal grain, it is fixed in this reflection cavity, and is electrically connected on this conduction region of this metal level.
3, a kind of photoelectric element-packaging structure comprises:
One silicon substrate, it has a first surface and a second surface, and this first surface is relative with this second surface, wherein has a reflection cavity on this first surface, have at least two electrode interlayer holes on this second surface, and described electrode interlayer hole penetrates into this reflection cavity, and this second surface has at least one groove that is positioned at the described electrode interlayer hole outside;
One first insulating barrier, it coats this first surface, this second surface and described groove;
One reflector, it is positioned on this reflection cavity;
One second insulating barrier, it is positioned on this reflector;
One first conductive layer, it is positioned on the described electrode interlayer hole, this first conductive layer as two electronic padses and with this reflector electric insulation; And
One second conductive layer, it is positioned under this second surface and is positioned at described electrode interlayer hole, and wherein this second conductive layer is electrically connected with this first conductive layer.
4, a kind of manufacture method of optoelectronic component encapsulation construction comprises the following step:
One silicon substrate is provided;
First surface at this silicon substrate forms at least one reflection cavity;
Second surface at this silicon substrate forms a plurality of electrode interlayer holes and a plurality of groove, and wherein said electrode interlayer hole penetrates this silicon substrate to this reflection cavity, and described groove is positioned at the described electrode interlayer hole outside;
Form one first insulating barrier to coat this reflection cavity, described a plurality of electrode interlayer holes and described a plurality of groove;
In this reflection cavity, cover a reflector;
On this reflector, form one second insulating barrier;
On this second insulating barrier, form one first conductive layer;
Form one second conductive layer on this second surface and in described a plurality of electrode interlayer holes, wherein this second conductive layer is electrically connected with this first conductive layer; And
At this reflection cavity internal fixation one crystal grain, and be electrically connected this crystal grain and this first conductive layer.
5, a kind of manufacture method of optoelectronic component encapsulation construction comprises:
One silicon substrate is provided;
One first surface of this silicon substrate of etching is to form a reflection cavity on this surface;
One second surface of this silicon substrate of etching, on this second surface, to form a plurality of electrode interlayer holes, and described electrode interlayer hole penetrates this silicon substrate to this reflection cavity, and on this second surface, form a plurality of grooves, wherein this second surface is relative with this first surface, and described groove is positioned at the described electrode interlayer hole outside;
Form one first insulating barrier to coat this reflection cavity, described a plurality of electrode interlayer holes and described a plurality of groove;
On this reflection cavity, form a reflector;
On this reflector, form one second insulating barrier;
On described a plurality of electrode interlayer holes, form one first conductive layer, this first conductive layer as two electronic padses and with this reflector electric insulation; And
Form one second conductive layer under this second surface, and this second conductive layer is positioned at described a plurality of electrode interlayer hole, wherein this second conductive layer is electrically connected with this first conductive layer.
6, a kind of manufacture method of optoelectronic component encapsulation construction comprises the following step:
One silicon substrate is provided;
First surface at this silicon substrate forms at least one reflection cavity;
Second surface at this silicon substrate forms a plurality of electrode interlayer holes and a plurality of groove, and wherein said electrode interlayer hole penetrates this silicon substrate to this reflection cavity, and described groove is positioned at the described electrode interlayer hole outside;
Form one first insulating barrier to coat this reflection cavity, described a plurality of electrode interlayer holes and described a plurality of groove;
Cover a metal level in this reflection cavity, wherein this metal level comprises echo area and conduction region;
On this echo area, form one second insulating barrier;
Form an electrode layer on this second surface and in described a plurality of electrode interlayer holes, wherein this conduction region is connected with this electrode layer; And
At this reflection cavity internal fixation one crystal grain, and be electrically connected this crystal grain and this conduction region.
7, a kind of manufacture method of optoelectronic component encapsulation construction comprises the following step:
One silicon substrate is provided;
First surface at this silicon substrate forms at least one reflection cavity;
Second surface at this silicon substrate forms a plurality of electrode interlayer holes and a plurality of groove, and wherein this electrode interlayer hole penetrates this silicon substrate to this reflection cavity, and this groove is positioned at this electrode interlayer hole outside;
At described reflection cavity internal fixation one crystal grain;
Seal the opening of described a plurality of electrode interlayer holes with the sealing barrier material; And
In described reflection cavity, described a plurality of electrode interlayer holes, form adhesive layer.
8, according to the manufacture method of the optoelectronic component encapsulation construction of claim 7, also comprise the following step:
Form one first insulating barrier to coat this reflection cavity, described a plurality of electrode interlayer holes and described a plurality of groove;
Cover a reflector in this reflection cavity;
On this reflector, form one second insulating barrier;
On this second insulating barrier, form one first conductive layer; And
Form one second conductive layer on this second surface and in described a plurality of electrode interlayer holes, wherein this second conductive layer is electrically connected with this first conductive layer.
9, according to the manufacture method of the optoelectronic component encapsulation construction of claim 7, also comprise the following step:
Form one first insulating barrier to coat this reflection cavity, described a plurality of electrode interlayer holes and described a plurality of groove;
Cover a metal level in this reflection cavity, wherein this metal level comprises echo area and conduction region;
On this echo area, form one second insulating barrier; And
Form an electrode layer on this second surface and in described a plurality of electrode interlayer holes, wherein this conduction region is connected with this electrode layer.
10, according to the manufacture method of claim 1,2 or 3 photoelectric element-packaging structure or claim 4,5,6,8 or 9 optoelectronic component encapsulation construction, wherein this first insulating barrier is by the formed silicon oxide layer of thermal oxidation method, and wherein this second insulating barrier is by the formed silicon dioxide of vapour deposition, silicon nitride or silicon oxynitride layer.
11, according to the manufacture method of the photoelectric element-packaging structure of claim 1 or 3 or claim 4,5 or 8 optoelectronic component encapsulation construction, wherein the material in this reflector is aluminium, silver, gold, tin, copper or platinum, and the step that forms this reflector realizes with galvanoplastic, vapour deposition method or electron beam epitaxy.
12, according to the photoelectric element-packaging structure of claim 11 or the manufacture method of optoelectronic component encapsulation construction, wherein the thickness in this reflector between 300A ° to 20, between 000A °.
13, according to the photoelectric element-packaging structure of claim 11 or the manufacture method of optoelectronic component encapsulation construction, wherein this first conductive layer and this second conductive layer are welding material, its material is silver, nickel, titanium/gold, titanium/nickel/gold, titanium/copper/nickel/gold, titanium tungsten/copper/nickel/gold or chromium/copper/nickel/gold, this first conductive layer and this second conductive layer are to form by plating, evaporation or chemical plating, form design transfer by using the etching method or the method for peeling off.
14, according to the manufacture method of the optoelectronic component encapsulation construction of the photoelectric element-packaging structure of claim 2 or claim 6 or 9, wherein this electrode layer and this metal level are welding material, be silver, nickel/gold, titanium/gold, titanium/nickel/gold, titanium/copper/nickel/gold, titanium tungsten/copper/nickel/gold or chromium/copper/nickel/gold, this metal level and this electrode layer are to form by plating, evaporation or chemical plating.
15, according to the manufacture method of the optoelectronic component encapsulation construction of the photoelectric element-packaging structure of claim 2 or claim 6 or 9, wherein the material of this metal level is aluminium, silver, gold, tin, copper or platinum, is to form by plating, evaporation or chemical plating.
16, according to the manufacture method of claim 1,2 or 3 photoelectric element-packaging structure or claim 4,5,6,7,8 or 9 optoelectronic component encapsulation construction, also comprise the adhesive layer of inserting in this reflection cavity.
17, according to the manufacture method of the photoelectric element-packaging structure of claim 1 or 2 or claim 4,6,8 or 9 optoelectronic component encapsulation construction, wherein this crystal grain is electrically connected with this first conductive layer or this metal level by a plurality of projections.
18, according to the manufacture method of the photoelectric element-packaging structure of claim 1 or 2 or claim 4,6,8 or 9 optoelectronic component encapsulation construction, wherein this crystal grain is through being electrically connected with this first conductive layer or this metal level by a plurality of plain conductors.
19, according to the manufacture method of the photoelectric element-packaging structure of claim 1 or 2 or claim 4,6,8 or 9 optoelectronic component encapsulation construction, wherein this crystal grain is light-emitting diode.
20, according to the manufacture method of claim 1,2 or 3 photoelectric element-packaging structure or claim 4,5,6,8 or 9 optoelectronic component encapsulation construction, wherein said groove is located at this second conductive layer outside.
21, according to the manufacture method of claim 1,2 or 3 photoelectric element-packaging structure or claim 4,5,6,8 or 9 optoelectronic component encapsulation construction, wherein said electrode interlayer hole is to be formed by wet etch method.
22,, also be included in the step that removes this sealing barrier material after this adhesive layer solidifies according to the manufacture method of the optoelectronic component encapsulation construction of claim 7.
23, according to the manufacture method of the optoelectronic component encapsulation construction of claim 7, wherein this sealing barrier material is an adhesive tape.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA200710199880XA CN101459210A (en) | 2007-12-14 | 2007-12-14 | Encapsulation structure for photoelectric element and manufacturing process thereof |
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| CNA200710199880XA CN101459210A (en) | 2007-12-14 | 2007-12-14 | Encapsulation structure for photoelectric element and manufacturing process thereof |
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| CN101459210A true CN101459210A (en) | 2009-06-17 |
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| CNA200710199880XA Pending CN101459210A (en) | 2007-12-14 | 2007-12-14 | Encapsulation structure for photoelectric element and manufacturing process thereof |
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| TWI450345B (en) * | 2010-11-03 | 2014-08-21 | Xintec Inc | Chip package and method for forming the same |
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