200834970 · 九、發明說明： Λ 【發明所屬之技術領域】 本發明係關於一種光電元件之封裝結構及其製造方法， 尤係關於使用矽基板於發光二極體（LED)的封裝結構及其 製造方法。 【先前技術】 由於光電元件中發光二極體（light emitting diode ; LED )有 I 體積小、發光效率高及壽命長等優點，因此被認為是次世代綠 色節能照明的最佳光源。另外液晶顯示器的快速發展及全彩螢 幕的流行趨勢，使白光系發光二極體除了應用於指示燈及大型 顯示幕等用途外，更切入廣大之消費性電子產品，例如：手機 及個人數位助理（PDA)。 目前有關發光二極體之研發重點是在於光的取出效益以 及散熱的速度。在光的取出效益中，可以在磊晶階段、晶 粒製造階段或是在封裝階段分別進行改善。而關於散熱方 φ 面目前主要是在封裝階段予以改良，藉由封裝結構或材料 之改善而增進散熱效率。 發光二極體的封裝目前有許多的方式，其中使用反射杯 的發光二極體元件可藉由提升反射率，以有效增加元件之 發光效率。同時，如果反射杯有較佳的設計，同時也能有 效提升發光二極體元件的散熱效率。目前朝這方面改善的 技術有美國專利第6,562,643號、第6,268,660號以及美國 專利公開號2004/0218390。另外，一種先前技術如美國專 利第6,531，328號所揭露，主要是使用矽基板80做為封裝 200834970 的基材。在矽基板80上使用微機電（MEMS)的製程製造反 射杯81，其結構如圖i所示。一絕緣層82以及一金屬層 83依序包覆矽基板8〇，其中金屬層83同時作為電極 及832。發光二極體84以打線方式電性連接於反射杯81 内，亚且使用環氧樹脂85覆蓋並保護於反射杯81内之發 光二極體84。 形成如圖1所示之結構之製程步驟，如圖2中標號S91 φ 〜S96所不，包含先提供一矽基板，然後以濕式蝕刻的方 式在矽基板上形成反射腔。接著，在矽基板的另一面以乾 式蝕刻的方式形成電極的介層孔。之後，以熱氧化法或是 氮化方式形成一層氧化矽層或是氮化矽層包覆該矽基板。 然後，以電鍍的方式形成一導體層包覆該矽基板。最後， 以雷射處理的方式在反射腔上形成金屬反射層而在另一面 形成電極。 然而，這樣的設計有一些缺點。首先，反射層金屬與電 春 極疋屬於同一個材料，目前沒有一種金屬可以同時滿足良 好的反射率以及可適用於後續的焊接製程。再者，對於不 同波長的發光二極體，不同的金屬會有不同的反射率，這 表示電極的材料也會因著改變。較佳的電極的材料是以焊 錫為主，但焊錫並不適用於可見光的反光材料。好的反射 材料，例如：金（Au)、銀（Ag)、鈀（Pd)、鉑（Pt)，並不適用 作為電極之材料。 另外，底部介層孔的蝕刻採用乾蝕刻，其蝕刻後的輪廓 (profile)的後續製程之彈性空間較低。再者，需要使用雷射200834970 · IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a package structure of a photovoltaic element and a method of fabricating the same, and more particularly to a package structure using a germanium substrate for a light emitting diode (LED) and manufacturing thereof method. [Prior Art] Since the light emitting diode (LED) in the photovoltaic element has the advantages of small volume I, high luminous efficiency, and long life, it is considered to be the best light source for the next generation of green energy-saving lighting. In addition, the rapid development of liquid crystal displays and the trend of full-color screens make the white light-emitting diodes not only be used for indicators and large display screens, but also into consumer electronics products such as mobile phones and personal digital assistants. (PDA). At present, the focus of research and development on light-emitting diodes lies in the efficiency of light extraction and the speed of heat dissipation. In the light extraction benefit, improvements can be made in the epitaxial stage, in the grain manufacturing stage, or in the packaging stage, respectively. At present, the heat dissipation side φ surface is mainly improved at the packaging stage, and the heat dissipation efficiency is improved by the improvement of the package structure or material. There are many ways to package a light-emitting diode, and a light-emitting diode element using a reflective cup can effectively increase the luminous efficiency of the element by increasing the reflectance. At the same time, if the reflector cup has a better design, it can also effectively improve the heat dissipation efficiency of the LED component. Techniques that are currently being improved in this regard are U.S. Patent Nos. 6,562,643, 6,268,660, and U.S. Patent Publication No. 2004/0218390. In addition, a prior art, such as U.S. Patent No. 6,531,328, discloses the use of a tantalum substrate 80 as a substrate for the package 200834970. A reflector cup 81 is fabricated on the ruthenium substrate 80 using a microelectromechanical (MEMS) process, the structure of which is shown in Figure i. An insulating layer 82 and a metal layer 83 are sequentially coated on the substrate 8A, wherein the metal layer 83 serves as both electrodes and 832. The light-emitting diode 84 is electrically connected to the reflective cup 81 in a wire-bonding manner, and is covered with an epoxy resin 85 and protected by the light-emitting diode 84 in the reflective cup 81. The process steps for forming the structure shown in Fig. 1, as indicated by reference numerals S91 φ to S96 in Fig. 2, include providing a substrate first, and then forming a reflective cavity on the ruthenium substrate by wet etching. Next, a via hole of the electrode is formed by dry etching on the other side of the germanium substrate. Thereafter, a tantalum oxide layer or a tantalum nitride layer is formed by thermal oxidation or nitridation to coat the germanium substrate. Then, a conductor layer is formed by plating to coat the germanium substrate. Finally, a metal reflective layer is formed on the reflective cavity by laser processing and an electrode is formed on the other side. However, such a design has some drawbacks. First, the reflective layer metal is the same material as the electric spring. Currently, no metal can satisfy both good reflectivity and can be applied to subsequent soldering processes. Furthermore, for light-emitting diodes of different wavelengths, different metals have different reflectivities, which means that the material of the electrodes is also changed. The preferred electrode material is based on solder, but the solder is not suitable for visible light reflective materials. Good reflective materials such as gold (Au), silver (Ag), palladium (Pd), and platinum (Pt) are not suitable as materials for the electrodes. In addition, the etching of the bottom via hole is dry etched, and the subsequent process of the etched profile has a lower elastic space. Furthermore, you need to use a laser
C S -6- 200834970 處理反射金屬層，因此製程成本較高。 綜上所述，市場上亟需要—種可靠且製程簡易之的高功 率光電元件或發光二極體元件，俾能改善上述習知發光二 極體元件之各種缺點。 【發明内容】 本發明係提供一種光電元件之封裝結構及其製造方法， 可使用矽基板做為封裝的基板以增加散熱效率，及可使用 成熟之微機電製程完成。 本發明係提供一種對於反射金屬層與電極可選擇不同的 材質之光電元件’其中反射金屬層可以針對特定光線的波 長進行選擇而不會影響電極材質的選擇’因而可以各自選 擇最佳化材料。 本發明可使用濕蝕刻形成底部的電極介層孔，對於後續 的製程空間（process window)較為充裕。 本發明係提供一種以絕緣層保護反射金屬層之光電元 件，避免金屬層產生氧化、硫化或是與其他化學物質產生 反應。且該絕緣層的厚度可以調整為對特定光線進行建設 性干涉。 為達上述目的，本發明揭示一種光電元件之封裝結構， 其係包含具有一第一表面與一第二表面之矽基材。該第一 :面與該第二表面相冑，又該第一表面具有一反射腔，該 第二表面具有至少兩個與該反射腔相連通之電極介層孔。 一第一絕緣層包覆該矽基材之該第一表面與該第二表面。 又一反射層設於該反射腔表面，及一第二絕緣層覆蓋該反 200834970 射層。一第一導電層設於該第二絕緣層及該第一絕緣層表 面，及一第二導電層係設於該第二表面並與該第一導電層 相連接。一晶粒固定於該反射腔内，並電性連接於該第一 導電層。 該第一絕緣層較佳地係氧化矽，又該第二絕緣層較佳地 係一氧化秒、氮化石夕或氮氧化石夕。 該反射層較佳地係鋁、銀、金、錫、銅或鉑，其厚度介 於 300A。至 20,000A。之間。 該第一導電層較佳地係延伸至該第一絕緣層，並與該第 一‘電層相連接，且二者為可焊接的材料，例如：銀、鎳/ 金、鈦/金、鈦/鎳/金、鈦/銅/鎳/金、鈦鎢湖/鎳/金或鉻/銅/ 錄/金。 本發明另包含一填入該反射腔内之封膠層。 該晶粒藉由複數個凸塊與該第一導電層電性連接，或藉 由複數個金屬導線與該第一導電層電性連接。 本發明另揭示一種光電元件之封裝結構，其係包含具有 弟表面與一弟二表面之石夕基材。該第一表面與該第二 表面相對，又該第一表面具有一反射腔，該第二表面具有 至少兩個與該反射腔相連通之電極介層孔。一第一絕緣層 包覆該矽基材之該第一表面與該第二表面。又一金屬層設 於該士射腔内，並包括一反射區及導電區，及一第二絕緣 層覆盍該反射區。一導電層係設於該第二表面，並與該金 屬層之導電區相連接。一晶粒固定於該反射腔内，並電性 連接於該導電區。 200834970 該金屬層較佳地係銘、銀、金、錫、銅或麵。該導電層 與該金屬層中該導電區相連接，且各為可焊接的材料，例 如：銀、鎳./金 '鈇/金 '鈦/鎳/金、鈦/銅/鎳/金、鈦鎢/銅/ 鎳/金或鉻/銅/鎳/金。 本發明亦提供一種光電元件之製造方法，提供一矽基 材’並於該梦基材之一第一表面形成至少一反射腔。之後， 於該矽基材之一第二表面形成複數個電極介層孔並穿透該 石夕基板至該反射腔，其中該第二表面相對於該第一表面。 再形成一第一絕緣層以包覆該矽基材。接著，覆蓋一反射 層於該反射腔上，以及在該反射層上形成一第二絕緣層。 再者’形成一第一導電層於該第二絕緣層上，以及形成一 第二導電層於該第二表面下以及位於該兩電極介層孔内， 其中該第二導電層與該第一導電層相連接。固定一晶粒於 該反射腔内，並電性連接於該第一導電層。 該第一絕緣層較佳地係由熱氧化法所形成之氧化矽層， 又該第二絕緣層較佳地係由氣相沉積所形成之二氧化矽、 氮化矽或氮氧化矽層。 該第 $電層與該第二導電層較佳地係藉由電鍍、蒸鍍 或是化鍍所形成，且該第一導電層與該第二導電層相連接。 該晶粒較佳地係以覆晶方式固定於該反射腔内，或藉由 打線方式與該第一導電層電性連接。 本發明另包含填封膠層於該反射腔及該電極介層孔内之 步驟。 本發明亦提供一種光電元件之製造方法，提供一矽基 200834970 材，並於該矽基材之一第一表面形成至少一反射腔。之後， 於該矽基材之一第二表面形成複數個電極介層孔並穿透該 梦基板至該反射腔，其中該弟一表面相對於該第一表面。 再形成一第一絕緣層以包覆該矽基材。接著，覆蓋一金屬 層於該反射腔上，其中該金屬層包括反射區及導電區，以 及在該反射區上形成一第二絕緣層。再者，形成一導電層 於該第二絕緣層上，以及形成一導電層於該第二表面下以 及位於該兩電極介層孔内，其中該導電層與該導電區相連 接。固定一晶粒於該反射腔内，並電性連接於該導電區。 該金屬層與該導電層較佳地係藉由電鍍、蒸鍍或是化鍍 所形成。 【實施方式】 圖3(a)〜3(〇)係本發明光電元件之製造方法之步驟示意 圖。如圖3(a)所示，一矽基材12具有一第一表面lu與一 第二表面112,在圖中第一表面ιη是上表面，而第二表面 112疋下表面。碎基材11可以是五对、六对、八对或是十 一对等南阻率之石夕晶圓，其阻率大於8〇〇Ω · cm，並可使 用 <100〉的結晶表面（eryStal 〇rientati〇n surfaee)之發晶圓。 另外，矽原子依據不同的結晶方式，又可區分成單晶矽、 多晶石夕及非晶石夕。使用矽基板11的優點就是散熱佳，以及 可以進行成熟的半導體製程或微機電製程。 如圖3(b)所不，於矽基板11上覆上介電材料層（dielectric layer)12及13(或絕緣層），此步驟可以利用電漿輔助化學氣 相沉積（PECVD)的方式進行沉積。介電材料層12及13的 200834970 選擇可為抗矽非等向性蝕刻劑的介電材料即可，抗矽非等 • 向性蝕刻劑為強鹼，例如··氫氧化鉀（KOH，· Potassium hydroxide) ^ TMAH(Tetramethyl ammonium hydroxide). EDP(EthylenediaminePyr〇Cat〇Ch〇l)、或 乂札等。介電材料 層12及13可使用氮化矽（siiie〇n nitride，· S^N4)、二氧化 矽及氮氧化矽等。在本實施例中，介電材料層12及13係 使用氮化矽。接著實施如圖3(e)所示之下一步驟，在介電 參 材料層12及13上分別覆上圖案化之光阻（photoresist)層14 及15。 如圖3(d)所示’將沒有覆蓋光阻層14及15之處的介電 材料層12及13以蝕刻方式去除，然後再移除光阻層14及 15。如此就能將沒有覆蓋介電材料層12的第一表面丨丨丨以 钱刻方式形成反射腔（reflect；ive 〇pening)i6，如圖3(e)所 示。並再將沒有覆蓋介電材料層13的第二表面112以蝕刻 方式形成電極介層孔17及18。 Φ 如圖3(e)〜3(f)所示，移去剩餘之介電材料層12及13， 而原本的石夕基板11又可分為基部11B及杯座部11A。若介 電材料層12及13為氮化矽，則可以使用經加熱的磷酸 (phosphoric acid)來進行剝除。在基部11B及杯座部11A周 圍分別形成第一絕緣層21A及21B，在本實施例中係選擇 使用二氧化矽（Si〇2)作為第一絕緣層21A及21B。將基部 11B及杯座部ΠΑ暴露在高溫且含氧的環境裡一段時間後， 可以在基部11B及杯座部11A之矽材料的表面長成一層與 矽附著性良好，且介電性質符合要求的第二絕緣體21A及 -11- 200834970 21B，例如：二氧化矽。 以下二化學反應式描述矽在氧或水蒸氣中的氧化反應： 1. 乾式氧化（dry oxidation)C S -6- 200834970 deals with reflective metal layers and therefore has a high process cost. In summary, there is a need in the market for a high-power photovoltaic element or a light-emitting diode element that is reliable and easy to process, which can improve various shortcomings of the above-mentioned conventional light-emitting diode elements. SUMMARY OF THE INVENTION The present invention provides a package structure of a photovoltaic element and a method of fabricating the same, which can be used as a package substrate to increase heat dissipation efficiency, and can be completed using a mature microelectromechanical process. SUMMARY OF THE INVENTION The present invention provides a photovoltaic element in which a reflective metal layer and an electrode can be selected from different materials. The reflective metal layer can be selected for the wavelength of a particular light without affecting the choice of electrode material. Thus, the optimized material can be selected individually. The present invention can use wet etching to form the bottom electrode via holes, which is sufficient for subsequent process windows. SUMMARY OF THE INVENTION The present invention provides a photovoltaic element that protects a reflective metal layer with an insulating layer to prevent oxidation, vulcanization or reaction with other chemicals. And the thickness of the insulating layer can be adjusted to constructively interfere with a specific light. To achieve the above object, the present invention discloses a package structure for a photovoltaic element, which comprises a tantalum substrate having a first surface and a second surface. The first surface is opposite to the second surface, and the first surface has a reflective cavity, and the second surface has at least two electrode via holes in communication with the reflective cavity. A first insulating layer covers the first surface and the second surface of the germanium substrate. A reflective layer is disposed on the surface of the reflective cavity, and a second insulating layer covers the reflective layer of the 200834970. A first conductive layer is disposed on the surface of the second insulating layer and the first insulating layer, and a second conductive layer is disposed on the second surface and connected to the first conductive layer. A die is fixed in the reflective cavity and electrically connected to the first conductive layer. Preferably, the first insulating layer is yttrium oxide, and the second insulating layer is preferably oxidized seconds, nitrided or oxynitride. The reflective layer is preferably aluminum, silver, gold, tin, copper or platinum having a thickness of 300A. To 20,000A. between. The first conductive layer preferably extends to the first insulating layer and is connected to the first 'electric layer, and the two are solderable materials, such as: silver, nickel/gold, titanium/gold, titanium / Nickel / Gold, Titanium / Copper / Nickel / Gold, Titanium Tungsten Lake / Nickel / Gold or Chromium / Copper / Record / Gold. The invention further comprises a sealant layer filled in the reflective cavity. The die is electrically connected to the first conductive layer by a plurality of bumps or electrically connected to the first conductive layer by a plurality of metal wires. The invention further discloses a package structure for a photovoltaic element, which comprises a stone substrate having a surface of a younger brother and a surface of a second body. The first surface is opposite the second surface, and the first surface has a reflective cavity, the second surface having at least two electrode via holes in communication with the reflective cavity. A first insulating layer covers the first surface and the second surface of the germanium substrate. A further metal layer is disposed in the cavity and includes a reflective region and a conductive region, and a second insulating layer covers the reflective region. A conductive layer is disposed on the second surface and connected to the conductive region of the metal layer. A die is fixed in the reflective cavity and electrically connected to the conductive region. 200834970 The metal layer is preferably embossed, silver, gold, tin, copper or face. The conductive layer is connected to the conductive region in the metal layer, and each is a solderable material, such as: silver, nickel, gold, germanium, gold, titanium, nickel, gold, titanium, copper, nickel, gold, titanium Tungsten/copper/nickel/gold or chrome/copper/nickel/gold. The present invention also provides a method of fabricating a photovoltaic element, which provides a substrate and forms at least one reflective cavity on a first surface of the dream substrate. Thereafter, a plurality of electrode via holes are formed on the second surface of the one of the germanium substrates and penetrate the stone substrate to the reflective cavity, wherein the second surface is opposite to the first surface. A first insulating layer is further formed to coat the germanium substrate. Then, a reflective layer is covered on the reflective cavity, and a second insulating layer is formed on the reflective layer. Forming a first conductive layer on the second insulating layer, and forming a second conductive layer under the second surface and in the two electrode via holes, wherein the second conductive layer and the first The conductive layers are connected. A die is fixed in the reflective cavity and electrically connected to the first conductive layer. The first insulating layer is preferably a ruthenium oxide layer formed by thermal oxidation, and the second insulating layer is preferably a ruthenium dioxide, tantalum nitride or ruthenium oxynitride layer formed by vapor deposition. The first electrical layer and the second conductive layer are preferably formed by electroplating, evaporation or plating, and the first conductive layer is connected to the second conductive layer. Preferably, the die is fixed in the reflective cavity in a flip chip manner or electrically connected to the first conductive layer by wire bonding. The invention further comprises the steps of filling a sealing layer in the reflective cavity and the electrode via. The invention also provides a method for fabricating a photovoltaic element, comprising a bismuth base 200834970 material, and forming at least one reflective cavity on a first surface of the enamel substrate. Thereafter, a plurality of electrode via holes are formed on the second surface of one of the germanium substrates and penetrate the dream substrate to the reflective cavity, wherein the first surface is opposite to the first surface. A first insulating layer is further formed to coat the germanium substrate. Then, a metal layer is covered on the reflective cavity, wherein the metal layer comprises a reflective region and a conductive region, and a second insulating layer is formed on the reflective region. Furthermore, a conductive layer is formed on the second insulating layer, and a conductive layer is formed under the second surface and in the two electrode via holes, wherein the conductive layer is connected to the conductive region. A die is fixed in the reflective cavity and electrically connected to the conductive region. The metal layer and the conductive layer are preferably formed by electroplating, evaporation or plating. [Embodiment] Figs. 3(a) to 3(〇) are schematic diagrams showing the steps of a method for producing a photovoltaic element of the present invention. As shown in Fig. 3(a), a substrate 12 has a first surface lu and a second surface 112, in which the first surface i n is the upper surface and the second surface 112 is the lower surface. The crushed substrate 11 may be a five-, six-, eight-, or eleven-pair south resistivity stone wafer having a resistivity greater than 8 〇〇Ω·cm and a crystalline surface of <100> Wafer of (eryStal 〇rientati〇n surfaee). In addition, the ruthenium atoms can be distinguished into single crystal ruthenium, polycrystalline glaze, and amorphous stone eve according to different crystallization modes. The advantage of using the germanium substrate 11 is that heat dissipation is good, and a mature semiconductor process or microelectromechanical process can be performed. As shown in FIG. 3(b), the dielectric substrate 11 is covered with dielectric layers 12 and 13 (or insulating layers). This step can be performed by plasma-assisted chemical vapor deposition (PECVD). Deposition. The 200834970 of the dielectric material layers 12 and 13 may be selected as a dielectric material which is a non-isotropic non-isotropic etchant, and the etchant is a strong alkali, such as potassium hydroxide (KOH, · Potassium hydroxide) ^ TMAH (Tetramethyl ammonium hydroxide). EDP (EthylenediaminePyr〇Cat〇Ch〇l), or 乂 等. As the dielectric material layers 12 and 13, tantalum nitride (siiie〇n nitride, · S^N4), ruthenium dioxide, ruthenium oxynitride or the like can be used. In the present embodiment, the dielectric material layers 12 and 13 are made of tantalum nitride. Next, a lower step as shown in Fig. 3(e) is carried out, and patterned photoresist layers 14 and 15 are respectively coated on the dielectric material layers 12 and 13. As shown in Fig. 3(d), the dielectric material layers 12 and 13 where the photoresist layers 14 and 15 are not covered are removed by etching, and then the photoresist layers 14 and 15 are removed. Thus, the first surface 没有 without covering the dielectric material layer 12 can be formed into a reflective cavity (i.e., ive 〇pening) i6 as shown in Fig. 3(e). The second surface 112, which does not cover the dielectric material layer 13, is then etched to form the electrode via holes 17 and 18. Φ As shown in Figs. 3(e) to 3(f), the remaining dielectric material layers 12 and 13 are removed, and the original stone substrate 11 can be further divided into a base portion 11B and a cup portion 11A. If the dielectric material layers 12 and 13 are tantalum nitride, the heated phosphoric acid can be used for stripping. The first insulating layers 21A and 21B are formed around the base portion 11B and the cup portion 11A, respectively. In the present embodiment, cerium oxide (Si 2 ) is selected as the first insulating layers 21A and 21B. After exposing the base portion 11B and the cup portion ΠΑ to a high temperature and oxygen-containing environment for a period of time, the surface of the material of the base portion 11B and the cup portion 11A can be grown to have a good adhesion to the crucible, and the dielectric properties meet the requirements. The second insulator 21A and -11-200834970 21B, for example, cerium oxide. The following two chemical reaction schemes describe the oxidation reaction of hydrazine in oxygen or water vapor: 1. dry oxidation
Si(固體）+ 02(氣體）—Si02(固體） 2. 溼式氧化（wet oxidation)Si (solid) + 02 (gas) - SiO 2 (solid) 2. Wet oxidation
Si(固體）+ 2H20(氣體）—Si02(固體）+ 2H2(氣體） 在本實施例中，第一絕緣體21A及21B係以溼式氧化的 方式來長成之熱氧化物，反應的製程溫度介於900°C至11 〇〇 °C。因所需反應之時間較短，所形成的厚度介於30A°至 10,000A。之間。 如圖3(h)〜3(i)所示，在第一絕緣體21A及21B的表面 分別披覆上反射層22A及22B，此步驟可以利用物理氣相 沉積技術（PVD)進行沉積。然後在反射層22A及22B的上 方覆蓋第二絕緣層23A及23B，可以利用電漿輔助化學氣 相沉積（PECVD )的方式沉積一被動層（passivation)以作為 該第二絕緣層23A及23B，例如：二氧化矽、氮化矽或氮 氧化石夕（Silicon-Qxy-NMde ; SiOxNy)，其主要的功能是形成或保護 層，可防止反射層22A及22B中的金屬被氧化。 氮氧化矽是一種性質介於二氧化矽與氮化矽之間的一種 介電材料，其特性是應力的大小較氮化矽為緩和，且對水 氣及雜質的阻擋能力較二氧化矽為理想，所以是常見的保 護層材料。雖然氧化矽可以以低壓化學氣相沉積（LPCVD) 的方式沉積，並在溫度高於850°C以上的環境形成。但是為Si (solid) + 2H20 (gas) - SiO 2 (solid) + 2H 2 (gas) In the present embodiment, the first insulators 21A and 21B are thermally oxide grown by thermal oxidation, and the process temperature of the reaction Between 900 ° C and 11 〇〇 ° C. The thickness formed is between 30A and 10,000A due to the short reaction time required. between. As shown in Figs. 3(h) to 3(i), the surfaces of the first insulators 21A and 21B are respectively coated with the reflective layers 22A and 22B, and this step can be deposited by physical vapor deposition (PVD). Then, the second insulating layers 23A and 23B are covered over the reflective layers 22A and 22B, and a passive layer may be deposited as a second insulating layer 23A and 23B by means of plasma-assisted chemical vapor deposition (PECVD). For example, ruthenium dioxide, ruthenium nitride or ruthenium oxynitride (Silicon-Qxy-NMde; SiOxNy), whose main function is to form or protect the layer, prevents the metal in the reflective layers 22A and 22B from being oxidized. Niobium oxynitride is a dielectric material with a property between cerium oxide and tantalum nitride. Its characteristic is that the stress is more moderate than that of tantalum nitride, and its barrier ability to moisture and impurities is lower than that of cerium oxide. Ideal, so it is a common protective layer material. Although ruthenium oxide can be deposited by low pressure chemical vapor deposition (LPCVD) and formed at temperatures above 850 °C. But for
C S •12- 200834970 了使做為防護層用的氮氧化矽的製程溫度能夠低於400°C( 以避免影響已在矽基材上的金屬層），在現有氮氧化矽的沉 積製程中，都是以電漿輔助化學氣相沉積的方式來進行。 如圖3(j)〜3(k)所示，再形成導電層121及122，其中導 電層121及122分別設於第二絕緣層層23A及23B之表 面，或延伸至第一絕緣層層22A及22B之表面。導電層121 及122材料可以選擇為可焊接的材料，並視後續封裝製程 不同而選擇適合的材料，例如··銀（Ag)、鎳/金（Ni/Au)、鈦 / 金（Ti/Au)、鈦 / 鎳 / 金（Ti/Ni/Ag)、鈦 / 銅 / 鎳 / 金 (Ti/Cu/Ni/Au)、鈦鎢 /銅 /鎳 / 金（TiW/Cu/Ni/Au)或鉻/銅 /鎳 / 金（Cr/Cu/Ni/Au)等。導電層121及122的圖案轉移可利用 光學微影製程（即圖案轉移以蝕刻方式形成）或是掀起 (lift-off)製程的方式來形成，而導電層121及122的形成方 式可以使用電鍍、蒸鍍或是化鍍。 反射層22 A及22B的目的主要是用來增加光電元件的亮 度。反射層22A及22B的材料可以選擇和導電層121及122 相同或不同的材料，若反射層22A及22B選擇和導電層121 及122相同的材料，可以使用Al/Ni/Au。反之如果反射層 22A及22B選擇和導電層121及122不同的材料，則可以 以用鋁（A1)、銀（Ag)、金（Au)、錫（Sn)、銅（Cu)或鉑（Pt)等 金屬，依光線波長的不同而選擇所需的材料，又反射層22 A 及22B的厚度介於300A。至20,000A。之間。 於下半部之第一絕緣層層21A及21B上形成背部電極 131及132，其中電極131電性連接著導電層 121，並電極CS •12- 200834970 The process temperature of ruthenium oxynitride used as a protective layer can be lower than 400 ° C (to avoid affecting the metal layer already on the ruthenium substrate), in the existing deposition process of ruthenium oxynitride, Both are carried out by means of plasma-assisted chemical vapor deposition. As shown in FIGS. 3(j) to 3(k), the conductive layers 121 and 122 are further formed, wherein the conductive layers 121 and 122 are respectively disposed on the surface of the second insulating layer 23A and 23B or extend to the first insulating layer The surface of 22A and 22B. The materials of the conductive layers 121 and 122 can be selected as solderable materials, and suitable materials can be selected according to different packaging processes, such as silver (Ag), nickel/gold (Ni/Au), titanium/gold (Ti/Au). ), titanium/nickel/gold (Ti/Ni/Ag), titanium/copper/nickel/gold (Ti/Cu/Ni/Au), titanium tungsten/copper/nickel/gold (TiW/Cu/Ni/Au) or Chromium/copper/nickel/gold (Cr/Cu/Ni/Au). The pattern transfer of the conductive layers 121 and 122 can be formed by an optical lithography process (ie, pattern transfer is formed by etching) or a lift-off process, and the conductive layers 121 and 122 can be formed by using plating. Evaporation or plating. The purpose of the reflective layers 22 A and 22B is primarily to increase the brightness of the photovoltaic elements. The materials of the reflective layers 22A and 22B may be the same or different materials as the conductive layers 121 and 122. If the reflective layers 22A and 22B are selected from the same materials as the conductive layers 121 and 122, Al/Ni/Au may be used. On the other hand, if the reflective layers 22A and 22B are different from the conductive layers 121 and 122, aluminum (A1), silver (Ag), gold (Au), tin (Sn), copper (Cu) or platinum (Pt) may be used. The metal, depending on the wavelength of the light, selects the desired material, and the thickness of the reflective layers 22 A and 22B is between 300 A. To 20,000A. between. The back electrodes 131 and 132 are formed on the first insulating layer 21A and 21B of the lower half, wherein the electrode 131 is electrically connected to the conductive layer 121, and the electrode
C S -13- 200834970 132電性連接著導電層122，此電極131及132的材料可 以選擇為可焊接的材料，或是一般導電性佳的材料皆可， 例如：Ag、Ni/Au、Ti/Au、Ti/Ni/Ag、Ti/Cu/Ni/Au、 TiW/Cu/Ni/Au、Cr/Cu/Ni/Au 等，電極 131 及 132 的圖案轉 移可利用光學微影製程（即圖案轉移以蝕刻方式形成）或是 掀起製程的方式來形成，而電極131及132的形成方式可 以使用電鍍、蒸鍍或是化鍍。 鲁如圖3(1)所示，光電半導體之晶粒31A固定於該反射腔 16内之‘笔層122，並藉由打線接合（wire b〇n(jing)的方式 電性連接於導電層121及122，亦即藉由金屬導線35和導 電層121及122電性相連。 如圖3(m)〜3(n)所示，可先用膠帶19將電極介層孔17 及18黏住，於反射腔16、電極介層孔17及18内形成封 膠層32。待封膠層32固化後，再將膠帶19移除。最後， 切割基部11B以形成獨立單體之光電元件33 a。 • 除了打線接合的方式，尚可採覆晶接合（flip_chip)的方式 使晶粒31B固定並與導電層121及122電性連接，如圖4(a) 所不。接著，如圖4(b)〜4(c)所示，先用膠帶19將電極介 層孔17及18黏住，於反射腔16、電極介層孔17及18 内形成封膠層32。待封膠層32固化後，再將膠帶19移除。 敢後’切割基部11B以形成獨立單體之光電元件33B，其 中晶粒31B係藉由凸塊34與導電層121及122電性連接。 前述實施例係將導電層121、122與反射層22A、22B於 不同步騍時沉積附著，然而可以於同一沉積步驟中形成， 200834970 如圖5及圖6所示，其中圖5係顯示打線接合型式之封裝 結構’又圖6係顯示覆晶接合型式之封裝結構。圖$及圖6 中導電層121，、122,與反射層22A，係於同一沉積步驟中形 成’亦即所選用之材料亦相同。 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾。因此，本發明之保護範圍 φ 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1係習知之發光二極體之封裝結構示意圖； 圖2顯示形成如圖1之結構的製程流程圖； 圖3(a)〜3(n)係本發明光電元件之製造方法之步驟示音CS -13- 200834970 132 is electrically connected to the conductive layer 122. The materials of the electrodes 131 and 132 can be selected as solderable materials or generally conductive materials, such as Ag, Ni/Au, Ti/ Au, Ti/Ni/Ag, Ti/Cu/Ni/Au, TiW/Cu/Ni/Au, Cr/Cu/Ni/Au, etc., pattern transfer of electrodes 131 and 132 can be performed by optical lithography process (ie, pattern transfer) It is formed by etching or by a process of picking up the process, and the electrodes 131 and 132 can be formed by plating, vapor deposition or plating. As shown in FIG. 3(1), the die 31A of the optoelectronic semiconductor is fixed to the 'pen layer 122' in the reflective cavity 16, and is electrically connected to the conductive layer by wire bonding. 121 and 122, that is, electrically connected by the metal wires 35 and the conductive layers 121 and 122. As shown in Figures 3(m) to 3(n), the electrode via holes 17 and 18 can be adhered by the tape 19 first. The sealing layer 32 is formed in the reflective cavity 16, the electrode via holes 17 and 18. After the adhesive layer 32 is cured, the adhesive tape 19 is removed. Finally, the base 11B is cut to form a separate single-cell photovoltaic element 33a. • In addition to the wire bonding method, the die 31A can be fixed and electrically connected to the conductive layers 121 and 122 by a flip-chip method, as shown in Fig. 4(a). Next, as shown in Fig. 4 ( b)~4(c), the electrode via holes 17 and 18 are first adhered by the tape 19, and the sealant layer 32 is formed in the reflective cavity 16 and the electrode via holes 17 and 18. The adhesive layer 32 is cured. Thereafter, the tape 19 is removed. The base 11B is cut to form a separate unit of the photovoltaic element 33B, wherein the die 31B is electrically connected to the conductive layers 121 and 122 by the bumps 34. The embodiment deposits the conductive layers 121, 122 and the reflective layers 22A, 22B when they are not synchronized, but can be formed in the same deposition step, 200834970, as shown in FIG. 5 and FIG. 6, wherein FIG. 5 shows the wire bonding pattern. The package structure 'Fig. 6 shows the package structure of the flip chip bonding type. The conductive layers 121, 122 of FIG. 6 and FIG. 6 are formed in the same deposition step as the reflective layer 22A, that is, the material selected. The technical content and technical features of the present invention have been disclosed as above, but those skilled in the art can still make various substitutions and modifications without departing from the spirit of the present invention based on the teachings and disclosures of the present invention. The φ is not limited to the embodiment, but includes various alternatives and modifications without departing from the invention, and is covered by the following patent application. [Simplified Schematic] FIG. 1 is a conventional package of a light-emitting diode. FIG. 2 is a flow chart showing the process of forming the structure of FIG. 1. FIG. 3(a) to FIG. 3(n) are diagrams showing the steps of the method for fabricating the photovoltaic element of the present invention.
TgJ · 圆， 圖4(a)〜4(c)係本發明另一實施例光電元件之製造方法 Φ 之步驟示意圖； 圖5係本發明另一實施例光電元件之封裝結構之示意 圖；以及 & 圖6係本發明另一實施例光電元件之封裝結構之示意圖。 【主要元件符號說明】 θ 11梦基材 14、15 光阻層 17、18電極介層孔 32 封膠層 12、13介電材料層 16 反射腔 19 膠帶 34凸塊 -15- 200834970 35 金屬導 線 80 矽基板 81 82 絕緣層 83 84 發光二 極體 85 11A 杯座部 11B 21A 、21B 第一絕緣層 22A 23A 、23B 第二絕緣層 31A 33A 、33B 光電元件 22A? 111 第一表面 112 121 〜122 導電層 131 12Γ 、1221 導電層 131 831 、832 電極 反射杯 金屬層 環氧樹脂 基部 、22B 反射層 、31B 晶粒 反射層 第二表面 、132 電極 v 132 電極 16-4(a) to 4(c) are schematic diagrams showing steps of a method for manufacturing a photovoltaic element according to another embodiment of the present invention; FIG. 5 is a schematic view showing a package structure of a photovoltaic element according to another embodiment of the present invention; Figure 6 is a schematic view showing a package structure of a photovoltaic element according to another embodiment of the present invention. [Main component symbol description] θ 11 dream substrate 14, 15 photoresist layer 17, 18 electrode via hole 32 sealing layer 12, 13 dielectric material layer 16 reflective cavity 19 tape 34 bump -15- 200834970 35 metal wire 80 矽 substrate 81 82 insulating layer 83 84 light emitting diode 85 11A cup holder portion 11B 21A, 21B first insulating layer 22A 23A, 23B second insulating layer 31A 33A, 33B photovoltaic element 22A? 111 first surface 112 121 ～ 122 Conductive layer 131 12 Γ , 1221 conductive layer 131 831 , 832 electrode reflective cup metal layer epoxy resin base, 22B reflective layer, 31B grain reflective layer second surface, 132 electrode v 132 electrode 16-