WO2015042884A1 - 一种存储资源的调度方法及设备 - Google Patents

一种存储资源的调度方法及设备 Download PDF

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Publication number
WO2015042884A1
WO2015042884A1 PCT/CN2013/084495 CN2013084495W WO2015042884A1 WO 2015042884 A1 WO2015042884 A1 WO 2015042884A1 CN 2013084495 W CN2013084495 W CN 2013084495W WO 2015042884 A1 WO2015042884 A1 WO 2015042884A1
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threshold
destination address
count value
unit
data block
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PCT/CN2013/084495
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English (en)
French (fr)
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张欲
宁科
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华为技术有限公司
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Priority to PCT/CN2013/084495 priority Critical patent/WO2015042884A1/zh
Priority to CN201380002945.0A priority patent/CN104685478B/zh
Publication of WO2015042884A1 publication Critical patent/WO2015042884A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

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  • the present invention relates to computer technology, and in particular, to a storage resource scheduling method and device.
  • the queue management unit after receiving the message transmission instruction sent by the message processing unit, the queue management unit sends a message to the memory management unit (Memory) Management Unit (MMU) applies for the destination address, and then sends the requested destination address and message transfer command to direct memory access (Direct Memory Access, DMA) unit, such that the DMA unit will move the second storage unit according to the destination address, such as double rate synchronous dynamic random access memory (Double Data Rate) Data blocks in Synchronous Dynamic Random Access Memory (DDR SDRAM), copied to the first storage unit, such as shared secondary (Share Level 2, SL2) memory, and the queue management unit writes the destination address to the receiving queue, so that the message processing unit can process the data block from the first storage unit according to the destination address in the receiving queue, and instruct the MMU after the processing is completed.
  • the corresponding storage resource in the first storage unit is released.
  • the release speed of the storage resource in the first storage unit is also relatively slow, but the queue management unit still requests the destination address from the MMU, and the DMA unit will store the second storage.
  • the data block in the unit is copied into the first storage unit, thereby causing insufficient storage resources of the first storage unit, which becomes a bottleneck of the message transmission system.
  • the embodiments of the present invention provide a storage resource scheduling method and device, so as to implement storage resources occupied by control data blocks and save storage resources.
  • an embodiment of the present invention provides a scheduling method for a storage resource, including:
  • the counting threshold includes a first threshold and a second threshold, where the first threshold is less than or equal to the second threshold, and the preset is preset according to the Count threshold, get the destination address, including:
  • the count value is greater than or equal to the first threshold and less than the second threshold, and the destination address is not suspended, the count value is incremented by one, and the destination address is obtained.
  • the method further includes:
  • the count value is decremented by one.
  • an embodiment of the present invention provides a scheduling device for storing resources, including:
  • a counting unit configured to count the first data block stored by the first storage unit to obtain a count value
  • An address requesting unit configured to apply to the MMU for a destination address according to the count value and a preset counting threshold to obtain the destination address
  • a sending unit configured to send the destination address and a message transmission indication to the DMA unit, so that the DMA unit extracts the second data block from the second storage unit, and stores the second data block according to the destination address The first storage unit.
  • the counting threshold includes a first threshold and a second threshold, where the first threshold is less than or equal to the second threshold, and the preset is preset according to the Count threshold, get the destination address, including:
  • the count value is greater than or equal to the first threshold and less than the second threshold, and the destination address is not suspended, the count value is incremented by one, and the destination address is obtained.
  • the device further includes: a receiving unit, configured to receive a resource release instruction;
  • the counting unit is further configured to decrement the count value by one.
  • Counting by the queue management unit, the data block in the first storage unit, and controlling the application destination address according to the count value and the counting threshold, so that the storage unit of the first storage unit can be controlled by the data block in the second storage unit. Occupancy, effectively saving valuable storage resources, effectively avoiding the shortage of storage resources of the first storage unit, and becoming a bottleneck of the message transmission system.
  • FIG. 1 is a schematic flowchart of a method for scheduling a storage resource according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a storage resource scheduling method according to an embodiment of the present invention.
  • FIG. 3 is a functional block diagram of a scheduling device for storing resources according to an embodiment of the present invention.
  • the embodiment of the present invention provides a scheduling method for a storage resource.
  • FIG. 1 it is a schematic flowchart of a method for scheduling a storage resource according to an embodiment of the present invention; as shown in FIG. 1 , the method includes the following steps:
  • Step 101 Count the first data block stored by the first storage unit to obtain a count value.
  • At least one sending queue and at least one receiving queue may be included in the queue management unit, and one sending queue corresponds to one receiving queue.
  • a buffer counter is configured for each sending queue;
  • the SDRAM can also be a FLASH flash memory; therefore, when the queue management unit obtains a destination address from the MMU, the count value of the buffer counter of the transmission queue corresponding to the destination address in the queue management unit needs to be increased by 1, so each transmission queue corresponds to The buffer counter is configured to count the first data block indicated by the message transmission instruction in the sending queue stored by the first storage unit, so that the queue management unit can obtain the count value of the first data block stored by the first storage unit, In the embodiment of the present invention, the queue management unit includes at least one cache counter, and at least one of the count values is obtained.
  • the first storage unit may be a shared memory, such as SL1 memory, SL2 memory, or SL3 memory.
  • Step 102 Apply a destination address to the MMU according to the count value and a preset count threshold to obtain the destination address.
  • the message processing unit obtains the counting threshold according to the copying speed of the data block by the DMA unit and the processing speed of the data block stored in the first storage unit by the message processing unit, and then sends the counting threshold to the queue management.
  • the message processing unit can flexibly configure the counting threshold corresponding to the buffer counter in the queue management unit to ensure that the speed of data block moving matches the speed of the data processing unit processing the data block.
  • the queue management unit receives a message transmission instruction sent by the message processing unit, where the message transmission instruction includes a source address of the data block and a length of the data block; after receiving the message transmission instruction, the queue management unit inserts the message transmission instruction into the corresponding transmission. The tail of the queue.
  • the queue management unit obtains the destination address according to the count value of the buffer counter of the send queue and the received count threshold; wherein the count threshold may include a first threshold and a second threshold, where the first threshold is less than or equal to The second threshold is described.
  • the following takes a sending queue as an example to illustrate the specific method for obtaining the destination address according to the counting value and the preset counting threshold:
  • the first threshold is equal to the second threshold, when the count value is less than the first threshold, the count value of the buffer counter of the sending queue is incremented by 1, and the queue management unit is configured according to the row in the sending queue.
  • the first message transmission instruction sends an address request message to the MMU. After receiving the address request message, the MMU obtains the destination address and sends it to the queue management unit, so that the queue management unit obtains the destination address.
  • the queue management unit suspends processing the message transmission instruction in the sending queue, that is, the pause is
  • the message transmission instruction in the sending queue requests the MMU for the destination address; but the queue management unit can still insert the newly received message transmission instruction into the sending queue, and pause processing the sending queue without affecting the queue management unit to process other transmissions.
  • Message transfer instructions in the queue when the count value is greater than or equal to the first threshold (corresponding to the count value being greater than or equal to the second threshold), the queue management unit suspends processing the message transmission instruction in the sending queue, that is, the pause is
  • the message transmission instruction in the sending queue requests the MMU for the destination address; but the queue management unit can still insert the newly received message transmission instruction into the sending queue, and pause processing the sending queue without affecting the queue management unit to process other transmissions.
  • the count value of the buffer counter of the sending queue is incremented by 1, and the queue management unit is configured according to the row in the sending queue.
  • the first message transmission instruction sends an address request message to the MMU. After receiving the address request message, the MMU obtains the destination address and sends it to the queue management unit, so that the queue management unit obtains the destination address.
  • the queue management unit pauses processing the message transmission instruction in the sending queue, that is, suspends the message transmission instruction in the sending queue, and requests the MMU for the destination address; but the queue management The unit can still insert the newly received message transmission instruction into the transmission queue, and pause processing the transmission queue without affecting the queue management unit processing the message transmission instruction in other transmission queues.
  • the processing status of the sending queue of the unit determines whether to suspend processing of the sending queue; if the processing status is that the queue management unit has suspended the requesting address of the message transmission instruction in the sending queue, when the count value is greater than or equal to the first threshold, And if the second threshold is less than, the queue management unit continues to suspend processing the message transmission instruction in the sending queue until the count value of the buffer counter of the sending queue is less than the first threshold; if the processing status is still processed by the queue management unit a message transmission instruction in the queue, when the count value is greater than or equal to the first threshold and less than the second threshold, the queue management unit continues to process the message transmission instruction in the sending queue, and transmits the message in the sending queue.
  • the instruction requests the MMU for the destination address until the count value is greater than or equal to the second threshold.
  • Step 103 Send the destination address and the message transmission indication to the DMA unit, so that the DMA unit extracts the second data block from the second storage unit, and stores the second data block according to the destination address to the The first storage unit.
  • the queue management unit sends the obtained destination address and the message transmission instruction to the DMA unit, where the message transmission instruction carries the source address of the data block, so that the DMA unit performs the second corresponding to the second storage unit according to the source address.
  • the data block is copied, and then the second data block obtained by the copy is stored in the cache block corresponding to the destination address in the first storage unit according to the destination address, and then the DMA unit sends the destination address to the queue management unit, and the queue management unit
  • the destination address is inserted into the end of the receiving queue, and waits for the message processing unit to process the data block.
  • the message processing unit obtains the first data block in the first storage unit according to the destination address, and processes the first data block.
  • the message processing unit may send a resource release instruction to the queue management unit, where the message is sent by the queue management unit, and the queue management unit receives the resource release instruction, and reduces the count value of the corresponding cache counter by 1 according to the send queue identifier.
  • the message processing unit sends a release address instruction to the MMU to cause the MMU to reclaim the destination address assigned to the first data block to allocate the destination address to the second data block in the other second storage unit for use.
  • Embodiments of the present invention further provide an apparatus embodiment for implementing the steps and methods in the foregoing method embodiments.
  • FIG. 3 is a functional block diagram of a scheduling device for storing resources according to an embodiment of the present invention.
  • the device may be the foregoing queue management unit. As shown, the device includes:
  • the counting unit 30 is configured to count the first data block stored by the first storage unit to obtain a count value
  • the address requesting unit 31 is configured to apply, to the MMU, a destination address according to the count value and a preset count threshold to obtain the destination address;
  • the sending unit 32 is configured to send the destination address and the message transmission indication to the DMA unit, so that the DMA unit extracts the second data block from the second storage unit, and stores the second data block according to the destination address. To the first storage unit.
  • the counting threshold includes a first threshold and a second threshold, where the first threshold is less than or equal to the second threshold, and the destination threshold is obtained according to the preset threshold, and includes:
  • the count value is less than the first threshold, add the count value to 1 and obtain the destination address; or, if the count value is greater than or equal to the second threshold, pause to obtain the destination address; Alternatively, if the count value is greater than or equal to the first threshold and less than the second threshold, and the destination address has been suspended, the destination address is continuously suspended; or if the count value is greater than or equal to the The first threshold is smaller than the second threshold, and the destination address is not suspended, the count value is incremented by 1, and the destination address is obtained.
  • the device further includes: a receiving unit 33, configured to receive a resource release instruction;
  • the counting unit 30 is further configured to decrement the count value by one.
  • the functions of the counting unit 30 and the address applying unit 31 may be implemented by a general-purpose processor or a dedicated processor.
  • the program may be implemented by a processor to call a program stored in the memory.
  • the specific hardware structure may be flexibly changed according to the usage scenario, and the present invention is not limited.

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Abstract

本发明实施例提供了一种存储资源的调度方法及设备，该方法包括：对第一存储单元存储的第一数据块进行计数，以获得计数值；依据所述计数值和预设的计数阈值，向MMU申请目的地址，以获得所述目的地址；将所述目的地址和消息传输指示发送给DMA单元，以使得DMA单元从第二存储单元中提取第二数据块，以及依据所述目的地址将所述第二数据块存储到所述第一存储单元。本发明实施例提供的技术方案，用以实现控制数据块占用的存储资源，节省存储资源。

Description

一种存储资源的调度方法及设备
【技术领域】
本发明涉及计算机技术，尤其涉及一种存储资源的调度方法及设备。
【背景技术】
目前，基于动态存储资源管理的消息传输机制中，队列管理单元收到消息处理单元发送的消息传输指令后，向内存管理单元（Memory Management Unit，MMU）申请目的地址，然后将申请到的目的地址和消息传输指令发送给直接内存存取（Direct Memory Access，DMA）单元，以使得DMA单元依据目的地址将第二存储单元，例如双倍速率同步动态随机存储器（Double Data Rate Synchronous Dynamic Random Access Memory，DDR SDRAM）中的数据块，复制到第一存储单元，例如共享二级（Share Level 2，SL2）内存，同时队列管理单元将目的地址写入接收队列，这样消息处理单元可以依据接收队列中的目的地址对从第一存储单元中的数据块进行处理，并在处理完成后指示MMU释放第一存储单元中相应的存储资源。
然而，当消息处理单元处理数据块的速度比较慢时，第一存储单元中存储资源的释放速度也比较慢，但是，队列管理单元仍然会向MMU申请目的地址，DMA单元就会将第二存储单元中的数据块复制到第一存储单元中，从而导致第一存储单元的存储资源不足，成为消息传输系统的瓶颈。
【发明内容】
有鉴于此，本发明实施例提供了一种存储资源的调度方法及设备，以实现控制数据块占用的存储资源，节省存储资源。
第一方面，本发明实施例提供了一种存储资源的调度方法，包括：
对第一存储单元存储的第一数据块进行计数，以获得计数值；
依据所述计数值和预设的计数阈值，向内存管理单元MMU申请目的地址，以获得所述目的地址；
将所述目的地址和消息传输指示发送给直接内存存取DMA单元，以使得DMA单元从第二存储单元中提取第二数据块，以及依据所述目的地址将所述第二数据块存储到所述第一存储单元。
在第一方面的第一种可能的实现方式中，所述计数阈值包括第一阈值和第二阈值，所述第一阈值小于或等于所述第二阈值，所述依据所述计数值预设的计数阈值，获得目的地址，包括：
若所述计数值小于所述第一阈值，将所述计数值加1，并获得所述目的地址；或者，
若所述计数值大于或等于所述第二阈值，暂停获得所述目的地址；或者，
若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且已经暂停获得目的地址，继续暂停获得所述目的地址；或者，
若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且没有暂停获得目的地址，将所述计数值加1，并获得所述目的地址。
在第一方面的第二种可能的实现方式中，所述方法还包括：
接收资源释放指令；
将所述计数值减1。
第二方面，本发明实施例提供了一种存储资源的调度设备，包括：
计数单元，用于对第一存储单元存储的第一数据块进行计数，以获得计数值；
地址申请单元，用于依据所述计数值和预设的计数阈值，向MMU申请目的地址，以获得所述目的地址；
发送单元，用于将所述目的地址和消息传输指示发送给DMA单元，以使得DMA单元从第二存储单元中提取第二数据块，以及依据所述目的地址将所述第二数据块存储到所述第一存储单元。
在第二方面的第一种可能的实现方式中，所述计数阈值包括第一阈值和第二阈值，所述第一阈值小于或等于所述第二阈值，所述依据所述计数值预设的计数阈值，获得目的地址，包括：
若所述计数值小于所述第一阈值，将所述计数值加1，并获得所述目的地址；或者，
若所述计数值大于或等于所述第二阈值，暂停获得所述目的地址；或者，
若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且已经暂停获得目的地址，继续暂停获得所述目的地址；或者，
若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且没有暂停获得目的地址，将所述计数值加1，并获得所述目的地址。
在第二方面的第二种可能的实现方式中，所述设备还包括：接收单元，用于接收资源释放指令；
所述计数单元，还用于将所述计数值减1。
本发明实施例的技术方案具有以下有益效果：
在队列管理单元对第一存储单元中的数据块进行计数，依据计数值和计数阈值，对申请目的地址进行控制，从而可以控制第二存储单元中的数据块对第一存储单元的存储资源的占用，有效节省宝贵的存储资源，有效避免第一存储单元的存储资源不足，成为消息传输系统的瓶颈的问题。
【附图说明】
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。
图1是本发明实施例所提供的存储资源的调度方法的流程示意图；
图2是本发明实施例所提供的存储资源的调度方法对应的结构示意图；
图3是本发明实施例所提供的存储资源的调度设备的功能方块图。
【具体实施方式】
为了更好的理解本发明的技术方案，下面结合附图对本发明实施例进行详细描述。
应当明确，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例给出一种存储资源的调度方法，请参考图1，其为本发明实施例所提供的存储资源的调度方法的流程示意图；如图1所示，该方法包括以下步骤：
步骤101，对第一存储单元存储的第一数据块进行计数，以获得计数值。
具体的，请参考图2，在队列管理单元中可以包含至少一个发送队列和至少一个接收队列，一个发送队列对应一个接收队列，本发明实施例中，为每个发送队列配置一个缓存计数器；由于当队列管理单元收到消息处理单元发送的消息传输指令时，将该消息传输指令插入对应的发送队列的尾部，队列管理单元将为发送队列中的排在第一位的消息传输指令，申请目的地址，即从MMU获得该目的地址，然后将目的地址和消息传输指令发送给DMA单元，DMA单元将第二存储单元中的第二数据块搬移到第一存储单元中，所述第二存储单元可以为DDR SDRAM，还可以为FLASH闪存；因此，当队列管理单元从MMU获得一个目的地址，队列管理单元中该目的地址对应的发送队列的缓存计数器的计数值就需要加1，因此，每个发送队列对应的缓存计数器用于对第一存储单元存储的该发送队列中消息传输指令所指示的第一数据块进行计数，从而队列管理单元可以获得第一存储单元存储的第一数据块的计数值，因此，本发明实施例中，队列管理单元中包含至少一个缓存计数器，获得至少一个所述计数值；其中，第一存储单元可以为共享存储器，如SL1内存、SL2内存或SL3内存。
步骤102，依据所述计数值和预设的计数阈值，向MMU申请目的地址，以获得所述目的地址。
具体的，消息处理单元依据DMA单元对数据块的复制速度，以及消息处理单元对第一存储单元中存储的数据块的处理速度，获得所述计数阈值，然后将所述计数阈值发送给队列管理单元；这里，消息处理单元可以灵活的配置队列管理单元中缓存计数器对应的计数阈值，保证数据块搬移的速度与消息处理单元处理数据块的速度相匹配。
队列管理单元接收消息处理单元发送的消息传输指令，所述消息传输指令中包含数据块的源地址和数据块的长度；队列管理单元在收到消息传输指令后，将消息传输指令插入对应的发送队列的尾部。
队列管理单元依据所述发送队列的缓存计数器的计数值和收到的计数阈值，获得目的地址；其中，所述计数阈值可以包括第一阈值和第二阈值，所述第一阈值小于或等于所述第二阈值。
下面以一个发送队列为例，说明依据所述计数值和预设的计数阈值，获得目的地址的具体方法：
若所述第一阈值等于所述第二阈值，当所述计数值小于所述第一阈值时，将所述发送队列的缓存计数器的计数值加1，队列管理单元依据所述发送队列中排位第一的消息传输指令，向MMU发送地址请求消息，MMU在收到地址请求消息后，获得目的地址并发送给队列管理单元，从而队列管理单元获得目的地址。或者，当所述计数值大于或等于所述第一阈值（相当于所述计数值大于或等于所述第二阈值）时，队列管理单元暂停处理该发送队列中的消息传输指令，即暂停为该发送队列中的消息传输指令，向MMU申请目的地址；但是队列管理单元依然可以将新收到的消息传输指令插入该发送队列，而且，暂停处理该发送队列，不影响队列管理单元处理其他发送队列中的消息传输指令。
若所述第一阈值小于所述第二阈值，当所述计数值小于所述第一阈值时，将所述发送队列的缓存计数器的计数值加1，队列管理单元依据所述发送队列中排位第一的消息传输指令，向MMU发送地址请求消息，MMU在收到地址请求消息后，获得目的地址并发送给队列管理单元，从而队列管理单元获得目的地址。当所述计数值大于或等于所述第二阈值时，队列管理单元暂停处理该发送队列中的消息传输指令，即暂停为该发送队列中的消息传输指令，向MMU申请目的地址；但是队列管理单元依然可以将新收到的消息传输指令插入该发送队列，而且，暂停处理该发送队列，不影响队列管理单元处理其他发送队列中的消息传输指令。
若所述第一阈值小于所述第二阈值，还存在一种情况，即所述计数值大于或等于所述第一阈值，且小于所述第二阈值，对于这种情况，需要依据队列管理单元对发送队列的处理状态，决定是否暂停处理发送队列；如果处理状态是队列管理单元已经暂停为该发送队列中的消息传输指令申请目的地址，则当计数值大于或等于所述第一阈值，且小于所述第二阈值时，队列管理单元继续暂停处理发送队列中的消息传输指令，直到该发送队列的缓存计数器的计数值小于所述第一阈值；如果处理状态为队列管理单元仍然处理发送队列中的消息传输指令，则当计数值大于或等于所述第一阈值，且小于所述第二阈值时，队列管理单元继续处理发送队列中的消息传输指令，为该发送队列中的消息传输指令向MMU申请目的地址，直到计数值大于或等于所述第二阈值。
步骤103，将所述目的地址和消息传输指示发送给DMA单元，以使得DMA单元从第二存储单元中提取第二数据块，以及依据所述目的地址将所述第二数据块存储到所述第一存储单元。
具体的，队列管理单元将获得的目的地址和消息传输指令发送给DMA单元，所述消息传输指令中携带数据块的源地址，以使得DMA单元依据源地址对第二存储单元中对应的第二数据块进行复制，然后依据目的地址将复制获得的第二数据块存储到第一存储单元中目的地址对应的缓存块中，然后DMA单元将该目的地址发送给队列管理单元，队列管理单元将该目的地址插入接收队列的队尾，并等待消息处理单元对该数据块进行处理，消息处理单元依据目的地址获得第一存储单元中的第一数据块，对第一数据块进行处理。
消息处理单元完成第一数据块的处理后，可以向队列管理单元发送资源释放指令，其中携带发送队列标识，队列管理单元接收资源释放指令，依据发送队列标识将对应的缓存计数器的计数值减1；消息处理单元向MMU发送释放地址指令，以使得MMU将分配给第一数据块的目的地址收回，以便将该目的地址分配给其他第二存储单元中的第二数据块使用。
本发明实施例进一步给出实现上述方法实施例中各步骤及方法的装置实施例。
请参考图3，其为本发明实施例所提供的一种存储资源的调度设备的功能方块图，该设备可以为上述队列管理单元。如图所示，该设备包括：
计数单元30，用于对第一存储单元存储的第一数据块进行计数，以获得计数值；
地址申请单元31，用于依据所述计数值和预设的计数阈值，向MMU申请目的地址，以获得所述目的地址；
发送单元32，用于将所述目的地址和消息传输指示发送给DMA单元，以使得DMA单元从第二存储单元中提取第二数据块，以及依据所述目的地址将所述第二数据块存储到所述第一存储单元。
其中，所述计数阈值包括第一阈值和第二阈值，所述第一阈值小于或等于所述第二阈值，所述依据所述计数值预设的计数阈值，获得目的地址，包括：
若所述计数值小于所述第一阈值，将所述计数值加1，并获得所述目的地址；或者，若所述计数值大于或等于所述第二阈值，暂停获得所述目的地址；或者，若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且已经暂停获得目的地址，继续暂停获得所述目的地址；或者，若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且没有暂停获得目的地址，将所述计数值加1，并获得所述目的地址。
所述设备还包括：接收单元33，用于接收资源释放指令；
所述计数单元30，还用于将所述计数值减1。
需要说明的是，上述装置实施例中，计数单元30和地址申请单元31的功能可以通过通用处理器或专用处理器来实现，例如，可以通过处理器调用存储在存储器中的程序来实现上述功能，具体硬件结构可以根据使用场景灵活变化，本发明不做限定。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明保护的范围之内。

Claims (6)

  1. 一种存储资源的调度方法，其特征在于，所述方法包括：
    对第一存储单元存储的第一数据块进行计数，以获得计数值；
    依据所述计数值和预设的计数阈值，向内存管理单元MMU申请目的地址，以获得所述目的地址；
    将所述目的地址和消息传输指示发送给直接内存存取DMA单元，以使得DMA单元从第二存储单元中提取第二数据块，以及依据所述目的地址将所述第二数据块存储到所述第一存储单元。
  2. 根据权利要求1所述的方法，其特征在于，所述计数阈值包括第一阈值和第二阈值，所述第一阈值小于或等于所述第二阈值，所述依据所述计数值预设的计数阈值，获得目的地址，包括：
    若所述计数值小于所述第一阈值，将所述计数值加1，并获得所述目的地址；或者，
    若所述计数值大于或等于所述第二阈值，暂停获得所述目的地址；或者，
    若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且已经暂停获得目的地址，继续暂停获得所述目的地址；或者，
    若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且没有暂停获得目的地址，将所述计数值加1，并获得所述目的地址。
  3. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    接收资源释放指令；
    将所述计数值减1。
  4. 一种存储资源的调度设备，其特征在于，所述设备包括：
    计数单元，用于对第一存储单元存储的第一数据块进行计数，以获得计数值；
    地址申请单元，用于依据所述计数值和预设的计数阈值，向MMU申请目的地址，以获得所述目的地址；
    发送单元，用于将所述目的地址和消息传输指示发送给DMA单元，以使得DMA单元从第二存储单元中提取第二数据块，以及依据所述目的地址将所述第二数据块存储到所述第一存储单元。
  5. 根据权利要求1所述的设备，其特征在于，所述计数阈值包括第一阈值和第二阈值，所述第一阈值小于或等于所述第二阈值，所述依据所述计数值预设的计数阈值，获得目的地址，包括：
    若所述计数值小于所述第一阈值，将所述计数值加1，并获得所述目的地址；或者，
    若所述计数值大于或等于所述第二阈值，暂停获得所述目的地址；或者，
    若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且已经暂停获得目的地址，继续暂停获得所述目的地址；或者，
    若所述计数值大于或等于所述第一阈值且小于所述第二阈值，且没有暂停获得目的地址，将所述计数值加1，并获得所述目的地址。
  6. 根据权利要求1所述的设备，其特征在于，
    所述设备还包括：接收单元，用于接收资源释放指令；
    所述计数单元，还用于将所述计数值减1。
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