WO2015025580A1

WO2015025580A1 - Power conversion device

Info

Publication number: WO2015025580A1
Application number: PCT/JP2014/064050
Authority: WO
Inventors: 彬三間; 健徳山; 佐藤　俊也
Original assignee: 日立オートモティブシステムズ株式会社
Priority date: 2013-08-23
Filing date: 2014-05-28
Publication date: 2015-02-26
Also published as: JP2015042116A; JP6053642B2

Abstract

Provided is a power conversion device in which the heat generated at branch terminals of a power semiconductor module can be uniformed between the branch terminals. The power conversion device comprises a capacitor element (2), a power semiconductor module (1) mounted with a power semiconductor element (30), a negative electrode connecting conductive plate (91), and a positive electrode connecting conductive plate (92). At least one of DC terminals is branched into a plurality of branch terminals (10a to 10c) having different resistance values and connected to the negative electrode connecting conductive plate (91). The negative electrode connecting conductive plate (91) has path resistance increasing portions (S5, S6) formed on the respective current paths (L1b, L1c) between a capacitor negative electrode terminal (13) and the other branch terminals (10b, 10c) excluding the branch terminal (10a) which has the largest resistance value among the branch terminals (10a to 10c), said path resistance increasing portions (S5, S6) being used for allowing the heat generated at the branch terminals (10a to 10c) to be uniformed between the branch terminals.

Description

Power converter

The present invention relates to a power converter equipped with a power semiconductor module.

In recent years, high output and high density of an inverter device as a power conversion device are demanded, and downsizing of a power semiconductor module has attracted attention. In general, power semiconductor modules are equipped with IGBTs (Insulated Gate Bipolar Transistors) and current return diodes as power switching elements. However, switching power loss due to high-speed switching is increasing as power semiconductor modules increase in current density. Reduction is essential.

Conventionally, a configuration has been proposed in which a parasitic inductance of a wiring connecting a smoothing capacitor and a power semiconductor module is reduced in order to suppress a voltage jump generated by high-speed switching (see, for example, Patent Document 1).

In the technique described in Patent Document 1, two terminals are provided on each of the negative electrode side plate-like conductor and the positive electrode side plate-like conductor to parallelize the current paths, and the negative electrode side plate-like conductor and the positive electrode side plate-like conductor are connected with an insulator. Thus, the wiring connecting the capacitor and the power semiconductor module is reduced in inductance.

JP 2001-286158 A

However, in the device described in Patent Document 1, the lengths of the two terminals described above are different, and the parasitic resistance values of the terminals may be different. If the parasitic resistance values are different, an imbalance of the current flowing through each terminal occurs. When current imbalance occurs, the heat generation of each terminal is unbalanced and the temperature tends to increase, which may reduce the current capacity of the entire power module.

A power conversion device according to the invention of claim 1 includes a power semiconductor module on which a power semiconductor element is mounted and having a DC positive electrode terminal and a DC negative electrode terminal, a capacitor that smoothes DC power and has capacitor terminals on the negative electrode side and the positive electrode side, The negative electrode side conductor plate to which the negative electrode side capacitor terminal and the DC negative electrode terminal of the power semiconductor module are connected, and the positive electrode side conductor plate to which the positive electrode terminal of the capacitor and the DC positive electrode terminal of the power semiconductor module are connected And at least one of the DC negative terminal or the DC positive terminal is composed of a plurality of branch terminals having different parasitic resistances, and the plurality of branch terminals are connected to each other. In the conductor plate, heat is generated at multiple branch terminals on the current path between the branch terminal and the capacitor terminal. Path resistance increasing unit for equalization between the branch terminals are formed, characterized in that.

According to the present invention, the heat generation at the branch terminals can be equalized between the branch terminals.

FIG. 1 is a cross-sectional view showing a schematic configuration of the inverter system 60. FIG. 2 is a diagram illustrating the structure inside the module case 53. FIG. 3 is a circuit diagram of the connection conductor plate layer 9, the power semiconductor module 1, and the capacitor element 2. FIG. 4 is a diagram for explaining the loss in the negative

electrode connection terminals

10a and 10b. FIG. 5 is a diagram showing the power semiconductor module 1 and the capacitor element 2 connected by the connection conductor plate layer 9. FIG. 6 is a diagram illustrating the relationship between the negative connection conductor plate 91 and the positive connection conductor plate 92 and each connection terminal. FIG. 7 is a view showing an AA cross section of FIG. FIG. 8 is a diagram for explaining the second embodiment. FIG. 9 is a diagram for explaining the third embodiment. FIG. 10 is a diagram for explaining the fourth embodiment. FIG. 11 is a diagram illustrating the negative electrode connection conductor plate 91 when there are three branch terminals.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a power conversion device according to the present invention. FIG. 1 is a cross-sectional view showing a schematic configuration of the inverter system 60. The inverter system 60 includes a power semiconductor module 1, a capacitor element 2, a control board 41, a connection conductor plate layer 9, and the like, and an inverter housing 50 that houses them. Although only one power semiconductor module 1 is illustrated in FIG. 1, the inverter system 60 of the present embodiment is a three-phase inverter system and includes a total of three power semiconductor modules 1.

The capacitor element 2 is connected to each power semiconductor module 1 via a connection conductor plate layer 9 composed of a negative electrode connection conductor plate 91 and a positive electrode connection conductor plate 92. The power semiconductor module 1 according to the present embodiment is a so-called 2-in-1 power semiconductor module in which two power semiconductor elements (not shown) are housed in a module case 53, respectively. From the module case 53, a plurality of terminals, that is, a first negative electrode connection terminal 10a, a second negative electrode connection terminal 10b, a first positive electrode connection terminal 11a, a second positive electrode connection terminal 11b, a power output terminal 12, and a control signal terminal are shown in the upper part of the figure. 40 is distracted.

The first negative electrode connection terminal 10 a and the second negative electrode connection terminal 10 b are connected to the negative electrode connection conductor plate 91 of the connection conductor plate layer 9. A capacitor negative electrode terminal 13 of the capacitor element 2 is connected to the negative electrode connection conductor plate 91. On the other hand, the first positive electrode connection terminal 11 a and the second positive electrode connection terminal 11 b are connected to the positive electrode connection conductor plate 92 of the connection conductor plate layer 9. The positive electrode connection conductor plate 92 is connected to the capacitor positive electrode terminal 14 of the capacitor element 2. The plurality of control signal terminals 40 are connected to a control board 41 disposed above the connection conductor plate layer 9.

A water channel 52 through which cooling water flows is formed in the inverter housing 50. The power semiconductor module 1 described above is disposed in the water channel 52 and is cooled by the cooling water flowing in the water channel 52. Radiation fins 53a are formed on the outer surface of the module case 53 in order to improve the cooling performance. The water channel 52 flows along the outer surface of the capacitor storage portion 51 in which the capacitor element 2 is stored, and is discharged from the inverter housing 50. The gap between the capacitor element 2 and the capacitor housing 51 is filled with a resin material.

During the operation of the inverter system 60, the power semiconductor module 1 is controlled by the control board 41, current flows from the capacitor element 2 through the connection conductor plate layer 9 to the power semiconductor module 1, and current flows to the power output terminal 12. Is output. At that time, heat is generated in the capacitor element 2, the connection conductor plate layer 9, the power semiconductor module 1, and the

connection terminals

10a, 10b, 11a, and 11b of the power semiconductor module in the current flow path.

Since the capacitor element 2 is in thermal contact with the inverter housing 50 via the resin material, and the connecting conductor plate layer 9 is also in thermal contact with the inverter housing 50 via the insulating layer, the capacitor element 2 and the connection conductor plate layer 9 are radiated to the cooling water in the water channel 52 through the inverter housing 50. Further, heat generated in the power semiconductor module 1 is also radiated to the cooling water through the module case 53 in which the radiation fins 53a are formed. However, since the

connection terminals

10a, 10b, 11a, and 11b of the power semiconductor module 1 are not directly cooled, it is important to suppress the heat generation of the

connection terminals

10a, 10b, 11a, and 11b.

FIG. 2 is a diagram for explaining the structure inside the module case 53. As described above, the power semiconductor module 1 has a 2-in-1 structure, and the two

power semiconductor elements

30 a and 30 b are accommodated in the module case 53. The power semiconductor element 30a is sandwiched between the

conductor plates

31a and 31b, and the power semiconductor element 30b is sandwiched between the

conductor plates

32a and 32b. The conductor plate 32b is electrically connected to the conductor plate 31a. The conductor plate 32a is formed with two branched terminals, that is, a first negative electrode connection terminal 10a and a second negative electrode connection terminal 10b. Similarly, a first positive electrode connection terminal 11a and a second positive electrode connection terminal 11b branched into two are formed on the conductor plate 31b.

In FIG. 2, an arrow 21 indicated by a solid line indicates a path of current flowing through the first negative electrode connection terminal 10a, and an arrow 20 indicated by a broken line indicates a path of current flowing through the second negative electrode connection terminal 10b. Thus, when the negative electrode connection terminal is branched into two, the first negative electrode connection terminal 10a arranged farther from the conductor plate 32a has a longer current path. As a result, when the resistance (parasitic resistance) from the power semiconductor element 30b to the first negative electrode connection terminal 10a is Rn1, and the resistance (parasitic resistance) from the power semiconductor element 30b to the second negative electrode connection terminal 10b is Rn2, Rn1> Rn2. Similarly, when the resistance (parasitic resistance) from the power semiconductor element 30a to the first positive electrode connection terminal 11a is Rp1, and the resistance (parasitic resistance) from the power semiconductor element 30a to the second positive electrode connection terminal 11b is Rp2, Rp1> Rp2.

FIG. 3 shows a circuit diagram of the connecting conductor plate layer 9 and the power semiconductor module 1 and the capacitor element 2 connected thereto. The

power semiconductor elements

30a and 30b (see FIG. 2) provided in the power semiconductor module 1 constitute a half bridge circuit as shown in FIG. The

power semiconductor elements

30 a and 30 b are connected in series (totem pole connection) between the positive electrode connection conductor plate 92 and the negative electrode connection conductor plate 91. For example, an IGBT or the like is used for the

power semiconductor elements

30a and 30b.

The collector electrode of the power semiconductor element 30a in the upper arm is connected to the positive connection conductor plate 92, and the emitter electrode is connected to the collector electrode of the power semiconductor element 30b in the lower arm. The emitter electrode of the lower arm power semiconductor element 30 b is connected to the negative electrode connecting conductor plate 91. Further, the power output terminal 12 is disposed at an intermediate connection portion (the conductor plate 32b in FIG. 2) between the two

power semiconductor elements

30a and 30b. By connecting in this way, an upper and lower arm series circuit is formed.

As described above, the resistance values from the power semiconductor element 30a to the first positive electrode connection terminal 11a and the second positive electrode connection terminal 11b are Rp1 and Rp2, and similarly, from the power semiconductor element 30b to the first negative electrode connection terminal 10a and the first negative electrode connection terminal 10a. The resistance values up to the two negative electrode connection terminals 10b are Rn1 and Rn2, respectively. Furthermore, resistance values (resistance in the negative electrode connecting conductor plate 91) between the negative

electrode connecting terminals

10a and 10b and the capacitor negative electrode terminal 13 are Rpbn1 and Rpbn2, respectively, and the positive

electrode connecting terminals

11a and 11b and the capacitor positive electrode terminal 14 are connected. The resistance values (resistance in the positive electrode connecting conductor plate 92) are Rpbp1 and Rpbp2, respectively.

As described above, the resistance values of the terminals of the

power semiconductor elements

30a and 30b are such that Rn1> Rn2 and Rp1> Rp2. On the other hand, since the negative electrode connection conductor plate 91 and the positive electrode connection conductor plate 92 are made of a wide range of conductors, Rpbn1≈Rpbn2 and Rpbp1≈Rpbp2 are satisfied before the present invention is applied. In the present embodiment, the shape of the connecting conductor plate layer 9 is devised to adjust the resistance values Rpbn1 and Rpbn2 and the resistance values Rpbp1 and Rpbp2 to equalize the heat generation at the terminals of the

power semiconductor elements

30a and 30b. I tried to do it.

Here, although the adjustment method regarding the resistance value of the negative electrode connection conductor plate 91 is demonstrated, the positive electrode connection conductor plate 92 can also be adjusted by the same method. Here, loss generated at the first negative electrode connection terminal 10a of the power semiconductor element 30b is Pn1, and loss generated at the second negative electrode connection terminal 10b is Pn2. In order to equalize the heat generation of the negative

electrode connection terminals

10a and 10b, it is necessary to satisfy Pn1≈Pn2.

If the current flowing through the first negative electrode connection terminal 10a having the resistance value Rn1 is In1, and the current flowing through the second negative electrode connection terminal 10b having the resistance value Rn2 is In2, the losses Pn1 and Pn2 are Pn1 = Rn1 × In1 ² and Pn2 = Rn2, respectively. XIn2 ² Therefore, assuming that Pn1≈Pn2, the relationship of Rn1 × In1 ² ≈Rn2 × In2 ² is established between the currents In1 and In2. Further, the total current In flowing on the negative electrode side is In = In1 + In2.

As described above, since the resistance value Rn2 of the second negative electrode connection terminal 10b is smaller than the resistance value Rn1 of the first negative electrode connection terminal 10a, the resistance value of the negative electrode connection conductor plate 91 to which the second negative electrode connection terminal 10b is connected. It is necessary to increase Rpbn2. For example, consider a case where the resistance value Rpbn2 (≈Rpbn1) of the negative electrode connecting conductor plate 91 is increased by ΔRpbn2, that is, Rpbn2 is set to Rpbn2 + ΔRpbn2. In that case, according to Kirchhoff's current law, the current In1 flowing through the first negative electrode connection terminal 10a can be expressed by the following equation (1). Further, the current In2 flowing through the second negative electrode connection terminal 10b is expressed by the following equation (2).

As described above, in order to equalize the heat generation of the first negative electrode connection terminal 10a and the heat generation of the second negative electrode connection terminal 10b, the relationship of Rn1 × In1 ² ≈Rn2 × In2 ² needs to be established. It is necessary to satisfy Expression (3). When Expression (3) is established, Expressions (4) and (5) are established.

Here, assuming that Rpbn1≈Rpbn2 and ΔRn = Rn1-Rn2, the relationship of equation (6) is obtained. Formula (6) is obtained when the resistances Rn1 and Rn2 of the first and second negative

electrode connection terminals

10a and 10b of the power semiconductor module 1 and the resistance Rpbn1 between the first negative electrode connection terminal 10a and the capacitor negative electrode terminal 13 are given. Is an equation for giving an increase ΔRpbn2 of the resistance Rpbn2 necessary for equalizing the heat generation between the

terminals

10a and 10b. Therefore, by adjusting the resistance value between the power semiconductor module 1 and the capacitor element 2 shown in FIG. 3 according to this relationship, the loss of each terminal in the power semiconductor module 1 is equalized as shown in FIG. 4B. It becomes. FIG. 4A shows the power consumption at the

terminals

10a and 10b before equalization. In FIG. 4B, these lines are indicated by broken lines. In FIG. 4, the first terminal corresponds to the first negative electrode connection terminal 10a, and the second terminal corresponds to the second negative electrode connection terminal 10b.

As described above, in this embodiment, in order to eliminate the difference between the heat generation of the first negative electrode connection terminal 10a and the heat generation of the second negative electrode connection terminal 10b, as shown in the equation (6), their resistance Based on Rn1, Rn2 and the difference ΔRn, the magnitude of the resistor Rpbn2 from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13 was set to be increased by ΔRpbn2.

The same applies to the equalization of heat generation between the first and second positive

electrode connection terminals

11a and 11b of the power semiconductor module 1. When the magnitude of the resistor Rpbp2 is increased by ΔRpbp2, the equation (6) is used. Rn1, Rn2, Rpbn1, and ΔRpbn2 may be replaced with parameters Rp1, Rp2, Rpbp1, and ΔRpbp2 related to the positive electrode.

In the present embodiment, ΔRpbn2 and ΔRpbp2 are given by devising the shape of the connecting conductor plate layer 9. Below, the specific shape of the connection conductor board layer 9 which gives (DELTA) Rpbn2 and (DELTA) Rpbp2 is demonstrated.

(First embodiment)
FIGS. 5 to 7 are views showing a first embodiment of the shape of the connection conductor plate layer 9. FIG. 5 is a diagram showing the power semiconductor module 1 and the capacitor element 2 connected by the connection conductor plate layer 9. In addition, about the power semiconductor module 1, illustration of the module case 53 was abbreviate | omitted so that the internal structure could be understood easily. As described above, the first and second negative

electrode connection terminals

10a and 10b are connected to the negative electrode connection conductor plate 91 of the connection conductor plate layer 9, and the first and second positive

electrode connection terminals

11a and 11b are connected to the connection conductor plate layer 9. Connected to the positive connection conductor plate 92. The connection conductor plate layer 9 is formed by laminating and integrating a negative electrode connection conductor plate 91 and a positive electrode connection conductor plate 92, and an insulating layer is provided between the negative electrode connection conductor plate 91 and the positive electrode connection conductor plate 92. Are formed and are electrically insulated from each other. However, the present invention is not limited to the laminated negative electrode connecting conductor plate 91 and positive electrode connecting conductor plate 92 but can be applied.

FIG. 6 is a diagram for explaining the relationship between the negative connection conductor plate 91 and the positive connection conductor plate 92 and each connection terminal. FIG. 6A shows a plan view of the negative electrode connection conductor plate 91, and FIG. 6B shows a plan view of the positive electrode connection conductor plate 92. FIG. 7 is a view showing the AA cross section of FIG. As shown in FIGS. 5 and 7, the negative connection conductor plate 91 is laminated on the upper surface side of the positive connection conductor plate 92.

As shown in FIG. 6, the negative connection conductor plate 91 has a through hole 910 through which the

terminals

10 a, 10 b, 11 a, and 11 b of the power semiconductor module 1 pass, a through hole 912 through which the capacitor negative terminal 13 passes, and a capacitor positive electrode A through hole 913 for passing the terminal 14 is formed. Similarly, through the positive connection conductor plate 92, a through hole 920 for passing the

terminals

10a, 10b, 11a, 11b of the power semiconductor module 1, a through hole 923 for passing the capacitor negative terminal 13, and the capacitor positive terminal 14 are passed. A through-hole 924 for each is formed. The through hole 910 and the through hole 920, the through hole 912 and the through hole 923, and the through hole 913 and the through hole 924 are formed so as to overlap each other. In the present embodiment, the through

holes

910, 920, 912, 913, 923, and 924 are used, but a slit cut from the edge of the connection conductor plate layer 9 may be used.

First, the negative electrode connection conductor plate 91 will be described. A terminal portion 91a to which the first negative electrode connecting terminal 10a is connected and a terminal portion 91b to which the second negative electrode connecting terminal 10b is connected are formed in the through hole 910 portion of the negative electrode connecting conductor plate 91. Further, a terminal portion 91 d to which the capacitor negative electrode terminal 13 is connected is formed in the through hole 912 portion of the negative electrode connecting conductor plate 91.

As described above, the resistance value Rn1 of the first negative electrode connection terminal 10a is larger than the resistance value Rn2 of the second negative electrode connection terminal 10b. Therefore, in the present embodiment, as described above, the resistance value Rpbn2 from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13 is increased by ΔRpbn2, thereby generating heat in the first negative electrode connection terminal 10a and the second negative electrode connection terminal 10b. To equalize the heat generation.

Therefore, in the negative electrode connecting conductor plate 91 shown in FIG. 6A, the first negative electrode connecting terminal 10a having a larger resistance value is arranged closer to the capacitor negative electrode terminal 13, and the slit 911 is connected to the negative electrode. The conductor plate 91 was formed.

6A, a solid line L1 indicates a current path from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13, and a solid line L2 indicates a current path from the first negative electrode connection terminal 10a to the capacitor negative electrode terminal 13. A broken line L10 indicates a current path from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13 when the slit 911 is not provided. Note that the current paths L1, L2, and L10 indicate regions having a high current density with lines.

The slit 911 communicates with the through hole 910 and extends from the through hole 910 in a direction orthogonal to the arrangement direction of the negative

electrode connection terminals

10a and 10b. Therefore, the current path from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13 is a path that bypasses the slit 911 as indicated by the solid line L1, and is a path that is longer than the current path L10 when the slit 911 is not provided. Become. That is, the path indicated by reference sign S1 functions as a path resistance increasing portion in the current path L1. As a result, the above-described resistance increase ΔRpbn2 can be set for the current path L1.

Thus, even when the resistances of the two negative

electrode connection terminals

10a and 10b are different, the negative electrode connection conductor plate 91 is configured as shown in FIG. Heat generation can be equalized. That is, in the present embodiment, the two negative

electrode connection terminals

10a and 10b are provided to reduce the inductance by paralleling the current paths, and also to equalize the heat generation between the terminals.

In addition, the broken line L10 of Fig.6 (a) has shown the electric current path | route when not forming the slit 911 as mentioned above. In this case, by arranging the first negative electrode connection terminal 10a closer to the capacitor negative electrode terminal 13, the current path L10 is longer than the current path L2 by the distance between the terminals. Therefore, although the heat generation unbalance between the terminals can be slightly reduced, the length of the current path cannot be arbitrarily changed as in the case where the slit 911 is formed. Is difficult.

Next, the positive electrode connecting conductor plate 92 will be described. As shown in FIG. 6B, in the portion of the through hole 920 of the positive electrode connecting conductor plate 92, a terminal portion 92a connected to the first positive electrode connecting terminal 11a and a terminal connected to the second positive electrode connecting terminal 11b. A portion 92b is formed. A terminal portion 92 d connected to the capacitor positive electrode terminal 14 is formed in the through hole 924 portion of the positive electrode connecting conductor plate 92.

As described above, the resistance value Rp1 of the first positive electrode connection terminal 11a is larger than the resistance value Rp2 of the second positive electrode connection terminal 11b. Therefore, it is necessary to make the resistance value Rpbp2 from the second positive electrode connection terminal 11b to the capacitor positive electrode terminal 14 larger than the resistance value Rpbp1 from the first positive electrode connection terminal 11a to the capacitor positive electrode terminal 14. That is, the resistance value Rpbp2 is increased as Rpbp2 → Rpbp2 + ΔRpbp2.

Incidentally, since the arrangement of the negative

electrode connection terminals

10a and 10b with respect to the capacitor negative electrode terminal 13 is set as described above, the arrangement of the positive

electrode connection terminals

11a and 11b with respect to the capacitor positive electrode connection terminal 41 is automatically determined. That is, the second positive electrode connection terminal 11 b having a smaller resistance value is closer to the capacitor positive electrode connection terminal 41. Therefore, in the case of the positive electrode connecting conductor plate 92,

slits

921 and 922 communicating with the through hole 920 are formed as shown in FIG.

In FIG. 6B, a broken line L3 indicates a current path from the first positive electrode connection terminal 11a to the capacitor positive terminal 14, and a solid line L4 indicates a current path from the second positive electrode connection terminal 11b to the capacitor positive terminal 14. . As described above, the resistance value Rp2 of the positive second connection terminal 11b is smaller than the resistance value Rp1 of the positive first connection terminal 11a. Therefore, slits 921 and 922 are formed in the positive connection conductor plate 92 to form a detour path (path resistance increasing portion S2) that moves away from the capacitor positive terminal 14 toward the terminal 11a, and the resistance value in the current path L4 is the current. It was made larger than the resistance value in the path L3. As a result, the heat generation between the

terminals

11a and 11b can be equalized.

(Second embodiment)
FIG. 8 is a diagram for explaining the second embodiment. In the first embodiment described above, the capacitor element 2 and the capacitor element 2 are arranged so that the arrangement direction of the capacitor negative terminal 13 and the capacitor positive terminal 14 and the arrangement direction of the

terminals

10a, 10b, 11a, 11b of the power semiconductor module 1 are orthogonal to each other. The power semiconductor module 1 was connected to the connection conductor plate layer 9. On the other hand, in the second embodiment, as shown in FIG. 8, the arrangement direction of the capacitor negative terminal 13 and the capacitor positive terminal 14 and the arrangement direction of the

terminals

10a, 10b, 11a, 11b of the power semiconductor module 1 are parallel. Thus, the capacitor element 2 and the power semiconductor module 1 are connected to the connection conductor plate layer 9. In the following description, the negative electrode connection conductor plate 91 will be described, but the same applies to the positive electrode connection conductor plate 92.

As shown in FIG. 8A, the negative electrode connecting conductor plate 91 has through

holes

912, 913, and 914 formed therein. In the portion of the through hole 912, a terminal portion 91d is formed as in the case shown in FIG. The through hole 914 has an elongated shape in the arrangement direction of the

terminals

13 and 14, and the

terminals

10a, 10b, 11a, and 11b are arranged in the vertical direction in the figure. A terminal portion 91a connected to the first negative electrode connection terminal 10a and a terminal portion 91b connected to the second negative electrode connection terminal 10b are formed in the through hole 914 portion. Further, a slit 915 is formed so as to communicate with the through hole 914.

In the example shown in FIG. 8A, the through hole 914 is formed in the negative electrode connecting conductor plate 91, and the

terminal portions

91a and 91b are formed at the edge of the through hole (that is, the edge of the negative electrode connecting conductor plate 91). However, as shown in FIG. 8B,

terminal portions

91a and 91b may be formed on the right edge of the negative electrode connecting conductor plate 91 in the drawing.

A solid line L5 indicates a current path from the first negative electrode connection terminal 10a to the capacitor negative electrode terminal 13, and a solid line L6 indicates a current path from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13. A broken line L60 indicates a current path from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13 when the slit 915 is not formed.

As described above, the resistance value Rn1 of the first negative electrode connection terminal 10a is larger than the resistance value Rn2 of the second negative electrode connection terminal 10b. Therefore, in order to equalize the heat generation of the

connection terminals

10a and 10b, the resistance value Rpbn2 from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13 is changed to the resistance value Rpb1 from the first negative electrode connection terminal 10a to the capacitor negative electrode terminal 13. Need to be bigger than. Specifically, the resistance value is increased by ΔRpbn2 given by the above-described equation (6).

Therefore, the slit 915 is formed so that the current path L6 is longer than the current path R5. The slit 915 extends in the terminal 13 direction (left direction in the figure) at the boundary between the second negative electrode connection terminal 10b and the first positive electrode connection terminal 11a, and the lower direction in the figure in which the first negative electrode connection terminal 10a is arranged from the middle. And is extended to the vicinity of the boundary between the second positive electrode connection terminal 11b and the first negative electrode connection terminal 10a.

By forming the slit 915 having such a shape, the current path L6 detours to the region of the current path L5 and then moves toward the capacitor negative electrode terminal 13. Therefore, the current path L6 is longer than the current path L5 by this detour amount. That is, the portion indicated by reference numeral S3 functions as a path resistance increasing portion in the current path L6. As a result, the resistance value Rpbn2 from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13 increases as the path becomes longer. Then, by adjusting the increase amount to ΔRpbn2 calculated from Expression (6), the heat generation of the first negative electrode connection terminal 10a and the heat generation of the second negative electrode connection terminal 10b can be equalized.

(Third embodiment)
FIG. 9 is a diagram for explaining the third embodiment. In the third embodiment, as in the case of the first embodiment described above (see FIG. 6A), through-

holes

910, 912, and 913 are formed in the negative electrode connecting conductor plate 91, and the through-holes are also formed. A slit 911 communicating with 910 is formed. A terminal portion 91d to which the capacitor negative electrode terminal 13 is connected is formed in the through hole 912 portion. A terminal portion 91a connected to the first negative electrode connection terminal 10a and a terminal portion 91b connected to the second negative electrode connection terminal 10b are formed in the through hole 910.

In the first embodiment described above, the thickness of the negative electrode connecting conductor plate 91 is uniform, but in the third embodiment, the thickness of the region C is made thinner than the other regions. That is, t2 <t1 is set. The

terminals

10a, 10b, 11a, and 11b are arranged in the horizontal direction in the figure, but the region C is set to a portion on the right side of the first negative electrode connection terminal 10a.

When the thickness of the negative electrode connection conductor plate 91 is configured in this way, the entire current path L7 from the first negative electrode connection terminal 10a to the capacitor negative electrode terminal 13 passes through the portion having a thickness t1. On the other hand, in the case of the current path L8 from the second negative electrode connection terminal 10b to the capacitor negative electrode terminal 13, a part passes through the region C having the thickness t2. Since the thickness t2 of the region C is t2 <t1, the resistance is larger than that in the case of the thickness t1. For this reason, in this embodiment, even if the length of the current path L8 is smaller than the current path L1 shown in the first embodiment, the resistance value increment ΔRpbn2 is set to the same level as in the first embodiment. Can do. That is, the depth of cut of the slit 911 (the vertical dimension in the figure) can be made smaller than in the first embodiment. Furthermore, the resistance value increment ΔRpbn2 can be set without forming the slit 911.

(Fourth embodiment)
FIG. 10 is a diagram for explaining the fourth embodiment. In the third embodiment described above, the resistance value Rpbp2 in the current path L8 is increased by thinning the region C of the negative electrode connecting conductor plate 91. On the other hand, in the fourth embodiment, the thickness of the negative electrode connecting conductor plate 91 is made uniform, and the notch 916 is formed in the region C, so that the width of the current path L8 in the region C is reduced. did. As a result, the resistance indicated by reference numeral S4 in this region C increases, and this portion functions as a path resistance increasing portion in the current path L8. That is, by providing the path resistance increasing portion S4, it is possible to set the resistance increment ΔRpbn2 for eliminating the heat generation imbalance in the

connection terminals

10a and 10b.

Here, the rectangular negative electrode connecting conductor plate 91 as shown in FIG. 6A is referred to as the notch 916, but here, the notch is not important, and the terminal portion 91b in the region C is not formed. It is important that the conductor plate width D1 of the formed portion is set smaller than the width D2 of the same region C in the negative electrode connection conductor plate 91 shown in FIG. As a result, the resistance value Rpbn2 in the current path L8 can be increased as in the case where the slit 911 having a large cut depth is formed in FIG. In the case of the present embodiment, it is not essential to form the slit 911, and the width D1 of the negative electrode connecting conductor plate 91 between the terminal 10a and the terminal 10b is a dimension that can obtain the necessary resistance increment ΔRpbn2. The slit 911 may not be formed. When the slit 911 is not formed, D2 corresponds to the width dimension between the terminal portion 91a and the edge of the conductor plate.

In the above-described embodiment, the case where the DC connection terminal is branched into two has been described as an example, but the present invention can be similarly applied to the case where the DC connection terminal is branched into three or more. For example, as shown in FIG. 11, the DC connection terminal has three branch terminals (first negative connection terminal 10a (resistance value Rn1), second negative connection terminal 10b (resistance value Rn2), and third negative connection terminal 10c (resistance The case of branching to the value Rn3)) will be described. Here, Rn1> Rn2> Rn3. In this case, a slit 911a is formed between the

terminal portions

91a and 91b as shown in FIG. 11, and a deeper slit 911b is formed between the

terminal portions

91b and 91c. Note that three

branch terminals

11a, 11b, and 11c are also formed on the positive electrode connection terminal side, and

terminal portions

92a, 92b, and 92c to which they are connected are formed on the positive electrode connection conductor plate 92.

With such a configuration, each of the current paths between the

other terminals

10b and 10c except the terminal 10a having the largest resistance value among the plurality of terminals and the capacitor negative terminal 13 is provided in the negative electrode connecting conductor plate 91. Path resistance increasing portions S5 and S6 for equalizing heat generation can be formed on L1b and L1c. As a result, the heat generation can be equalized between the

terminals

10a, 10b, and 10c, and the reliability can be improved by suppressing the temperature rise, and the current capacity can be improved by suppressing the temperature rise.

6, the power semiconductor module 1 on which the capacitor element 2 and the power semiconductor element 30 are mounted, the capacitor negative terminal 13 of the capacitor element 2 and the direct current on the negative side of the power semiconductor module 1. A negative connection conductor plate 91 to which the terminals (10a, 10b) are connected, a positive electrode connection conductor plate 92 to which the capacitor positive terminal 14 of the capacitor element 2 and the DC terminal (11a, 11b) on the positive side of the power semiconductor module 1 are connected. And at least one of the DC terminals (the DC terminal on the negative side in FIG. 6) is connected to the first DC connection terminal 10a and the second DC connection terminal 10b having a smaller resistance value than the first DC connection terminal 10a. If it is branched, the configuration is as follows.

That is, the negative electrode connection conductor plate 91 to which the first and second

DC connection terminals

10a and 10b are connected has the capacitor negative electrode terminal 13 and the resistance value between the capacitor negative electrode terminal 13 and the first DC connection terminal 10a. A path resistance increasing portion S1 set based on the resistance value of the first DC connection terminal 10a and the resistance value of the second DC connection terminal 10b is set so that the resistance value between the second DC connection terminal 10b and the second DC connection terminal 10b increases. And formed on the current path L1 between the capacitor negative electrode terminal 13 and the second DC connection terminal 10b.

Thus, by providing the path resistance increasing portion S1 on the current path L1 between the terminal 10b and the capacitor negative terminal 13 for the second DC connection terminal 10b having a small parasitic resistance, the above-described formula (6) The resistance of the current path L1 can be increased by the resistance increase ΔRpbn2 calculated in (1). As a result, the heat generation of the

terminals

10a and 10b can be equalized, and the reliability can be improved by suppressing the temperature rise, and the current capacity can be improved by suppressing the temperature rise.

As one method for forming the path resistance increasing portion, as shown in FIG. 6A, a terminal portion 91b to which the first negative electrode connecting terminal 10a is connected and a terminal portion 91b to which the second negative electrode connecting terminal 10b is connected are provided. A slit 911 that cuts from the edge of the conductor plate is formed between the two, and a current path L1 that wraps around the slit 911 is formed by blocking the current flow as indicated by the line L10 by the slit 911.

As another forming method, when the second positive electrode connection terminal 11b having a small resistance value is formed near the capacitor positive electrode terminal 14 as shown in FIG. 6B, in addition to the slit 921, the second positive electrode is connected. At the edge of the conductor plate located on the opposite side of the slit 921 across the terminal portion 92b to which the connection terminal 11b is connected, a slit cut into the conductor plate side deeper than the slit 921 from the edge, and the terminal portion 92a from the slit There is a method of forming a slit 922 having a slit extending to bend to the side. In this case, the conductor plate region sandwiched between the slit 921 and the slit 922 constitutes the path resistance increasing portion S2.

As a third forming method, as shown in FIG. 8, the terminal portion 91 b is formed from the capacitor negative electrode terminal 13 among the

terminal portions

91 a and 91 b formed at the edge of the negative electrode connecting conductor plate 91. Is the case. In this case, a slit formed on the edge of the conductor plate located on the opposite side of the terminal portion 91a with the terminal portion 91b interposed therebetween, and formed so as to cut from the edge to the conductor plate side, and the terminal portion 91a from the slit. A slit 915 having a slit extending to be bent to the side is provided. The conductor plate region surrounded by the slit 915 constitutes the path resistance increasing portion S3.

Further, as shown in FIG. 9, the conductor plate thickness t2 of the conductor plate region on the terminal portion 91b side relative to the terminal portion 91a is set to be the conductor plate thickness t1 of the conductor plate region on the capacitor negative electrode terminal 13 side including the terminal portion 91a. Configure thinner. With such a configuration, the conductor plate region included in the region C in the current path L8 functions as a path resistance increasing portion.

Furthermore, as shown in FIG. 10, the conductor plate width dimension D1 in the direction substantially orthogonal to the current path L8 in the conductor plate region closer to the terminal portion 91b than the terminal portion 91a is set to the capacitor negative electrode terminal 13 including the terminal portion 91a. You may make it set smaller than the conductor board width dimension of the direction substantially orthogonal to an electric current path | route in the side conductor board area | region. As a result, the narrowed region S4 functions as a path resistance increasing portion.

Note that the present invention is not limited to the above embodiment as long as the characteristics of the present invention are not impaired. Further, the above-described embodiments may be used in combination. The power converter according to the present invention includes an inverter system used in HEV (hybrid vehicle), EV (electric vehicle) and the like as shown in FIG. 1 and a motor-driven power converter used in general work machines. It can also be applied to.

1: power semiconductor module, 2: capacitor, 9: connection conductor plate layer, 10a, 10b, 10c: negative connection terminal, 13: negative connection terminal, 11a: first positive connection terminal, 11b: second positive connection terminal, 13 : Capacitor negative terminal, 14: Capacitor positive terminal, 30a, 30b: Power semiconductor element, 60: Inverter system, 91: Negative electrode connecting conductor plate, 91a, 91b, 91c, 91d, 92a, 92b, 92c, 92d: Terminal part, 92: Positive connection conductor plate, 910, 912, 913, 920, 923, 924: Through hole, 911, 915, 921, 922: Slit, L1 to L8, L1a to L1c, L10, L60: Current path, S1 to S6 : Path resistance increasing part

Claims

A power semiconductor module equipped with a power semiconductor element and having a DC positive terminal and a DC negative terminal;
A capacitor that smoothes DC power and has capacitor terminals on the negative electrode side and the positive electrode side;
A conductor plate on the negative electrode side to which a capacitor terminal on the negative electrode side of the capacitor and a DC negative electrode terminal of the power semiconductor module are connected;
A positive electrode side conductor plate to which a positive electrode terminal of the capacitor and a DC positive electrode terminal of the power semiconductor module are connected, and a power converter that converts DC power into AC power,
At least one of the DC negative terminal or the DC positive terminal is composed of a plurality of branch terminals having different parasitic resistances,
On the conductor plate to which the plurality of branch terminals are connected, on the current path between the branch terminal and the capacitor terminal, the path resistance is increased to equalize the heat generated in the plurality of branch terminals between the branch terminals. The power converter device characterized by the above-mentioned.
The power conversion device according to claim 1,
At least one of the DC negative terminal or the DC positive terminal is composed of a first branch terminal and a second branch terminal having a smaller resistance value than the first branch terminal,
Based on the parasitic resistance of the first and second branch terminals, the conductor plate to which the first and second branch terminals are connected is more than the resistance value between the capacitor terminal and the first branch terminal. A path resistance increasing portion set so that a resistance value between the capacitor terminal and the second branch terminal is larger is formed on a current path between the capacitor terminal and the second branch terminal; The power converter characterized by the above-mentioned.
The power conversion device according to claim 2,
The conductive plate to which the first and second branch terminals are connected is
A first terminal portion formed on an edge of the conductor plate;
A second terminal portion formed on the edge at a predetermined interval from the first terminal portion;
A first slit formed between the first terminal portion and the second terminal portion so as to be cut from the edge toward the conductor plate;
The first terminal portion is connected to the first branch terminal;
The second terminal portion is connected to the second branch terminal;
The path resistance increasing portion is a conductor plate region formed so as to go around the first slit from the second terminal portion.
The power conversion device according to claim 3,
Of the first and second terminal portions, the second terminal portion is disposed closer to the capacitor terminal,
The conductive plate to which the first and second branch terminals are connected is
On the edge of the conductor plate located on the opposite side of the first slit across the second terminal portion, a second slit cut from the edge to the conductor plate side deeper than the first slit,
A third slit extending from the second slit so as to bend toward the first terminal portion, and
The path resistance increasing portion is a conductor plate region sandwiched between the first slit and the second and third slits.
The power conversion device according to claim 2,
The conductive plate to which the first and second branch terminals are connected is
A first terminal portion formed on an edge of the conductor plate;
A second terminal portion formed on the edge located near the capacitor terminal at a predetermined interval from the first terminal portion;
A first slit formed on the edge of the conductor plate located on the opposite side of the first terminal part across the second terminal part so as to cut from the edge to the conductor plate side;
A second slit extending from the first slit so as to bend toward the first terminal portion, and
The first terminal portion is connected to the first branch terminal;
The second terminal portion is connected to the second branch terminal;
The path resistance increasing portion is a conductor plate region surrounded by the first slit and the second slit.
The power conversion device according to claim 2,
The conductive plate to which the first and second branch terminals are connected is
A first terminal portion formed on an edge of the conductor plate;
A second terminal portion formed on the edge located near the capacitor terminal at a predetermined interval from the first terminal portion,
The first terminal portion is connected to the first branch terminal;
The second terminal portion is connected to the second branch terminal;
The conductor plate thickness of the conductor plate region on the second terminal portion side of the first terminal portion is thinner than the conductor plate thickness of the conductor plate region on the capacitor terminal side including the first terminal portion. Power converter.
The power conversion device according to claim 2,
The conductive plate to which the first and second branch terminals are connected is
A first terminal portion formed on an edge of the conductor plate;
A second terminal portion formed on the edge located near the capacitor terminal at a predetermined interval from the first terminal portion,
The first terminal portion is connected to the first branch terminal;
The second terminal portion is connected to the second branch terminal;
In the conductor plate region on the second terminal portion side of the first terminal portion, the conductor plate width dimension in the direction substantially perpendicular to the current path is in the conductor plate region on the capacitor terminal side including the first terminal portion, A power conversion device, characterized in that it is set to be smaller than a width of a conductor plate in a direction substantially perpendicular to the current path.