WO2015015620A1 - Data transfer device, data output device, data transfer method, and data output method - Google Patents

Abstract

A data transfer device is provided with a mixed data creation unit (35) for mixing received data input from a plurality of first communication paths and creating mixed data when the data transmission speed of the received data input from the plurality of first communication paths is lower than the data transmission performance value of a second communication path, and an output unit (35) for outputting the mixed data created by the mixed data creation unit (35) to the second communication path. Thereby, it is possible to enhance data transfer efficiency.

Description

Data transfer device, data output device, data transfer method, and data output method

The present invention relates to a data transfer device, a data output device, a data transfer method, and a data output method.

In recent years, high-speed interfaces have been developed one after another in network systems, and the demand for higher speed is increasing. As a result, in the future, a system in which old and new system devices are mixed will increase, and a data transfer device that supports a plurality of transmission speeds is desired in the system devices.
For example, in Ethernet (registered trademark), products having a transmission rate of 100 Gbps have recently been released. As a result, data transfer devices such as Ethernet switches are expected to support multiple data transmission rates such as 1 Gbps, 10 Gbps, 40 Gbps, and 100 Gbps. Hereinafter, an example in which the data transfer apparatus is an Ethernet switch (simply referred to as a switch) will be described.

FIG. 20 is a diagram illustrating a configuration example of a conventional network system. The network system shown in FIG. 20 includes a plurality of servers (Server) # 00, # 01, # 10 to # 14, and a plurality of switches (SW) # 1 to # 5.
In the network system shown in FIG. 20, for example, when data is transmitted from server # 00 to server # 10, the data (frame) is server # 00 → SW # 1 → SW # 2 → SW # 4 → server #. 10 routes are transmitted. In this transmission route, the throughput (data transmission performance) of each transmission path connecting server # 00 to server # 10 is 10 Gbps, and each SW # 1, # 2, # 4 is simple. Data transfer is performed.

On the other hand, when data is transmitted from the server # 00 to the server # 14, the data is transmitted through the route of the server # 00 → SW # 1 → SW # 3 → SW # 5 → server # 14. In this transmission route, the throughput of the transmission path between server # 00 and SW # 1 is 10 Gbps, and the throughput of each transmission path from SW # 1 to server # 14 is 100 Gbps. Therefore, in SW # 1, a 10 Gbps frame is converted into a 100 Gbps frame.

In FIG. 20, data transferred between the devices is indicated by arrows for convenience. When a 100 Gbps frame is transmitted on a transmission path between devices, there is a method of transmitting using a plurality of lanes such as 4 lanes and 10 lanes.
FIG. 21 is a diagram schematically showing data transfer in a conventional data relay device, and FIG. 22 is a diagram showing the transfer method.

The switch includes a switch chip having a function of outputting (transferring) an input frame corresponding to a desired destination.
In FIG. 21, each shaded rectangle represents data, and one rectangle represents one unit of data. One rectangle (data) has a data size of 8 bytes, for example. A collection of multiple data is called a frame.

The switch chip shown in FIG. 21 is configured to be able to input 10 Gbps and 100 Gbps frames and to be able to output 10 Gbps and 100 Gbps frames. In other words, frame transfer can be performed with all combinations of 10 Gbps and 100 Gbps inputs and 10 Gbps and 100 Gbps outputs.
In FIG. 21, the internal operation by the combination of input and output frame speeds in the switch chip is indicated by dotted arrows.

In this switch chip, a frame is transferred by either a CT (Cut Through) method or an S & F (Store & Forward) method.
Specifically, when transferring from the same speed and a fast speed to a slow speed, data transfer is performed using the CT method, and when transferring from a slow speed to a fast speed, S & F is performed so that the frame data can be transmitted continuously. Transfer using the method. That is, as shown in FIG. 22, the S & F method is used when a frame input at 10 Gbps is output at 100 Gbps, and the CT method is used for other combinations.

Here, the CT method is a method of transferring received data one after another before reading all the data of the input frame. Since the output data transmission rate is equal to or less than the input data transmission rate, even if the data is transferred by CT, the data is not exhausted in the switch chip and the output frame is not interrupted. And sent out.
On the other hand, the S & F method is a method in which all data of a received frame is once stored in a buffer inside the switch chip and then transferred. When a frame input at 10 Gbps is output at 100 Gbps, the output data transmission speed is faster than that of the input data. Therefore, when the CT method is used for output, the output data is exhausted inside the switch. That is, data cannot be sent continuously.

Generally, the CT method can be transferred with less latency than the S & F method. Therefore, it can be said that the CT method is superior to the S & F method in terms of performance. Further, when data transfer can be performed by the CT method, it can also be performed by the S & F method. In order to perform processing such as frame checking, there is a case where the data is transferred by the S & F method so as to be buffered once in the switch chip.

The performance specifications that are important in such a switch chip are throughput and latency. Throughput here refers to the amount of data per unit time that can be transferred by the switch chip, and the larger the throughput value, the greater the amount of data that can be processed. Latency refers to the time required for data to pass through the switch chip. The smaller the latency value, the faster the data transfer process.
JP-A-6-97904

In the conventional data transfer apparatus described above, the S & F method is used when a frame received via a 10 Gbps transmission path is transferred to a 100 Gbps transmission path. In the S & F method, the received frame is buffered once in the switch chip and then transferred at a rate of 100 Gbps, so that the latency at the switch chip increases.
For example, when a large frame having a data size of about 9 KByte is received and transferred through a 10 Gbps transmission path, it is estimated that it takes at least 7200 ns to store the frame in a buffer in the switch chip. On the other hand, when the CT method is adopted, the latency through the switch chip is about several hundred ns.

Therefore, in the conventional data transfer apparatus, there is a problem in that the latency increases in the switch chip and the transmission performance of the network system is lowered by adopting the S & F method.
It is also conceivable to transmit by the CT method by allowing only 10 Gbps data to flow through the 100 Gbps transmission path on the output side. However, in this case, only 10% of the bandwidth is used in the transmission line on the output side having a transmission performance of 100 Gbps, and the high-speed interface performance cannot be used effectively.

As described above, the conventional data transfer apparatus has a problem that data transfer cannot be performed efficiently when transfer at different transmission rates is processed in the switch chip.
In one aspect, an object of the present invention is to improve data transfer efficiency.

In addition, the present invention is not limited to the above-described object, and other effects of the present invention can be achieved by the functions and effects derived from the respective configurations shown in the embodiments for carrying out the invention which will be described later. It can be positioned as one of

For this reason, this data transfer device is a data transfer device that transfers data between a plurality of first communication paths and one or more second communication paths, and inputs from each of the plurality of first communication paths. Mixed to create mixed data by mixing the received data input from each of the plurality of first communication channels when the data transmission rate of the received data is lower than the data transmission performance value of the second communication channel A data creation unit; and an output unit that outputs the mixed data created by the mixed data creation unit to the second communication path.

The data transfer method is a data transfer method in a data transfer device that transfers data between a plurality of first communication paths and one or more second communication paths, wherein the plurality of first communication paths When the data transmission rate of the received data input from each of the channels is lower than the data transmission performance value of the second communication channel, the received data input from each of the plurality of first communication channels is mixed and mixed Data is created, and the created mixed data is output to the second communication path.

The data output device outputs data to a communication path capable of transmitting a first frame having a first transmission rate and a second frame having a second transmission rate higher than the first transmission rate. A data output device for performing a multiplexing processing unit that multiplexes the number of the first frames determined by dividing the second transmission rate by the first transmission rate to create a multiplexed frame; An output unit for outputting the multiplexed frame created by the multiplexing processing unit to the communication path.

According to one embodiment, data transfer efficiency can be improved.

It is a figure which shows typically the structure of the switch chip with which the switch as an example of embodiment is equipped. It is a figure which illustrates a network structure provided with the switch as an example of embodiment. It is a figure which illustrates the structure of the flame | frame transferred in a network system provided with the switch as an example of embodiment. It is a figure which illustrates the structure of the flame | frame transferred in a network system provided with the switch as an example of embodiment. It is a figure which illustrates the structure of the output buffer in the switch as an example of embodiment. It is a figure which illustrates the preparation method of the mixed frame in the switch as an example of embodiment. It is a figure which shows the transfer method of the mixed frame in the switch as an example of embodiment. It is a figure which shows the state of the flame | frame in the transmission line of the network system provided with the switch as an example of embodiment. It is a figure which shows the state of the flame | frame in the transmission line of the network system provided with the switch as an example of embodiment. It is a figure which shows the state of the flame | frame in the transmission line of the network system provided with the switch as an example of embodiment. It is a figure explaining the frame selection algorithm in mode 1 (100G priority) in the switch as an example of an embodiment. It is a figure explaining the frame selection algorithm in mode 2 (10G priority) in the switch as an example of an embodiment. It is a figure which shows the operation | movement as a next stage switch of the switch as an example of embodiment. It is a figure which shows the operation | movement as a next stage switch of the switch as an example of embodiment. It is a figure which shows operation | movement of the switch as an example of embodiment. It is a flowchart explaining the frame transmission method in the mode 1 by the output buffer of the switch as an example of embodiment. It is a flowchart explaining the frame transmission method in the mode 2 by the output buffer of the switch as an example of the embodiment. It is a figure which shows the 1st modification of the network system provided with the switch as an example of embodiment. It is a figure which shows the 2nd modification of the network system provided with the switch as an example of embodiment. It is a figure which shows the structural example of the conventional network system. It is a figure which shows typically the data transfer in the conventional data relay apparatus. It is a figure which shows the data transfer method in the conventional data relay apparatus.

Hereinafter, embodiments of the data transfer device, the data output device, the data transfer method, and the data output method will be described with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude application of various modifications and techniques not explicitly described in the embodiment. In other words, the present embodiment can be implemented with various modifications (combining the embodiments and modifications) without departing from the spirit of the present embodiment. Each figure is not intended to include only the components shown in the figure, and may include other functions.

(A) Configuration FIG. 1 is a diagram schematically showing a configuration of a switch chip (data transfer circuit) 100 provided in a switch (data transfer device, data output device) 2 as an example of an embodiment, and FIG. It is a figure which illustrates the structure of the network system 1 which has a switch provided with.
The network system 1 illustrated in FIG. 2 includes a plurality of servers 3 and a plurality of switches (SW) 2. In the example shown in FIG. 2, seven servers 3 of servers # 00, # 01, and # 10 to # 14 and five switches 2 of switches # 01 to # 05 are provided.

Hereinafter, in the case of indicating a server, when it is necessary to specify one of a plurality of servers, reference numerals # 00, # 01, and # 10 to # 14 are attached. Use. Similarly, in the following, when a switch is indicated, reference numeral # 01 to # 05 are attached when it is necessary to specify one of a plurality of switches, but reference numeral 2 is used to indicate any switch.

In the network system 1, the switch 2 transfers the input data by the frame transfer method. Each switch 2 supports data input / output at a plurality of transmission rates, and enables data input and data output at each transmission rate of 1 Gpbs, 10 Gbps, 40 Gbps, and 100 Gbps, for example.
Hereinafter, in this embodiment, for convenience, a frame (first frame) transmitted at a transmission rate of 10 Gbps (first transmission rate) and a frame (first transmission rate) transmitted at a transmission rate of 100 Gbps (second transmission rate) ( An example in which frames of two types of transmission rates (second frame) are mixed is shown. Also, consider the maximum speed (maximum transmission speed) of 100 Gbps. That is, the maximum value of the data transfer rate in the network system 1 is 100 Gbps.

Note that the network system 1 is not limited to the mixed speed of 100 Gbps and 10 Gbps, but can be implemented with various modifications. For convenience of explanation, the specific speed is 100 Gbps and 10 Gbps for easy understanding. Will be described.
Hereinafter, data transmitted at a transmission rate of 10 Gbps is simply referred to as 10 Gbps data or 10 G frame. Similarly, data transmitted at a transmission rate of 100 Gbps is simply referred to as 100 Gbps data or 100 G frame.

In the present embodiment, in the network system 1 shown in FIG. 2, data (frames) transmitted from the servers # 00 and # 01 are transferred to any of the servers # 10 to # 14 via the plurality of switches 2. An example is shown. In the network system 1 shown in FIG. 2, the left side in the figure, that is, the servers # 00 and # 01 side may be referred to as the upstream side, and the right side in the figure, that is, the servers # 10 to # 14 side may be referred to as the downstream side.

The servers # 00 and # 01 and the switches # 02 and # 03 are connected to the switch # 01. Switches # 01 and # 04 are connected to the switch # 02, and switches # 01 and # 05 are connected to the switch # 03, respectively. Servers # 10 and # 11 and switch # 02 are connected to switch # 04. Servers # 12, # 13, # 14 and switch # 03 are connected to switch # 05.

Hereinafter, among the switches 2 provided in the network system 1, the switch 2 to which the server 3 is connected may be referred to as an edge switch 2. Further, the switch 2 arranged between the switches 2 and connected to the server 3 via another switch 2 may be referred to as a next-stage switch 2. In the example shown in FIG. 2, the switches # 01, # 04, and # 05 are the edge switches 2, and the switches # 02 and # 03 are the next stage switches 2.

Further, in the example shown in FIG. 2, the maximum values of the data transfer rates supported by the interfaces of the servers # 00, # 10, # 12, and # 13 are 10 Gbps, respectively, and the servers # 01, # 11, and # 14 The maximum data transfer rate supported by the interface is 100 Gbps each.
Between server # 00 and switch # 01, between switch # 01 and switch # 02, between switch # 04 and server # 10, between switch # 05 and server # 12, and between switch # 05 and server The throughput of each transmission line with # 13 is 10 Gbps.

On the other hand, between server # 01 and switch # 01, between switch # 01 and switch # 03, between switch # 02 and switch # 04, between switch # 03 and switch # 05, and switch # 04 The throughput of each transmission path between the server # 11 and between the switch # 05 and the server # 14 is 100 Gbps. These transmission paths with a throughput of 100 Gbps are used with a setting of 100 Gbps.

In the network system 1 shown in FIG. 2, a range (area) with a throughput of 100 Gbps is referred to as a maximum speed transmission area, and is surrounded by a dotted line and indicated by a symbol a in FIG.
Each switch 2 has the same configuration, and includes the switch chip 100 shown in FIG. That is, the function as each switch 2 is realized by various settings of the switch chip 100.

For example, the edge switches # 01, # 04, and # 05 are set for the edge portion in the network system 1 configured by a switch group, and the next-stage switches # 02 and # 03 are set for other switches in the system. Settings for connecting the switch chip 100 are performed.
Specifically, in the switches # 01, # 04, and # 05, the ports for the edge, that is, the ports connected to the server 3 (server side and upstream side) are supported by the interface of the connected server 3. It is set according to the speed. In addition, each port (switch chip side, downstream side) connected to the other switch 2 in the switches # 01, # 04, and # 05 is fixed to 100 Gbps which is the upper limit in the specification of the network system 1. Is set.

On the other hand, in the switches # 02 and # 03, the ports on the server # 00 and # 01 side (server side and upstream side) match the speed supported by the interface of the server 3 connected via the switch # 01. Are shown as examples. The switch chip side (downstream side) of the switches # 02 and # 03 is set to be fixed at 100 Gbps, which is the upper limit in the specifications of the network system 1.

Each output port 30 of the switch 2 connected to the maximum speed transmission area a is set to be fixed at 100 Gbps, which is the upper limit in the specification.
FIGS. 3 and 4 are diagrams illustrating the configuration of a frame transferred in the network system 1 including the switch 2 as an example of the embodiment. FIG. 3 illustrates a 10G mode frame, and FIG. It is a figure which illustrates the frame of a mode.

In the present storage system 1, the frames shown in FIGS. 3 and 4 are transferred. In FIGS. 3 and 4, the left side is the head of the frame, and the right side is the tail of the frame.
A 10G mode frame (10G mode frame) is a frame created to pass through a 10 Gbps transmission path. A 100G mode frame (100G mode frame) is a frame created to pass through a 100 Gbps transmission path.

When a 100G mode frame passes through a 100 Gbps transmission path, it is transmitted using 100% bandwidth of this transmission path, and when a 10G mode frame passes through a 100 Gbps transmission path, it is 1/10 of this transmission path. It is transmitted using a band.
As shown in FIGS. 3 and 4, the 10G mode frame and the 100G mode frame include fields of PR, DA, SA, TP, IP packet (IP Packet), and FCS, respectively.

The field “PR (Preamble)” includes an 8-byte data storage area, for example. In this field “PR”, 7-byte information indicating the head of data is stored. Specifically, 7-byte data configured by repeating 7 consecutive 1-byte data (10101010) repeating 0 and 1 is stored as information indicating the head of the data.
Further, 1-byte identification information (data transmission rate information) indicating the transmission rate of the frame is stored in the field “PR”. That is, the data transmission rate information indicates whether the frame is a 10G mode frame or a 100G mode frame.

Specifically, in the 10G mode frame, for example, 8′b01011011, that is, 1 byte (8 bits) information having a pattern of “01011011” is set as data transmission rate information. On the other hand, in the 100G mode frame, for example, 8′b01101011, that is, 1 byte (8 bits) information having a pattern of “01101011” is set as data transmission rate information. This data transmission rate information is provided following the 7-byte information indicating the head of the data described above.

In this way, in the field “PR”, 1-byte data transmission rate information (“01011011” or “01101011”) is stored at the trailing end of 01 of 7 bytes indicating the head of data.
Note that the data transmission rate information of the field “PR” in these 10G mode frame and 100G mode frame is added by the MAC 33 of the switch 2 connected to the server 3 that is the data transmission source in the network system 1, for example.

For example, in the network system 1 shown in FIG. 2, the maximum value of the data transfer rate supported by the interface of the server # 00 that is the frame transmission source is 10 Gbps. 8'b01011011 is set as data transmission rate information in the PR of the frame received from 00. As a result, the frame output from the server # 00 becomes a 10G mode frame.

Similarly, since the maximum value of the data transfer rate supported by the interface of the server # 01 that is the frame transmission source is 100 Gbps, the switch # 01 on the downstream side sets the PR of the frame received from the server # 01. 8'b01101011 is set as the data transmission rate information. As a result, the frame output from the server # 01 becomes a 100G mode frame.
The speed of the interface is determined in the link-up process, and is realized by, for example, an auto-negotiation function. The determination of the interface speed can be realized by using various known methods, and detailed description thereof will be omitted.

The field “DA” stores information indicating the destination of the frame (Destination Address), and the field “SA” stores information indicating the transmission source of the frame (Source Address). The field “TA” stores information indicating the type of the frame, and the field “IP Packet” stores data to be transferred (IP packet). The field “FCS” stores data error check data.

As illustrated in FIG. 1, the switch chip 100 includes n (n is a natural number) input ports 20, m (m is a natural number) output ports 30, and a control unit 10.
The switch chip 100 is configured to be able to input 10 Gbps and 100 Gbps frames, and to be able to output 10 Gbps and 100 Gbps frames. In other words, frame transfer can be performed with all combinations of 10 Gbps and 100 Gbps inputs and 10 Gbps and 100 Gbps outputs.

Data (packets) are input to the input port 20 from a server or another switch. In the following, when an input port is indicated, reference numerals # 1 to #n are given when it is necessary to specify one of a plurality of input ports, but reference numeral 20 is used to indicate any input port. Each input port 20 has the same configuration. In FIG. 1, for convenience, only the configuration of the input port # 0 is shown, and the configuration of the other input ports 20 is not shown.

Either a transmission line with a throughput of 10 Gbps or a transmission line with a throughput of 100 Gbps can be connected to the input port 20, and both a 10G mode frame and a 100G mode frame can be input. In the switch 2, the transmission path to which the input port 20 is connected is the first communication path, and the transmission path to which the output port 30 described later is connected is the second communication path.
As shown in FIG. 1, the input port 20 includes a PMA (Physical Medium Attachment) / PMD (Physical Medium Dependent) 21, a PCS (Physical Coding Sublayer) 22, a MAC (Media Access Control) 23, and a frame parser (Frame Parser) 24. And an input buffer (IBuf) 25.

The PMA / PMD 21 and the PCS 22 perform processing of a PHY (Physical layer) layer (physical layer), which is the first layer of the OSI (Open System Interconnection) 7 layer. That is, PMA / PMD 21 performs serial / parallel conversion and signal waveform conversion, and PCS 22 performs frame coding. The PMA / PMD 21 directly connected to the transmission path transmits the data received at the input port 2 as a digital signal inside the switch chip 100. The MAC 23 recreates the MAC frame.

The PCS 22 decodes the data sent after being encoded, and the MAC 23 regenerates the MAC frame.
For example, in the case of a 100G mode frame, the MAC 23 transfers the data as it is. In the case of a 10G mode frame, the MAC 23 thins out the data to 1/10 and transfers it within the switch chip 100. At this time, data is stored and transferred in the width of an internal bus (not shown). That is, the transfer is performed at the usage rate of 1/10 internal bus at the time of transfer of the 100G mode frame.

The frame parser 24 decodes the frame created by the MAC 23. Information and data decoded by the frame parser 24 are stored in the input buffer 25.
The frame parser 24 functions as a reading unit that reads out data transmission rate information included in reception data input from the first communication path to which the input port 20 is connected.
Data stored in the input buffer 25 is sequentially written into the shared memory 11 of the control unit 10.

Thus, the input port 20 writes the frame data of the received frame to the shared memory 11.
As illustrated in FIG. 2, the control unit 10 includes a shared memory 11, a frame / memory controller 12, and a table (TBL) 13.
The shared memory 11 is a storage device that stores data input to each input port 20. The frame / memory controller 12 controls writing of data to the shared memory 11 by the input port 20 and reading of data from the shared memory 11 from the output port 30 described later. The frame / memory controller 12 stores the data in the shared memory 11 and simultaneously notifies the output buffer 30 of the request.

In the table 13, for example, the destination information of the frame and the output port 30 are recorded in association with each other, and the frame / memory controller 12 outputs the output destination of the frame to be transferred based on the destination information recorded in the table 13. The output port 30 is determined.
Further, the frame / memory controller 12 notifies the determined output port 30 of a frame transfer request (hereinafter simply referred to as a request).

In the present switch 2, when frame data is received at the input port 20, the blurred data is stored in the shared memory 11, and the frame / memory controller 12 stores all the data constituting the frame in the shared memory 11. The request selector 352 is sequentially notified without waiting for the data to be stored.
In response to notification from the frame / memory controller 12, the request selector 352 sequentially reads the frames transferred from the shared memory 11 and stores them in the data buffer 354. That is, in this switch 2, data transfer is performed by the CT method (data non-retention transfer method) that sequentially outputs the received frame data without waiting for the output until all the data of the frame is completed.

The output port 30 reads data from the shared memory 11 and outputs data (packets) to the server and other switches. Hereinafter, when an output port is indicated, reference numerals # 1 to #m are used when one of a plurality of output ports needs to be specified, but reference numeral 30 is used to indicate an arbitrary output port. Each output port 30 has the same configuration. In FIG. 1, for convenience, only the configuration of the output port # 0 is shown, and the configuration of the other output ports 30 is not shown.

Either a transmission line with a throughput of 10 Gbps or a transmission line with a throughput of 100 Gbps can be connected to the output port 30, and both a 10G mode frame and a 100G mode frame can be output.
In the switch chip 100, since each input data from the input port 20 is transferred, a number of requests for output may be accumulated in the output port 30 in some cases.

In the output port 30, when a 100G mode frame is output through a 100 Gbps transmission path, the frame is transmitted using all bands, and when a 10 G mode frame is transmitted through a 100 Gbps transmission path, a maximum of 10 frames are transmitted. Multiplex and transmit.
As shown in FIG. 1, the output port 30 includes a PMA (Physical Medium Attachment) / PMD (Physical Medium Dependent) 31, a PCS (Physical Coding Sublayer) 32, a MAC (Media Access Control) 33, and an output buffer (OBuf) 35. Prepare.

FIG. 5 is a diagram illustrating a configuration of the output buffer 35 in the switch 2 as an example of the embodiment.
As shown in FIG. 5, the output buffer 35 includes a timer 351, a request selector 352, a request buffer 353, a data buffer 354, an AND circuit 355, and a mode register 356.

The timer 351 measures time according to an instruction from the request selector 352. In addition, the timer 351 notifies the request selector 352 of the measured time. The timer 351 also resets the time according to the instruction from the request selector 352.
The mode register 356 is a storage device that stores mode setting values. The mode setting value indicates a selected transfer mode from among transfer modes 1 to 3 described later. That is, any one of modes 1 to 3 is set in the mode register 356 in advance.

In the mode register 356, for example, “00” is set when mode 1 is set, “01” is set when mode 2 is set, and “mode” is set when mode 3 is set. “11” is stored. The transfer mode will be described later with reference to FIGS.
It is desirable that the mode setting value of the mode register 356 can be arbitrarily set by a system administrator or the like.

The request buffer 353 stores a request (transfer request) notified from the frame / memory controller 12. The request notified from the frame / memory controller 12 of the control unit 10 described above is stored in the request buffer 353.
Data read from the shared memory 11 is stored in the data buffer 354. In the data buffer 354, the storage position of data read from the shared memory 11 is also designated by the request selector 352 and the request buffer 353.

The AND circuit 355 receives an output signal from the data buffer 354 and a signal obtained by inverting the output signal from the MAC 33, and inputs an ANDed signal to the MAC 33. Thereby, when the output from the MAC 33 is completed, the next input is performed to the MAC 33.
The request selector 352 selects a request to be executed from the requests stored in the request buffer 353. The request selector 352 selects a request to be executed from among the requests stored in the request buffer 353 in accordance with an instruction from the frame / memory controller 12, and stores the frame transferred from the shared memory 11 in the read data buffer 354. .

For example, when outputting a 100 G mode frame at a rate of 100 Gbps, the request selector 352 reads a frame to be transferred from the shared memory 11 and stores it in the data buffer 354.
When outputting a 10G mode frame at a rate of 100 Gbps, the request selector 352 causes the 10G mode frame to be transferred to be read from the shared memory 11 at a period 10 times that of reading the 100G mode frame, The data is stored in the data buffer 354.

Further, in the case of outputting a 10G mode frame at a speed of 100 Gbps, when the output destination of the frame input from the plurality of input ports 20 is the output port 30 fixed to a common 100 Gbps, the request selector 352 The 10G mode frames from the plurality of input ports 20 are read out and stored in the data buffer 354, respectively.
In this way, the request selector 352 creates a mixed frame obtained by mixing a plurality of 10G mode frames in the data buffer 354.

That is, the request selector 352 functions as a mixed data generating unit that generates a mixed frame (mixed data), and also functions as a multiplexing processing unit that generates a multiplexed frame by multiplexing a plurality of 10 mode frames.
FIG. 6 is a diagram illustrating a mixed frame creation method in the switch 2 as an example of the embodiment, and FIG. 7 is a diagram illustrating the transfer method.

The switch 2 shown in FIG. 6 corresponds to the switch # 01 of FIG. In the example shown in FIG. 6, only some of the input ports 20 and output ports 30 provided in the switch 2 are illustrated.
In FIG. 6, 10G mode frames are input to the input ports # 1 to # 3 of the switch 2 at a transmission rate of 10 Gbps, respectively, and these 10G mode frames are output from the common output port # 4 having a fixed transmission rate of 100 Gbps. An example is shown. Specifically, 10G mode frames F1 and F4 are sequentially input to the input port # 1. Similarly, 10G mode frames F2 and F5 are sequentially input to input port # 2, and 10G mode frames F3 and F6 are sequentially input to input port # 3.

When the output destination of the frame input from the plurality of input ports 20 is the common output port # 4 fixed at 100 Gbps, the request selector 352 of the switch chip 100 is input to the plurality of input ports 20. A mixed frame (F01, F02) is created by mixing the frames.
The output port 30 uses a 100 Gbps frame transfer mechanism and inserts three 10 Gbps frames (for example, F1 to F3) respectively input from the three input ports 20 into a 100 Gbps frame (for example, F01). . As a result, three 10 Gbps frames respectively input from the three input ports 20 are overlapped (mixed) in a 100 Gbps frame (for example, F01). By outputting the 100 Gbps frame created in this way, the output port 30 transfers data using the 30% bandwidth in the 100 Gbps frame transfer mechanism.

In FIG. 6, the rectangles included in each frame on the input side and the output side indicate data, and one rectangle indicates one unit of data. One rectangle (data) has a data size of 8 bytes, for example.
In FIG. 6, the codes F1 to F6 attached to the input side frame indicate the same data as the codes F1 to F6 attached to the output side data frame. Each of these frames F1 to F6 has a fixed size (for example, 8 bytes) as described above.

Further, in the example shown in FIG. 6, 10 Gbps frames F1, F2, and F3 are included in one 100 Gbps frame F01. Further, 10 Gbps frames F4, F5, and F6 are included in the 100 Gbps frame F02 output next to the frame F01.
Also, frames input from each input port 20 are transferred at regular intervals. For example, the data F1 and F4 of the 10 Gbps input port # 1 are transferred at regular intervals (for example, 6.4 ns) from the 100 Gbps output port # 4.

That is, the ratio of the data transmission performance value (for example, 100 Gbps) of the second communication path connected to the output port 30 to the data transmission performance value (for example, 10 Gbps) of the first communication path connected to the input port 20 (100/10 = 10), a number of received data within this ratio is mixed at the output port 30 to create a mixed frame.
When receiving a frame at the input port 20, the request selector 352 immediately transfers the frame to the output port 30 via the shared memory 11.

As described above, the switch chip 100 outputs a low-speed frame (for example, 10 Gbps) as a mixed frame obtained by mixing (multiplexing) low-speed frames when transferring a low-speed (for example, 10 Gbps) frame using a high-speed (for example, 100 Gbps) interface. .
That is, the switch chip 100 multiplexes and transmits a frame having a transmission rate slower than the maximum transmission rate by a number equal to or less than the maximum multiplexing number = (maximum transmission rate / transfer rate to be transmitted).

As described above, in the switch 2, when a frame is received at the input port 20, the frame is immediately transferred to the output port 30 via the shared memory 11. Further, the output port 30 multiplexes a plurality of inputted low speed (for example, 10 Gbps) frames and outputs them from a high speed interface.
As a result, even when a frame input at 10 Gbps is output at 100 Gbps, frame transfer using the CT method is realized as shown in FIG.

FIG. 8 to FIG. 10 are diagrams showing frame states in the transmission path of the network system 1 including the switch 2 as an example of the embodiment. 8 is a diagram showing a 10G mode frame in a 100 Gbps transmission path, FIG. 9 is a diagram showing a 100 G frame in a 100 Gbps transmission path, and FIG. 10 is a diagram in which 10 G frames and 100 G frames are mixed in a 100 Gbps transmission path. It is a figure which shows the example which transmits.

In FIG. 8, each rectangle indicates a 10G frame, and a state (10G mode) in which a plurality of 10G frames are multiplexed and transferred in a 100 Gbps transmission path. That is, 10G frames are multiplexed and transferred to 100G.
FIG. 9 shows a state (100G mode) in which a 100 G frame is transferred on a 100 Gbps transmission path. Each 100G frame has a data size corresponding to 10 10G frames. In this 100G mode, data is sent using 100% of the transmission capacity of a 100 Gbps transmission line.

In the example shown in FIG. 9, each rectangle represents data, and one rectangle represents one unit of data. One rectangle (data) has a data size of 8 bytes, for example.
In the transmission line, 10G mode data and 100G mode data cannot be mixed and transmitted. Therefore, as shown in FIG. 10, by transmitting the frame of the other mode after the transmission of the frame of one mode is completed, the 100G mode frame and the 10G mode frame are switched and transferred.

Now, since there are two types of speed frames, 10G mode frame and 100G mode frame, in the output port 30, it is necessary to output the frame according to the state. In the switch chip 100, a frame to be output is selected using any one of three types of frame selection algorithms of modes 1 to 3.
FIG. 11 is a diagram illustrating a frame selection algorithm in mode 1 (100G priority) in the switch 2 as an example of the embodiment, and FIG. 12 is a diagram illustrating a frame selection algorithm in the mode 2 (10G priority).

The frame selection algorithm at the output port 30 will be described for the three control algorithms of modes 1 to 3.
In mode 1, a 100G mode frame is transferred with priority over a 10G mode frame. That is, as shown in FIG. 11, in principle, if the number of 100G mode frames is greater than or equal to the first predetermined number (for example, one), the 10G mode frame is put in a transfer waiting state, the transfer is suppressed, and the 100G mode frame is transferred. .

However, when the transfer waiting time of the 10G mode frame exceeds the first predetermined time (time limit), the 10G mode frame is transferred. The 10G mode frame is also transferred when a predetermined number (eg, 10) or more of 10G mode frames are accumulated.
In mode 2, the 10G mode frame is transferred with priority over the 100G mode frame. That is, as shown in FIG. 12, in principle, if there are more than a second predetermined number (for example, one) of 10G mode frames, the 100G mode frames are put in a transfer waiting state, the transfer is suppressed, and the 10G mode frames are transferred. .

However, when the transfer waiting time of the 100G mode frame exceeds the second predetermined time, the 100G mode frame is transferred.
In mode 3, mode 1 and mode 2 are switched at a constant cycle. Continuing mode 1 or mode 2 may cause either 100 G mode frame or 10 G mode frame to stay excessively in switch 2. Therefore, by periodically switching between mode 1 and mode 2 at a constant cycle, it is possible to prevent either the 100G mode frame or the 10G mode frame from staying in the switch 2.

Which of the modes 1 to 3 is adopted as the frame selection algorithm is registered in advance in the mode register 356 in the output port 30, for example, and the request selector 352 reads out the value of the mode register 356, and the modes 1 to 3 are selected. Select one of the following. Then, the request selector 352 selects a frame to be transmitted in the request buffer 353 according to the selected mode.

In the above modes 1 to 3, the first and second predetermined numbers and the first and second predetermined times can be implemented with various modifications. Further, it is desirable to set a value for specifying the first and second predetermined numbers and the first and second predetermined times in a register or the like and to change the values. This example provides a method in which a 10G mode frame and a 100G mode frame can be output without much waiting. The algorithm for determining the frame to be output from the number of 10G mode frames and 100G mode frames will be described, and the individual number and algorithm are not limited.

For example, as the first and second predetermined numbers, setting a value obtained by dividing the maximum transfer rate in the switch chip 100 by the minimum transfer rate (maximum transfer rate / minimum transfer rate) can effectively use the bus without waste. It is thought that. In the present embodiment, the maximum transfer rate of the switch chip 100 is 100 Gbps, and the minimum transfer rate is 10 Gbps. Therefore, in the example shown in FIGS. 11 and 12, 100/10 = 10 is set as the first predetermined number and the second predetermined number.

Further, when the frame selection algorithm as shown in the above modes 1 to 3 is adopted, overtaking between frames at different speeds occurs in the switch chip 100. However, since frames from the same transmission source have the same speed, frame overtaking does not occur between frames from these same transmission sources, so there is no effect.
In the example shown in FIG. 6, in the switch # 01, a 10G mode frame is input at a transmission rate of 10 Gbps, and these 10G mode frames are output from a common output port # 4 having a fixed transmission rate of 100 Gbps. Although shown, the switch chip 100 also realizes data transfer other than these.

FIG. 13 and FIG. 14 are diagrams showing the operation as the next-stage switch of the switch 2 as an example of the embodiment. Note that the switch 2 shown in FIGS. 13 and 14 corresponds to the switch # 03 shown in FIG. In the switch # 03, the input port 20 and the output port 30 each operate as a 100 Gbps interface. In FIGS. 13 and 14, only a part of the plurality of input ports 20 and output ports 30 are shown for convenience.

In the case of the switch # 03, when the switch chip 100 outputs a 10G mode frame group input from one input port 20 at a transmission rate of 100 Gbps at a transmission rate of 100 Gbps from one output port 30, FIG. Thus, the input data group is transferred as it is by the CT method.
On the other hand, when the switch # 03 outputs 10G mode frames F1 to F6 input from one input port 20 at a transmission rate of 100 Gbps at three transmission ports 30 at a transmission rate of 100 Gbps, the switch # 03 As shown in FIG. 14, the chip 100 transfers back to the 10G mode frame at each output port 30.

FIG. 15 is a diagram illustrating the operation of the switch 2 as an example of the embodiment. Note that the switch 2 illustrated in FIG. 15 corresponds to the switch # 05 illustrated in FIG. However, in the example shown in FIG. 15, it is assumed that each of the three output ports 30 of the switch 2 outputs at a transmission rate of 10 Gbps.
In the switch # 05, the input port 20 operates as a 100 Gbps interface, and the plurality of output ports 30 each operate as a 10 Gbps interface. In FIG. 15, only a part of the plurality of input ports 20 and output ports 30 are shown for convenience.

In the example shown in FIG. 15, in the switch # 05, the switch chip 100 receives 10G mode frames F1 to F6 input at a transmission rate of 100 Gbps from one input port 20 from the three output ports 30 respectively. Output at the transmission speed.
(B) Operation The processing of the switch chip 100 in the network system 1 as an example of the embodiment configured as described above will be described with reference to FIG.

In the switch chip 100, for example, each input port 20 receives three 10G mode frames at a transmission rate of 100 Gbps and three 100G mode frames at a transmission rate of 100 Gbps.
The received six frames are transmitted after determining the order of transmission at the output port 30 of the output destination and performing processing such as multiplexing.

Hereinafter, in the switch chip 100, an example in which all of the input port 20 and the output port 30 are set to a transmission rate of 100 Gbps will be described.
At the input port 20, the frame parser 24 checks whether the frame received at 100 Gbps is a 100G mode frame or a 10G mode frame.

Here, in the edge switch 2 such as the switch # 01 shown in FIG. 2, the frame parser 24 uses, for example, a frame input to the input port 20 based on the interface speed determined at the time of link-up as a 100G mode frame. Or a 10G mode frame.
When data transmission rate information is included in the PR of the received frame, the frame parser 24 determines whether the frame is a 100G mode frame or a 10G mode frame based on the data transmission rate information. You may judge.

In the next-stage switch 2 such as the switches # 02 and # 03 shown in FIG. 2, the frame parser 24 refers to the data transmission rate information included in the PR of the received frame, so that the frame is in the 100G mode. Whether it is a frame or a 10G mode frame can be determined. Since PR data is not necessary as original information, transmission to the inside of the chip is unnecessary, but the speed information is transmitted from the MAC 23 to the frame parser 24.

Here, when the frame parser 24 recognizes the received frame as a 10G mode frame, only a portion where actual data exists is extracted and written to the shared memory 11 via the input buffer 25. In the case of a 100G mode frame, data is continuously stored in the shared memory 11 via the input buffer 25.
Further, at the same time as storing data in the shared memory 11, information such as a transmission destination necessary for transferring the data is sent to the frame / memory controller 12. The frame / memory controller 12 confirms the data and refers to the table 13 to determine from which output port 30 the data of the destination information is transmitted.

After determining the output port 30, the frame / memory controller 12 passes the information to the output port 30. Thereby, the output port 30 understands what data it should transmit.
The output port 30 determines which of the 10G mode frame and the 100G mode frame is to be transmitted according to any one of the frame selection algorithms of modes 1 to 3, and transmits the frame according to this determination.

Here, processing in the output port 30 of the switch chip 100 will be described. The output port 30 receives information about a frame transmitted from the frame / memory controller 12. Information (request information) received from the frame / memory controller 12 is sequentially stored in the request buffer 353.
The request selector 352 selects one of the modes 1 to 3 according to the set value of the mode register 356, and determines a request to be transmitted according to a frame selection algorithm corresponding to the selected mode.

Here, an example in which three 10G mode frame transmission requests and three 100G mode frame transmission requests are stored in the request buffer 353 will be described.
When transmitting a 10G mode frame, the request selector 352 and the request buffer 353 select the corresponding data, and extract the respective data from the shared memory 11 for each predetermined unit in order and multiplex them to the data buffer 354. Store. As a result, a mixed frame (see FIG. 8) is created in the data buffer 354.

At this time, the timing for storing data in the data buffer 354 is adjusted using a known method such as a frame editor. Thereafter, the data is sent to the MAC 33 and sent by the known method via the PCS 32 and the PMA / PMD 31.
Next, when transmitting a 100G mode frame, the request selector 352 and the request buffer 353 sequentially connect the three 100G mode frames one by one (see FIG. 9), and transmit them to the MAC 33.

In the example illustrated in FIG. 10, an example in which frames are output in the order of a 10G mode frame, a 100G mode frame, and a 10G mode frame is illustrated.
In the output port 30, if the data transmission rate information is not stored in the PR of the frame, the data transmission rate information is inserted into the PR of the frame in the MAC 33. For example, the MAC 33 determines the data transmission rate information based on information from which input port 20 the frame is received, and sets it to PR.

In the example described so far, in the switch chip 100, the input port 20 and the output port 30 are all described as having a speed of 100 Gbps. However, the present invention is not limited to this, and various modifications are made. be able to. When the speeds of the input port 20 and the output port 30 are different, they may be appropriately controlled so as to match the configuration and setting. That is, a mixed frame is created at the output port 30 in accordance with the speed difference between the frame input to the input port 20 and the frame output from the output port 30.

For example, when a frame (XG mode frame) created to pass through an XGbps transmission path is passed through a YGbps transmission path (where X <Y), (Y / X) frames are output at the output port 30. A mixed frame is created by mixing the XG mode frames. In this embodiment, the example of X = 10 and Y = 100 was shown.
Next, processing in the switch chip 100 will be described.

First, the switch chip 100 detects data reception by finding the PR of the input frame. In the MAC 23, when the frame data is 100 Gbps, the data is transferred as it is.
On the other hand, in the case of 10 Gbps frame data, when the data is input to the input buffer 25, the data is thinned out to 1/10 and transferred within the switch chip 100. At this time, the data is stored in the width of the internal bus and transferred. That is, transfer is performed with the usage rate of the internal bus of the normal switch chip 100 being 1/10.

Thereafter, the frame data is transferred to the shared memory 11. Data used for frame transfer such as DA is sent to the frame / memory controller 12. The frame / memory controller 12 determines an output port 30 to which data is transferred, and instructs writing to the shared memo 11. You are now ready to transfer data.
When the frame / memory controller 12 stores the data in the shared memory 11, it notifies the output buffer 30 of the request. The notified request is stored in the request buffer 353, and a request to be transmitted is determined by the request selector 352 and the timer 351 according to the frame selection algorithm described above.

The determined requests are sequentially read from the shared memory 11 and stored in the data buffer 354.
That is, the output port 30 reads data. At this time, since each input data is transferred to the output port 30 in the output port 30, many requests for output are accumulated in the output port 30 depending on the case.

In the output buffer 35, data is read from the shared memory 11 in accordance with an instruction from the request selector 352 and stored in the data buffer 354, thereby generating mixed data in the data buffer 354.
In the output port 30, when a 100G mode frame is output, one frame occupies the entire band. On the other hand, when a 10G mode frame is transmitted, a maximum of 10 frames are multiplexed and transmitted. In other words, the 10G mode frame is read at a cycle 10 times that of reading the 100G mode frame and stored in the data buffer 354.

Further, the request selector 352 reads the value of a register (not shown) and selects any one of modes 1 to 3 according to the value of this register. Then, the request selector 352 selects a frame to be transmitted in the request buffer 353 according to the selected mode.
The data stored in the data buffer 354 is transmitted to the MAC 33 as soon as a transmission port (not shown) is ready. At this time, when editing a frame, for example, setting data transmission speed information in the PR of the frame, the processing is performed using, for example, a frame editor.

Next, a frame transmission method in mode 1 by the output buffer 35 of the switch 2 as an example of the embodiment will be described according to the flowchart (steps S1 to S14) shown in FIG.
First, in step S1, the request selector 352 refers to, for example, the request buffer 353 and determines whether there is a request to be transmitted. If there is no request (refer to the NO route in step S1), step S1 is repeated to wait for a request.

When one or more requests exist (see YES route in step S1), in step S2, the request selector 352 determines whether or not there is a 100G mode frame transfer request (100G request: 100G Request). That is, it is confirmed whether 100G Request = 0.
If there is no 100G mode frame request (see YES route in step S2), in step S3, the oldest data in the 10G mode frame transfer request (10G request: 10Gbps Request) is transmitted to the MAC 33 for processing. finish.

When the process is completed in this flowchart, that is, when the transmission data is confirmed, the process returns to the start again to perform the process.
On the other hand, if a 100G request exists as data to be transmitted (see the NO route in step S2), then in step S4, the request selector 352 performs a 10G mode frame transfer request (10G request: 10G Request). Whether or not there is. That is, it is confirmed whether 10G Request = 0.

If there is no 10G mode frame request (see YES route in step S4), in step S5, the oldest data in the 100G mode frame transfer request (100G request: 100Gbps Request) is transmitted to the MAC 33, and the process is performed. finish.
On the other hand, if the 10G request exists as data to be transmitted (see NO route in step S4), then in step S6, there are one or more and 9 or less 10G requests, and one It is confirmed whether or not the above 100G request exists. That is, the operation is changed depending on the number of 10 requests and 100G requests.

When one or more and 9 or less 10G requests exist, and one or more 100G requests exist (see YES route in step S6), the request selector 352 selects the timer 351 in step S7. To check if it is running. Here, when the timer 351 is not counting time (see the NO route in step S7), the request selector 352 instructs the timer 351 to start timing in step S8. The timer 351 starts timing according to this instruction.

If the timer 351 has already been started and time is being measured (see YES route in step S7), the request selector 352 exceeds the predetermined time in the time measured by the timer 351 in step S9 (see FIG. Check if the timer is over. If timer over is not detected (see NO route in step S9), in step S11, the oldest data in the 100G request is transmitted to the MAC 33, and the process ends.

In addition, when it transfers to step S8 from step S7, since timer over does not arise even if it transfers to step S9, step S9 may be skipped and it may transfer to step S11 directly from step S8.
If timer over is detected (see YES route in step S9), in step S10, the oldest data in the 10G request is transmitted to the MAC 33 in order.
If the timer is over, a 10G mode frame is preferentially transmitted because the 10G request has been held for a long time. It is desirable that the value of the timer 351 can be set in a register in the switch chip that can be changed after hardware design. Thereafter, the process ends.

On the other hand, in step S6, when one or more and 9 or less 10G requests exist and the condition that one or more 100G requests exist (see the NO route in step S6), In step S12, it is confirmed whether there are 10 or more 10G requests and one or more 100G requests. If there are 10 or more 10G requests and one or more 100G requests (see YES route in step S12), either a 10G mode frame or a 100G mode frame is transmitted in step S13. Which frame is to be transmitted may be determined by hardware, or may be set by a register in the switch chip.

on the other hand. In step S12, if the condition that there are 10 or more 10G requests and one or more 100G requests is not satisfied (see the NO route in step S12), this is an abnormal state that is not possible.
Therefore, in step S14, the request selector 352 records a flag indicating that an error has occurred in an error flag set in a register area (not shown) in the switch chip 100, and ends the processing.

FIG. 17 is a flowchart (steps S1 to S5, S61, S7 to S9, S101, S111, S12 to S14) for explaining a frame transmission method in mode 2 by the output buffer 35 of the switch 2 as an example of the embodiment.
The flowchart shown in FIG. 17 includes S101 and S111 instead of S10 and S11 in the flowchart shown in FIG. In addition, since the step which attached | subjected the code | symbol same as the already-described code | symbol has shown the same process, the description is abbreviate | omitted.

In step S9, if timer over is not detected (see NO route in step S9), in step S111, the oldest data in the 10G request is transmitted to the MAC 33 in order, and the process is terminated. If a timer over is detected (see YES route in step S9), the oldest data in the 100G request is transmitted to the MAC 33 in step S101.

(C) Effect As described above, in the switch 2 as an example of the embodiment, when data input to the input port 20 is received, it is immediately transferred to the output port 30. Then, in this output port 30, a mixed frame obtained by mixing (multiplexing) the input 10 Gbps data is created and output from the output port 30 at a transmission rate of 100 Gbps.

At this time, the switch 2 performs data transfer by the CT method of sequentially outputting the received frame data without waiting for the output until all the data of the frame is completed.
As a result, it is not necessary to perform a data store that causes an increase in latency, and low latency and high throughput can be realized.

In addition, by transmitting a frame with a low speed (for example, 10G) with a gap on a transmission line with a high speed (for example, 100G), the time required for the data store required in the ST method can be reduced and the latency can be shortened. It is possible.
At this time, the low-speed reception data from the plurality of input ports 20 is inserted into the gaps by mixing (multiplexing) the low-speed reception data input from the plurality of input ports 20. Thus, data can be transmitted continuously without a gap.

For example, as illustrated in the above embodiment, when a 100 Gbps frame and a 10 Gbps frame are mixed as data input to the switch 2, the 100 Gbps frame uses 100% of the bandwidth of the 100 Gbps transmission path. Forward. On the other hand, a 10 Gbps frame is transferred utilizing a 10% bandwidth of a 100 Gbps transmission path. At 10 Gbps, only 10% of the bandwidth is used. Therefore, the data store that causes an increase in latency can be reduced by transferring the 10 Gbps frame with a maximum of 10 frames. The mixed frame is created by mixing (superposing) the frame data in a certain amount in the order of arrival in the output buffer 35.

In other words, when frames of a plurality of speeds are transferred in the switch 2, the frames can be efficiently transferred with low latency without lowering the throughput. This can be realized with lower latency while maintaining the above.
In the maximum transmission area that is the core of the network system 1, since the transfer is performed at the maximum speed of the switch chip 100, the setting of the network system 1 is simplified. Also, the same cable can be used in that area, and the cost for constructing the network system 1 can be reduced.

(D) Others The disclosed technique is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment. Each structure and each process of this embodiment can be selected as needed, or may be combined suitably.
For example, in the above-described embodiment, the data transmission rate information of the field “PR” in the 10G mode frame and the 100G mode frame is added by the MAC 33 of the switch 2 connected to the server 3 that is the data transmission source in the network system 1. ing. That is, although the speed mixing in the switch chip 100 of the switch 2 has been described, the present invention is not limited to this.

FIG. 18 is a diagram illustrating a first modification of the network system 1 including the switch 2 as an example of the embodiment.
In the network system 1 shown in FIG. 18, the data transmission rate information of the field “PR” in the 10G mode frame and the 100G mode frame is set in each server 3. That is, the server 3 also mixes speeds of 100 Gbps and 10 Gbps.

As a result, as shown in FIG. 18, the maximum speed transmission area a in the network system 1 can be widened, whereby the data flow in the network system 1 can be further optimized.
An output port (not shown) of the server (data output device) 3 has the same function as the output port 30 of the switch chip 100 described above. As a result, the server 3 generates a multiplexed frame by multiplexing frames of the first transmission rate (for example, 10 Gbps), and uses the multiplexed frame as a second transmission rate that is faster than the first transmission rate. The data can be output from a communication path that can be transmitted at (eg, 100 Gbps).

FIG. 19 is a diagram illustrating a second modification of the network system 1 including the switch 2 as an example of the embodiment.
In the above-described embodiment, the case where all the ports 20 and 30 have a speed of 100 G has been described. However, when the speeds of the input port and the output port are different, it may be controlled to match the configuration and setting.

The network system 1 shown in FIG. 19 includes a switch_0 (SW_0) instead of the switch # 04 in the network system 1 shown in FIG. The switch_0 supports only 10 Gbps, which is a low transmission rate, and includes a switch chip that does not support a transmission rate of 100 Gbps.
In this way, in the network system 1, it is possible to mix switches 2 that support only 10 Gbps, which is a low transmission rate. In such a network system 1, as shown in FIG. 19, the switch_0 is excluded from the maximum speed transmission area a, and the boundary with the maximum speed transmission area a is between SW_O and the SW group.

Further, the configuration of the network system 1 is not limited to the configuration illustrated in FIGS. 2, 18 and 19, and can be implemented with appropriate modifications. For example, the number of servers 3, edge switches 2, and next-stage switches 2 can be changed as appropriate.
Further, in the above-described embodiment and the modification, the two types of transmission rate frames, ie, the 10G mode frame and the 100G mode frame are exemplified, but the present invention is not limited to this. That is, it may be a frame with a transmission rate other than 10G or 100G, or a mixture of frames with three or more types of transmission rates.

Furthermore, in the above-described embodiment and modification, the request buffer 353 is provided in the output buffer 35, but is not limited thereto, and may be in the frame / memory controller 12, for example. Various modifications can be made.
In the above-described embodiments and modifications, the processor and the storage device are provided, and the processor executes the program stored in the storage device, thereby realizing the functions as the request selector 352 and the timer 351 described above. May be.

Further, according to the above-described disclosure, this embodiment can be implemented and manufactured by those skilled in the art.

1 Network system 2 Switch (data transfer device, data output device)
3 Server (data output device)
10 Control Unit 11 Shared Memory 12 Frame / Memory Controller 13 Table 20 Input Port 21, 31 PMA / PMD
22, 32 PCS
23,33 MAC
24 frame parser 25 input buffer 30 output port 35 output buffer 351 timer 352 request selector 353 request buffer 354 data buffer 355 AND circuit 356 mode register a maximum speed transmission area

Claims (20)

1. In a data transfer device that transfers data between a plurality of first communication paths and one or more second communication paths,
   The reception input from each of the plurality of first communication paths when the data transmission rate of the reception data input from each of the plurality of first communication paths is lower than the data transmission performance value of the second communication path. A mixed data creation unit that mixes data to create mixed data;
   A data transfer apparatus comprising: an output unit that outputs the mixed data created by the mixed data creation unit to the second communication path.
2. Based on the ratio of the data transmission performance value of the second communication path to the data transmission performance value of the first communication path, the mixed data creation unit mixes the received data of the number within the ratio to form one mixture The data transfer device according to claim 1, wherein the data transfer device is created as data.
3. A reading unit for reading data transmission rate information included in the received data input from each of the plurality of first communication paths;
   When the value of the data transmission rate information is lower than the data transmission performance value of the second communication path, the mixed data creation unit mixes reception data input from each of the plurality of first communication paths. 3. The data transfer apparatus according to claim 1, wherein mixed data is created.
4. Receiving multiple received data transmitted at different data transmission rates,
   4. The data transfer apparatus according to claim 1, wherein any one of the received data is preferentially processed according to the number of received data.
5. The data transfer apparatus according to any one of claims 1 to 4, wherein any one of the received data is preferentially processed according to each processing waiting time of the received data.
6. The data transfer according to any one of claims 1 to 5, wherein the output unit performs data transfer by a data non-retention output method in which data received from the first communication path is sequentially output. apparatus.
7. A data output device for outputting data to a communication path capable of transmitting a first frame having a first transmission rate and a second frame having a second transmission rate higher than the first transmission rate,
   A multiplexing processor for multiplexing the number of the first frames determined by dividing the second transmission rate by the first transmission rate to create a multiplexed frame;
   A data output device comprising: an output unit that outputs the multiplexed frame created by the multiplexing processing unit to the communication path.
8. The multiplexing processing unit includes:
   8. The data output device according to claim 7, wherein a frame to be output is divided into predetermined data units, and each divided data is multiplexed in order at a constant period.
9. The output unit outputs the multiplexed frame as the multiplexed frame to the communication path when outputting the first frame, and outputs the multiplexed frame without multiplexing when outputting the second frame. The data output device according to claim 7 or 8.
10. 10. The data output device according to claim 7, wherein the output data includes data transmission rate information indicating a transmission rate of the data.
11. A data transfer method in a data transfer device for transferring data between a plurality of first communication paths and one or more second communication paths,
    The reception input from each of the plurality of first communication paths when the data transmission rate of the reception data input from each of the plurality of first communication paths is lower than the data transmission performance value of the second communication path. Create mixed data by mixing data,
    A data transfer method, wherein the created mixed data is output to the second communication path.
12. Based on the ratio of the data transmission performance value of the second communication path to the data transmission performance value of the first communication path, a number of the received data within the ratio is mixed to create one mixed data. The data transfer method according to claim 11.
13. Read data transmission rate information included in the received data input from each of the plurality of first communication paths,
    When the value of the data transmission rate information is lower than the data transmission performance value of the second communication path, the reception data input from each of the plurality of first communication paths is mixed to create mixed data. 13. The data transfer method according to claim 11, wherein the data transfer method is a data transfer method.
14. Receiving multiple received data transmitted at different data transmission rates,
    The data transfer method according to any one of claims 11 to 13, wherein one of the received data is preferentially processed according to the number of received data.
15. 15. The data transfer method according to claim 11, wherein one of the received data is preferentially processed according to each processing waiting time of the received data.
16. The data transfer method according to any one of claims 11 to 15, wherein data transfer is performed by a data non-retention output method in which data received from the first communication path is sequentially output.
17. A data output method for outputting data to a communication path capable of transmitting a first frame of a first transmission rate and a second frame of a second transmission rate higher than the first transmission rate,
    A number of the first frames determined by dividing the second transmission rate by the first transmission rate to create a multiplexed frame;
    A data output method comprising: outputting the multiplexed frame created by the multiplexing processing unit to the communication path.
18. 18. The data output method according to claim 17, wherein a frame to be output is divided into predetermined data units, and each divided data is multiplexed in order at a constant period.
19. The output of the first frame as the multiplexed frame is output to the communication path, and the output of the second frame is performed without multiplexing when the second frame is output. The data output method described.
20. 20. The data output method according to claim 17, wherein the output data includes data transmission rate information indicating a transmission rate of the data.

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