WO2014208830A1 - Solar cell and manufacturing method therefor - Google Patents

Solar cell and manufacturing method therefor Download PDF

Info

Publication number
WO2014208830A1
WO2014208830A1 PCT/KR2013/010192 KR2013010192W WO2014208830A1 WO 2014208830 A1 WO2014208830 A1 WO 2014208830A1 KR 2013010192 W KR2013010192 W KR 2013010192W WO 2014208830 A1 WO2014208830 A1 WO 2014208830A1
Authority
WO
WIPO (PCT)
Prior art keywords
solar cell
pattern
type semiconductor
semiconductor layer
convex
Prior art date
Application number
PCT/KR2013/010192
Other languages
French (fr)
Korean (ko)
Inventor
김준동
김현엽
윤주형
Original Assignee
군산대학교산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 군산대학교산학협력단 filed Critical 군산대학교산학협력단
Publication of WO2014208830A1 publication Critical patent/WO2014208830A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035209—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures
    • H01L31/035227—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures the quantum structure being quantum wires, or nanorods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/035281—Shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a solar cell and a method for manufacturing the same, and more particularly to a solar cell and a method for manufacturing the same excellent in light efficiency and electrical characteristics.
  • Solar cells can be divided into solar cells that generate steam required to rotate turbines using solar heat and solar cells that convert sunlight into electrical energy using the properties of semiconductors.
  • solar cells photovoltaic cells
  • electrons of p-type semiconductors generated by absorbing light and holes in n-type semiconductors are converted into electrical energy are being actively conducted.
  • the solar cell has a structure of a p-n junction semiconductor layer composed of a p-type semiconductor layer and an n-type semiconductor layer between electrodes facing each other.
  • the solar cell may be classified into a silicon solar cell, a thin film solar cell, a dye-sensitized solar cell, an organic polymer solar cell, and the like according to the constituent materials thereof, and silicon solar cells are the mainstream.
  • a silicon solar cell it is very important to increase the conversion efficiency (Efficiency) related to the rate of converting incident sunlight into electrical energy.
  • the present invention is to provide a solar cell and a method of manufacturing the solar cell excellent in the conversion efficiency to overcome the above problems.
  • Solar cell according to an embodiment of the present invention for solving the above problems includes a substrate comprising a p-type semiconductor layer and an n-type semiconductor layer, the surface of the substrate includes a convex pattern having a specific period, The distance of the depletion layer from the center part of the said convex part pattern is 1 micrometer or less.
  • band gap energy which is an energy difference between a conduction band and a valence band of a material forming the semiconductor layer.
  • the generated free electrons and holes are called excess carriers, and the excess carriers are diffused by concentration differences in the conduction band or the valence band.
  • the excess carriers that is, electrons excited in the p-type semiconductor layer and holes made in the n-type semiconductor layer are defined as respective minority carriers, and carriers in the n-type or p-type semiconductor layer before the conventional bonding (that is, , p-type holes and n-type electrons) are defined as majority carriers.
  • the plurality of carriers are interrupted by the flow due to the energy barrier (energy barrier) due to the electric field, but electrons that are a minority carrier of the p-type semiconductor layer can move to the n-type semiconductor layer.
  • a potential difference occurs in the semiconductor layer due to diffusion of minority carriers, and the first and second electrodes positioned on both sides of the semiconductor layer are connected to an external circuit to utilize electromotive force, thereby providing the semiconductor layer. It will be used as a battery.
  • the energy absorption efficiency is improved by increasing the light absorption rate of the solar cell, thereby increasing the potential difference in the semiconductor layer.
  • the efficiency of a solar cell can be improved.
  • the solar cell of the present invention can increase the surface area of the incident surface of light by having the pattern structure as described above.
  • a space charge region may be formed on all surfaces except the lower surface.
  • the space charge region has a higher carrier collection probability than other regions in the semiconductor absorber. From an electrical point of view, the position of the space charge region can affect the collection length along the diameter, and in particular can regulate the photogenerated current and voltage.
  • the depletion layer formed on the surface (p-n junction surface) in contact with the p-type semiconductor and the n-type semiconductor may be 1 ⁇ m or less from the center of the convex pattern.
  • increasing the surface area may improve the solar cell characteristics, while the surface recombination effect may also result, which offsets the improved performance.
  • the depletion layer is formed at a position exceeding 1 ⁇ m from the center of the convex portion pattern, the surface recombination effect cannot be canceled out, which is not preferable.
  • the width of the convex pattern is not particularly limited as long as it is micro size, but may be, for example, in the range of 1 to 2 ⁇ m. If the width is less than 1 ⁇ m, the space of the p-type semiconductor layer is narrow to obtain desired efficiency and electrical properties. If the width is greater than 2 ⁇ m, the distance between the depletion layer and the center of the convex pattern becomes longer, thereby improving efficiency. It is not preferable because it may not be sufficient or a process disadvantage may occur to deeply form the depletion layer.
  • the shape of the convex pattern is also not particularly limited, but in order to obtain the same effect while increasing the surface area, a protrusion shape, a pyramid shape, a column shape having a plane on the upper surface, or a line in which the shapes extend in the uniaxial horizontal direction For example, the (line) form.
  • the average diameter of the protrusion or the pillar may be in the range of 1 to 2 ⁇ m, similarly to the width.
  • the thickness of the n-type semiconductor layer is not particularly limited as long as the position of the depletion layer is as described above, but may be, for example, in the range of 100 nm to 400 nm.
  • the height of the convex portion pattern may be in the range of 0.8 times to 1.2 times the width of the convex portion pattern, but is not limited thereto. Since it is preferable to form a pattern in a range where the movement distance of the light generating carrier generated inside is similar, it is preferable to set the height of the convex portion in the above range.
  • the period of the convex pattern refers to a cycle in which the convex pattern is repeatedly formed, and means a length obtained by adding a width of the pattern to an interval between inner surfaces of adjacent patterns. Therefore, the period of the convex portion pattern is larger than the width of the convex portion pattern. Specifically, the period of the convex portion pattern is in the range larger than the width of the convex portion pattern, it can be mentioned that the range of 2 to 10 ⁇ m, but is not limited to these. If the spacing between the convex portions is less than 2 ⁇ m, there is a problem in that the manufacturing process is difficult and the screening effect may occur between the patterns, which is not preferable.
  • the period of the convex portion pattern is preferably in the range of 2 to 6 ⁇ m in a range larger than the width of the convex portion pattern.
  • the solar cell of the present invention may further include a protective film layer in contact with an opposite surface of the p-n junction surface of the n-type semiconductor.
  • the protective layer not only protects the p-type and n-type semiconductor layers, but may also function as an anti-reflection film.
  • the protective layer may be formed of silicon nitride, but is not limited thereto.
  • the thickness of the protective layer may be in the range of 50 to 90 nm. When the thickness of the protective film layer is less than 50 nm, it may not be effective to protect the semiconductor layer, and when the thickness of the protective film layer is greater than 90 nm, the incident light utilization efficiency may be lowered, which is not preferable.
  • forming a pattern that is repeated at a specific cycle on at least one surface of the p-type semiconductor substrate, and forming an n-type semiconductor layer on the surface on which the pattern is formed include.
  • the patterning method is not particularly limited, but may be, for example, a photoresist method.
  • the n type doping method As a method of forming an n type semiconductor in the said patterned surface, the n type doping method is mentioned, for example.
  • an n-type doping source is heat-treated on a patterned p-type semiconductor to dope a surface with an n-type semiconductor.
  • the n-type doping source include compounds containing antimony (Sb), arsenic (As), phosphorus (P), and the like, and examples thereof include POCl 3 , but are not limited thereto.
  • the heat treatment may be performed for 30 minutes to 60 minutes in the 700 to 900 °C range, but is not limited to this range.
  • the heat treatment temperature and time can be adjusted in consideration of the type of material used, the doping concentration, the doping thickness, and the like.
  • the n-type semiconductor may be deposited in a separate layer.
  • the p-type semiconductor patterning needs to be more precise, and the p-type semiconductor patterning needs to be uniformly deposited on the side portions of the convex patterning.
  • the solar cell manufacturing method of the present invention may further include forming a protective film on the n-type semiconductor layer.
  • the protective film may be used as long as it protects the p-type and n-type semiconductor layers and does not seriously affect the performance of the solar cell.
  • the protective layer may be silicon nitride, silicon oxide (SiO x ), MgF 2 , MgO, Al 2 O 3 and the like. In some cases, the protective film may also serve as an antireflection film.
  • the present invention provides a solar cell excellent in conversion efficiency and excellent electrical characteristics and a method of manufacturing the same.
  • FIG. 1 is a schematic perspective view of a convex portion of a solar cell according to an embodiment of the present invention.
  • FIG. 2 shows a microscope image of a patterned semiconductor layer in accordance with Example 1 of the present invention.
  • FIG. 3 shows a microscope image of a patterned semiconductor layer in accordance with Example 2 of the present invention.
  • first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the technical spirit of the present invention.
  • spatially relative terms below “, “ beneath “, “ lower”, “ above “, “ upper” It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as “below or beneath” of another device may be placed “above” of another device. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be oriented in other directions as well, in which case spatially relative terms may be interpreted according to orientation.
  • FIG. 1 is a schematic perspective view of a convex portion 100 of a solar cell according to an embodiment of the present invention.
  • a p-type semiconductor 10 is positioned at a deep portion, an n-type semiconductor 30 is surrounded by the p-type semiconductor 10, and the p-type semiconductor
  • the depletion layer 20 is formed at the interface between the 10 and the n-type semiconductor 30.
  • the protective film layer 40 surrounds the n-type semiconductor 30.
  • pn junction occurs not only in the upper portion y of the convex portion 100 but also in the side portion x, so that the space charge region (depletion layer) 20 is formed in the convex portion. It may be formed on all surfaces except the lower surface of the (100).
  • the photo-generating carrier 50 When the solar cell receives sunlight, the photo-generating carrier 50 is generated at the center of the p-type semiconductor, and the photo-generating carrier 50 moves not only through the upper side y of the convex part 100 but also through the side surface x. As a result, the overall travel distance can be shortened, so that high light efficiency and electrical characteristics can be improved.
  • a PR pattern was formed on the silicon substrate to serve as a protective mask during etching.
  • C 4 F 8 gas was added to form a polymer coated film, and the silicon substrate without the PR mask and the PR mask was etched with SF 6 plasma.
  • a pillar-shaped pattern having an average width of 2 m and a height of 2 m and a period of 7 m was formed.
  • the columnar silicon wafer was doped by heating at 800 ° C. for 40 minutes in a furnace using POCl 3 as an n-type dopant.
  • 5% HF buffer was used to remove the phosphosilicate glass (PSG).
  • PSG phosphosilicate glass
  • PECVD plasma-enhanced chemical vapor deposition
  • a pn junction semiconductor layer was manufactured in the same manner as in Example 1, except that the photoresist was used to form a pillar-shaped pattern having an average diameter of 2 ⁇ m, a height of 2 ⁇ m, and a spacing of 4 ⁇ m. The photograph observed with is shown in FIG.
  • a p-n junction semiconductor layer was manufactured in the same manner as in Example 1, except that no pattern was formed.
  • First and second electrodes were formed on both surfaces of the semiconductor layers of Examples 1 to 2 and Comparative Example 1 to manufacture solar cells, respectively. Then, the solar cell performance test for each solar cell and the results are shown in Table 1 together with the structure of each solar cell.
  • the efficiency of the solar cells of Examples 1 and 2 having a columnar pattern of 2 ⁇ m diameter shows higher photoelectric efficiency than the solar cell of Comparative Example 1 having no pattern as described above. This is because, as the moving distance of the light generating carriers is shortened, the number of moving carriers increases, and the surface area increases, so that the incident light is relatively received. In addition, it can be confirmed that the generated voltage and current are also higher in the solar cells of Examples 1 and 2 than the solar cell of Comparative Example 1. This allows the light generating carrier to move from the convex portion not only to the upper surface but also to the side surface, thereby increasing the moving efficiency and increasing the voltage and current.

Abstract

The present invention relates to a solar cell and a manufacturing method therefor. The solar cell of the present invention comprises: a substrate which includes a p-type semiconductor layer and an n-type semiconductor layer, wherein the surface of the substrate includes a pattern of convex parts having specific intervals, and the distance from the center portion of the pattern of convex parts to a depletion layer is 1 ㎛ or less. Furthermore, the solar cell of the present invention has excellent optical efficiency and electrical properties.

Description

태양전지 및 그 제조방법Solar cell and manufacturing method
본 발명은 태양전지 및 그 제조방법에 관한 것으로, 보다 구체적으로는 광효율 및 전기적 특성이 우수한 태양전지 및 그 제조방법에 관한 것이다.The present invention relates to a solar cell and a method for manufacturing the same, and more particularly to a solar cell and a method for manufacturing the same excellent in light efficiency and electrical characteristics.
최근 환경문제와 에너지 고갈에 대한 관심이 높이지면서, 에너지 자원이 풍부하고 환경오염에 대한 문제점이 없으며 에너지 효율이 높은 대체 에너지로서의 태양전지에 대한 관심이 높아지고 있다.Recently, as interest in environmental problems and energy depletion has increased, there is a growing interest in solar cells as an alternative energy with abundant energy resources, no problems with environmental pollution, and high energy efficiency.
태양전지는 태양열을 이용하여 터빈을 회전시키는데 필요한 증기를 발생시키는 태양열전지와 반도체의 성질을 이용하여 태양빛을 전기에너지로 변환시키는 태양광 전지로 나눌 수 있다. Solar cells can be divided into solar cells that generate steam required to rotate turbines using solar heat and solar cells that convert sunlight into electrical energy using the properties of semiconductors.
그 중에서도 빛을 흡수하여 생성된 p-형 반도체의 전자와 n-형 반도체의 정공이 전기에너지로 변환하는 태양광 전지(이하, 태양전지라 함)에 대한 연구가 활발히 진행되고 있다.Among them, researches on photovoltaic cells (hereinafter referred to as solar cells) in which electrons of p-type semiconductors generated by absorbing light and holes in n-type semiconductors are converted into electrical energy are being actively conducted.
태양전지는 서로 마주하는 전극 사이에 p형 반도체층과 n형 반도체층으로 구성된 p-n 접합 반도체층의 구조로서 이루어지고 있다.The solar cell has a structure of a p-n junction semiconductor layer composed of a p-type semiconductor layer and an n-type semiconductor layer between electrodes facing each other.
이러한 태양전지를 태양광 등의 광원에 노출하면, n형 반도체층과 p형 반도체층을 가로질러 전류가 흐르게 되는 광기전력 효과(photovoltaic effect)에 의해 기전력이 발생한다.When such a solar cell is exposed to a light source such as sunlight, electromotive force is generated by a photovoltaic effect in which current flows across the n-type semiconductor layer and the p-type semiconductor layer.
상기 태양전지는 그 구성 물질에 따라서 실리콘 태양전지, 박막형 태양전지, 염료감응형 태양전지 및 유기고분자형 태양전지 등으로 구분될 수 있으며, 그 중 실리콘 태양전지가 주류를 이루고 있다. 이러한 태양전지에서는, 입사되는 태양광을 전기 에너지로 변환시키는 비율과 관계된 변환효율(Efficiency)을 높이는 것이 매우 중요하다.The solar cell may be classified into a silicon solar cell, a thin film solar cell, a dye-sensitized solar cell, an organic polymer solar cell, and the like according to the constituent materials thereof, and silicon solar cells are the mainstream. In such a solar cell, it is very important to increase the conversion efficiency (Efficiency) related to the rate of converting incident sunlight into electrical energy.
본 발명은, 상기와 같은 문제점들을 극복하고 변환효율이 우수한 태양전지 및 상기 태양전지를 제조하는 방법을 제공하는 것이다.The present invention is to provide a solar cell and a method of manufacturing the solar cell excellent in the conversion efficiency to overcome the above problems.
본 발명이 해결하고자 하는 과제들은 이상에서 언급한 과제들로 제한되지 않으며, 언급되지 않은 또 다른 과제들은 아래의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.
상기 과제를 해결하기 위한 본 발명의 일 실시예에 따른 태양전지는 p형 반도체층 및 n형 반도체층을 포함하는 기판을 포함하고, 상기 기판의 표면은 특정 주기를 가지는 볼록부 패턴을 포함하며, 상기 볼록부 패턴의 중심부로부터 공핍층의 거리가 1 ㎛ 이하이다.Solar cell according to an embodiment of the present invention for solving the above problems includes a substrate comprising a p-type semiconductor layer and an n-type semiconductor layer, the surface of the substrate includes a convex pattern having a specific period, The distance of the depletion layer from the center part of the said convex part pattern is 1 micrometer or less.
태양전지는 상기 반도체층들 내에서 전자들이 비대칭적으로 존재하는데, 열적 평형상태에서 n형 반도체층과 p형 반도체층의 접합으로 이루어진 반도체층 내에서는 캐리어의 농도 구배에 의한 확산으로 전하의 불균형이 생기고, 이로 인해 전기장(electric field)이 형성된다.In the solar cell, electrons are asymmetrically present in the semiconductor layers, and in the thermal equilibrium, in the semiconductor layer formed by the junction of the n-type semiconductor layer and the p-type semiconductor layer, the imbalance of charge is caused by diffusion due to the concentration gradient of the carrier. Resulting in the formation of an electric field.
이에, 반도체층 내부로, 반도체층을 이루는 물질의 전도대(conduction band)와 가전자대(valence band) 사이의 에너지 차이인 밴드갭 에너지(band gap energy)보다 큰 에너지를 갖는 빛이 조사되었을 경우, 빛 에너지를 받은 전자들은 가전자대에서 전도대로 여기(excite)되며, 전도대로 여기된 전자들은 자유롭게 이동할 수 있게 된다.Accordingly, when light having a larger energy than band gap energy, which is an energy difference between a conduction band and a valence band of a material forming the semiconductor layer, is irradiated into the semiconductor layer, The energized electrons are excited at the valence band to the conduction band, and the electrons excited at the conduction band are free to move.
또한, 가전자대에는 전자들이 빠져나간 자리에 정공이 생성된다.In the valence band, holes are generated where electrons escape.
이렇게 생성된 자유전자와 정공을 과잉(excess) 캐리어라고 하며, 과잉 캐리어들은 전도대 또는 가전자대 내에서 농도 차이에 의해서 확산하게 된다.The generated free electrons and holes are called excess carriers, and the excess carriers are diffused by concentration differences in the conduction band or the valence band.
이때, 과잉 캐리어, 즉 p형 반도체층에서 여기된 전자들과 n형 반도체층에서 만들어진 정공을 각각의 소수 캐리어(minority carrier)라 정의하며, 기존 접합 전의 n형 또는 p형 반도체층 내의 캐리어(즉, p형의 정공 및 n형의 전자)는 이와 구분해 다수 캐리어(majority carrier)라 정의된다.In this case, the excess carriers, that is, electrons excited in the p-type semiconductor layer and holes made in the n-type semiconductor layer are defined as respective minority carriers, and carriers in the n-type or p-type semiconductor layer before the conventional bonding (that is, , p-type holes and n-type electrons) are defined as majority carriers.
이때, 다수 캐리어들은 전기장으로 인한 에너지 장벽(energy barrier) 때문에 흐름의 방해를 받지만, p형 반도체층의 소수 캐리어인 전자는 n형 반도체층으로 이동할 수 있게 된다.At this time, the plurality of carriers are interrupted by the flow due to the energy barrier (energy barrier) due to the electric field, but electrons that are a minority carrier of the p-type semiconductor layer can move to the n-type semiconductor layer.
따라서, 소수 캐리어의 확산에 의해 반도체층 내부에 전압차(potential difference)가 생기게 되며, 반도체층 양측에 위치하는 제1 전극 및 제2 전극을 외부 회로에 연결하여 기전력을 활용함으로써, 상기 반도체층을 전지로서 사용하게 된다.Accordingly, a potential difference occurs in the semiconductor layer due to diffusion of minority carriers, and the first and second electrodes positioned on both sides of the semiconductor layer are connected to an external circuit to utilize electromotive force, thereby providing the semiconductor layer. It will be used as a battery.
이에, 태양전지 내부로 많은 광이 입사되고, 입사된 광의 경로를 향상시키게 되면, 태양전지의 광 흡수율을 높이게 됨으로써 에너지 변환효율이 향상되고, 이를 통해 반도체층 내부의 전압차(potential difference)가 더욱 커지게 됨으로써, 태양전지의 효율을 향상시킬 수 있는 것이다.Therefore, when a lot of light is incident into the solar cell and the path of the incident light is improved, the energy absorption efficiency is improved by increasing the light absorption rate of the solar cell, thereby increasing the potential difference in the semiconductor layer. By becoming large, the efficiency of a solar cell can be improved.
본 발명의 태양전지는, 상기와 같은 패턴 구조를 가짐으로써, 빛의 입사면의 표면적을 증가시킬 수 있다. 또한, 상기 볼록부의 상부뿐만 아니라 측면부에서도 p-n 접합이 발생하므로, 공간 전하 영역(space charge region)이 하면을 제외한 모든 면에 형성될 수 있다.The solar cell of the present invention can increase the surface area of the incident surface of light by having the pattern structure as described above. In addition, since the p-n junction occurs not only on the upper portion of the convex portion but also on the side portion, a space charge region may be formed on all surfaces except the lower surface.
상기 공간 전하 영역은 반도체 흡수체(absorber)에서 다른 영역 보다 더 높은 캐리어 수집 확률을 가진다. 전기적 관점에서, 공간 전하 영역의 위치는 직경에 따른 수집 길이에 영향을 미칠 수 있고, 특히 광발생 전류 및 전압을 조절할 수 있다.The space charge region has a higher carrier collection probability than other regions in the semiconductor absorber. From an electrical point of view, the position of the space charge region can affect the collection length along the diameter, and in particular can regulate the photogenerated current and voltage.
상기 볼록부 내부의 광발생 캐리어의 이동 거리가 짧을수록, 즉 상기 볼록부 패턴의 중심부로부터 거리가 짧을수록 광효율 및 전기적 특성을 향상시킬 수 있다.The shorter the moving distance of the light generating carrier inside the convex portion, that is, the shorter the distance from the center of the convex portion pattern, the better the light efficiency and electrical characteristics.
하나의 예에서, 상기 p형 반도체와 n형 반도체가 접하는 면(p-n 접합면)에서 형성되는 공핍층은 상기 볼록부 패턴의 중심부로부터 거리가 1 ㎛ 이하일 수 있다. In one example, the depletion layer formed on the surface (p-n junction surface) in contact with the p-type semiconductor and the n-type semiconductor may be 1 ㎛ or less from the center of the convex pattern.
상기에서 설명한 바와 같이, 표면적이 증가하면 태양전지 특성을 향상시킬 수 있지만, 반면에 이로 인하여 향상된 성능을 상쇄시키는 표면 재결합 효과도 나타날 수 있다.As described above, increasing the surface area may improve the solar cell characteristics, while the surface recombination effect may also result, which offsets the improved performance.
상기 공핍층이 볼록부 패턴의 중심부로부터 1 ㎛를 초과하는 위치에 형성될 경우에는, 상기 표면 재결합 효과를 상쇄시킬 수 없어 바람직하지 않다.When the depletion layer is formed at a position exceeding 1 μm from the center of the convex portion pattern, the surface recombination effect cannot be canceled out, which is not preferable.
상기 볼록부 패턴의 폭은 마이크로 사이즈이면 특별히 한정되는 것은 아니지만, 예를 들어, 1 내지 2 ㎛ 범위일 수 있다. 상기 너비가 1 ㎛ 미만인 경우에는 p형 반도체층의 공간이 협소하여 소망하는 효율 및 전기적 특성을 얻기 힘들고, 2 ㎛ 초과인 경우에는 공핍층과 볼록부 패턴의 중심부의 거리가 길어지므로 효율 향상 효과가 충분하지 않거나, 공핍층을 깊이 형성하기 위하여 공정상 불이익이 발생할 수 있어 바람직하지 않다.The width of the convex pattern is not particularly limited as long as it is micro size, but may be, for example, in the range of 1 to 2 μm. If the width is less than 1 μm, the space of the p-type semiconductor layer is narrow to obtain desired efficiency and electrical properties. If the width is greater than 2 μm, the distance between the depletion layer and the center of the convex pattern becomes longer, thereby improving efficiency. It is not preferable because it may not be sufficient or a process disadvantage may occur to deeply form the depletion layer.
상기 볼록부 패턴의 형상 역시 특별히 한정되지는 않지만, 표면적을 증가시키면서 상기와 같은 효과를 얻기 위하여, 돌기 형태, 피라미드 형태, 상면에 평면을 가지는 기둥 형태 또는 상기 형태들이 일축 수평 방향으로 연장되어 있는 라인(line) 형태인 것을 예로 들 수 있다.The shape of the convex pattern is also not particularly limited, but in order to obtain the same effect while increasing the surface area, a protrusion shape, a pyramid shape, a column shape having a plane on the upper surface, or a line in which the shapes extend in the uniaxial horizontal direction For example, the (line) form.
상기 볼록부의 형상이 돌기 형태 또는 기둥 형태인 경우에 상기 돌기 또는 기둥의 평균 직경은 상기 너비와 마찬가지로 1 내지 2 ㎛ 범위일 수 있다.When the convex portion is in the form of a protrusion or a pillar, the average diameter of the protrusion or the pillar may be in the range of 1 to 2 μm, similarly to the width.
상기 n형 반도체층의 두께는 공핍층의 위치를 상기와 같도록 하는 범위이면 특별히 한정되는 것은 아니지만, 예를 들어, 100 nm 내지 400 nm 범위일 수 있다.The thickness of the n-type semiconductor layer is not particularly limited as long as the position of the depletion layer is as described above, but may be, for example, in the range of 100 nm to 400 nm.
상기 볼록부 패턴의 높이는 상기 볼록부 패턴의 폭 대비 0.8배 내지 1.2배 범위인 것을 들 수 있지만 이것으로 한정되는 것은 아니다. 내부에서 발생된 광발생 캐리어의 이동거리가 유사한 범위로 패턴을 형성하는 것이 바람직하므로, 상기 범위에서 상기 볼록부의 높이를 설정하는 것이 바람직하다.The height of the convex portion pattern may be in the range of 0.8 times to 1.2 times the width of the convex portion pattern, but is not limited thereto. Since it is preferable to form a pattern in a range where the movement distance of the light generating carrier generated inside is similar, it is preferable to set the height of the convex portion in the above range.
상기 볼록부 패턴의 주기는 상기 볼록부 패턴이 반복 형성되는 사이클(cycle)을 의미하는 것으로, 인접하는 패턴들의 내측 면 사이의 간격에 패턴의 폭을 합한 길이를 의미한다. 따라서, 상기 볼록부 패턴의 주기는 상기 볼록부 패턴의 폭 보다 크다. 구체적으로 상기 볼록부 패턴의 주기는 상기 볼록부 패턴의 폭 보다 큰 범위에서, 2 내지 10 ㎛ 범위인 것을 들 수 있지만, 이들만으로 한정되는 것은 아니다. 상기 볼록부 사이의 간격이 2 ㎛ 미만인 경우에는 제조 공정이 어려운 문제가 있고 패턴 사이에 가리움 효과가 발생할 수 있어 바람직하지 않고, 10 ㎛ 초과인 경우에는 상기 패턴이 너무 드물게 분포되어 있어 효율 향상 효과가 미미하여 바람직하지 않다. 상기와 같은 이유로, 상기 볼록부 패턴의 주기는 상기 볼록부 패턴의 폭보다 큰 범위에서, 2 내지 6 ㎛ 범위인 것이 바람직하다.The period of the convex pattern refers to a cycle in which the convex pattern is repeatedly formed, and means a length obtained by adding a width of the pattern to an interval between inner surfaces of adjacent patterns. Therefore, the period of the convex portion pattern is larger than the width of the convex portion pattern. Specifically, the period of the convex portion pattern is in the range larger than the width of the convex portion pattern, it can be mentioned that the range of 2 to 10 ㎛, but is not limited to these. If the spacing between the convex portions is less than 2 μm, there is a problem in that the manufacturing process is difficult and the screening effect may occur between the patterns, which is not preferable. In the case of more than 10 μm, the pattern is distributed very rarely, resulting in an efficiency improvement effect. It is insignificant and undesirable For the same reason as above, the period of the convex portion pattern is preferably in the range of 2 to 6 μm in a range larger than the width of the convex portion pattern.
본 발명의 태양전지는 상기 n형 반도체의 p-n 접합면의 반대 면에 접하는 보호막층을 더 포함할 수 있다. 상기 보호막층은 상기 p형 및 n형 반도체층을 보호하는 역할뿐만 아니라, 반사 방지막으로서의 기능도 수행할 수 있다. 상기 보호막층은 질화 실리콘으로 형성될 수 있으나 이것만으로 한정되는 것은 아니다. 또한, 상기 보호막층의 두께는 50 내지 90 nm 범위일 수 있다. 상기 보호막층의 두께가 50 nm 미만인 경우에는 반도체층 보호 역할을 효과적으로 발휘하지 못할 수 있고, 90 nm 초과인 경우에는 입사광 이용 효율을 저하시킬 수 있어 바람직하지 않다.The solar cell of the present invention may further include a protective film layer in contact with an opposite surface of the p-n junction surface of the n-type semiconductor. The protective layer not only protects the p-type and n-type semiconductor layers, but may also function as an anti-reflection film. The protective layer may be formed of silicon nitride, but is not limited thereto. In addition, the thickness of the protective layer may be in the range of 50 to 90 nm. When the thickness of the protective film layer is less than 50 nm, it may not be effective to protect the semiconductor layer, and when the thickness of the protective film layer is greater than 90 nm, the incident light utilization efficiency may be lowered, which is not preferable.
본 발명의 하나의 실시예에 따른 태양전지의 제조방법은, p형 반도체 기판의 적어도 일면에 특정 주기로 반복되는 패턴을 형성하는 단계, 및 상기 패턴이 형성된 면에 n형 반도체층을 형성하는 단계를 포함한다.In the solar cell manufacturing method according to an embodiment of the present invention, forming a pattern that is repeated at a specific cycle on at least one surface of the p-type semiconductor substrate, and forming an n-type semiconductor layer on the surface on which the pattern is formed Include.
상기 패터닝하는 방법은 특별히 한정되지는 않지만, 예를 들어, 포토레지스트법으로 이루어질 수 있다.The patterning method is not particularly limited, but may be, for example, a photoresist method.
상기 패터닝된 면에 n형 반도체를 형성하는 방법으로는, 예를 들어, n형 도핑법을 들 수 있다. 상기 n형 도핑법은 상기와 같이 패턴이 형성된 p형 반도체에 n형 도핑 소스를 열처리하여 표면을 n형 반도체로 도핑시키는 것이다. 상기 n형 도핑 소스는 안티몬(Sb), 비소(As), 인(P) 등을 포함하는 화합물을 들 수 있고, 예를 들어 POCl3를 들 수 있지만 이것만으로 한정되는 것은 아니다.As a method of forming an n type semiconductor in the said patterned surface, the n type doping method is mentioned, for example. In the n-type doping method, an n-type doping source is heat-treated on a patterned p-type semiconductor to dope a surface with an n-type semiconductor. Examples of the n-type doping source include compounds containing antimony (Sb), arsenic (As), phosphorus (P), and the like, and examples thereof include POCl 3 , but are not limited thereto.
상기 열처리는 700 ℃ 내지 900 ℃ 범위에서 30분 내지 60분 동안 이루어질 수 있으나, 이 범위만으로 한정되는 것은 아니다. 사용되는 물질의 종류, 도핑 농도, 도핑 두께 등을 고려하여 열처리 온도 및 시간을 조절할 수 있음은 물론이다.The heat treatment may be performed for 30 minutes to 60 minutes in the 700 to 900 ℃ range, but is not limited to this range. Of course, the heat treatment temperature and time can be adjusted in consideration of the type of material used, the doping concentration, the doping thickness, and the like.
또한, n형 반도체를 별도의 층으로 증착시킬 수도 있다. 다만, 이 경우에는 p형 반도체 패터닝을 더욱 정밀하게 해야할 필요가 있고, 상기 볼록부 패터닝의 측면부에도 균일하게 증착될 수 있도록 해야한다.In addition, the n-type semiconductor may be deposited in a separate layer. In this case, however, the p-type semiconductor patterning needs to be more precise, and the p-type semiconductor patterning needs to be uniformly deposited on the side portions of the convex patterning.
본 발명의 태양전지 제조방법은, 상기 n형 반도체층 상에 보호막을 형성하는 단계를 추가로 포함할 수 있다. 상기 보호막은 p형 및 n형 반도체층을 보호하고, 태양전지의 성능에 심각한 악영향을 주지 않는 물질이면 어느 것이나 사용이 가능하다. 하나의 바람직한 예로는, 상기 보호막층은 질화 실리콘, 실리콘 산화물(SiOx), MgF2, MgO, Al2O3 등을 들 수 있다. 또한, 경우에 따라, 상기 보호막은 반사 방지막으로서의 역할도 할 수 있다.The solar cell manufacturing method of the present invention may further include forming a protective film on the n-type semiconductor layer. The protective film may be used as long as it protects the p-type and n-type semiconductor layers and does not seriously affect the performance of the solar cell. As a preferred example, the protective layer may be silicon nitride, silicon oxide (SiO x ), MgF 2 , MgO, Al 2 O 3 and the like. In some cases, the protective film may also serve as an antireflection film.
본 발명은 변환효율이 우수하고, 전기적 특성이 뛰어난 태양전지 및 이의 제조방법을 제공한다.The present invention provides a solar cell excellent in conversion efficiency and excellent electrical characteristics and a method of manufacturing the same.
도 1은 본 발명의 일 실시예에 따른 태양전지의 볼록부의 개략적인 투시도이다.1 is a schematic perspective view of a convex portion of a solar cell according to an embodiment of the present invention.
도 2는 본 발명의 실시예 1에 따른 패턴화된 반도체층에 대한 현미경 이미지를 도시한 도면이다.FIG. 2 shows a microscope image of a patterned semiconductor layer in accordance with Example 1 of the present invention.
도 3은 본 발명의 실시예 2에 따른 패턴화된 반도체층에 대한 현미경 이미지를 도시한 도면이다.FIG. 3 shows a microscope image of a patterned semiconductor layer in accordance with Example 2 of the present invention.
본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다.Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.
비록 제1, 제2 등이 다양한 소자, 구성요소 및/또는 섹션들을 서술하기 위해서 사용되나, 이들 소자, 구성요소 및/또는 섹션들은 이들 용어에 의해 제한되지 않음은 물론이다. 이들 용어들은 단지 하나의 소자, 구성요소 또는 섹션들을 다른 소자, 구성요소 또는 섹션들과 구별하기 위하여 사용하는 것이다. 따라서, 이하에서 언급되는 제1 소자, 제1 구성요소 또는 제1 섹션은 본 발명의 기술적 사상 내에서 제2 소자, 제2 구성요소 또는 제2 섹션일 수도 있음은 물론이다.Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the technical spirit of the present invention.
소자(elements) 또는 층이 다른 소자 또는 층의 "위(on)" 또는 "상(on)"으로 지칭되는 것은 다른 소자 또는 층의 바로 위뿐만 아니라 중간에 다른 층 또는 다른 소자를 개재한 경우를 모두 포함한다. 반면, 소자가 "직접 위(directly on)" 또는 "바로 위"로 지칭되는 것은 중간에 다른 소자 또는 층을 개재하지 않은 것을 나타낸다.When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between. It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that no device or layer is intervened in the middle.
공간적으로 상대적인 용어인 "아래(below)", "아래(beneath)", "하부(lower)", "위(above)", "상부(upper)" 등은 도면에 도시되어 있는 바와 같이 하나의 소자 또는 구성 요소들과 다른 소자 또는 구성 요소들과의 상관관계를 용이하게 기술하기 위해 사용될 수 있다. 공간적으로 상대적인 용어는 도면에 도시되어 있는 방향에 더하여 사용시 또는 동작시 소자의 서로 다른 방향을 포함하는 용어로 이해되어야 한다. 예를 들면, 도면에 도시되어 있는 소자를 뒤집을 경우, 다른 소자의 "아래(below 또는 beneath)"로 기술된 소자는 다른 소자의 "위(above)"에 놓여질 수 있다. 따라서, 예시적인 용어인 "아래"는 아래와 위의 방향을 모두 포함할 수 있다. 소자는 다른 방향으로도 배향될 수 있으며, 이 경우 공간적으로 상대적인 용어들은 배향에 따라 해석될 수 있다.The spatially relative terms " below ", " beneath ", " lower ", " above ", " upper " It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as "below or beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be oriented in other directions as well, in which case spatially relative terms may be interpreted according to orientation.
본 명세서에서 사용된 용어는 실시예들을 설명하기 위한 것이며 본 발명을 제한하고자 하는 것은 아니다. 본 명세서에서, 단수형은 문구에서 특별히 언급하지 않는 한 복수형도 포함한다. 명세서에서 사용되는 "포함한다(comprises)" 및/또는 "포함하는(comprising)"은 언급된 구성요소, 단계, 동작 및/또는 소자는 하나 이상의 다른 구성요소, 단계, 동작 및/또는 소자의 존재 또는 추가를 배제하지 않는다.The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.
다른 정의가 없다면, 본 명세서에서 사용되는 모든 용어(기술 및 과학적 용어를 포함)는 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 공통적으로 이해될 수 있는 의미로 사용될 수 있을 것이다. 또 일반적으로 사용되는 사전에 정의되어 있는 용어들은 명백하게 특별히 정의되어 있지 않는 한 이상적으로 또는 과도하게 해석되지 않는다. Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.
이하, 본 발명의 일 실시예에 따른 볼록부 패턴을 도 1을 참조하여 설명한다.Hereinafter, a convex portion pattern according to an embodiment of the present invention will be described with reference to FIG. 1.
도 1은 본 발명의 일 실시예에 따른 태양전지의 볼록부(100)의 개략적인 투시도이다. 도 1에 도시한 바와 같이, 태양전지의 볼록부(100)은 p형 반도체(10)이 심부에 위치하고, 상기 p형 반도체(10)을 n형 반도체(30)이 둘러싸고 있으며, 상기 p형 반도체(10)과 n형 반도체(30)의 계면에 공핍층(20)이 형성된다. 또한, 상기 n형 반도체(30)을 보호막층(40)이 둘러싸고 있는 구성으로 이루어져 있다.1 is a schematic perspective view of a convex portion 100 of a solar cell according to an embodiment of the present invention. As shown in FIG. 1, in the convex portion 100 of the solar cell, a p-type semiconductor 10 is positioned at a deep portion, an n-type semiconductor 30 is surrounded by the p-type semiconductor 10, and the p-type semiconductor The depletion layer 20 is formed at the interface between the 10 and the n-type semiconductor 30. In addition, the protective film layer 40 surrounds the n-type semiconductor 30.
상기 태양전지의 볼록부(100)으로 인하여, 상기 볼록부(100)의 상부(y)뿐만 아니라 측면부(x)에서도 p-n 접합이 발생하므로, 공간 전하 영역(공핍층)(20)이 상기 볼록부(100)의 하면을 제외한 모든 면에 형성될 수 있다.Due to the convex portion 100 of the solar cell, pn junction occurs not only in the upper portion y of the convex portion 100 but also in the side portion x, so that the space charge region (depletion layer) 20 is formed in the convex portion. It may be formed on all surfaces except the lower surface of the (100).
태양전지가 태양광을 받으면, p형 반도체 중심부에서 광발생 캐리어(50)이 발생하고, 상기 볼록부(100)의 상부(y)뿐만 아니라 측면(x)를 통해서도 광발생 캐리어(50)이 이동할 수 있으므로, 전체 이동 거리가 짧아지므로 높은 광효율 및 전기적 특성을 향상시킬 수 있다.When the solar cell receives sunlight, the photo-generating carrier 50 is generated at the center of the p-type semiconductor, and the photo-generating carrier 50 moves not only through the upper side y of the convex part 100 but also through the side surface x. As a result, the overall travel distance can be shortened, so that high light efficiency and electrical characteristics can be improved.
실시예 1Example 1
p형 실리콘 웨이퍼 상에, 식각하는 동안 보호 마스크로 작용할 PR 패턴을 상기 실리콘 기판 상에 형성하였다. C4F8 기체를 가하여 고분자 코팅 막을 형성하고, SF6 플라즈마로 잔여 폴리머 층 및 PR 마스크 없는 실리콘 기판을 식각하였다. PR-마스크를 기판에서 제거함으로써, 평균 폭 2 ㎛, 높이 2 ㎛이고, 주기가 7 ㎛인 기둥 형태의 패턴을 형성하였다.On the p-type silicon wafer, a PR pattern was formed on the silicon substrate to serve as a protective mask during etching. C 4 F 8 gas was added to form a polymer coated film, and the silicon substrate without the PR mask and the PR mask was etched with SF 6 plasma. By removing the PR-mask from the substrate, a pillar-shaped pattern having an average width of 2 m and a height of 2 m and a period of 7 m was formed.
p-n 접합 형성을 위해, 기둥 구조인 실리콘 웨이퍼에 n형 도핑제로 POCl3를 이용하여 화로에서 40분 간 800℃에서 가열하여 도핑시켰다. 포스포실리케이트 유리(PSG)를 제거하기 위해 5%의 HF 완충용액을 사용하였다. 이후, 얇은 SiNx 층을 플라즈마-강화 화학기상 증착법(PECVD)를 이용하여 증착시켜 p-n 접합 반도체층을 제조하였고, 이를 현미경으로 관찰한 사진을 도 1에 나타내었다.To form a pn junction, the columnar silicon wafer was doped by heating at 800 ° C. for 40 minutes in a furnace using POCl 3 as an n-type dopant. 5% HF buffer was used to remove the phosphosilicate glass (PSG). Subsequently, a thin SiNx layer was deposited using a plasma-enhanced chemical vapor deposition (PECVD) to prepare a pn junction semiconductor layer, and a photograph of the pn junction semiconductor layer was shown in FIG. 1.
실시예 2Example 2
상기 포토레지스트를 사용하여 평균 직경 2 ㎛, 높이 2 ㎛이고, 간격이 4 ㎛인 기둥 형태의 패턴을 형성하였다는 것을 제외하고는 상기 실시예 1과 동일하게 p-n 접합 반도체층을 제조하였고, 이를 현미경으로 관찰한 사진을 도 2에 나타내었다.A pn junction semiconductor layer was manufactured in the same manner as in Example 1, except that the photoresist was used to form a pillar-shaped pattern having an average diameter of 2 μm, a height of 2 μm, and a spacing of 4 μm. The photograph observed with is shown in FIG.
비교예 1Comparative Example 1
패턴을 형성하지 않았다는 것을 제외하고는 상기 실시예 1과 동일하게 p-n 접합 반도체층을 제조하였다.A p-n junction semiconductor layer was manufactured in the same manner as in Example 1, except that no pattern was formed.
실험예 1Experimental Example 1
상기 실시예 1 내지 2 및 비교예 1의 반도체층의 양면에 제1 전극 및 제2 전극을 형성하여 태양전지를 각각 제조하였다. 이후, 각 태양전지에 대하여 태양전지 성능 시험을 실시하여 그 결과를 각 태양전지의 구조와 함께 하기 표 1에 나타내었다.First and second electrodes were formed on both surfaces of the semiconductor layers of Examples 1 to 2 and Comparative Example 1 to manufacture solar cells, respectively. Then, the solar cell performance test for each solar cell and the results are shown in Table 1 together with the structure of each solar cell.
표 1
직경(㎛) 간격(㎛) 효율(%) Voc(V) Jsc(mA/cm2)
실시예 1 2 7 15.8 0.599 35.00
실시예 2 2 4 16.2 0.610 35.44
비교예 1 - - 14.3 0.587 33.90
Table 1
Diameter (μm) Thickness (㎛) efficiency(%) V oc (V) J sc (mA / cm 2 )
Example 1 2 7 15.8 0.599 35.00
Example 2 2 4 16.2 0.610 35.44
Comparative Example 1 - - 14.3 0.587 33.90
표 1을 참조하면, 2 ㎛ 직경의 기둥 형태 패턴을 가지는 실시예 1 및 2의 태양전지의 효율이 상기와 같은 패턴을 가지지 않는 비교예 1의 태양전지 대비 높은 광전 효율을 나타내는 것을 확인할 수 있다. 이는 광발생 캐리어의 이동 거리가 짧아지면서, 이동하는 캐리어 수가 증가함과 더불어, 표면적이 증가하여 입사광을 상대적으로 많이 받은 것으로 판단된다. 또한, 발생하는 전압 및 전류도 실시예 1 및 2의 태양전지가 비교예 1의 태양전지보다 높은 것을 확인할 수 있다. 이는 광발생 캐리어가 볼록부에서 상면만이 아닌 측면으로도 이동할 수 있게 됨으로써, 이동 효율이 증가하여 전압 및 전류가 상승한 것을 확인할 수 있다.Referring to Table 1, it can be seen that the efficiency of the solar cells of Examples 1 and 2 having a columnar pattern of 2 μm diameter shows higher photoelectric efficiency than the solar cell of Comparative Example 1 having no pattern as described above. This is because, as the moving distance of the light generating carriers is shortened, the number of moving carriers increases, and the surface area increases, so that the incident light is relatively received. In addition, it can be confirmed that the generated voltage and current are also higher in the solar cells of Examples 1 and 2 than the solar cell of Comparative Example 1. This allows the light generating carrier to move from the convex portion not only to the upper surface but also to the side surface, thereby increasing the moving efficiency and increasing the voltage and current.
이상 실험예 및 첨부된 도면을 참조하여 본 발명의 실시예들을 설명하였지만, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명의 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시예들은 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해해야만 한다.Although the embodiments of the present invention have been described with reference to the experimental examples and the accompanying drawings, those skilled in the art may implement the present invention in other specific forms without changing the technical spirit or essential features of the present invention. I can understand that it can be. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Claims (14)

  1. p형 반도체층 및 n형 반도체층을 포함하는 기판을 포함하고,a substrate comprising a p-type semiconductor layer and an n-type semiconductor layer,
    상기 기판의 표면은 특정 주기를 가지는 볼록부 패턴을 포함하며,The surface of the substrate includes a convex pattern having a specific period,
    상기 볼록부 패턴의 중심부로부터 공핍층의 거리가 1 ㎛ 이하인 태양전지.A solar cell having a distance of 1 μm or less from the center of the convex pattern.
  2. 제1 항에 있어서,The method of claim 1,
    상기 볼록부 패턴의 폭은 1 내지 2 ㎛ 범위인 태양전지.A width of the convex pattern is in the range of 1 to 2 ㎛ solar cell.
  3. 제1 항에 있어서,The method of claim 1,
    상기 볼록부 패턴은 돌기 형태, 피라미드 형태, 기둥 형태 또는 상기 형태들이 일측 방향으로 연결되어 있는 라인(line) 형태인 태양전지.The convex pattern has a protrusion shape, a pyramid shape, a pillar shape or a line shape in which the shapes are connected in one direction.
  4. 제1 항에 있어서,The method of claim 1,
    상기 볼록부 패턴의 높이는 상기 볼록부 패턴의 폭 대비 0.8배 내지 1.2배 범위인 태양전지.The height of the convex pattern is a solar cell range of 0.8 times to 1.2 times the width of the convex pattern.
  5. 제1 항에 있어서,The method of claim 1,
    상기 볼록부 패턴의 주기는 상기 볼록부 패턴의 폭 보다 큰 태양전지.The period of the convex portion pattern is larger than the width of the convex portion pattern solar cell.
  6. 제5 항에 있어서,The method of claim 5,
    상기 볼록부 패턴의 주기는 상기 볼록부 패턴의 폭 보다 큰 범위에서 2 내지 6 ㎛ 범위인 태양전지.The period of the convex pattern is a solar cell in the range of 2 to 6 ㎛ in a range larger than the width of the convex pattern.
  7. 제1 항에 있어서,The method of claim 1,
    상기 n형 반도체층의 p-n 접합면의 반대 면에 접하는 보호막층을 더 포함하는 태양전지.The solar cell further comprises a protective film layer in contact with the opposite surface of the p-n junction surface of the n-type semiconductor layer.
  8. 제7 항에 있어서,The method of claim 7, wherein
    상기 보호막층은 질화실리콘, 실리콘 산화물(SiOx), MgF2, MgO 및 Al2O3로 이루어진 군에서 선택되는 하나 이상을 사용하는 태양전지.The protective layer is a solar cell using at least one selected from the group consisting of silicon nitride, silicon oxide (SiO x ), MgF 2 , MgO and Al 2 O 3 .
  9. 제7 항에 있어서,The method of claim 7, wherein
    상기 보호막층의 두께는 50 내지 90 nm 범위인 태양전지.The thickness of the protective layer is a solar cell in the range of 50 to 90 nm.
  10. p형 반도체 기판의 적어도 일면에 특정 주기로 반복되는 패턴을 형성하는 단계, 및forming a pattern which is repeated at a specific cycle on at least one surface of the p-type semiconductor substrate, and
    상기 패턴이 형성된 면에 n형 반도체층을 형성하는 단계를 포함하는 태양전지 제조방법.Forming an n-type semiconductor layer on the surface on which the pattern is formed.
  11. 제10 항에 있어서,The method of claim 10,
    상기 패턴을 형성하는 방법은 포토레지스트법으로 이루어지는 태양전지 제조방법.The method of forming the pattern is a solar cell manufacturing method comprising a photoresist method.
  12. 제10 항에 있어서,The method of claim 10,
    상기 n형 반도체를 형성하는 단계는 n형 도핑법으로 이루어지는 태양전지 제조방법.Forming the n-type semiconductor is a solar cell manufacturing method consisting of n-type doping method.
  13. 제12 항에 있어서,The method of claim 12,
    n형 도핑법은 상기 패턴이 형성된 면에 n형 도핑 소스를 열처리하여 이루어지는 태양전지 제조방법.The n-type doping method is a solar cell manufacturing method by heat-treating the n-type doping source on the surface on which the pattern is formed.
  14. 제13 항에 있어서,The method of claim 13,
    상기 n형 반도체층 상에 보호막을 형성하는 단계를 추가로 포함하는 태양전지 제조방법.Forming a protective film on the n-type semiconductor layer further comprising the solar cell manufacturing method.
PCT/KR2013/010192 2013-06-28 2013-11-11 Solar cell and manufacturing method therefor WO2014208830A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2013-0075643 2013-06-28
KR20130075643 2013-06-28

Publications (1)

Publication Number Publication Date
WO2014208830A1 true WO2014208830A1 (en) 2014-12-31

Family

ID=52142141

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2013/010192 WO2014208830A1 (en) 2013-06-28 2013-11-11 Solar cell and manufacturing method therefor

Country Status (1)

Country Link
WO (1) WO2014208830A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645627A (en) * 1992-07-21 1994-02-18 Sanyo Electric Co Ltd Photovoltaic element
JP2002009314A (en) * 2000-06-20 2002-01-11 Mitsui High Tec Inc Solar battery and method for manufacturing the same
KR20020031489A (en) * 2000-10-20 2002-05-02 김순택 Polycrystalline silicon solar cell and manufacturing method thereof
KR20100059410A (en) * 2008-11-26 2010-06-04 삼성전자주식회사 Solar cell and method of fabricating the same
JP2012023342A (en) * 2010-06-18 2012-02-02 Semiconductor Energy Lab Co Ltd Photoelectric conversion device and method of producing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645627A (en) * 1992-07-21 1994-02-18 Sanyo Electric Co Ltd Photovoltaic element
JP2002009314A (en) * 2000-06-20 2002-01-11 Mitsui High Tec Inc Solar battery and method for manufacturing the same
KR20020031489A (en) * 2000-10-20 2002-05-02 김순택 Polycrystalline silicon solar cell and manufacturing method thereof
KR20100059410A (en) * 2008-11-26 2010-06-04 삼성전자주식회사 Solar cell and method of fabricating the same
JP2012023342A (en) * 2010-06-18 2012-02-02 Semiconductor Energy Lab Co Ltd Photoelectric conversion device and method of producing the same

Similar Documents

Publication Publication Date Title
AU2007277401B2 (en) Solar cell with reduced base diffusion area
WO2010150943A1 (en) Solar cell and method of manufacturing the same
US9159862B2 (en) Solar cell and manufacturing method thereof
WO2010101350A2 (en) Solar cell and method of manufacturing the same
WO2010013972A2 (en) Solar cell and method for manufacturing the same
WO2016186317A1 (en) Perovskite solar cell module
WO2010140740A1 (en) Solar cell and method of manufacturing the same
WO2009104899A2 (en) Method of etching asymmetric wafer, solar cell including the asymmetrically etched wafer, and method of manufacturing the same
US8936949B2 (en) Solar cell and manufacturing method thereof
WO2011162433A1 (en) High-density p-doped quantum dot solar cell obtained by the active doping of inp and a production method therefor
WO2016182128A1 (en) Method for manufacturing solar cell module
WO2011129503A1 (en) Solar cell and method for manufacturing the same
KR102547804B1 (en) Bifacial silicon solar cell and method for manufacturing the same
JP6114029B2 (en) Photovoltaic element and manufacturing method thereof
WO2011002130A1 (en) Solar cell and method of manufacturing the same
KR20120077840A (en) Front and back contact electric field solar cell and method thereof
WO2014208830A1 (en) Solar cell and manufacturing method therefor
WO2012036364A1 (en) Solar photovoltaic device and a production method therefor
WO2011004937A1 (en) Solar cell and method of manufacturing the same
WO2013081329A1 (en) Low-cost, mass-produced, high-efficiency solar cell having a do- type electrode and method for manufacturing same
WO2013073769A1 (en) Rear surface electrode-type solar cell and method for manufacturing same
KR101348848B1 (en) Method for fabricating back contact solar cell
KR20120129013A (en) Back contact solar cell and method for fabricating the same
WO2011065611A1 (en) Solar cell and solar cell fabrication method
WO2012057515A2 (en) Solar cell module

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13887855

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13887855

Country of ref document: EP

Kind code of ref document: A1