WO2014206842A1

WO2014206842A1 - Optoelectronic semiconductor chip

Info

Publication number: WO2014206842A1
Application number: PCT/EP2014/062863
Authority: WO
Inventors: Tony Albrecht; Markus Klein; Jan Marfeld
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2013-06-26
Filing date: 2014-06-18
Publication date: 2014-12-31
Also published as: DE102013212294A1

Abstract

The invention relates to an optoelectronic semiconductor chip. The semiconductor chip has a semiconductor layer sequence that comprises a first semiconductor region, a second semiconductor region and an active zone for generating radiation arranged therebetween. The semiconductor chip has a first contact electrically connected to the first semiconductor region, a second contact electrically connected to the second semiconductor region, and a third contact electrically connected to the first semiconductor region. The first contact and the third contact are arranged in the region of opposite sides of the semiconductor chip. The invention further relates to a device comprising a plurality of optoelectronic semiconductor chips.

Description

description

The invention relates to an optoelectronic semiconductor chip and to a device comprising a plurality of optoelectronic semiconductor chips.

This patent application claims the priority of German Patent Application 10 2013 212 294.2, the disclosure of which is hereby incorporated by reference.

An optoelectronic semiconductor chip for generating an electromagnetic radiation has a semiconductor layer sequence with an active zone. An example is one

LED chip (LED, Light Emitting Diode) for emitting a light radiation. The active zone is located between two semiconductor regions with different conductivities. By applying a voltage, a current flow is caused by the semiconductor layer sequence, whereby a

Radiation is generated in the active zone. For this purpose, the semiconductor chip connection contacts, which are electrically connected to the semiconducting ^¬ terbereichen the layer sequence. A device for lighting applications comprises in the

Usually several LED chips. In the production of a package or COB package (chip-on-board) design unhoused semiconductor chips on a common Trä ^¬ ger, for example, a board arranged. A high power and radiation density can be achieved with a high packing density of many individual semiconductor chips. Here ^¬ to the semiconductor chips connected in series in a confined space or paral ^¬ lel with each other. Known semiconductor chips have a front-side contact and a rear-side contact. Such chips can be arranged with the back side contacts, for example via a solder on contact surfaces of a circuit board. The printed circuit board can have additional contact surfaces to which bonding wires intended for contacting the front-side contacts are attached. be concluded. However, such an embodiment is at the expense of the achievable packing density.

This disadvantage can be circumvented with the aid of flip chips, which have a front-side transparent chip substrate and only rear-side contacts. Therefore, the use of bonding wires is eliminated. With this approach, however, no combination of semiconductor chips is possible, which emit a blue and a red light radiation. For a blue one

Radiation can be a semiconductor layer sequence based on

InGaN, and be set for a red radiation based on AlInGaP ^¬ . An InGaN layer sequence can be formed on a Sa ^¬ phir or SiC substrate. For AlInGaP chips, no corresponding transparent substrate material is available.

Known semiconductor chips can only be contacted on those sides on which the connection contacts are formed. This restricts the possibility of using a design of a semiconductor chip in various lighting devices. Lighting devices may differ, for example, from different carriers, as well as different wirings of semiconductor chips. The object of the present invention is to provide a

Solution for an improved optoelectronic semiconductor chip, and a corresponding device comprising a plurality of optoelectronic semiconductor chips specify. This problem is solved by the features of the independent Pa ^¬ tentansprüche. Further advantageous embodiments of the invention are specified in the dependent claims.

According to one aspect of the invention, an optoelectronic semiconductor chip is proposed. The optoelectronic semiconductor chip has a semiconductor layer sequence comprising a first semiconductor region, a second semiconductor region and an active zone arranged there between for generating radiation. on. The semiconductor chip has a first contact, which is electrically connected to the first semiconductor region. The semiconductor chip has a second contact, which is electrically connected to the second semiconductor region. The semiconductor chip further has a third contact, which is also electrically connected to the first semiconductor region. The first contact and the third contact are arranged in the region of opposite sides of the semiconductor chip.

In the optoelectronic semiconductor chip, a contact can be made either via the first contact and the second contact or via the additional third contact and the second contact. The first contact and the third contact, which are electrically connected to each other, are in the

Area arranged by opposite sides of the semiconductor chip. In this way, the semiconductor chip allows a high flexibility for electrical contacting. The first contact or the third contact can be used, depending on which is simpler or more suitable for contacting or interconnecting the semiconductor chip. Here, for example, space or the configuration of a lighting device or a carrier of the lighting device, for which the semiconductor chip is provided, be decisive.

Furthermore, the semiconductor chip can be arranged relatively close with respect to another optoelectronic semiconductor chip, which may have the same design. In this case, a direct and space-saving electrical connection between terminal contacts of the semiconductor chips can be realized via a suitable contact structure. Possible, for example, is a connection via a bonding wire or via a structure in the form of a so-called CPHF metallization (Compact Planar High Flux). A connection of contacts of the

The semiconductor chip can also have a metallic structure of a connection ^¬ used for supporting the semiconductor chip Carrier, for example in the form of a contact surface or Lei ^¬ terbahn done.

As a result, the above-described design of the optoelectronic semiconductor chip with the third contact offers the

Possibility of an apparatus in a flexible manner with a high packing density of semiconductor chips to verwirkli ^¬ chen. Due to the high packing density, the device can have a high power and radiation density.

The feature that a contact is electrically connected to a semiconducting ^¬ ders of the semiconductor layer sequence, signified ^¬ tet that via the contact an electrical connection to the respective semiconductor region is prepared, and conse- which an electrical potential is applied to the semiconductor region with the aid of the contact can. For this purpose, the connection contact can be connected directly to the semiconductor region, ie directly adjacent to the semiconductor region and contact the latter. It is also a medium-nent connection, so that the contact via one or several ^¬ re electrically conductive layers, components and / or structures with the semiconductor region may be connected.

In the following, possible embodiments of the semiconductor chip will be described.

The optoelectronic semiconductor chip may in particular be a light-emitting diode chip. The semiconductor layer sequence may be based, for example, on a III-V compound semiconductor material. The first and second semiconductor regions of the semiconductor layer sequence have different conductivities or dopings. For example, the first semiconductor region may be n-type and the second semiconductor region may be p-type. However, inverse conductivities of the first and second semiconductor regions are also possible for this purpose. The active zone may, for example, be a pn-junction or else another for radiation generation have suitable structure such as a quantum well structure or a Mehrfachquantentopfstruktur.

At the opposite sides of the semiconductor chip are vorgese ^¬ hen in de-ren range of the first contact and the third contact, it may be a front side and a back side of the semiconductor chip ^¬. The semiconductor chip may be designed so that a substantial part of the radiation generated in the active zone is emitted via the front side or via a front-side surface. For this purpose, the semiconductor chip can be realized in the form of a so-called surface emitter.

In a further embodiment, the first and second contacts are arranged in the region of the same side of the semiconductor ^chip . This makes it possible to electrically connect a plurality of semiconductor chips equipped with this structure in a simple and direct manner via their first and second contacts.

In a further embodiment, the first and second contacts in the region of a front side of the semiconductor ^chip to ^¬ ordered front side contacts. The third contact is a rear contact arranged in the region of a rear side of the semiconductor chip. This configuration provides the possi ^¬ ness, the semiconductor chip to contact a flexible way either exclusively on the front, or alternatively at the front and at the back. In a further embodiment of first and second contacts in the region of a rear side of the semiconductor chip is arranged ^¬ back contacts. The third contact is arranged at Be ^¬ rich a front side of the semiconductor chip before ^¬ derseitenkontakt one. This configuration offers the possibility of the semiconductor chip in a flexible way eventually to contact either ^¬ at the back, or alternatively at the front and at the back. For the electrical connection of the first contact and the third contact with the first semiconductor region, wherein the first and the third contact are arranged on opposite chip sides, different configurations of the semiconductor chip may be considered.

A further embodiment proposes for this purpose that the semiconductor chip has an electrically conductive substrate. The substrate can serve as a carrier of the semiconductor layer ^sequence , and at the same time can be used for an electrical connection. In this embodiment, the third contact can be arranged on the electrically conductive substrate. In this way, the third contact via the electrically conductive substrate, and optionally one or more further

Layers or structures to be electrically connected to the first semiconductor region of the semiconductor layer sequence. The electrically conductive substrate may comprise a doped semiconductor material. For example, it is possible for the electrically conductive substrate to form a backside carrier substrate of the semiconductor chip. The third contact may be a rear contact arranged on the carrier substrate. The semiconductor layer sequence can be arranged on the front side in this embodiment.

In another embodiment, the electrically conductive substrate is transparent to the erzeug ^¬ te in the active zone of radiation. In this embodiment, the electrically conductive substrate may be arranged in the region of a front side, and the semiconductor layer sequence may be arranged in the region of a rear side of the semiconductor chip. The third contact, which may be arranged on the electrically conductive substrate, may in this case be a front-side contact.

In a further embodiment, the semiconductor chip has a plated-through hole. The via can extend through a portion of the semiconductor layer sequence. It is also possible that the via additionally extends through an electrically conductive substrate of semiconducting ^¬ terchips. The via allows a direct space-saving electrical connection. It can be provided that the first contact and optionally also the third contact are electrically connected to the first semiconductor region of the semiconductor layer sequence via the via. In a further embodiment, the first and second contacts are each arranged laterally next to the semiconductor layer sequence. In this embodiment, the semiconductor layer sequence may be present in the region of the front side of the semiconductor chip, and the first and second contact may be front side contacts. By positioning the first and second contacts laterally next to the semiconductor layer sequence, it can be achieved that the first and second contacts do not cause shading and / or absorption of a radiation emerging from the semiconductor layer sequence.

In a further embodiment, the semiconductor layer sequence has a step shape. The first contact is on the first semiconductor region, and the second contact is disposed on the second semiconductor region. Due to the stepped shape of the semiconductor layer sequence, both the first semiconducting ^¬ ders and the second semiconductor region may have a direct contacting zugängige portions are disposed on which the first and second contact. The optoelectronic semiconductor chip may be formed such that the semiconductor chip can be contacted via the first and second contact or via the third and second contact in order to provide an electrical connection to the first and the second semiconductor region for causing a current to flow through the active semiconductor Zone.

In a further embodiment, the semiconductor chip has a plurality of first, a plurality of second and / or a third third contact te on. The plurality of contacts may be at different locations or lateral positions in a respective side (front or back) of the semiconductor chip is arranged ^¬. As a result, the flexibility for contacting the semiconductor chip can be further improved.

According to a further aspect of the invention, a device is proposed which comprises a carrier and a plurality of optoelectronic semiconductor chips. The plurality of semiconductor chips have the structure described above or a structure according to one of the embodiments described above. In this way, a high degree of flexibility can be made available for an electrical connection of semiconductor chips undertaken in the course of the manufacture of the device. The semiconductor chips can be connected to each other in a direct manner and arranged on the carrier in a space-saving manner or with a high packing density. In this way, the ^device can have high power and luminance. This proves to be advantageous, for example, in an ^{embodiment of} the device as a directed light source. Due to the high luminance, it is possible to form a semiconductor system downstream of the optical system, which may for example have a lens and / or a reflector, with small dimensions.

In one possible embodiment of the device, the plurality of semiconductor chips each have two front-side contacts and one rear-side contact. The front side contacts of two of the plurality of semiconductor chips are electrically connected via a contact ^¬ structure. This may be, for example, a bonding wire or a planar connection or CPHF connection. It is possible to provide a series connection of all the semiconductor chips in the foregoing manner, that is, the front-side contacts of each two of said plurality of semiconducting ^¬ terchips via a corresponding contact structure electrically are connected. The rear-side contacts of the semiconductor chips interconnected in this way are not used here.

However, the flexibility of making electrical contact with semiconductor chips with two front-side contacts and a back contact also allows other electrical Verbindun ^¬ gen.

A further embodiment provides for this purpose that the device comprises a plurality of first optoelectronic semiconductor chips, which are designed for a flexible contacting and each have two front side contacts and a back ^¬ contact. The device comprises at least one second optoelectronic semiconductor chip, which has a front contact and a back contact. Of the

Front-side contact of the second semiconductor chip and an on ^¬ derseitenkontakt one of the first semiconductor chip are electrically connected via a contact structure, such as a bonding wire. The backside contact of the second semiconductor chip and the backside contact of another of the first semiconducting ^¬ terchips are electrically connected via a connection structure of the carrier. In this embodiment, one of the first semiconductor chips is using a front-side contact, and another one of the first semiconductor chips is electrically connected to the second semiconductor chip using a back-side contact.

The device can be realized with a plurality of second semiconductor chips, wherein a connection to the first semiconductor chips can each be made in the manner described above. Furthermore, an electrical connection of first semiconductor chips to one another can take place exclusively via their front side contacts. As a result, all the first and second semiconductor chips of the device can be connected in series. It is also possible that a second semiconductor chip is likewise designed for flexible contacting and has two front-side contacts and one rear-side contact. In a further embodiment, the device comprises a plurality of optoelectronic semiconductor chips, each of which has two rear side contacts and a front side contact. The back contacts of two of the plurality of semiconductor chips are connected elekt ^¬ driven via a connection structure of the carrier.

It is possible to provide a series connection of all the semiconductor chips in the aforementioned manner, i. that the

Rear side contacts of each two of the plurality of semiconductor chips ^¬ are electrically connected via a corresponding connection structure of the carrier. The front-side contacts of the semiconductor chips interconnected in this way are not used here.

However, the flexibility of electrical contacting with semiconductor chips having two backside contacts and a front contact also allows other electrical connections.

In this regard, according to a further embodiment, it is provided that the device comprises a plurality of first optoelectronic semiconductor chips, which are designed for flexible contacting and each have two rear side ^contacts and a front side contact. The device comprises at least a second optoelectronic semiconductor chip having a front side contact and a back print ^¬ tenkontakt. The backside contact of the second semi-conductor chips, and a back contact of the first half ^¬ semiconductor chip are electrically connected via a connection structure of the carrier. The front-side contact of the second semiconductor chip and the front-side contact of another of the first semiconductor chips are electrically connected via a contact structure. In this embodiment, one of the first semiconductor chips is using a backside contact, and another one of the first semiconductor chips is using a front side contact electrically connected to the second semiconductor chip.

The apparatus may be realized with a plurality of second semiconductor chips, wherein a connection with the first half ^¬ semiconductor chip may be formed in the manner described above. Furthermore, an electrical Verbin ^¬-making of the first semiconductor chip can be made to each other only through their backside contacts. As a result, all semiconductor chips of the device can be connected in series. It may be provided further that a second semiconductor chip is also formed on a flexible contact and having two rear-side contacts, and a front side For ^¬ tenkontakt.

As indicated above, suitable for a flexible Kontakt ^¬ animals optoelectronic semiconductor chip can be realized in the form of a surface emitter. A Vorrich ^¬ tion, for which a structure as described above can be provided, can be formed exclusively with surface emitters. As a result, the achievement of a high luminance can be promoted. Because surface emitters can radiate a substantial part of the generated radiation over the front side or a front side surface upwards. A lateral radiation with the consequence of a lateral absorption of radiation at respectively adjacent semiconductor chips, on the other hand, can be avoided.

In addition, further embodiments are conceivable for devices with a plurality of optoelectronic semiconductor chips. For example, parallel connections, or combinations of series and parallel connections of semiconductor chips may be provided instead of series connections. A device can be realized with densely packed optoelectronic semiconductor chip further having semiconducting ^¬ terschichtenfolgen based on different semiconductor materials. As a result, the semiconductor chips can Radiations of different wavelength ranges or colors, for example blue and red, emit. Apart from the different semiconductor materials, the semiconductor chips may otherwise be constructed substantially identically or in accordance with one of the embodiments described above and suitable for flexible contacting.

It should be noted that features and details which have been mentioned above with respect to the structure of the optoelectronic semiconductor chip with the flexible contacting possibility can also be used in the device or in its embodiments.

The above-explained and / or reproduced in the dependent claims advantageous embodiments and refinements of the invention can - except for example in cases of clear dependencies or incompatible alternatives - individually or in any combination with each other are used.

The above-described characteristics, features and advantages of this invention, as well as the manner in which they are achieved, will become clearer and more clearly understood in connection with the following description of embodiments which will be described in connection with the schematic drawings. Show it:

Figure 1 is a simplified side view of a optoe ^¬ lektronischen semiconductor chips, which contacts two Vorderseitenkon- and having a rear-side contact, one of said

Front side contacts and the rear side contact are electrically connected to the same semiconductor region of a semiconductor layer sequence of the semiconductor chip; Figures 2 to 4 are side views of possible embodiments of the optoelectronic semiconductor chip of Figure 1; Figure 5 is a plan view of a carrier with a light emitting device chip positions optoelectronic semiconductor chip for which an electrical series connection is vorgese ^¬ hen;

FIG. 6 shows a top view of a lighting device comprising optoelectronic semiconductor chips arranged on a carrier and having a structure corresponding to FIG. 1, the front side contacts of which are electrically connected via bonding wires;

Figure 7 is a side view of the device of Figure 6 illustrating a layered structure; FIG. 8 shows a side view of the device of FIG. 6, in which the electrical connection of the semiconductor chips via bonding wires is illustrated;

Figure 9 is another side view of the device of Figure 6 illustrating an alternative layer construction;

Figure 10 is a plan view of another light emitting device having disposed on a support optoelectronic semiconductor chip, said optoelectronic semiconductor chip ge ^¬ Mäss Figure 1 are combined with other optoelectronic semiconductor chip and an electrical connection Herge ^¬ is alternately via bonding wires and connecting structures of the carrier;

Figure 11 is a side view of the apparatus of Figure 10 illustrating a layered structure;

Figures 12 and 13 lateral views of possible Ausges- taltungen of the lighting device of Figure 10 with different optoelectronic semiconductor chip, wherein the electrical connection of the semiconductor chips to each other is illustrated ^¬ light; Figure 14 is a plan view of another light emitting device having disposed on a support optoelectronic semiconductor chip, said optoelectronic semiconductor chip 1 are combined with other optoelectronic semiconductor chips ACCORDING and an electrical connection Herge ^¬ provides both via bonding wires and connecting structures of the carrier; Figure 15 is a side view of the device of Figure 14 illustrating a layered structure;

FIG. 16 shows a side view of a possible embodiment of the lighting device of FIG. 14, wherein the electrical connection of semiconductor chips to one another is illustrated;

FIG. 17 is an elevational view of a semiconductor chip having a plurality of front side contacts;

Figure 18 comprises a simplified side view of a optoe ^¬ lektronischen semiconductor chips, which has two rear-side contacts, and a front contact, wherein one of the rear-side contacts and the front side contact are electrically connected to the same semiconductor region of a semiconductor layer sequence of the semiconductor chip;

Figures 19 to 21 are side views of possible embodiments of the optoelectronic semiconductor chip of Figure 18;

FIG. 22 shows a top view of a lighting device, comprising optoelectronic semiconductor chips arranged on a carrier and having a structure according to FIG. 18, whose rear side contacts are electrically connected via connecting structures of the carrier; Figure 23 is a side view of the device of Figure 22 illustrating a layered structure;

FIG. 24 shows a side view of the device of FIG. 22, in which the electrical connection of the semiconductor chips via connecting structures of the carrier is illustrated;

Figure 25 is a plan view of another light emitting device having disposed on a support optoelectronic semiconductor chip, said optoelectronic semiconductor chip ge ^¬ Mäss figure 18 are combined with other optoelectronic semiconductor chip and an electrical connection Herge ^¬ is alternately connecting structures of the carrier and bonding wires;

Figures 26 and 27 are side views of possible embodiments of the lighting device of Figure 25 with different optoelectronic semiconductor chips, wherein the electrical connection of the semiconductor chips is illustrated with each other;

Figure 28 is a plan view of another light emitting device having disposed on a support optoelectronic semiconductor chip, said optoelectronic semiconductor chip figure 18 are combined with other optoelectronic semiconductor chip ACCORDING and an electrical connection is both connection structures of the carrier and bond wires Herge ^¬ represents; Figure 29 is a side view of a possible embodiment of the lighting device of Figure 28, wherein the electrical connection of the semiconductor chips is illustrated with each other; FIG. 30 shows a simplified side ^{view of a} further optoelectronic semiconductor chip, which has several front side ^contacts in comparison to the semiconductor chip of FIG. and Figure 31 is an illustration of a back side of an opto-electro ^¬ African semiconductor chip having a plurality of back contacts. On the basis of the following schematic figures, a concept is described by means of which arrangements of optoelectronic semiconductor chips for lighting devices can be realized in a space-saving and flexible manner. For this purpose, a design of an optoelectronic semiconductor chip is used, which is suitable for flexible Kontak ^¬ animals. Here, a semiconductor region of a semiconductor layer sequence is electrically connected to connection contacts of the semiconductor chip, which are arranged on different sides of the semiconductor chip. As a result, optionally one of the contacts can be used for establishing an electrical connection to the relevant semiconductor region.

The embodiments shown in the figures and described below can be produced by means of semiconductor processes and the production of optoelectronic semiconductor chips and optoelectronic devices of known processes. Customary Ma ^¬ terialien can be used, so that is then only partially received in the area. In the same way, it is conceivable that, in addition to the components and structures shown and described, further components, structures and / or layers may be present, in particular in the case of the semiconductor chips. It is fer ^¬ ner noted that the figures are only of schematic nature and are not to scale. In this

For the sake of clarity, components and structures shown in the figures may be exaggerated or oversized for clarity. FIG. 1 shows a greatly simplified lateral representation of an optoelectronic semiconductor chip 100, which is designed to generate electromagnetic radiation. The semiconductor chip 100 may in particular be a light-emitting diode chip to generate a light radiation. The semiconductor chip 100 has a front 105 and a thereto opposite ge ^¬ put back side 106. Via the front side 105, the semiconductor chip 100 can emit a substantial part of the radiation during operation when electrical energy is supplied. For contacting and thereby enabling the application of an electrical voltage, the semiconductor chip 100 has a plurality of connection contacts 101, 102, 103. In the region of the front ^¬ page 105, two contacts 101, 102 are arranged, which constitute so-using front-side contacts 101, 102 of the semiconductor chip 100th In the area of the rear side 106, a further contact 103 is arranged, which is thus a rear-side contact 103. For generating the light radiation, the semiconductor chip 100 has a semiconductor layer sequence 120 with an active zone 125. The active zone 125 is arranged between two semiconductor ^regions 121, 122 with different conductivity types (not shown in FIG. 1, compare the embodiments of FIGS. 2 to 4). In the following, the semiconductor regions 121, 122 arranged on both sides of the active zone 125 are also referred to as first semiconductor region 121 and second semiconductor region 122. One of the two semiconductor regions 121, 122 is n-type, and the other of the two semiconductor regions 121, 122 is p-type. The active zone 125, in wel ^¬ cher the radiation is generated in the operation of the semiconductor chip 100 may comprise a p-n junction, or any other suitable structure for generating radiation, for example a multiple quantum well structure have. The semiconductor layer sequence 120 may be based on a III-V compound semiconductor material.

For the generation of the radiation, an electrical voltage is applied to the semiconductor layer sequence 120 or to the first and second semiconductor region 121, 122 in order to cause an electric current flow through the semiconductor layer sequence 120 and thus through the active zone 125. This can be done with the aid of the contacts 101, 102, 103 shown in FIG Semiconductor chips 100 are realized, via which an electrical connection to the different semiconductor regions 121, 122 can be produced. The contacts 101, 102, 103 may be formed of a metallic material, and in the form of contact surfaces.

In the semiconductor chip 100, the front-side contact 101 is electrically connected to the first semiconductor region 121. The other front-side contact 102 is electrically connected to the second semiconductor region 122. The front-side contacts 101, 102 are also referred to below as first contact 101 and second contact 102. The backside contact 103 is also electrically connected to the first semiconductor region 121. The contact 103 is referred to below as the third contact or additional contact 103.

In Figure 1, but also in other figures, is the affiliation or electrical connection of contacts and Halblei ^¬ terbereichen and thus the polarity of the contacts based on different representations of the contacts, present in

Shape of a hatched or not hatched contact representation illustrated. If the first semiconductor region 121 is n-type and the second semiconductor region 122 is p-type, the contacts 101, 103 may be n-type contacts, and the contact 102 may be a p-type contact. Alternatively, an inverse embodiment with reversed conductivities and thus polarities of the contacts 101, 102, 103 may be provided.

The structure of the semiconductor chip 100 makes it possible to make contact via the first contact 101 and the second contact 102 or via the third contact 103 and the second contact 102. Contacting for establishing an electrical connection to the first semiconductor region 121 can optionally take place via the front-side contact 101 or the back additional contact 103. The semiconductor chip 100 therefore offers a high flexibility with regard to a wiring in a lighting device. Furthermore, a Chip assembly can be realized with a high packing density.

Possible embodiments of the semiconductor chip 100 will be described in more detail with reference to the following FIGS. 2 to 4. These may each be surface emitters. It should be noted that features and details, which are called in Be ^¬ train on a configuration may also apply in relation to other embodiments.

FIG. 2 shows a side view of a possible embodiment of a semiconductor or light-emitting diode chip 111, which may be considered for the semiconductor chip 100 of FIG. The semiconductor chip 111 has the above-mentioned semiconductor layer sequence 120 with the first semiconducting ^¬ ders 121, the second semiconductor region 122 and the interposed active zone 125th The semiconductor layer sequence 120 provided on the front side is structured in the form of a semiconductor body, and is arranged with the second semiconductor region 122 on an electrically conductive current spreading layer 133. The current spreading layer 133 contacts the second semiconductor region 122. In the current spreading layer 133 of the second front-side contact 102 is arranged laterally next to the semiconducting ^¬ terschichtenfolge 120th

The semiconductor chip 111 further includes a via 135. For the via 135, a recess extending vertically through the current spreading layer 133, the second semiconductor region 122, the active region 125 and into the first semiconductor region 121 is formed, which is peripherally surrounded by an insulating layer 132 and by an insulating layer 132 conductive layer 131 is filled. The conductive layer 131 contacts the first semiconductor region 121. Outside the via 135, the current spreading layer 133, the insulating layer 132, and the conductive layer 131 are superimposed in the form of a layer stack. It is possible lent to realize the semiconductor chip 111 with a plurality of laterally juxtaposed vias 135.

As further shown in FIG. 2, the conductive layer 131 laterally adjacent to the semiconductor layer sequence 120 has an exposed portion on which the front-side first contact 101 is arranged. The conductive layer 131 is further disposed on an electrically conductive substrate 130. It is possible that between the

Layer 131 and the substrate 130, an additional electrically conductive connection layer is disposed (not Darge ^¬ asserted). On the substrate 130, the third Kon ^¬ clock 103 is arranged on the back. The conductive substrate 130 may comprise a do ^¬ patented semiconductor material. The conductive layers 131, 133 may be formed from suitable electrically conductive materials, for example metallic materials or doped semiconductor materials.

Based on FIG. 2, the electrical connection between the different semiconductor regions 121, 122 of the semiconductor layer sequence 120 and the associated contacts 101, 102, 103 becomes clear. The second contact 102 is electrically connected to the second semiconductor region 122 via the current spreading layer 133. The first contact 101 is connected elekt ^¬ centrally over the conductive layer 131 and the via hole 135 with the first semiconductor region 121st The third contact 103 is connected to the first semiconductor region 121 via the conductive substrate 130, the conductive layer 131 and the via 135. By positioning the first and second contacts 101, 102 laterally next to the semiconductor layer sequence 120, shading or absorption of a radiation emerging from the semiconductor layer sequence 120 can be avoided. In the case of the semiconductor chip 111, the contacts 101, 102, 103 are electrically connected to the associated semiconductor regions 121, 122 of the semiconductor device via components such as the substrate 130, the via 135 and corresponding layers 131, 133. layer sequence 120 connected. But are also possible UNMIT ^¬ nent electrical connections, as is the case in the following configurations. Figure 3 shows a side view of another embodiment of a semiconductor chip 112, which may come into consideration for the half ^¬ semiconductor chip 100 of FIG. 1 In the semiconductor chip 112, the semiconductor layer sequence 120 with the first semiconductor region 121 is arranged on an electrically conductive substrate 130. There is a reverse arrangement of the semiconductor regions 121, 122 compared to FIG. The semiconductor layer sequence 120 has a stepped ^¬ form. This point of the first semiconductor region 121 and the second semiconductor region 122 for clocking of zugängige a front con- partial regions. In these areas, the first and second contacts 101, 102 are arranged directly on the first and second semiconductor regions 121, 122, so that they are contacted directly by the contacts 101, 102. Between the semiconductor layer sequence 120 and the substrate 130 may be an electrically conductive interconnect layer provided ^¬ (not shown). On the leitfä ^¬ higen substrate 130, the third contact 103 is rear ^¬ ordered. The contact 103 is electrically connected to the first semiconductor region 121 via the conductive substrate 130.

Figure 4 shows a side view of another embodiment of a semiconductor chip 113 which can be provided for the semi-conductor chip ^¬ 100 of FIG. 1 The semiconductor layer sequence 120 of the semiconductor chip 113 is likewise arranged with the first semiconductor region 121 on an electrically conductive substrate 130. On the front side, the second contact 102 is arranged directly on the second semiconductor region 122 of the semiconductor layer sequence 120. Between the semiconductor layer sequence 120 and the substrate 130, an electrically conductive connection layer may be provided (not shown). On the conductive substrate 130, the third contact 103 is arranged on the rear side. The contact 103 is electrically connected via the conductive substrate 130 to the ERS ^¬ th semiconductor region 121st

The semiconductor chip 113 further has a via 155. For the via hole 155 is located verti ^¬ kal through the second semiconductor region 122, the active region is formed 125 and into the first semiconductor region 121 extending recess which with an iso ^¬ lationsschicht at the edge 152, and electrically conductive with a region surrounded by the insulating layer 152 Layer 151, for example made of a metallic material, is filled. The conductive layer 151 contacts the first Halbleiterbe ^¬ rich 121. Outside of the via 155 or in the region of the front face 105 comprises the insulating layer 152 NEN egg laterally projecting partial region. In this area and on the insulating layer 152, the first contact 101 is arranged. The first contact 101 may, as is indicated in FIG ^¬ 4 is to be a portion of the conductive layer 151st However, it is also possible to form the contact 101 in the form of a separate layer connected to the layer 151. Via the via 155, the first contact 101 is connected to the first semiconductor region 121.

The structure of the semiconductor chip 100 of FIG. 1, for which the embodiments of FIGS. 2 to 4 or other embodiments can be considered, makes it possible to realize a lighting device in a flexible manner with closely adjacent semiconductor chips. Possible embodiments are described in more detail below.

Here, in each case, as shown in the AufSichtsdarstellung of Figure 5, a carrier 160 for twenty-one optoelectronic semiconductor chips is used. These are arranged in the form of a matrix, as indicated by chip positions 168. Since unpackaged chips are used, the device can be referred to as a package or COB package (chip-on-board). The chips are placed relatively close to each other ^¬, making the device a high Can have power and luminance. Furthermore, the chips are space-saving or directly connected in series in series elekt ^¬ risch. The row connection has a meandering course indicated in FIG. 5 by an arrow, and extends between two chips marked "+" and at the ends of the row.

FIG. 6 shows a top view of a luminous device 191, in which (only) optoelectronic semiconductor chips 100 of FIG. 1 are arranged on a carrier 160 and electrically connected to one another via bonding wires 165. An associated lateral layer structure is shown in FIG. The carrier 160 has a base substrate 161, for example made of a ceramic material or a metallic material such as copper, and a large-area insulating layer 162. The semiconductor chips 100 are disposed on the insulation 162, and may be attached thereto using, for example, an adhesive, not shown.

The series connection of the semiconductor chips 100 in the device 191 via the bonding wires 165 is illustrated in ^{detail in} FIG. 8. The arranged on the left in Figure 8 Half ^¬ semiconductor chip 100 is the chip marked in Figure 6 with "+" 100. In figure 8 is different from the top view of Figure 6 a merely extending in a direction of arrangement next to each other positioned chip 100 is shown. Such Representation is also chosen for devices described below.

It is clear from FIG. 8 that a front-side first contact 101 and a front-side second contact 102 of two adjacent semiconductor chips 100 are directly connected via the bonding wires 165. As a result, in each case n-type and p-type semiconductor regions are adjacent

Semiconductor chips 100 connected in series. The semiconductor chips 100 may include, for example, an n-type first semiconductor region 121 and a p-type second semiconductor region 122, whereby in each case an n-contact 101 is connected to a p-contact 102. Alternatively, inverse polarities are possible. The additional contact 103 of the semiconductor chips 100 is not used in this embodiment.

FIG. 9 shows an alternative layer structure of the device 191. In this case, the carrier 160 has the base substrate 161 without a large-area insulation. Instead, separate subsections of an insulation 162 in the region of the individual semiconductor chips 100 are arranged on the base substrate 161. As a result, a mounting position for the semiconductor chips 100 on the carrier 160 can be specified. It is also possible that the insulation 162 is, for example, an insulating adhesive used to secure the chips 100 to the base substrate 161.

Using the following figures more lighting devices are described with the semiconductor chip 100 in which at SämT ^¬ union or a portion of the semiconductor chip 100, the clock is used Zusatzkon- clocking of 103 instead of the contact 101 for electrical con-. Identical and equivalent compo ^¬ nents are hereinafter not detail again beschrie ^¬ ben. Instead, reference is made to the above description. Also features and details, which are mentioned with regard to an embodiment, may apply with respect to another embodiment.

FIG. 10 shows a top view of another

Luminous device 192 with a chip arrangement on a carrier 160. Here, a combination of optoelectronic semiconductor chips 100 with optoelectronic semiconductor chips 170 is used. The semiconductor chips 100, 170 are connected in series, wherein in each case a semiconductor chip 100 is connected to a semiconductor chip 170 in a periodic manner. A variant with semiconductor chips 180 instead of the semiconducting ^¬ terchips 170 is described in more detail below. Figure 10 shows that a direct electrical connection Zvi ^¬ rule the chip is manufactured 100, 170 alternately via bonding wires 165, and a metallization of the carrier 160 in the form of separate and adapted to the series connection area connecting structures 163rd The connection structures 163 serve as contact surfaces and conductor tracks, and are referred to below as contact surfaces 163. Each of the contact surfaces 163 carries two semiconductor chips 100, 170. As in the associated lateral layer structure of Figure 11 is shown, 160, the support has a base substrate 161, a thereto arranged large-area insulation 162, and here ^¬ up the contact surfaces 163 on.

The series connection of the semiconductor chips 100, 170 in the device 192 via the bonding wires 165 and contact surfaces

163 is partially illustrated in FIG. Here, the structure of the semiconductor chips 170 is also indicated using the un ^¬ terschiedlichen contact representations. A semiconductor chip 170 is formed comparable to a semiconductor chip 100 for flexible contacting and has two front ^¬ side contacts 171, 172 and a rear side contact 173. The front-side contacts 171, 172 of a chip 170 are driven with different elekt ^¬ arranged on both sides of an active region of a semiconductor regions Halbleiterschichten- follow connected. The back contact 173 is 171 is closed ^¬ at the same semiconductor region as the front-side contact. A semiconductor chip 170 may, for example, have a structure analogous to FIGS. 2 to 4. As shown in FIG. 12, the semiconductor chips 100 are

170 arranged with the rear side contacts 103, 173 on the Kontaktflä ^¬ Chen 163 of the carrier 160. An attachment and electrical connection to the contact surfaces 163 may be realized, for example, via a solder or an electrically conductive adhesive (not shown). The rows ^¬ connection is established in that in each case two neighboring and ^¬ be on a common contact surface 163 is arranged ^¬ semiconductor chips 100, 170, the rear-side contacts 103, 173 are electrically connected via the associated contact surface 163 verbun ^¬ . In each two adjacent and on different ^¬ union contact surfaces 163 arranged semiconductor chips 100, 170 is a front-side contact 102 is connected via a bonding wire 165 to a front side contact 172nd The contacts 101, 171 of the semiconductor chips 100, 170 are not used in this Ausges ^¬ taltung.

The semiconductor chips 100, 170 are configured and interconnected with each other, that the n-type and p-type semiconducting ^¬ terbereiche adjacent semiconductor chips 100, 170 electrically connected in series. The bonding wires 165 on the contacts 102 interconnected, 173 and 163 on the Kontaktflä ^¬ chen interconnected contacts 103, 173 provide this contacts of different polarities (n- and p-

Contacts) which are electrically connected to semiconductor regions of different conductivities in the respective semiconductor chips 100, 170. This is indicated in FIG. 12 on the basis of the different contact representations. For this purpose, the semiconductor chips 100, 170 may be constructed in the same way but with reversed conductivities of the respective semiconductor regions of the semiconductor layer sequences.

FIG. 13 shows a detail of a modified embodiment of the device 192, in which the semiconductor chips 170 are replaced by optoelectronic semiconductor chips 180. FIGS. 10, 11 can be used analogously. The semiconductor chips 100, 180 are connected in series also alternately via bonding wires ^¬ 165 and contact surfaces 163 of the carrier 160th A semiconductor chip 180 has a front-side contact 181 and a rear-side contact 182. The Kon ^¬ contacts 181, 182 are electrically connected to different, arranged on both sides of an active region of semiconductor regions of a semiconductor layer sequence, as clock representations indicated by means of the con-. The semiconductor chips 100, 180 are arranged with the rear side contacts 103, 182 on the contact surfaces 163 of the carrier 160, and for example via a solder or a conductive adhesive thereon attached. In each two adjacent and on a ge ^¬ common contact surface 163 arranged semiconductor chips 100, 180 are the rear-side contacts 103, 182 electrically connected via the associated contact surface 163rd In each case two adjacent semiconductor chips 100, 180 arranged on different contact surfaces 163, a front-side contact 102 is connected to a front-side contact 181 via a bonding wire 165. The contacts 101 of the semiconductor chips 100 are not used in this embodiment.

In the embodiment of FIG. 13, alternating n-conducting and p-conducting semiconductor ^{regions of} the semiconductor chips 100, 180 are likewise connected electrically in series. Here stel ^¬ len represents the contacts 102, 181 and the contacts 103, 182, contacts of different polarities, which are electrically connected to the respective semiconductor chips 100, 180 having the semiconductor regions of different conductivities.

FIG. 14 shows a top view of another

Lighting device 193, in which semiconductor chips 100 are combined with semiconductor chips 170 or 180 and connected in series via bonding wires 165 and a metallization of a carrier 160 in the form of connecting structures or contact surfaces 163. The device 193 represents a combination of the previously explained devices 191, 192. One part of the semiconductor chips 100 is on an insulation 162, and another part of the semiconductor chips 100 is arranged on contact surfaces 163 of the carrier 160, here together with semiconductor chips 170 or 180 , This is also shown in the side layer construction of FIG.

FIG. 16 shows a partial view of the series connection present in the device 193 when using the semiconductor chips 170. Several semiconductor chips 100 are connected in the manner explained with reference to FIG. 8 by connecting bonding wires 165 to the front side contacts 101, 102. With respect to the semiconductor chip 170 to a ^¬ Fi gur 12 similar embodiment is obtained. The backside contact 173 a semiconductor chip 170 is connected via a contact surface 163 with the rear side contact 103 of a semiconductor chip 100 verbun ^¬ the. On the contact surface 163, the two chips 100, 170 are arranged. A connection of the respective semiconductor chip 170 with another, on the insulation 162 arranged

Semiconductor chip 100 is fabricated via bond wire 165 which is connected to front side contacts 102, 172. The contact diagrams make it clear that n-type and p-type semiconductor regions of the semiconductor chips 100, 170 are connected in series.

When semiconductor chips 180 are used, a structure comparable to FIG. 16 is present. Here, a semiconductor chip 180 is connected via a bonding wire 165 to a semiconductor chip 100, and via a contact surface 163 to another semiconductor chip 100 (see FIG.

The devices 191, 192, 193 represent possible examples by means of which the flexible contacting possibilities of a semiconductor chip 100, ie via the contacts 101, 102 or via the contacts 103, 102, become clear. There are possible other apparatuses which for example are charged at ^¬ other and may have geometric arrangements of chips. Furthermore, parallel connections or combinations of series and parallel connections of chips can be provided instead of series connections. The different devices can each be realized with a plurality of identically constructed semiconductor chips 100. An un ^¬ terschiedliches interconnection of the semiconductor chip 100 may, for example, available space, the design of a

Be given carrier or other components of a device.

Figure 17 shows in a plan view of another Va riante of a semiconductor chip 100. The semiconductor chip 100 sits ^¬ be a rectangular or square contour. The semiconducting ^¬ terchip 100 has two first contacts 101 and two second contacts 102 at the front. The contacts 101, 102 are arranged in the region of the corners of the semiconductor chip 100. The ^¬ se embodiment allows even greater flexibility for contacting the semiconductor chip 100. This can be re ^¬ latively space-saving and short electrical connections to other chips can be realized.

Apart from the illustration in Figure 17 other possible variants of the semiconductor chip 100 having a plurality of front side For ^¬ tenkontakten 101, 102 are conceivable. By way of example, three first contacts 101 and only one second contact 102, o, and also a different number and / or positioning of contacts 101, 102 may be considered.

On the basis of the following figures, further possible embodiments of optoelectronic semiconductor chips and

Lighting devices described. These have a similar structure as the embodiments described above. With regard to details of matching features, advantages, etc., reference is made to the above description.

Is forms Figure 18 shows a greatly simplified side view of another optoelectronic semiconductor chip 200, wel ^¬ cher for generating an electromagnetic radiation excluded. The semiconductor chip 200, which may be a light-emitting diode chip, has a contact 203 in the region of a front side 105 and two contacts 201, 202 in the region of a rear side 106 opposite the front side 105. For generating radiation, the semiconductor chip 200 has a semiconductor layer sequence 120, which is the one already mentioned

Structure, ie with an active zone 125 between a first and a second semiconductor region 121, 122 having different conductivity types (not shown in FIG. 18, see the embodiments of FIGS. 19 to 21). The contacts 201, 202, 203 may be formed of a metallic material and be in the form of contact surfaces. The backside contact 201 of the semiconductor chip 200 is electrically connected to the first semiconductor region 121. The further backside contact 202 is electrically connected to the second semiconductor region 122. The rear side contacts 201, 202 are also referred to below as first contact 201 and second contact 202. The front-side contact 203, which is likewise electrically connected to the first semiconductor region 121, is referred to below as the third contact or additional contact 203. The affiliation to the semiconductor regions 121, 122 and is indicated by the different contact representations. If the first semiconductor region 121 is n-type and the second semiconductor region 122 is p-type, the contacts can

201, 203 n contacts, and the contact 202 may be a p-contact. Alternatively, an inverse embodiment is possible.

The structure of the semiconductor chip 200 makes it possible to make contact via the contacts 201, 202 or via the contacts 203,

202. The semiconductor chip 200 therefore has, like the previously prescribed loading semiconductor chip 100, a high flexibility in loading ^¬ train to a use or wiring in a light-emitting device.

Possible configurations of the semiconductor chip 200 will be described in more detail with reference to the following FIGS. 19 to 21. It should be understood that features and details referred to in an embodiment may also be applicable with respect to other embodiments. Figure 19 shows a side view of an execution ^¬ form of a semiconductor chip 211 which can be provided for the semiconductor chip 200th In the semiconductor chip 211, the semiconductor layer sequence 120 on a substrate 140 angeord ^¬ net. In contrast to the semiconductor chips 111, 112, 113, the semiconductor layer sequence 120 is the back, and the Sub ^¬ strat 140 other hand, is provided on the front side. The semiconducting ^¬ terschichtenfolge 120 has a stepped shape, whereby the first and second semiconductor regions 121, 122 for a rücksei- tige contacting accessible sections have. In the ^¬ sen areas of the first and second contacts 201, 202 di ^¬ rectly on the first and second semiconductor region 121, 122 are arranged so that they are contacted directly by the contacts 201, 202.

The substrate 140 of the semiconductor chip 211 is electrically leit ^¬ capable and permeable to the erzeug ^¬ te in the active zone 125 radiation. The substrate 140 may be formed of doped Sic, for example. As a result of the transmissive Ausges ^¬ taltung the come of the semiconductor layer sequence 120 ^¬ de radiation coupled into the substrate 140, and are discharged through the substrate 140 again. On the substrate 140, the third contact 203 is arranged. The contact 203 is electrically connected to the first semiconductor region 121 via the conductive substrate 140.

FIG. 20 shows a side view of a further embodiment of a semiconductor chip 212 which may be provided for the semiconductor chip 200 of FIG. In this case, a backside semiconductor layer sequence 120 is likewise arranged on a conductive and radiation-permeable substrate 140. The second contact 202 is located directly on the second semiconductor region 122 of the Halbleiterschichtenfol- ge 120. The third contact 203 is integrally ^¬ arranged on the substrate 140 and connected across the substrate 140 to the first Halbleiterbe ^¬ rich 121st

The semiconductor chip 212 further includes a via 155. For this one is vertically through the second

Semiconductor region 122, the active region 125 and formed in the first semiconductor region 121 extending recess which is filled with an insulating layer 152 and with an electrically conductive layer 151. The conductive layer 151 contacts the first semiconductor region

121. Outside the plated-through hole 155 or in the region of the rear side 106, the insulating layer 152 has a laterally projecting partial region. In this area and on the Insulation layer 152, the first contact 201 is arranged. The first contact 201 may be a portion of the conductive layer 151 or a separate composites ^¬ ne with the layer 151 layer. Via the via 155, the first contact 201 is connected to the first semiconductor region 121.

Provide the semiconductor chips 211, 212, due to the Ausgestal ^¬ processing is with the front side provided for the transparent substrate 140, possible variants of a flip-chip structure. Therefore, it may be in the semiconductor chips 211, 212 be so-called volume emitter in which a radiation both can be emitted via a front surface or upwards as well as ^{seit ¬} lich.

FIG. 21 shows a further embodiment of a semiconductor chip 213 which may be provided for the semiconductor chip 200 of FIG. The semiconductor chip 213 may be a surface emitter, wherein in contrast to the semiconductor chips 211, 212, the semiconductor layer sequence is placed front side For ^¬ tig 120th The semiconductor layer sequence 120 is arranged with the second semiconductor region 122 on an electrically conductive substrate 130. Between the semiconductor layer sequence 120 and the substrate 130, an electrically conductive bonding layer may be provided (not Darge ^¬ asserted). The third contact 203 is on the first semiconducting ^¬ ders 121 of the layer sequence 120, and the second contact 202 is located at the back on the substrate 130th Via the substrate 130, the contact 202 is connected to the second semiconductor region 122.

The semiconductor chip 213 also has a Durchkontaktie ^¬ tion 155th This is a vertically through the sub ^¬ strat 130, the second semiconductor region 122, the active region 125 and formed extending recess in the first semiconductor region 121 into which is filled with an insulation ^¬ layer 152 and an electrically conductive layer 151st The layer 151 contacts the first semiconductor area 121. In the area of the rear side 106 has the isolati ^¬ onsschicht 152 a laterally projecting portion. In this area there is the first contact 201, wel ^¬ cher a portion of the layer 151 or may be a separate, adjacent to the layer 151 layer. About the

Through-hole 155, the first contact 201 is connected to the first semiconductor region 121.

The structure of the semiconductor chip 200 of FIG. 18, for which the embodiments of FIGS. 19 to 21 or other configurations can be provided, makes it possible to implement a lighting device in a flexible manner with tightly packed semiconductor chips. Possible embodiments are described in more detail below. Here, ER-, respectively, a carrier 160 neut used, and the chips are positioned in accordance with the scheme of Figure 5 and electrically connected together in Rei ^¬ he.

FIG. 22 shows a top view of a luminous device 291, in which (only) optoelectronic semiconductor chips 200 from FIG. 18 are arranged on a carrier 160. The semiconductor chips 200 are electrically connected to one another via a metallization of the carrier 160 in the form of correspondingly adapted connecting structures or contact surfaces 163. The carrier 160 further has, as shown in the associated side layer structure of Figure 23, a base substrate 161 and a large-area insulation 162 on which the contact surfaces 163 are arranged. Figure 24 illustrates detail of the present 291 series connection of the semiconductor chips at the on ^¬ direction

200. The semiconductor chips 200 are with the back side contacts

201, 202 on the contact surfaces 163 of the carrier 160 angeord ^¬ net. An attachment and electrical connection to the contact surfaces 163 may, for example, be realized via a solder or an electrically conductive adhesive (not shown). Each semiconductor chip 200 is connected to the rückseiti ^¬ gen contacts 201, 202 angeord- two contact surfaces 163 net. Therefore, in each case one ers ^¬ ter contact 201 and a second contact 202 of two adjacent semiconductor chips 200 are connected in a direct manner via a contact surface 163. As a result, in each case n-conducting and p-conducting semiconductor regions of adjacent semiconductor chips 200 are connected in series. The semiconductor chips 200 may include, for example, an n-type first semiconductor region 121 and a p-type second semiconductor region 122, whereby an n-type contact 201 is connected to a p-type contact 202, respectively. Alternatively, inverse polarities are possible. The additional contact 203 of the semiconductor chips 200 is not used in this embodiment.

Using the following figures further be Leuchtvorrichtun- gene having the semiconductor chip 200 described in which the auxiliary contact 200 is used clocking of 203 instead of the contact 201 for electrical con- at SämT ^¬ union or a portion of the semiconductor chip. Identical and equivalent compo ^¬ nents are not re-ben described in detail below. Instead, it is made to the above description Be ^¬ train. Also, features and details which are out ^¬ clearly called one embodiment, apply in relation to a different configuration. Fig. 25 is a perspective view of another one

Lighting device 292, in which a combination of optoelectronic semiconductor chips 200 with optoelectronic semiconductor chips 270 on a support 160 is used. The semiconductor chips 200, 270 are connected in series, wherein in each case a semiconductor chip 200 is connected to a semiconductor chip 270 in a periodic manner. A variant with semiconductor chips 280 instead of the semiconductor chips 270 will be described in more detail below. A series connection of the semiconductor chips 200, 270 is produced alternately via bonding wires 165 and contact surfaces 163 of the carrier 160. Each of the con ^¬ tact surfaces 163 carries two semiconductor chips 200, 270th The series connection of the semiconductor chips 200, 270 in the device 292 is illustrated in ^detail in FIG. 26. On the basis of the different contact representations, the structure of the semiconductor chips 270 is further indicated. A semiconductor chip 270 is formed similar to a semiconductor chip 200 for flexible contacting, and has two rear-side contacts 271, 272 and a front-side contact 273. The rear side contacts 271, 272 of a chip 270 are electrically connected to different semiconductor regions of a semiconductor layer sequence arranged on both sides of an active zone. The back contact 271 is connected to the ^¬ same semiconductor region as the front-side contact 273rd A semiconductor chip 270 may, for example, have a structure analogous to FIGS. 19 to 21.

The semiconductor chips 200, 270 are angeord ^¬ net with the rear side contacts 202, 272 on the contact surfaces 163 of the carrier 160 and, for example, via a solder or an electrically conductive adhesive ^¬ attached to this. In each two adjacent and on a common contact surface 163 arranged semiconductor chips 200, 270, the contacts 202, 272 electrically connected via the corresponding contact surface 163 verbun ^¬. In each case two adjacent semiconductor chips 100, 170 arranged on different contact surfaces 163, a front-side contact 273 is connected to a front-side contact 203 via a bonding wire 165. The contacts 201, 271 of the semiconductor chips 100, 170 remain unused in this embodiment. In the case of the semiconductor chips 200, 270, n-conducting and p-conducting semiconductor ^{regions of} adjacent semiconductor chips 200, 270 are likewise electrically connected in series. In this connection is indicated in Figure 26, that it is in transactions via the contact surfaces 163 interconnected contacts 202, 272 and the bonding wires 165 together peeled ^¬ th contacts 203, 273 to contacts of different polarities, which are electrically different with semiconductor regions conductivities are connected. The semiconductor Chips 200, 270 may be made identical for this purpose, but with reversed conductivities of the respective semiconductor regions of the semiconductor layer sequences. Figure 27 shows part of a modified Ausgestal ^¬ processing of the device 292, in which the semiconductor chips 270 are replaced by optoelectronic semiconductor chips 280th The Aufsichtsdarstellung of Figure 25 may be analogous to the application. Here, too, the semiconductor chips 200, 280 are connected in series alternately via bonding wires 165 and contact surfaces 163 of the carrier 160. A semiconductor chip 280 has a front-side contact 281 and a rear-side contact 282, which are electrically connected to different semiconductor regions of a semiconductor layer sequence arranged on both sides of an active zone. The semiconductor chips 200, 280 are arranged with the rear side contacts 202, 282 on the contact surfaces 163 of the carrier 160, and attached thereto, for example, via a solder or a conductive adhesive. In the case of two adjacent semiconductor chips 200, 280 arranged on a common contact surface 163, the back side contacts 202, 282 are electrically connected via the relevant contact surface 163. In each case two neighboring and ^¬ be arranged on different contact surfaces 163/2 chip 200, 280, a front side contact 203 is connected to a front side contact 281 via a bonding wire 165th The contacts 201 of the semiconductor chips 200 are not used in this embodiment.

Also in the embodiment of FIG. 27, alternating n-conducting and p-conducting semiconductor ^{regions of} the semiconductor chips 200, 280 are electrically connected in series. The contacts 202, 282 and the contacts 203, 281 are contacts Various ^¬ ner polarities, which are electrically connected to the respective semiconductor chips 100, 180 having the semiconductor regions of different conductivities.

FIG. 28 shows an overview of another

Lighting device 293 with semiconductor chips 200 and semiconductor chips are connected in series 270 or 280, which via bonding wires 165 and contact surfaces 163 ^¬ a carrier 160th The device 293 represents a combination of the devices 291, 292 explained above. The series connection present in the device 293 when using the semiconductor chips 270 is shown partially in FIG. Several semi ^¬ semiconductor chip 200 and the back contacts 201, 202 are connected in the explained with reference to Figure 24 manner via the contact surfaces 163rd With regard to a semiconductor chip 270, an embodiment comparable to FIG. 26 is present. The backside contact 272 of the semiconductor chip 270 is connected via a contact surface 163 with the backside contact 202 ei ^¬ nes semiconductor chips 200th On the contact surface 163, the two chips 200, 270 are arranged. A connection of the semiconductor chip 270 to another semiconductor chip 200 is realized via a bonding wire 165, which is connected to the front side contacts 203, 273. Based on the contact diagrams, the series connection of n-type and p-type semiconductor regions of the semiconductor chips 200, 270 becomes clear.

When using semiconductor chips 280, a structure comparable to FIG. 29 is present. Here, a semiconductor chip 280 is connected via a contact surface 163 to a semiconductor chip 200, and via a bonding wire 165 to another semiconductor chip 200 (see FIG.

The devices 291, 292, 293 represent possible examples by means of which the flexible contacting possibilities of a semiconductor chip 200, ie via the contacts 201, 202 or via the contacts 203, 202, become clear. There are other devices conceivable which are charged, for example, to other ^¬ and geometrical arrangements of chips which may have from compounds series parallel connections, or com- binations of series and parallel connections of chips instead. The different devices can each be realized with a plurality of identically constructed semiconductor chips 200. FIG. 30 shows a further embodiment of a semiconductor chip 200, in which, in contrast to FIG. 18, two third contacts 203 are arranged in the region of the front side 105. The two contacts 203 are located at the edge of each

Semiconductor chips 200. This embodiment allows an even greater flexibility for the contacting of the semiconductor chip 200. As a result, relatively space-saving and short electrical connections to other chips can be realized.

This applies in the same way to the embodiment of a semiconductor chip 200 shown in FIG. Shown here is a rear side of the semiconductor chip 200. The semiconductor chip 200 has, in addition to a second contact 202, two first contacts 201 arranged in the region of corners.

Apart from FIGS. 30, 31, further possible variants of the semiconductor chip 200 are conceivable, which may have different numbers and / or positions of contacts 201, 202, 203. It is also possible to combine the embodiments described in FIGS. 30 and 31 in a semiconductor chip 200.

The embodiments explained with reference to the figures represent preferred or exemplary embodiments of the invention. In addition to the described and illustrated embodiments, further embodiments are conceivable which may comprise further modifications or combinations of features. It is particularly possible to realize flexible contactable semiconductor chips different from the dargestell ^¬ th in the figures and described embodiments with a different structure. For lighting devices, further embodiments are conceivable instead of the examples shown. Furthermore, other materials may be used in place of the materials listed above.

It is further pointed out the possibility to realize a Vorrich ^¬ device with optoelectronic semiconductor chips, whose semiconductor layer sequences are based on different semiconductor materials. In this way, the semiconductor chips can emit light radiation of different colors, for example blue and red. It is possible that the semiconductor chips differ from each other by the semiconductor materials, and are otherwise substantially identical in construction.

Furthermore, semiconductor chips can be combined with other components. This includes, for example, using one or more conversion materials, for example in the form of platelet-shaped and on the semiconductor chips is arrange ^¬ th conversion elements to a primary light radiation generated by the semiconductor chip at least partially in a rated secondary light radiation of a different wavelength range Co ^¬ which also to konvertie ^¬ ren in a plurality of secondary light rays).

Another variant is to use for direct electrical connection of front side contacts of semiconductor chips no bonding wires, but other contact structures. Consider, for example, the use of a CPHF metallization (Compact Planar High Flux). The preparation can be done by a sealing compound layer is applied (for example, silicone) to a loaded with semiconductor chips support a light emitting device, are generated at the front-side contacts zoom reaching openings in the encapsulation ^¬ layer and subsequently metal contact ^¬ structures on the cast layer and forms are excluded in the apertures to the front-side contacts heranrei ^¬ chen.

A lighting device may also have further components. This includes, for example, an optical system, which may comprise a lens and / or a reflector. A high packing density of semiconductor chips, preferably in the form of surface emitters, enables a high luminance density, whereby the optical system can be made small.

Although the invention in detail by the preferred embodiment has been illustrated and described in detail, the invention is not limited ^¬ by the disclosed examples and other variations can be derived therefrom by the skilled artisan without departing from the scope of the invention.

Reference sign list

100 semiconductor chip

101, 102 contact

103 contact

105 front side

106 Backside

111, 112 semiconductor chip

113 semiconductor chip

120 semiconductor layer sequence

121, 122 semiconductor region

125 Active Zone

130 substrate

131 Conductive layer 132 Insulation layer

133 current spreading layer

135 through-hole

140 substrate

151 Conductive layer 152 Insulation layer

155 via

160 carriers

161 base substrate

162 insulation

163 contact area

165 bonding wire

168 Chipposition

170 semiconductor chip

171, 172 contact

173 contact

180 semiconductor chip

181, 182 contact

191, 192 device

193 device

200 semiconductor chip

201, 202 contact

203 contact

211, 212 semiconductor chip Semiconductor chip semiconductor chip, 272 contact

Contact

Semiconductor chip, 282 contact

, 292 device

contraption

Claims

claims

1. An optoelectronic semiconductor chip (100, 111, 112, 113, 200, 211, 212, 213), comprising: a semiconductor layer sequence (120) comprising a ers ^¬ th semiconductor region (121), a second semiconductor region (122) and an interposed active Zone (125) for generating radiation; a first contact (101, 201) electrically connected to the first semiconductor region (121); a second contact (102, 202) electrically connected to the second semiconductor region (122); and a third contact (103, 203), which is electrically connected to the first semiconductor region (121), wherein the first contact (101, 201) and the third Kon ^¬ clock (103, 203) in the region of opposite sides of the semiconductor chip are arranged.

2. Optoelectronic semiconductor chip claim 1,

wherein the first and second contact (101, 102) are arranged in the region of a front side (105) of the semiconductor chip front-side contacts, and wherein the third contact (103) is arranged a the region of a rear side (106) of the semiconducting ^¬ terchips backside contact.

3. Optoelectronic semiconductor chip according to claim 1,

wherein the first and second contact (201, 202) in the region of a back side (106) of the semiconductor chip arranged rear side contacts, and wherein the third contact (203) in the region of a front side (105) of the semiconductor chip ^¬ arranged front side contact.

4. Optoelectronic semiconductor chip according to one of the preceding claims,

further comprising at least one of the following:

an electrically conductive substrate (130, 140);

an electrically conductive substrate (140) which is permeable to the radiation ^generated in the active zone (125);

a via (135, 155).

5. Optoelectronic semiconductor chip according to one of the preceding claims,

wherein the first and second contacts (101, 102) are each arranged laterally next to the semiconductor layer ^sequence (120).

6. Optoelectronic semiconductor chip according to one of claims 1 to 4,

wherein the semiconductor layer sequence (120) has a step shape, and wherein the first contact (101, 201) on the first semiconductor region (121) and the second contact (102, 202) on the second semiconductor region (122) are arranged.

7. Optoelectronic semiconductor chip according to one of the preceding claims,

wherein the opposite sides of the semiconductor chip are a front side (105) and a back side (106) of the semiconductor chip.

8. Optoelectronic semiconductor chip according to one of the preceding claims,

wherein the first and second contact (101, 102, 201, 202) are integrally ^¬ arranged in the same side of the semiconductor chip.

9. Optoelectronic semiconductor chip according to one of the preceding claims,

wherein the semiconductor chip over the first and second Contact (101, 102, 201, 202) or via the third and second contact (102, 103, 202, 203) is contactable to an electrical connection to the first and the second semiconductor region (121, 122) for inducing a current flow through the active zone (125) ^{herzustel ¬} len.

Optoelectronic semiconductor chip according to one of the preceding claims,

comprising a plurality of first, a plurality of second and / or more ^¬ re third contacts.

Apparatus comprising a support (160) and a plurality of optoelectronic semiconductor chip according to any preceding ^¬ preceding claim.

Device according to claim 11,

wherein the plurality of semiconductor chips (100) are each two front-side contacts (101, 102) and a Rückseitenkon ^¬ clock (103), and wherein the front-side contacts (101, 102) of two of the semiconductor chips (100) via a contact structure (165) electrically connected ,

Device according to one of claims 11 or 12, comprising a plurality of first optoelectronic semiconductor chips ^¬ (100), each having two front side contacts (101, 102) and a rear side contact (103), wherein the device at least one second opto ^¬ lectronic semiconductor chip (170, 180) having a front-side contact (172, 181) and a Rücksei ^¬ tenkontakt (173, 182),

wherein the front side contact (172, 181) of the second semiconductor chip (170, 180) and a front side contact

(102) a first semiconductor chip (100) via a clock-Kon ^¬ structure (165) are electrically connected,

and wherein the rear-side contact (173, 182) of the second semiconductor chip (170, 180) and the rear-side contact

(103) another of the first semiconductor chip (100) are electrically connected via a connection structure (163) of the carrier (160).

Device according to claim 11,

wherein the plurality of semiconductor chips (200) each have two rear side contacts (201, 202) and a Vorderseitenkon ^¬ clock (203), and wherein the backside contacts (201, 202) of two of the semiconductor chips (200) via a connection structure (163) of the support ( 160) are electrically connected.

Device according to one of claims 11 or 14, comprising a plurality of first optoelectronic semiconductor chips ^¬ (200), each having two rear side contacts (201, 202) and a front side contact (203) aufwei ^¬ sen,

said apparatus comprising at least one second optoe ^¬ lektronischen semiconductor chip (270, 280) having a front side contact (273, 281) and a back print ^¬ tenkontakt (272, 282);

wherein the rear side contact (272, 282) of the second half ^¬ semiconductor chip (270, 280) and a back contact (202) of a first semiconductor chip (200) via a Verbin ^¬ making structure (163) of the carrier (160) are electrically connected,

and wherein the front-side contact (273, 281) of the second semiconductor chip (270, 280) and the front-side contact (203) of another of the first semiconductor chip (200) are electrically connected via a contact structure (165).