Classifications

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  • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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  • H01L21/02436—Intermediate layers between substrates and deposited layers
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  • H01L21/02612—Formation types
  • H01L21/02617—Deposition types
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  • H01L33/005—Processes
  • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
  • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
  • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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  • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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  • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
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  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/26—Materials of the light emitting region
  • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
  • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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  • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
  • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
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  • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
  • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction

Definitions

• the invention particularly relates to a method of manufacturing a semiconductor structure and a semiconductor compound having such a structure.
• Controlled manufacturing processes of semiconductor structures such as gallium nitride (GaN) wires must take into account the constraints related to the materials constituting them, as well as those related to the type of semiconductor structures and the materials composing the support.
• a process for manufacturing structures comprising gallium (Ga), such as gallium nitride (GaN) semiconductor wires, on a surface comprising silicon (Si) remains particularly problematic insofar as a phenomenon of silicon etching (Si) by gallium (Ga) competes with the phenomenon of crystallization of the material to be deposited.
• the present invention aims to remedy these disadvantages.
• An object of the invention is therefore to provide a method of manufacturing a semiconductor structure on the surface of a support, the structure comprising gallium and the surface of the support comprising silicon, not having the problems inherent to the use of an aluminum nitride nucleation (AIN) layer and does not require lengthy adaptation procedures.
• AIN aluminum nitride nucleation
• the invention relates to a method of manufacturing at least one semiconductor structure comprising the following steps:
• the at least one semiconductor structure in contact with the silicon carbide layer, said structure comprising at least one part, which is said contact portion, in contact with the surface of the silicon carbide layer, which comprises gallium.
• a layer of silicon carbide is described as amorphous when it has a diffraction pattern in electron microscopy in transmission, in correspondence with the layer itself, comprising one or more diffuse rings or diffuse spots.
• the corresponding transmission electron microscopy diffraction pattern exhibits diffraction spots associated with the crystals as well as one or more diffuse rings or diffuse spots associated with the amorphous parts of the layer.
• Such a method allows the formation of a semiconductor structure having improved electrical contact with a semiconductor structure formed according to a prior art method using an aluminum nitride (AlN) buffer layer, this without requiring lengthy adaptation procedures.
• AlN aluminum nitride
• SiC silicon carbide
• when in an amorphous form has, as shown by the work of Losurdo et al. published in 2005 in the journal "Journal of Applied Physics" No. 97, pages 103504, a band gap of 2.5 eV, a bandgap more than two times lower than that of aluminum nitride.
• silicon carbide is a chemically stable material, and therefore may be prone to react with gallium (Ga), this up to temperatures above 1000 ° C.
• Ga gallium
• a silicon carbide layer makes it possible to protect the silicon surface from any gallium etching reaction thereon during the step of forming the at least one semiconductor structure comprising gallium.
• the silicon carbide in its amorphous form makes it possible, by the absence of an epitaxial relationship with respect to the surface of the substrate on which it is in contact, to relax any constraints that may exist between the surface of silicon and the structure that is formed on the surface of the silicon carbide layer.
• a structure formed by such a method has little or no dislocation despite the possible presence of a strong mismatch between the silicon surface and the material forming the contact part of the structure.
• such a method because of the role of the amorphous silicon carbide layer in stress relaxation and for the protection it offers for the silicon surface, does not therefore require a long adaptation procedure for each type. of structure to form.
• Such a method is therefore well suited for the growth of structures regardless of their type, unlike the methods of the prior art for which the growth of structures takes place directly on a silicon surface.
• the at least one structure may be a semiconductor wire.
• semiconductor wire is understood to mean a semiconducting structure having 3 dimensions, one of whose dimensions, called longitudinal dimensions, is at least 5 times and preferably, at least 10 times, larger than the larger of the other two dimensions, which are called lateral.
• semiconductor wire includes nano-son semiconductors, that is to say the son whose lateral dimensions are less than or equal to 100 nm, and semiconductor micro-son, that is to say the son whose lateral dimensions are between 100 nm and 100 ⁇ .
• Such a method is particularly suitable for the growth of semiconductor wires by allowing the possibility of forming a wire having a good electrical contact with the silicon surface.
• the thickness of the silicon carbide layer may be less than 10 nm and preferably 5 nm.
• a thickness of the silicon carbide layer of less than 10 nm and preferably less than 5 nm makes it possible to transmit through the silicon carbide layer, despite its amorphous nature, the crystalline orientation of the silicon surface at the less a semiconductor structure.
• the step of forming the silicon carbide layer may comprise a step of chemical deposition on the semiconductor silicon surface, such as plasma enhanced chemical vapor deposition.
• Such growth methods make it possible to provide amorphous silicon carbide layers with a well-controlled thickness and composition.
• the contact portion may be gallium nitride.
• a structure comprising a contact gallium nitride (GaN) portion particularly benefits from the use of an amorphous silicon carbide layer.
• the structure may be a gallium nitride structure.
• a gallium nitride (GaN) structure benefits particularly from the use of an amorphous silicon carbide layer.
• the step of forming the silicon carbide layer may comprise the following substeps:
• Such a deposition procedure makes it possible to obtain good control of the thickness of the silicon carbide layer over the entire thickness of the silicon surface, whatever the size of this surface.
• the sub-step of removing a portion of the thickness of the amorphous silicon carbide layer can be obtained by a mechanical method such as for example a polishing procedure of the thick silicon carbide layer.
• the step of forming the at least one structure may comprise the following substeps: forming a mask in contact with the surface of the silicon carbide layer, said mask leaving free at least a surface portion of the silicon carbide layer which is said forming portion,
• the mask may comprise silicon nitride or silica.
• Such a method allows a growth of the at least one structure that is localized by the definition of the at least one formation portion.
• a method is particularly advantageous in the case where the structure must be related to other structures in the substrate.
• the mask when the material component is adapted, can also passivate the portion of the substrate surface on which the at least one structure has not grown.
• the step of forming the at least one structure may comprise the sub-step of depositing a first material comprising gallium under deposition conditions suitable for the formation of self-organized structures on the surface of the carbide layer of silicon.
• Such a growth process makes it possible to form the semiconductor structures over the entire surface of the silicon carbide layer, thus making it possible to functionalise the latter in a single step.
• the step of forming the at least one structure may comprise the following substeps:
• Such a method allows a growth of the at least one structure which is localized by the definition of the at least one formation portion without the latter being found covered with a mask.
• the contact portion of the structure may be formed of a first material comprising gallium, the step of forming the at least one structure may comprise a substep of forming a layer of the first material in contact with at least one a portion of the silicon carbide layer, a portion of said layer forming part of the at least one structure.
• a method implementing a layer of the first material offers the possibility of forming a structure with its contacting part which has a good electrical contact since it is obtained by means of the layer of the first material.
• the contact portion of the structure may be formed of a first material comprising gallium,
• the step of forming the at least one structure may comprise the following substeps:
• the mask when the material component is adapted, can also passivate the surface of the substrate on which the at least one structure has not grown.
• a layer of the first material offers the possibility of forming a structure with its part in contact with the layer of the first material with good crystallographic quality since it is possible to form by homoepitaxy.
• the contact portion of the structure may be formed of a first material having gallium, the step of forming the at least one structure may comprise the following substeps of:
• first material comprising gallium under suitable deposition conditions for the formation of self-organized structures on the surface of the layer of the first material.
• Such a growth process makes it possible to form the semiconductor structures over the entire surface of the silicon carbide layer, thus making it possible to functionalize the latter surface in a single step.
• the use of a layer of the first material offers the possibility of forming the structure with its part in contact with the layer of the first material with good crystallographic quality throughout its thickness, which comprises a step of growth through homoepitaxy.
• the contact portion of the structure may be formed of a first gallium-containing material.
• the step of forming the at least one structure may comprise the following sub-steps:
• the invention also relates to a semiconductor component comprising:
• a substrate comprising at least one semiconductor silicon surface
• an amorphous silicon carbide layer in contact with at least a portion of the semiconductor silicon surface
• At least one semiconductor structure in contact with the silicon carbide layer the part of the structure in contact with the silicon carbide layer comprising gallium.
• Such a component can be obtained by a manufacturing method that does not require a long adaptation procedure when it is put in place with an electrical contact between the at least one wire and the silicon surface improved with respect to that of a component of the prior art comprising a layer of aluminum nitride (AlN).
• AlN aluminum nitride
• the at least one structure can be a semiconductor wire
• the silicon carbide layer has a thickness of less than 10 nm and preferably of 5 nm.
• a layer of a first material comprising gallium may be provided, the structure comprising a portion of the layer through which it is in contact with the silicon carbide layer.
• the structure may comprise a gallium nitride body through which it is in contact with the silicon carbide layer.
• FIG. 1 illustrates an example of a semiconductor component according to a first embodiment of the invention
• FIGS. 2a to 2g illustrate the main steps of a method of manufacturing a component as illustrated in FIG.
• FIG. 3 illustrates a semiconductor component according to a second embodiment, in which it provides a layer of a first material in contact with the silicon carbide layer.
• the present invention relates to the manufacture of semiconductor structures, for example of microfilts, nanowires or pyramid-shaped elements.
• the described embodiments relate to the manufacture of microfilts or nanowires.
• these embodiments can be implemented for the manufacture of semiconductor structures other than microwires or nanowires, for example for the manufacture of three-dimensional pyramid-shaped structures.
• yarns, nanowires or semiconductor microwires are understood to mean semiconductor structures having three dimensions and of elongate shape, of which two are of the same order of magnitude between 5 nm and 2.5 ⁇ , the third dimension being at least equal to 2 times, 5 times or preferably 10 times the larger of the other two dimensions.
• FIG. 1 illustrates a semiconductor component 100 comprising semiconductor structures according to the invention which are semiconductor wires, which is intended for light emission.
• the component 100 illustrated in Figure 1 is a component according to a particular application of the invention which is adapted to emit light whose wavelength is in the range of wavelength of the visible. Values and materials, when cited in relation to the particular application, are given by way of example only and are therefore not limiting of the invention.
• the component 100 illustrated in FIG. 1 comprises:
• 130 semiconductor son having at least one portion 131, said contact portion, in contact with the silicon carbide layer 120.
• the substrate 110 is a preferentially semiconducting plane support and having a semiconductor silicon 111 surface.
• the substrate 110 may be a semiconductor silicon substrate.
• the substrate 110 in the case where during the operation of the component the wires 130 are polarized through the substrate 110, presents a majority carrier concentration of at least 10 18 cm 3 .
• the conductivity type of the substrate is a first type of conductivity.
• the substrate 110 is a planar silicon substrate whose conductivity type is that for which the majority carriers are electrons.
• the polarization of the wires 130 being made through the substrate 110, the majority carrier concentration is at least 10 18 cm ⁇ 3 .
• the silicon carbide layer 120 is in contact with the silicon surface 111 and is an amorphous silicon carbide layer.
• An amorphous silicon carbide layer is understood to mean that the silicon carbide layer 120 has, in correspondence with the layer itself, a diffraction pattern in transmission electron microscopy comprising one or more diffuse rings or diffuse spots.
• the silicon carbide layer 120 has a thickness which is between 1 and 100 nm and is preferably between 1 and 10 nm and even more advantageously between 1 and 5 nm. According to another possibility for which a large part of the conductivity between the wires 130 and the substrate 110 is obtained by tunneling effect, the thickness of the silicon carbide layer 120 is less than 3 nm.
• the silicon carbide layer 120 may comprise a concentration of doping elements which are adapted to provide majority carriers corresponding to the first type of conductivity to the silicon carbide layer 120.
• doping elements in the case where during operation of the component son 130 are biased through the substrate 110, are adapted to allow ohmic contact between the substrate 110 and the contact portion 131 of the son 130, that is to say they provide majority carriers of the first type conductivity.
• the majority carriers of the silicon carbide layer 120 may be provided by the crystalline defects of the silicon carbide layer 120.
• the silicon carbide layer 120 is preferably adapted to present a type of conductivity for which the majority carriers are electrons.
• the majority carrier concentration of the silicon carbide layer 120 is preferably greater than 10 18 cm 3 .
• the component 100 also comprises, in contact with the silicon carbide layer 120, a mask 140.
• the mask 140 may be a mask conventionally used in the microelectronics industry such as, for example, a silica Si0 2 mask, silicon nitride of the S13N4 type, or of the Si x Ni y type , or else Ti titanium.
• the mask 140 is configured to cover the areas of the silicon carbide layer 120 that are not in contact with the wires 130.
• the mask 140 forms a protective layer of the areas of the silicon carbide layer 120 that are not in contact with the wires 130.
• a suitable material such as silicon nitride S13N4
• the mask is preferably in a silicon nitride of the type Si x Ni y random such as in particular described in the document WO2012 / 136665.
• the portions 121 of the surface of silicon carbide 120 which are not covered by the mask 140 are called forming portions.
• the wires 130 are each in contact with the silicon carbide surface 120 on one of the forming portions 121 of the silicon carbide surface 120.
• Each wire 130 in the configuration illustrated in FIG. 1, comprises:
• a wire body 131 by which they are in contact with the layer of silicon carbide 120, the wire body 131 being of the first type of conductivity, an active zone 132, preferably of the unintentionally doped type and comprising a carrier confinement system, said active zone 132 being in contact with the wire body 131 at the end of the wire body which is opposite to the layer of silicon carbide 120,
• a zone 133 of the second type of conductivity in contact with the active zone 132, so as to form with the wire body 131 of the first type of conductivity a semiconducting junction extending in the active zone 132.
• the majority carrier concentration in said zone is that of a material in which no doping elements have been intentionally introduced. that is, adapted to provide carriers, and which then has a majority carrier concentration which is said to be unintentionally doped.
• the value and the type of carriers in an unintentionally doped type zone are related to the formation process of said zone.
• each of the wires 130 extends longitudinally from the forming portion 121 of the silicon carbide layer 120 in a direction substantially perpendicular to the surface 111 of the substrate 110.
• the lateral dimensions of each of the bodies of wire 131 correspond to that of the forming portion corresponding to said wire body 131.
• each wire body 131 has a constant lateral section which may be, for example, circular.
• the diameter of the lateral section of each of the yarn bodies is between 5 nm and 2.5 ⁇ m.
• the length of each wire body 131 is between 50 nm and 50 ⁇ .
• Each wire body 131 is formed in a first semiconductor material comprising gallium Ga, such as, for example GaN gallium nitride, gallium arsenide GaAs or indium gallium arsenide In x As x vering with x being between 0 and 1.
• the wire bodies 131 have the first conductivity type, preferably with a majority carrier concentration of greater than 10 18 cm 3 .
• the wire body 131 of each wire 130 forms a contact portion of said wire 130.
• each wire body 131 is gallium nitride GaN.
• the wire bodies 131 have a conductivity type for which the majority carriers are electrons. According to this same particular application, the majority carrier concentration in each body is greater than or equal to 10 18 cm 3 .
• Each active zone 132 is in contact with the end of the corresponding wire body 131 which is opposed to the silicon carbide layer 120. Each active zone is in contact over a portion of the length of the corresponding wire body 131 which represents a proportion of length between one tenth and one half of the total length of the wire body 131.
• Each active zone 132 is formed by a semiconductor layer which is preferably of the unintentionally doped type. At least a portion of each of the active zones 132, and preferably all of them, has a direct gap so as to allow radiative electron-hole pairs recombinations in the active zone 132. According to a particularly advantageous possibility of the invention, when the wires 130 are light-emitting wires, each of the active zones 132 comprises at least one confinement means for at least one type of carrier such as a plurality of potential wells.
• the material having such a direct gap comprises a maximum of energy of its valence band and a minimum of energy of its conduction band which are at a minimum. value of the wave vector k substantially also in the energy dispersion diagram of said material.
• each active area 132 is formed of a layer of gallium nitride in which are arranged the quantum wells in gallium arsenide indium-type In x vering x As, the dimensions and proportion x indium being adapted according to the emission wavelength of the corresponding wire 130.
• Each zone 133 of the second type of conductivity is in contact with the corresponding active zone 132 so that said active zone 132 forms an interface between the wire bodies 131 and corresponding zone 133.
• the zones 133 of the second type of conductivity are formed of at least one semiconductor layer of the second conductivity type and are adapted to be electrically contacted by means of polarization means.
• each of the zones 133 of the second type of conductivity comprises two semiconductor layers 133a, 133b, a first layer 133a adapted to form with the wire body 131 a semiconductor junction in the active zone 132 and a second layer 133b adapted to promote an ohmic contact with a polarization means.
• said first and second layers 133a, 133b are both of the first type of conductivity.
• the zones 133 of the second type of conductivity are each formed by a first GaN gallium nitride layer 133a in contact with the corresponding active zone 132 which is in contact with a second layer 133b of aluminum-gallium nitride.
• the first and second layers 133a, 133b are both of a conductivity type for which the majority carriers are holes.
• Each zone 133 is in contact with a polarization means adapted to electrically contact said zone.
• Said means, for wires 130 adapted for light emission, are adapted to electrically contact the zones of the second conductivity type while allowing at least a portion of the light emitted into the active zones 132.
• Such polarization means can in particular take the form of a semi-transparent layer, such as an indium-tin oxide layer (better known by its acronym ITO) or nickel-gold (Ni / Au) supplemented by a comb contact according to a configuration similar to that described in patent FR 2 922 685.
• FIGS. 2a to 2g illustrate a method of manufacturing a component as illustrated in FIG. 1. Such a method comprises the following steps of:
• a hard mask 140 of silicon nitride or silicon dioxide in contact with the surface of the silicon carbide layer 120 which is opposite to the substrate 110, the hard mask 140 being adapted to leave free only the formation portions 121 of the silicon carbide layer 120, as illustrated in FIG. 2b,
• the wire bodies 131 each in contact with a forming portion 121 of the silicon carbide layer 120, the growth outside the forming portions 121 being inhibited by the hard mask 140, the wire bodies 130 being made in a first semiconductor material comprising gallium Ga, as illustrated in FIG. 2c,
• first layers 133a of the second conductivity type each in contact with a corresponding active zone 132, each of the first layers being adapted to form with the corresponding wire body 131 a semiconductor junction extending in said active zone 132, as is illustrated in Figure 2e,
• each of the second layers 133b being adapted to form an ohmic contact with a polarization means, as illustrated in FIG. 2f, forming a biasing means in contact with each of the second layers 133b, said biasing means being adapted to electrically contact the zones 133 of the second conductivity type while allowing at least a portion of the light emitted into the active areas 132 as shown in Figure 2g.
• the silicon carbide layer 120 may be formed, for example, during a physical deposition of silicon carbide obtained, such as by sputtering of the radiofrequency type.
• a physical deposition of silicon carbide obtained such as by sputtering of the radiofrequency type.
• the step of forming the silicon carbide layer 120 may comprise the following sub-steps:
• the sub-step of removing a part of the thickness of the thick amorphous silicon carbide layer can be obtained by a mechanical method such as for example a polishing procedure of the thick layer of carbide. silicon.
• This same sub-step can also be obtained by a chemical method such as, for example, by reactive ion etching.
• the substrate 110 and the silicon carbide layer 120 may be subjected to temperatures sufficiently high to partially crystallize the carbide layer.
• silicon 120 may, in the final component, further comprise crystalline areas.
• the crystalline zones have at least two zones having either different crystalline orientations from each other or different silicon carbide polytypes, each zone forming a different crystalline grain.
• the corresponding transmission electron microscopy diffraction pattern exhibits diffraction spots associated with the crystals as well as one or more diffuse rings or diffuse spots associated with the crystals. amorphous parts.
• FIG. 3 illustrates a component 100 according to a second embodiment of the invention.
• a component differs from a component according to the first embodiment in that it further comprises a semiconductor layer 125 comprising gallium (Ga) in contact with the silicon carbide layer 120, each wire having a portion 131b of said semiconductor layer 125.
• Ga gallium
• a component 100 therefore comprises a semiconductor layer 125 of a first semiconductor material comprising gallium in contact with the silicon carbide layer 120 on its face which is opposite to the substrate 110.
• the semiconductor layer 125 has a thickness of between 1 and 5 nm.
• the semiconductor layer 125 has the first conductivity type and has a majority carrier concentration sufficient to provide good electrical contact with the silicon carbide layer 120.
• Each wire body 131 comprises the portion 131b of the semiconductor layer 125 which is between the silicon carbide layer 120 and the remainder 131a of the corresponding wire body 131.
• the semiconductor layer 125 and the wire bodies 131b are made of the first semiconductor material.
• the semiconductor layer 125 and the wire bodies 131b have the first type of conductivity.
• the majority carrier concentration of the semiconductor layer 125 and the wire bodies 131b is adapted to provide ohmic contact with the substrate through the silicon carbide layer 120.
• the semiconductor layer 125 and the wire bodies 131b preferably have a majority carrier concentration greater than 10 18 cm 3 .
• the first material is gallium nitride.
• the semiconductor layer 125 and the wire bodies 131b have a conductivity type for which the majority carriers are electrons.
• the semiconductor layer 125 and the wire bodies 131b have a majority carrier concentration preferentially greater than 10 18 cm 3 .
• a method of manufacturing a component 100 according to this second embodiment differs from a method of manufacturing a component 100 according to this second embodiment in that the step of forming the semiconductor wire bodies 131 comprises the following substeps:
• the wire bodies 131 comprise the portions 131b of the semiconductor layer 125 between each of the wire bodies 131 and the silicon carbide layer 120 .
• the structures described are semiconductor wires having a shell configuration, that is to say an active zone covering the end of a longitudinal wire body as illustrated on FIG. Figure 1, the invention is not limited to this configuration alone and also relates to structures having another type of configuration.
• the invention also covers other types of semiconductor structures such as semiconductor wires having a wire configuration, that is to say having a junction on a plane perpendicular to the axis of the wire, or structures of the pyramidal type. .
• the step of growth of the structures is carried out by means of a mask by growth of threads on mask-free surface portions, the growth of the threads on the remainder of the surface being inhibited by the presence of the mask.
• structures, whether they are son or not, can also be obtained by a growth step of another type without departing from the scope of the invention.
• the structures can be formed, without departing from the scope of the invention, by a process comprising a step of depositing a first material comprising gallium under deposition conditions suitable for the formation of self-organized structures on the surface of the silicon carbide layer.
• the method may also include the following steps:
• the method may comprise the following steps:

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• 2013
  • 2013-06-21 FR FR1355923A patent/FR3007574B1/fr active Active
• 2014
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