WO2014201865A1 - 一种nand闪存设备及其随机写入方法 - Google Patents

一种nand闪存设备及其随机写入方法 Download PDF

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Publication number
WO2014201865A1
WO2014201865A1 PCT/CN2014/070547 CN2014070547W WO2014201865A1 WO 2014201865 A1 WO2014201865 A1 WO 2014201865A1 CN 2014070547 W CN2014070547 W CN 2014070547W WO 2014201865 A1 WO2014201865 A1 WO 2014201865A1
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nand flash
volatile memory
flash memory
memory device
data
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PCT/CN2014/070547
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English (en)
French (fr)
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楚一兵
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深圳市瑞耐斯技术有限公司
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Publication of WO2014201865A1 publication Critical patent/WO2014201865A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

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  • the invention belongs to the technical design field of NAND flash memory devices, and in particular relates to a NAND flash memory device and a random writing method thereof.
  • NAND flash memory chips are widely used in computer systems, digital cameras, portable music due to their low power consumption, better physical shock resistance and electromagnetic compatibility, smaller physical size, and lighter weight.
  • electronic devices such as players, USB flash drives, and memory cards.
  • NAND flash chips have different capacities and configurations depending on the technology and model of manufacture and use.
  • a NAND flash chip includes a number of blocks, each block being divided into pages, the size of which may be, but not limited to, 256K, 512K, 1M or 2M bytes, and the number of pages may be 32, 64, 128. Or more, the size of each page may be, but not limited to, 256, 512, 1K, 2K, 4K, 8K bytes or more.
  • a NAND flash device refers to a storage device based on a NAND flash chip.
  • a typical structure of a NAND flash memory device provided by the prior art is shown in FIG. 1, including: a virtual file system, a flash controller, at least one NAND flash chip, and a volatile memory.
  • the virtual file system refers to the NAND flash device used in conjunction with The interface part connected to the external master device, for example, the SATA interface in the SSD hard disk, the USB interface in the USB disk, etc.; the volatile memory is mainly used to store temporary data during system operation, a mapping table of the flash transport layer, or as an external A buffer for transferring data between master devices, which may typically be: random access memory (Random) Access Memory, RAM), Synchronous Dynamic Random Access Memory, SDRAM), Double Rate Synchronous Dynamic Random Access Memory (Double Data Rate, DDR), etc.
  • SDRAM and DDR are generally used in consideration of capacity and price.
  • NAND flash devices It is well known that basic operations on NAND flash devices include read operations, write operations, and erase operations. Among them, the write operation and the read operation are performed in units of pages, and the erase operation is performed in units of blocks, and the block containing the page must be erased before the page is written. Due to the fact that the NAND flash chip cannot be rewritten in situ and the write operation is performed in units of pages, in the prior art, when the content stored in the NAND flash device is replaced, the flash controller needs to first be in the NAND flash chip. The corresponding page is read and saved to the volatile memory, and then the corresponding content is replaced with the new data, and then the data is rewritten into the NAND flash chip.
  • the flash controller needs to first read the 4K byte page from the NAND flash chip and save it to volatile.
  • the 512 bytes are replaced with new data.
  • the replaced data needs to be rewritten immediately.
  • the entire replacement process involves one read operation, one write operation, and a combination of data, while the write operation to the NAND flash chip takes much longer than the time to perform the read operation, thus making the NAND flash device random. Write speed is slow and performance is poor.
  • the NAND storage device uses the volatile memory to store the mapping table of the flash transport layer, after the NAND flash device is powered down and powered back on, it is necessary to reconstruct the mapping table of the flash transport layer, thereby reducing the NAND flash device. Electric starting speed.
  • the present invention is implemented as such a NAND flash memory device, the NAND flash memory device comprising:
  • At least one NAND flash chip At least one NAND flash chip
  • non-volatile memory for storing a mapping table of a flash transport layer and buffering transmission data between the external host device and the NAND flash chip
  • a flash controller configured to receive, by the virtual file system, an operation instruction and a logical address of the external host device, and to find the received logic by searching a mapping table of the flash transport layer stored by the non-volatile memory The address is converted into a physical address of the NAND flash chip, and then a corresponding operation on the NAND flash chip is performed according to the received operation instruction and the obtained physical address.
  • the present invention also provides a random write method for a NAND flash memory device as described above, the method comprising the steps of:
  • the flash controller receives the read operation instruction of the external host device and the logical address of the read content through the virtual file system;
  • the flash controller searches a mapping table of a flash transport layer of the non-volatile memory storage to obtain a physical address of the NAND flash chip corresponding to the logical address of the read content;
  • the flash controller reads corresponding data from the NAND flash memory chip to the non-volatile memory according to the read operation instruction and the obtained physical address;
  • the flash controller receives update data of an external host device through the virtual file system, and replaces the corresponding data in the non-volatile memory with the update data.
  • the NAND flash memory device and the random write method thereof proposed by the present invention use a non-volatile memory as a cache to store a mapping table of a flash transport layer and transmit data between the external master device and the NAND flash chip. Cache. Due to the non-volatile nature of the non-volatile memory itself, when the NAND flash memory device is powered off, its stored flash transfer layer mapping table and the already cached data are not lost, then after the NAND flash memory device is powered on again, Rebuilding the mapping table of the flash transport layer improves the power-on startup speed of the NAND flash device.
  • FIG. 1 is a typical structural diagram of a NAND flash memory device provided by the prior art
  • FIG. 2 is a structural diagram of a NAND flash memory device according to a first embodiment of the present invention
  • FIG. 3 is a structural diagram of a NAND flash memory device according to a second embodiment of the present invention.
  • FIG. 4 is a flow chart of a random write method of a NAND flash memory device according to a third embodiment of the present invention.
  • the present invention proposes a NAND flash memory device that uses a non-volatile memory as a cache.
  • a non-volatile memory as a cache.
  • FIG. 2 shows the structure of a NAND flash memory device provided by the first embodiment of the present invention, for convenience of explanation. Only parts related to the first embodiment of the present invention are shown.
  • the NAND flash memory device provided by the first embodiment of the present invention includes: a virtual file system 11; at least one NAND flash memory chip 13; and a non-volatile memory 14 for storing a mapping table of the flash transport layer and for external host devices and The transfer data between the NAND flash chips 13 is buffered; the flash controller 12 is configured to receive an operation instruction and a logical address of the external host device through the virtual file system 11, and to find a mapping of the flash transport layer stored by the non-volatile memory 14 The table converts the received logical address into the physical address of the NAND flash chip 13, and then performs a corresponding operation on the NAND flash chip 13 based on the received operation instruction and the obtained physical address.
  • the non-volatile memory 14 is a non-volatile random access memory (Non-Volatile Random Access Memory, NVRAM), which refers to a random access memory that does not lose data stored after power-off. It has the following features: fast access speed, high-speed interface, high ease of use, non-volatile, and high unit storage unit price.
  • NVRAM Non-Volatile Random Access Memory
  • the non-volatile memory 14 is a magnetic random access memory (Magnetic Random Access Memory (MRAM), Phase Change Memory (PCM).
  • MRAM Magnetic Random Access Memory
  • PCM Phase Change Memory
  • the NAND flash memory device uses the non-volatile memory 14 as a cache to store a mapping table of the flash memory layer and buffers the transmission data between the external host device and the NAND flash chip 13. Due to the non-volatility of the non-volatile memory 14 itself, when the NAND flash memory device is powered off, the storage map of the stored flash memory layer and the already cached data are not lost, after the NAND flash device is powered on again, The power-on startup speed of the NAND flash device is improved without rebuilding the mapping table of the flash transport layer.
  • the non-volatile memory 14 can also be used to store data related to power-on startup of the NAND flash memory device.
  • the data related to the power-on startup is stored in the volatile memory, and after the power is turned off, the data related to the power-on startup is lost, and after the power is turned on again, the system cannot be
  • the non-volatile memory 14 of the first embodiment of the present invention is used to store the data without causing the power loss of the data to disappear, thereby ensuring that the system can be powered up again after being powered on, thereby improving the reliability of the NAND flash memory device. .
  • FIG. 3 shows the structure of a NAND flash memory device provided by the second embodiment of the present invention for convenience of explanation. Only parts related to the second embodiment of the present invention are shown.
  • the NAND flash memory device further includes a volatile memory 15 for storing temporary data during system operation or other data unrelated to power-on startup.
  • the volatile memory 15 is coupled to the non-volatile memory 14 via an AMBA bus interface, and in some applications, data transfer between the volatile memory 15 and the non-volatile memory 14 is enabled.
  • the volatile memory 15 is a random access memory, a synchronous dynamic random access memory, and a double rate synchronous dynamic random access memory.
  • the second embodiment of the present invention can realize the cooperative operation of the volatile memory 15 and the non-volatile memory 14, reduce the storage pressure of the non-volatile memory 14, and improve the system performance.
  • FIG. 4 shows a flow of a random write method of the NAND flash memory device as described above according to the third embodiment of the present invention.
  • the random write method of the NAND flash memory device includes:
  • Step S1 The flash controller receives the read operation instruction of the external host device and the logical address of the read content through the virtual file system.
  • Step S2 The flash controller searches the mapping table of the flash transport layer of the non-volatile memory storage, and obtains the physical address of the NAND flash chip corresponding to the logical address of the read content.
  • Step S3 The flash controller reads the corresponding data from the NAND flash chip to the non-volatile memory according to the read operation instruction and the obtained physical address.
  • Step S4 The flash controller receives the update data of the external master device through the virtual file system, and replaces the corresponding data in the non-volatile memory with the update data.
  • the random write method of the NAND flash memory device provided by the third embodiment of the present invention is based on the random write method of the NAND flash memory device provided by the first embodiment and the second embodiment described above. Since the NAND flash memory device uses a non-volatile memory, when the random write operation is performed, the update data is written into the non-volatile memory to ensure reliable storage of the data, which can save time and time compared with the prior art. The write operation execution time of the NAND flash chip improves the performance of random writes.
  • step S4 Can include:
  • Step S5 The flash controller determines whether the update data is larger than the capacity of the non-volatile memory, if yes, step S8 is performed, otherwise step S6 is performed.
  • Step S6 The flash controller monitors the state of the transmission channel between the NAND flash chip, the virtual file system and the non-volatile memory, and updates the update data in the non-volatile memory when the state of the transmission channel is monitored to be idle. Write to the corresponding NAND flash chip.
  • Step S7 The flash controller updates the mapping table of the flash transport layer of the non-volatile memory storage.
  • Step S8 The flash controller sequentially writes the update data in the non-volatile memory back to the corresponding NAND flash chip.
  • the NAND flash memory device and the random writing method thereof proposed by the present invention use the non-volatile memory 14 as a cache to store a mapping table of the flash memory layer and between the external master device and the NAND flash memory chip 13. Transfer data for caching. Due to the non-volatility of the non-volatile memory 14 itself, when the NAND flash memory device is powered off, the storage map of the stored flash memory layer and the already cached data are not lost, after the NAND flash device is powered on again, The power-on startup speed of the NAND flash device is improved without rebuilding the mapping table of the flash transport layer.
  • the non-volatile memory 14 when random write data is performed on the NAND flash memory chip 13, it is not necessary to immediately rewrite the data updated to the non-volatile memory 14 into the NAND flash memory chip 13, but can wait for the NAND flash memory device to be idle, and then update the updated The data is written into the NAND flash chip 13, which improves the performance of the system by improving the random write speed of the NAND flash memory device while ensuring reliable storage of data.
  • the non-volatile memory 14 also stores data related to the power-on startup, it can ensure that the system can be normally started when the system is powered on again, thereby improving the reliability of the operation of the NAND flash memory device.

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Abstract

本发明属于NAND闪存设备的结构设计领域，提供了一种NAND闪存设备及其随机写入方法。该NAND闪存设备采用非挥发性存储器作为缓存，由于非挥发性存储器本身的非易失性，当NAND闪存设备掉电后，其存储的闪存传输层的映射表及已经缓存的数据并不会失去，再次上电后，无需重新构建闪存传输层的映射表，提高了NAND闪存设备的上电启动速度。同时，对NAND闪存芯片执行随机写数据时，无需将更新到非挥发性存储器的数据立即重新写入到NAND闪存芯片中，而是可等待NAND闪存设备空闲时，再将更新后的数据写入到NAND闪存芯片中，在保证可靠存储数据的同时，提高了NAND闪存设备随机写入的速度，从而提高了系统的性能。

Description

一种NAND闪存设备及其随机写入方法 技术领域
本发明属于NAND闪存设备的结构设计领域，尤其涉及一种NAND闪存设备及其随机写入方法。
 背景技术
当前，NAND闪存芯片由于其低功耗、更好的抗物理撞击性和电磁兼容特性、更小的物理尺寸、以及更轻的重量等优点，而被广泛应用于计算机系统、数码相机、便携式音乐播放器、USB闪存驱动器、存储卡等电子设备中。
公知地，根据制造、使用的技术和型号的不同，NAND闪存芯片有不同的容量和构造。典型地，NAND闪存芯片包括若干块块（block），每一块又被分成若干页，块的尺寸可以但不限于是256K、512K、1M或2M字节，页的数量可以是32、64、128或更多，每页的尺寸可以但不限于是256、512、1K、2K、4K、8K字节或更多。
NAND闪存设备是指基于NAND闪存芯片的存储设备。如图1示出了现有技术提供的NAND闪存设备的典型结构，包括：虚拟文件系统，闪存控制器，至少一个NAND闪存芯片，以及挥发性存储器。其中，虚拟文件系统是指NAND闪存设备中用来与 外部主设备连接的接口部分，例如，SSD硬盘中的SATA接口、U盘中的USB接口等；挥发性存储器主要用来存储系统运行时的临时数据、闪存传输层的映射表、或者作为与外部主设备之间传输数据的缓冲器，该挥发性存储器典型的可以是：随机访问存储器（Random Access Memory，RAM），同步动态随机存储器（Synchronous Dynamic Random Access Memory，SDRAM），双倍速率同步动态随机存储器（Double Data Rate，DDR）等，在实际中，考虑到容量和价格，一般采用SDRAM和DDR。
公知地，对NAND闪存设备的基本操作包括：读取操作、写入操作、擦除操作。其中，写入操作和读取操作是以页为单位执行的，擦除操作是以块为单位执行的，且在页写入前，必须先对包含页的块进行擦除。由于NAND闪存芯片不能原地重写的特点以及写入操作以页为单元执行的特点，现有技术中，当对NAND闪存设备存储的内容进行替换时，闪存控制器需要先将NAND闪存芯片中的相应页读出并保存到挥发性存储器中，之后用新的数据替换掉相应内容后，再将数据重新写入NAND闪存芯片中。例如，若要替换掉一个4K字节的页中从第1024字节开始的512个字节，闪存控制器需要先将该4K字节的页从NAND闪存芯片中读出，并保存到挥发性存储器中，之后，用新的数据替换掉该512个字节，之后，由于挥发性存储器的断电易失性，为了保证替换后的数据的可靠存储，需要立即再将替换后的数据重新写入NAND闪存芯片的另一个页中。这样，整个替换过程涉及一个读取操作，一个写入操作，还涉及数据的组合，而对NAND闪存芯片执行写入操作的时间远长于执行读取操作的时间，因此会使得NAND闪存设备的随机写入速度较慢，性能差。另外，由于NAND存储设备采用挥发性存储器来存储闪存传输层的映射表，这样，在NAND闪存设备掉电并重新上电后，需要重新构建闪存传输层的映射表，降低了NAND闪存设备的上电启动速度。
 技术问题
本发明的目的在于提供一种NAND闪存设备及其随机写入方法，旨在解决现有技术提供的NAND闪存设备采用具有易失性的挥发性存储器作为缓存，在挥发性存储器中更新的数据需立即写入NAND闪存芯片，造成NAND闪存设备随机写入速度慢的问题，以及由于挥发性存储器的易失性造成的上电启动速度慢的问题。
技术解决方案
本发明是这样实现的，一种NAND闪存设备，所述NAND闪存设备包括：
虚拟文件系统；
至少一个NAND闪存芯片；
非挥发性存储器，用于存储闪存传输层的映射表，并对外部主设备与所述NAND闪存芯片之间的传输数据进行缓存；
闪存控制器，用于通过所述虚拟文件系统接收外部主设备的操作指令及逻辑地址，并通过查找所述非挥发性存储器存储的所述闪存传输层的映射表，将接收到的所述逻辑地址转换成所述NAND闪存芯片的物理地址，之后根据接收到的所述操作指令及得到的所述物理地址，执行对所述NAND闪存芯片的相应操作。
本发明还提供一种如上所述的NAND闪存设备的随机写入方法，所述方法包括以下步骤：
闪存控制器通过虚拟文件系统接收外部主设备的读取操作指令及读取内容的逻辑地址；
所述闪存控制器查找非挥发性存储器存储的闪存传输层的映射表，得到所述读取内容的逻辑地址对应的NAND闪存芯片的物理地址；
所述闪存控制器根据所述读取操作指令和得到的所述物理地址，从所述NAND闪存芯片中读取相应数据到所述非挥发性存储器；
所述闪存控制器通过所述虚拟文件系统接收外部主设备的更新数据，并将所述非挥发性存储器中的所述相应数据替换为所述更新数据。
 有益效果
综上所述，本发明提出的NAND闪存设备及其随机写入方法是采用非挥发性存储器作为缓存，来存储闪存传输层的映射表，并对外部主设备与NAND闪存芯片之间的传输数据进行缓存。由于非挥发性存储器本身的非易失性，当NAND闪存设备掉电后，其存储的闪存传输层的映射表及已经缓存的数据并不会失去，则在NAND闪存设备再次上电后，无需重新构建闪存传输层的映射表，提高了NAND闪存设备的上电启动速度。同时，对NAND闪存芯片执行随机写数据时，无需将更新到非挥发性存储器的数据立即重新写入到NAND闪存芯片中，而是可等待NAND闪存设备空闲时，再将更新后的数据写入到NAND闪存芯片中，这样可在保证可靠存储数据的同时，提高NAND闪存设备随机写入的速度，从而提高了系统的性能。
 附图说明
图1是现有技术提供的NAND闪存设备的典型结构图；
图2是本发明第一实施例提供的NAND闪存设备的结构图；
图3是本发明第二实施例提供的NAND闪存设备的结构图；
图4是本发明第三实施例提供的NAND闪存设备的随机写入方法的流程图。
 本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
针对现有技术存在的问题，本发明提出了一种NAND闪存设备，其采用非挥发性存储器作为缓存。以下结合实施例详细说明本发明实现方式：
图2示出了本发明第一实施例提供的NAND闪存设备的结构，为了便于说明。仅示出了与本发明第一实施例相关的部分。
详细地，本发明第一实施例提供的NAND闪存设备包括：虚拟文件系统11；至少一个NAND闪存芯片13；非挥发性存储器14，用于存储闪存传输层的映射表，并对外部主设备与NAND闪存芯片13之间的传输数据进行缓存；闪存控制器12，用于通过虚拟文件系统11接收外部主设备的操作指令及逻辑地址，并通过查找非挥发性存储器14存储的闪存传输层的映射表，将接收到的逻辑地址转换成NAND闪存芯片13的物理地址，之后根据接收到的操作指令及得到的物理地址，执行对NAND闪存芯片13的相应操作。
本发明第一实施例中，非挥发性存储器14即非易失性随机访问存储器 （Non-Volatile Random Access Memory，NVRAM），其是指断电之后所存储的数据不丢失的随机访问存储器，具有以下特点：访问速度快，高速接口，易用性高，非挥发性，单位存储单元价格高。优选地，非挥发性存储器14是磁性随机存储器（Magnetic Random Access Memory，MRAM)，相变存储器（Phase Change Memory，PCM）。
本发明第一实施例提供的NAND闪存设备是采用非挥发性存储器14作为缓存，来存储闪存传输层的映射表，并对外部主设备与NAND闪存芯片13之间的传输数据进行缓存。由于非挥发性存储器14本身的非易失性，当NAND闪存设备掉电后，其存储的闪存传输层的映射表及已经缓存的数据并不会失去，则在NAND闪存设备再次上电后，无需重新构建闪存传输层的映射表，提高了NAND闪存设备的上电启动速度。同时，对NAND闪存芯片13执行随机写数据时，无需将更新到非挥发性存储器14的数据立即重新写入到NAND闪存芯片13中，而是可等待NAND闪存设备空闲时，再将更新后的数据写入到NAND闪存芯片13中，这样可在保证可靠存储数据的同时，提高NAND闪存设备随机写入的速度，从而提高了系统的性能。
另外，本发明第一实施例中，非挥发性存储器14还可用于存储与NAND闪存设备的上电启动相关的数据。由于在现有技术中，该与上电启动相关的数据是存储在挥发性存储器中，在掉电后，该与上电启动相关的数据会失去，则在再次上电后，会导致系统无法启动，而采用本发明实施例一的非挥发性存储器14来存储该数据，不会造成该数据的掉电消失，保证了系统再次上电可正常启动，从而提高了NAND闪存设备工作的可靠性。
图3示出了本发明第二实施例提供的NAND闪存设备的结构，为了便于说明。仅示出了与本发明第二实施例相关的部分。
与第一实施例不同，在本发明第二实施例中，NAND闪存设备还包括：挥发性存储器15，用于存储系统运行时的临时数据、或其它与上电启动无关的数据。
优选地，挥发性存储器15与非挥发性存储器14之间通过AMBA总线接口连接，在某些应用下，可实现挥发性存储器15与非挥发性存储器14之间的数据传输。
优选地，挥发性存储器15是随机访问存储器，同步动态随机存储器，双倍速率同步动态随机存储器。
相对于本发明第一实施例，本发明第二实施例可实现挥发性存储器15与非挥发性存储器14的协同工作，降低非挥发性存储器14的存储压力，提高系统工作性能。
图4示出了本发明第三实施例提供的如上所述的NAND闪存设备的随机写入方法的流程。
详细地，本发明第三实施例提供的NAND闪存设备的随机写入方法包括：
步骤S1：闪存控制器通过虚拟文件系统接收外部主设备的读取操作指令及读取内容的逻辑地址。
步骤S2：闪存控制器查找非挥发性存储器存储的闪存传输层的映射表，得到读取内容的逻辑地址对应的NAND闪存芯片的物理地址。
步骤S3：闪存控制器根据读取操作指令和得到的物理地址，从NAND闪存芯片中读取相应数据到非挥发性存储器。
步骤S4：闪存控制器通过虚拟文件系统接收外部主设备的更新数据，并将非挥发性存储器中的相应数据替换为该更新数据。
本发明第三实施例提供的NAND闪存设备的随机写入方法是基于上述第一实施例和第二实施例提供的NAND闪存设备的随机写入方法。由于NAND闪存设备采用了非挥发性存储器，因此，在进行随机写入操作时，将更新数据写入非挥发性存储器即可保证数据的可靠存储，相对于现有技术，可节约耗时较长的NAND闪存芯片的写入操作执行时间，提高了随机写入的性能。
当然，在将更新数据写入到非挥发性存储器后，后续还是需要将更新数据写回到NAND闪存芯片，因此，本发明第三实施例中，如图4所示，在步骤S4之后，还可包括：
步骤S5：闪存控制器判断更新数据是否大于非挥发性存储器的容量，是则执行步骤S8，否则执行步骤S6。
步骤S6：闪存控制器监测其与NAND闪存芯片、虚拟文件系统和非挥发性存储器之间的传输通道的状态，并当监测到传输通道的状态均空闲时，将非挥发性存储器中的更新数据写入到相应的NAND闪存芯片中。
步骤S7：闪存控制器更新非挥发性存储器存储的闪存传输层的映射表。
步骤S8：闪存控制器将非挥发性存储器中的更新数据顺序写回到相应的NAND闪存芯片中。
综上所述，本发明提出的NAND闪存设备及其随机写入方法是采用非挥发性存储器14作为缓存，来存储闪存传输层的映射表，并对外部主设备与NAND闪存芯片13之间的传输数据进行缓存。由于非挥发性存储器14本身的非易失性，当NAND闪存设备掉电后，其存储的闪存传输层的映射表及已经缓存的数据并不会失去，则在NAND闪存设备再次上电后，无需重新构建闪存传输层的映射表，提高了NAND闪存设备的上电启动速度。同时，对NAND闪存芯片13执行随机写数据时，无需将更新到非挥发性存储器14的数据立即重新写入到NAND闪存芯片13中，而是可等待NAND闪存设备空闲时，再将更新后的数据写入到NAND闪存芯片13中，这样可在保证可靠存储数据的同时，提高NAND闪存设备随机写入的速度，从而提高了系统的性能。另外，若非挥发性存储器14还存储与上电启动相关的数据，则可保证系统重新上电时可正常启动，从而提高了NAND闪存设备工作的可靠性。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (8)

  1. 一种NAND闪存设备，其特征在于，所述NAND闪存设备包括：
    虚拟文件系统；
    至少一个NAND闪存芯片；
    非挥发性存储器，用于存储闪存传输层的映射表，并对外部主设备与所述NAND闪存芯片之间的传输数据进行缓存；
    闪存控制器，用于通过所述虚拟文件系统接收外部主设备的操作指令及逻辑地址，并通过查找所述非挥发性存储器存储的所述闪存传输层的映射表，将接收到的所述逻辑地址转换成所述NAND闪存芯片的物理地址，之后根据接收到的所述操作指令及得到的所述物理地址，执行对所述NAND闪存芯片的相应操作。
  2. 如权利要求1所述的NAND闪存设备，其特征在于，所述非挥发性存储器还用于存储与所述NAND闪存设备的上电启动相关的数据。
  3. 如权利要求1所述的NAND闪存设备，其特征在于，所述NAND闪存设备还包括：
    挥发性存储器，用于存储系统运行时的临时数据、或与上电启动无关的数据。
  4. 如权利要求3所述的NAND闪存设备，其特征在于，所述挥发性存储器与所述非挥发性存储器之间通过AMBA总线接口连接。
  5. 如权利要求3所述的NAND闪存设备，其特征在于，所述挥发性存储器是随机访问存储器，同步动态随机存储器，或双倍速率同步动态随机存储器。
  6. 如权利要求1所述的NAND闪存设备，其特征在于，所述非挥发性存储器是磁性随机存储器或相变存储器。
  7. 一种如权利要求1至6任一项所述的NAND闪存设备的随机写入方法，其特征在于，所述方法包括以下步骤：
    闪存控制器通过虚拟文件系统接收外部主设备的读取操作指令及读取内容的逻辑地址；
    所述闪存控制器查找非挥发性存储器存储的闪存传输层的映射表，得到所述读取内容的逻辑地址对应的NAND闪存芯片的物理地址；
    所述闪存控制器根据所述读取操作指令和得到的所述物理地址，从所述NAND闪存芯片中读取相应数据到所述非挥发性存储器；
    所述闪存控制器通过所述虚拟文件系统接收外部主设备的更新数据，并将所述非挥发性存储器中的所述相应数据替换为所述更新数据。
  8. 如权利要求7所述的NAND闪存设备的随机写入方法，其特征在于，在所述闪存控制器通过所述虚拟文件系统接收外部主设备的更新数据，并将所述非挥发性存储器中的所述相应数据替换为所述更新数据的步骤之后，所述方法还包括：
    所述闪存控制器判断所述更新数据是否大于所述非挥发性存储器的容量；
    若所述闪存控制器判断所述更新数据大于所述非挥发性存储器的容量，则所述闪存控制器将所述非挥发性存储器中的所述更新数据顺序写回到相应的所述NAND闪存芯片中；
    若所述闪存控制器判断所述更新数据不大于所述非挥发性存储器的容量，则所述闪存控制器监测所述闪存控制器与所述NAND闪存芯片、所述虚拟文件系统和所述非挥发性存储器之间的传输通道的状态，并当监测到所述传输通道的状态均空闲时，将所述非挥发性存储器中的所述更新数据写入到相应的所述NAND闪存芯片中，之后，所述闪存控制器更新所述非挥发性存储器存储的所述闪存传输层的映射表。
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