WO2014200077A1 - Microstructure forming method, semiconductor device manufacturing method, and cmos forming method - Google Patents

Microstructure forming method, semiconductor device manufacturing method, and cmos forming method Download PDF

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WO2014200077A1
WO2014200077A1 PCT/JP2014/065665 JP2014065665W WO2014200077A1 WO 2014200077 A1 WO2014200077 A1 WO 2014200077A1 JP 2014065665 W JP2014065665 W JP 2014065665W WO 2014200077 A1 WO2014200077 A1 WO 2014200077A1
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indium phosphide
silicon substrate
heating
semiconductor
indium
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PCT/JP2014/065665
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French (fr)
Japanese (ja)
Inventor
軍司　勲男
友策 井澤
大輔 大場
佳幸 近藤
勇作 柏木
正和 杉山
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東京エレクトロン株式会社
国立大学法人 東京大学
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Publication of WO2014200077A1 publication Critical patent/WO2014200077A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to a fine structure forming method for forming a fine structure of a heterogeneous semiconductor on a substrate, a semiconductor device manufacturing method, and a CMOS forming method.
  • Group III elements aluminum (Al), gallium (Ga), indium (In)
  • group V elements phosphorus (P), arsenic (As), antimony (Sb)
  • germanium Ge
  • Some semiconductors have higher carrier mobility and smaller band gap than silicon (Si), which is common as a semiconductor, and therefore, semiconductor elements exceeding the physical properties of silicon can be created by using different types of semiconductors. .
  • GaAs gallium arsenide
  • GaSb gallium antimony
  • InP indium phosphide
  • InAs indium arsenide
  • InSb indium antimony
  • InGaAs indium gallium arsenide
  • an LPE (Liquid Phase Epitaxy) method is known as one of the methods for growing a heterogeneous semiconductor with few crystal defects, for example, indium phosphide.
  • liquid indium slightly containing phosphorus filled in a crucible around which a heater is wound is brought into contact with a crystal substrate of indium phosphorus provided on a slider in a crystal growth furnace.
  • crystal substrate of indium phosphide is formed from the crystal plane of the crystal substrate.
  • Epitaxial growth is performed (for example, see Patent Document 1).
  • Patent Document 1 to 3 There have also been reports of attempts to grow indium phosphide crystals on a silicon substrate using the LPE method (see, for example, Non-Patent Documents 1 to 3).
  • the temperature of the indium solution cannot be controlled by the heater wound around the crucible because the indium solution cannot be filled and held in the crucible.
  • the temperature of the indium solution is lowered at places other than the vicinity of the boundary between the indium solution and the crystal substrate of indium phosphide, and grains of indium phosphide are produced at the places. Since grains change the electrical characteristics of indium phosphide, for example, the resistivity, it is difficult to exhibit the performance expected of a fine structure made of indium phosphide. That is, it is difficult to form a high quality heterogeneous semiconductor microstructure on a wafer.
  • An object of the present invention is to provide a fine structure forming method, a semiconductor device manufacturing method, and a CMOS forming method capable of forming a high quality heterogeneous semiconductor fine structure on a substrate.
  • the filled dissimilar semiconductor is heated by at least an upper heat source arranged on the upper surface side of the silicon substrate,
  • a microstructure is formed to cool the molten dissimilar semiconductor by reducing the amount of heating from the upper heat source. The law is provided.
  • a high-quality heterogeneous semiconductor microstructure can be formed on a substrate.
  • FIG. 1A to FIG. 1E are process diagrams showing a fine structure forming method according to a first embodiment of the present invention.
  • FIGS. 2A to 2E are process diagrams showing a fine structure forming method according to the present embodiment.
  • FIG. 3 is a cross-sectional view schematically showing a configuration of a heat treatment apparatus used in the microstructure forming method according to the present embodiment.
  • FIG. 4 is a graph showing extinction coefficients of indium phosphide, germanium and silicon.
  • FIG. 5 is a cross-sectional view showing how laser light is absorbed by indium phosphide, a Si 3 N 4 film, and a SiO 2 film in the microstructure forming method according to the present embodiment.
  • FIG. 1A to FIG. 1E are process diagrams showing a fine structure forming method according to a first embodiment of the present invention.
  • FIGS. 2A to 2E are process diagrams showing a fine structure forming method according to the present embodiment.
  • FIG. 3 is a
  • FIG. 6 is a flowchart showing indium phosphide recrystallization processing executed by the heat treatment apparatus of FIG. 3 in the microstructure forming method according to the present embodiment.
  • FIG. 7 is a diagram for explaining scanning of a trench by laser light performed in the recrystallization process of FIG. [FIGS. 8A to 8C]
  • FIGS. 8A to 8C are diagrams for explaining temperature gradient control in the depth direction of indium phosphide performed in the recrystallization process of FIG.
  • FIG. 9 is a cross-sectional view schematically showing a configuration of an indium gallium arsenide / indium aluminum arsenide quantum well channel formed by the microstructure forming method according to the present embodiment.
  • FIG. 7 is a diagram for explaining scanning of a trench by laser light performed in the recrystallization process of FIG.
  • FIGS. 8A to 8C are diagrams for explaining temperature gradient control in the depth direction of indium phosphide performed in the recrystallization process of FIG.
  • FIG. 10 is a cross-sectional view schematically showing the configuration of a planar channel having indium gallium arsenide / indium aluminum arsenide quantum well channels to which the microstructure forming method according to the present embodiment is applied.
  • FIG. 11 A cross-sectional view schematically showing a configuration of a laminated indium gallium arsenide / indium aluminum arsenide quantum well channel to which the microstructure forming method according to the present embodiment is applied.
  • FIG. 12 is a cross-sectional view schematically showing a configuration of a heat treatment apparatus used in the microstructure forming method according to the second embodiment of the present invention.
  • FIG. 13 is a graph showing the amount of absorption of silicon nitride (Si 3 N 4 ) with respect to wave number.
  • FIG. 14 is a graph showing the extinction coefficient of silicon oxide (SiO 2 ).
  • FIG. 15 is a cross-sectional view showing how laser light is absorbed by indium phosphide, a Si 3 N 4 film, and a SiO 2 film in the microstructure forming method according to the third embodiment of the present invention.
  • FIG. 16 is a cross-sectional view schematically showing a configuration of quantum dots and nanorods formed by the microstructure forming method according to the present embodiment.
  • FIG. 17 is a cross-sectional view for explaining the case where indium phosphide and germanium are simultaneously recrystallized in each trench.
  • FIGS. 1A to 1E and FIGS. 2A to 2E are process diagrams showing a fine structure forming method according to the present embodiment. Each drawing shows a single crystal silicon substrate 10 to which the fine structure forming method is applied. It is an expanded sectional view near the surface (upper surface).
  • a single crystal silicon substrate 10 is prepared (FIG. 1A), and Si 3 is deposited on the surface of the single crystal silicon substrate 10 by a deposition method, for example, a thermal CVD method, a plasma CVD method, an ALD method, or an SOD (Spin On Dielectric) method.
  • a deposition method for example, a thermal CVD method, a plasma CVD method, an ALD method, or an SOD (Spin On Dielectric) method.
  • An N 4 film 11 is formed (FIG. 1B), and an SiO 2 film 12 and an Si 3 N 4 film 13 are sequentially formed on the Si 3 N 4 film 11 by a deposition method (FIG. 1C).
  • the covering layer is formed by three layers of the Si 3 N 4 film 11, the SiO 2 film 12, and the Si 3 N 4 film 13, but the covering layer is formed by one or two layers. Alternatively, it may be formed of three or more layers.
  • the Si 3 N 4 film 13 and the SiO 2 film 12 are sequentially etched by photolithography to form a trench 14 (concave portion) (FIG. 1D), and the Si 3 N 4 film 11 is further etched to form the bottom of the trench 14.
  • FIG. 1E the (001) crystal plane 15 of the single crystal silicon substrate 10 is exposed (FIG. 1E) (recess formation step).
  • reactive ion etching or wet etching may be used.
  • CFx gas is used as a processing gas in reactive ion etching
  • phosphoric acid (H, for example, is used as an etchant in wet etching.
  • 3 PO 4 can be used.
  • the trench 14 has, for example, a width of 10 nm to 50 nm, preferably 10 nm, a depth of 10 nm to 100 nm, and an aspect (depth / width) ratio of 1 or more, preferably 3 to 10.
  • the (001) crystal face 15 exposed at the bottom of the trench 14 is cleaned using a chemical solution, for example, sulfuric acid hydrogen peroxide solution (SPM), hydrochloric acid hydrogen peroxide solution (SC2), dilute hydrofluoric acid (DHF),
  • SPM sulfuric acid hydrogen peroxide solution
  • SC2 hydrochloric acid hydrogen peroxide solution
  • DHF dilute hydrofluoric acid
  • the crystal orientation in the (001) crystal plane 15 is adjusted (FIG. 1E).
  • the cleaning of the (001) crystal plane 15 may be performed by dry etching using a mixed gas of hydrogen fluoride (HF) and ammonia (NH 3 ), for example.
  • the trench 14 is filled with indium phosphide (InP) 16 in a gas phase or a solid phase (filling step).
  • a chemical vapor deposition (CVD) method is used for filling indium phosphide 16.
  • MOCVD metal organic chemical vapor deposition
  • a single crystal silicon substrate 10 is heated while trimethyl which is a group III compound.
  • TMIn indium
  • TBP tertiary butylphosphine
  • the entire single crystal silicon substrate 10 is preferably set to, for example, 400 ° C. to 650 ° C.
  • the temperature is preferably set to 400 ° C. to 450 ° C.
  • the pressure of the atmosphere is preferably 10 ⁇ 10 4 Pa to 10 ⁇ 10 5 Pa, for example.
  • indium phosphide 16 When indium phosphide 16 is filled in the trench 14, the (001) crystal plane 15 is exposed at the bottom of the trench 14, while the surface of the single crystal silicon substrate 10 is covered with the Si 3 N 4 film 13, so that (001) Due to the difference in chemical state between the crystal plane 15 and the surface of the Si 3 N 4 film 13, indium phosphide 16 is preferentially generated in the (001) crystal plane 15 over the Si 3 N 4 film 13. This preferentially fills the trench 14 with indium phosphide 16 (FIG. 2A).
  • the method for filling the trench 14 with the indium phosphide 16 is not limited to the CVD method, and any method may be used as long as the indium phosphide 16 is filled into the trench 14 except for the liquid phase.
  • a physical vapor deposition (PVD) method or an atomic layer volume (ALD) method using indium or indium phosphorus as a target may be used.
  • PVD physical vapor deposition
  • ALD atomic layer volume
  • a method of directly embedding fine powder of indium phosphide into the trench 14 may be used.
  • indium phosphorus may be formed by performing treatment in a phosphorus atmosphere, or indium phosphorus may be formed by doping phosphorus after forming indium.
  • a plurality of film forming methods may be combined.
  • the surface of the single crystal silicon substrate 10 including the tops of the indium phosphines 16 filled in the trenches 14 is covered with a SiO 2 film 17 by a deposition method (FIG. 2B), and then a recrystallization process of FIG.
  • the indium phosphide 16 is heated (heating step), and when the indium phosphide 16 melted by the heating is gradually cooled from the vicinity of the (001) crystal face 15, the crystallized indium phosphide 18 is precipitated using the (001) crystal face 15 as a seed.
  • Recrystallization of indium phosphide 16 (FIG. 2C) (cooling step).
  • the melting point of indium phosphide 16 is 1062 ° C.
  • the melting point of SiO 2 is 1650 ° C.
  • the SiO 2 film 17 is melted do not do. Therefore, the melted indium phosphide 16 is retained in the trench 14 by the SiO 2 film 17. Further, since the SiO 2 film 17 is formed so as to cover the indium phosphorus 16, it is possible to prevent phosphorus from being detached from the indium phosphorus 16.
  • the crystallized indium phosphide 18 When crystallized indium phosphide 18 precipitates, the crystallized indium phosphide 18 inherits the crystallinity of the Miller index (001). However, since the lattice constants of silicon and indium phosphide are different, the lattice mismatch from (001) crystal plane 15 occurs. A threading dislocation defect 19 is generated due to the above. Here, the threading dislocation defect 19 is not perpendicular to the (001) crystal plane 15 but grows obliquely, for example, along a direction of 45 °. Therefore, if the aspect ratio of the trench 14 is 1 or more, the threading dislocation defect 19 does not reach the top of the trench 14.
  • the aspect ratio is 2 or more, the threading dislocation defect 19 in the crystallized indium phosphorus 18. It is possible to secure a sufficient portion where no exists. Further, if the aspect ratio is 3 to 10, a portion where the threading dislocation defect 19 does not exist in the crystallized indium phosphide 18 can be more sufficiently secured.
  • the SiO 2 film 17 and the Si 3 N 4 film 13 are removed by wet etching, dry etching, CMP, or the like (FIG. 2D).
  • the SiO 2 film 12 is removed by wet etching or dry etching to obtain a fin-type channel 20 of crystallized indium phosphide 18 (FIG. 2E) (removal step). Since the shape of the trench 14 is reflected in the obtained channel 20, the aspect ratio of the channel 20 is substantially the same as the aspect ratio of the trench 14 and is 1 or more, preferably 3 to 10. Next, after obtaining the channel 20, the fine structure forming method according to the present embodiment is finished.
  • the temperature gradient in the depth direction of the indium phosphide 16 filled in the trench 14 must be controlled.
  • the temperature of the portion other than the vicinity of the (001) crystal plane 15 is lowered before the temperature of the vicinity of the (001) crystal plane 15, and the grains of indium phosphide 16 are generated at the location.
  • the temperature gradient in the depth direction of the indium phosphide 16 is controlled.
  • FIG. 3 is a cross-sectional view schematically showing a configuration of a heat treatment apparatus used in the fine structure forming method according to the present embodiment.
  • the heat treatment apparatus 21 of FIG. 3 is used for melting, gradual cooling, and recrystallization of the indium phosphide 16 filled in the trench 14.
  • a heat treatment apparatus 21 contains a single crystal silicon substrate 10, a chamber 22 made of quartz (quartz), and a table-like susceptor placed in the chamber 22 and on which the single crystal silicon substrate 10 is placed. 23, a laser scanner 24 (upper heat source, laser light irradiation device) disposed above the susceptor 23 in the chamber 22, and a plurality of lamp heaters disposed to face the susceptor 23 below the chamber 22 25 (downward heat source).
  • a laser scanner 24 upper heat source, laser light irradiation device
  • the laser scanner 24 moves in parallel with the surface of the single crystal silicon substrate 10 while facing the single crystal silicon substrate 10 placed on the susceptor 23 (see white arrows in the figure).
  • the laser scanner 24 includes two laser light irradiation units 24a and 24b (one laser light irradiation unit and another laser light irradiation unit) arranged in the moving direction.
  • the two laser light irradiation units 24 a and 24 b irradiate the surface of the single crystal silicon substrate 10 placed on the susceptor 23 with laser light to heat the indium phosphide 16 filled in the trench 14.
  • a transmission window 26 is fitted into the bottom of the chamber 22 interposed between the lamp heater 25 and the susceptor 23, and the lamp heater 25 causes the single crystal silicon substrate 10 placed on the susceptor 23 to be moved by the lamp light transmitted through the transmission window 26. Heat.
  • the indium phosphide 16 filled in the trench 14 is melted, it is preferable to selectively heat only the indium phosphide 16 in order to prevent the breakdown of the electrodes and the insulating film in the transistor due to heating.
  • the wavelength of the laser light irradiated by the parts 24a and 24b is set to a wavelength that is easily absorbed by the indium phosphide 16.
  • FIG. 4 is a graph showing the extinction coefficients of indium phosphide, germanium, and silicon.
  • the horizontal axis of the graph of FIG. 4 is the wavelength of the laser light irradiated to indium phosphorus or the like, and the vertical axis is the extinction coefficient.
  • the extinction coefficient of indium phosphide or germanium is higher by one digit or more than the extinction coefficient of silicon.
  • the absorption coefficient of silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ) is almost 0 in the range where the wavelength of the laser beam is 800 nm to 950 nm.
  • silicon nitride transmits the laser light.
  • the laser light wavelength range is set to 800 nm to 950 nm and the laser light is irradiated to indium phosphide, germanium, silicon, silicon oxide, or silicon nitride
  • the energy of the laser light is absorbed by indium phosphide or germanium. While phosphorus and germanium are heated, silicon, silicon oxide, and silicon nitride almost transmit laser light, so silicon, silicon oxide, and silicon nitride are hardly heated. As a result, indium phosphorus and germanium are selectively used. Can be heated.
  • the range of the wavelength of the laser light irradiated by the two laser light irradiation units 24a and 24b is set to 800 nm to 950 nm.
  • the laser light L irradiated by the two laser light irradiation units 24a and 24b toward the surface of the single crystal silicon substrate 10 is absorbed by the indium phosphorus 16 when passing through the indium phosphorus 16 as shown in FIG. While passing through the SiO 2 film 17, Si 3 N 4 film 13, SiO 2 film 12 and Si 3 N 4 film 11, the film passes through these films with almost no absorption, and single crystal silicon. Even the substrate 10 is gradually absorbed and gradually decreased. Thereby, only the indium phosphide 16 can be selectively heated by irradiation with the laser beam L.
  • FIG. 6 is a flowchart showing indium phosphide recrystallization processing executed by the heat treatment apparatus of FIG. 3 in the microstructure forming method according to the present embodiment.
  • the lamp heater 25 is moved to the lamp heater 25.
  • the lower side of the susceptor 23 is irradiated with light (not shown) to start heating the entire single crystal silicon substrate 10, and the entire single crystal silicon substrate 10 is heated to a temperature lower than the melting point of indium phosphide (1062 ° C.), for example, Heat to 800 ° C. (step S61).
  • the laser scanner 24 irradiates the surface of the single crystal silicon substrate 10 with the laser light L and starts heating the indium phosphide 16 (step S62). At this time, as shown in FIG. 7, the laser scanner 24 moves along each trench 14 formed in the single crystal silicon substrate 10 (see the white arrow in the figure), so that each trench 14 is irradiated with laser light. Scan.
  • the laser scanner 24 includes the two laser light irradiation units 24a and 24b arranged along the movement (scanning) direction, but the laser beam irradiated by the laser light irradiation unit 24a disposed forward in the scanning direction.
  • the intensity of the light L 1 is set to be larger than the intensity of the laser light L s irradiated by the laser light irradiation unit 24b disposed rearward in the scanning direction.
  • the intensity of the laser beam L 1 is set to twice the intensity of the laser beam L s .
  • the indium phosphide 16 at the point A in the trench 14 is first irradiated with the laser beam L 1 having a high intensity, and then irradiated with the laser beam L s having a low intensity. , Neither of the laser beams L 1 and L s is irradiated.
  • indium phosphide 16 strength is greater the laser beam L l of the point A is illuminated, the laser light L l incident on indium phosphide 16 while attenuating reached (001) crystal plane 15, the entire indium phosphide 16 Fully heated, all temperatures of indium phosphide 16 exceed the melting point of indium phosphide, as shown in the temperature gradient graph of indium phosphide 16 in the depth direction of FIG. 8A. Thereby, all of the indium phosphide 16 filled in the trench 14 is melted.
  • the laser scanner 24 moves and the indium phosphide 16 at the point A is irradiated with the low intensity laser light L 1 , the laser light L s incident on the indium phosphide 16 is attenuated and is halfway in the indium phosphide 16. Disappears.
  • the temperature of the indium phosphor 16 is the (001) crystal plane as shown in the graph of the temperature gradient in the depth direction of the indium phosphor 16 in FIG. 8B.
  • the temperature gradient decreases in the vicinity of 15, and the temperature gradient shifts to a lower temperature side than the temperature gradient in FIG. 8A. That is, slow cooling of the indium phosphide 16 by the laser scanner 24 is started (step S63).
  • the indium phosphide 16 corresponding to the portion below the point P where the temperature gradient that has shifted to the low temperature side intersects the melting point solidifies, and crystallized indium phosphide 18 precipitates using the crystal plane 15 as a seed.
  • the indium phosphide 16 corresponding to the portion above P remains molten.
  • the temperature of the indium phosphide 16 decreases over the entire indium phosphide 16, and eventually FIG. 8C As shown in the graph of the temperature gradient with respect to the depth direction of indium phosphide 16, all the temperatures of indium phosphide 16 are lower than the melting point of indium phosphide. Thereby, the indium phosphide 16 is solidified and recrystallized as a whole. Thereafter, this process is terminated.
  • the laser light irradiation units 24 a and 24 b of the laser scanner 24 sequentially irradiate the indium phosphorus 16 at the point A with the laser light L 1 and L s in order.
  • the amount of heating from above is gradually reduced to shift the temperature gradient in the depth direction of the indium phosphide 16 to the low temperature side, and the molten indium phosphide 16 is gradually cooled from the (001) crystal plane 15 side.
  • the temperature of indium phosphide 16 filled in the trench 14 decreases from the vicinity of the (001) crystal plane 15, and locations other than the vicinity of the (001) crystal plane 15 are ahead of the vicinity of the (001) crystal plane 15.
  • the temperature never drops.
  • the indium phosphide 16 is recrystallized using the (001) crystal plane 15 as a seed, it is possible to prevent the generation of grains in the crystallized indium phosphide 18, and thus the channel of the high quality crystallized indium phosphide 18 20 can be formed on the substrate.
  • the laser scanner 24 scans each trench 14 with a laser beam
  • the laser beam irradiation unit 24a. , 24b irradiates all the indium phosphides 16 filled in the trenches 14 with the laser beams L 1 and L s in order, so that the recrystallization process of FIG. 16 and all the indium phosphide 16 is recrystallized.
  • the portions irradiated with the laser beams L l and L s are very small as compared with the entire single crystal silicon substrate 10, so that the temperature rises due to the irradiation of the laser beams L l and L s
  • the portion to be processed is very small and does not induce warping or cracking of the single crystal silicon substrate 10 due to thermal shock during heating, and can suppress the thermal influence on other parts. Further, since the amount of heat necessary for heating the portion may be small, the power consumption of the laser scanner 24 can be reduced.
  • the laser lights L 1 and L s from the laser scanner 24 necessary for melting the indium phosphide 16 are used. Therefore, it is not necessary to configure the laser scanner 24 with a high-power laser irradiation device, and the configuration of the laser scanner 24 can be simplified. Further, the laser beam L l takes charge, the temperature rise of indium phosphide 16 required to melt the indium phosphide 16 is reduced, by adjusting the intensity of the laser beam L l, the temperature of the indium phosphide 16 Whether or not the melting point is exceeded can be accurately controlled.
  • the indium phosphide 16 is irradiated with laser light L s having a low intensity, and the indium phosphide 16 is irradiated. Slow cooling may be started. Thereby, the amount of heating from below to the indium phosphide 16 can be reduced, and the temperature of the indium phosphide 16 can be reliably lowered from the vicinity of the (001) crystal plane 15.
  • the indium phosphide 16 is irradiated with laser light L s having a low intensity to start slow cooling of the indium phosphide 16, and then the lamp heater 25 applies the single crystal silicon substrate 10 to the single crystal silicon substrate 10. The amount of heating may be reduced.
  • the laser scanner 24 includes two laser light irradiation units 24a and 24b arranged along the scanning direction.
  • the laser scanner 24 includes three or more laser light irradiation units arranged along the scanning direction.
  • the laser scanner 24 may be configured by one laser light irradiation unit. In these cases also, the intensity of the laser beam irradiated from the front to the rear in the scanning direction is reduced.
  • the lamp heater 25 heats the entire single crystal silicon substrate 10 via the susceptor 23 and does not selectively heat the indium phosphorus 16. There are no particular restrictions on. In the recrystallization process of FIG. 6 described above, it is preferable to use the lamp heater 25 in consideration of responsiveness, but a resistance heater may be used instead of the lamp heater 25.
  • the fin-type channel 20 formed by the microstructure forming method according to the present embodiment described above includes an indium aluminum arsenide (InAlAs) layer 27 as a lower layer barrier and arsenic as a channel layer. Covered by an indium gallium (InGaAs) layer 28 and an indium phosphide layer 29 as an upper barrier constitutes an indium gallium arsenide / indium aluminum arsenide quantum well channel.
  • InAlAs indium aluminum arsenide
  • InGaAs indium gallium
  • indium phosphide layer 29 as an upper barrier constitutes an indium gallium arsenide / indium aluminum arsenide quantum well channel.
  • microstructure formation method according to the present embodiment is applied not only to the formation of the indium gallium arsenide / indium aluminum arsenide quantum well channel shown in FIG. 9, but also to the formation of other microstructures.
  • FIG. 10 is a cross-sectional view schematically showing the structure of a planar channel having an indium gallium arsenide / indium aluminum arsenide quantum well channel to which the microstructure forming method according to the present embodiment is applied.
  • the fin-shaped crystallized indium phosphide 18 formed by the microstructure forming method according to the present embodiment includes an indium aluminum arsenide layer 27 as a lower barrier, an indium gallium arsenide layer 28 as a channel layer, and The indium phosphide layer 29 as an upper barrier is covered, and the side surface of the crystallized indium phosphide 18 is covered with the SiO 2 film 12.
  • FIG. 11 is a cross-sectional view schematically showing a configuration of a laminated indium gallium arsenide / indium aluminum arsenide quantum well channel to which the microstructure forming method according to the present embodiment is applied.
  • the top surface of the fin-shaped crystallized indium phosphide 18 formed by the microstructure forming method according to the present embodiment is an indium aluminum arsenide layer 27 as a lower layer barrier and an indium gallium arsenide layer as a channel layer. 28 and an indium phosphide layer 29 as an upper barrier, and the side surfaces of the crystallized indium phosphide 18 and the indium arsenide aluminum layer 27 are covered with the SiO 2 film 12.
  • This embodiment is basically the same in configuration and operation as the above-described first embodiment, and the configuration of the heat treatment apparatus used is different from that in the above-described first embodiment. Therefore, the description of the duplicated configuration and operation is omitted, and the description of the different configuration and operation is given below.
  • FIG. 12 is a cross-sectional view schematically showing a configuration of a heat treatment apparatus used in the fine structure forming method according to the present embodiment.
  • the heat treatment apparatus 30 includes a plurality of heat exchangers arranged to face the single crystal silicon substrate 10 placed on the susceptor 23 above the outside of the chamber 22 instead of the laser scanner 24 included in the heat treatment apparatus 21.
  • An LED lamp 31 (upper heat source) is provided.
  • a transmissive window 32 is fitted into the ceiling portion of the chamber 22 interposed between the LED lamp 31 and the susceptor 23, and the LED lamp 31 is monocrystalline silicon placed on the susceptor 23 by the LED lamp light R that passes through the transmissive window 32.
  • the entire substrate 10 is heated from above.
  • the range of the wavelength of the LED lamp light R irradiated by the LED lamp 31 is set to 800 nm to 950 nm.
  • the heat treatment apparatus 30 executes the recrystallization process of indium phosphide in FIG. Specifically, first, the lamp heater 25 starts heating the entire single crystal silicon substrate 10 placed on the susceptor 23, and the entire single crystal silicon substrate 10 is heated to a temperature lower than the melting point of indium phosphorus, for example, 800 Heat to ° C. (step S61).
  • the LED lamp 31 irradiates the LED lamp light R toward the surface of the single crystal silicon substrate 10 to start heating the indium phosphide 16 (step S62).
  • the LED lamp 31 irradiates the entire single crystal silicon substrate 10 from above with the LED lamp light R of the single crystal silicon substrate 10 as shown in FIG. Although it is attenuated, it reaches the (001) crystal plane 15 and all the temperatures of the indium phosphide 16 exceed the melting point of the indium phosphide as shown in the graph of the temperature gradient in the depth direction of the indium phosphide 16 in FIG. 8A. Thereby, all of the indium phosphide 16 filled in the trench 14 is melted.
  • the LED lamp 31 gradually reduces the output of the LED lamp light R to be irradiated.
  • the temperature of the indium phosphorus 16 is the (001) crystal plane as shown in the graph of the temperature gradient in the depth direction of the indium phosphorus 16 in FIG. 8B.
  • the temperature gradient decreases in the vicinity of 15, and the temperature gradient shifts to a lower temperature side than the temperature gradient in FIG. 8A. That is, the slow cooling of the indium phosphide 16 by the LED lamp 31 is started (step S63).
  • the LED lamp 31 stops the irradiation of the LED lamp light R.
  • the temperature of the indium phosphide 16 is lowered throughout the indium phosphide 16, and eventually, as shown in the graph of the temperature gradient in the depth direction of the indium phosphide 16 in FIG. Below the melting point. Thereby, the indium phosphide 16 is solidified and recrystallized as a whole. Thereafter, this process is terminated.
  • the LED lamp 31 gradually reduces the output of the LED lamp light R, thereby gradually reducing the amount of heating from above to the indium phosphorus 16 and reducing the temperature gradient in the depth direction of the indium phosphorus 16 to a low temperature. Since the molten indium phosphide 16 is gradually cooled from the (001) crystal plane 15 side, the same effects as the effects of the first embodiment can be obtained.
  • the present embodiment unlike the first embodiment, all the indium phosphines 16 filled in the trenches 14 are simultaneously heated and melted by the LED lamp light R, so that the fin-type channel 20 The formation throughput can be improved.
  • each LED lamp 31 gradually decreases the output of the LED lamp light R at the same time, but each LED lamp 31 may gradually decrease the output of the LED lamp light R at different timings.
  • the LED lamp 31 is used as the upper heat source instead of the laser scanner 24.
  • the LED lamp 31 is inexpensive, the manufacturing cost of the heat treatment apparatus 30 can be reduced.
  • the single crystal silicon substrate 10 is heated by the lamp heater 25. Or after the amount of heating from the lamp heater 25 to the single crystal silicon substrate 10 is reduced, the output of the LED lamp light R may be gradually decreased to start slow cooling of the indium phosphide 16. Alternatively, the heating amount of the single crystal silicon substrate 10 from the lamp heater 25 may be reduced after gradually decreasing the output of the LED lamp light R and starting the slow cooling of the indium phosphide 16.
  • This embodiment is basically the same in configuration and operation as the first embodiment described above, and the object to be heated by the laser light emitted by the laser scanner 24 is not indium phosphide 16 but Si 3 N 4. It is different from the first embodiment described above in that the films 11 and 13 and the SiO 2 films 12 and 17 are used. Therefore, the description of the duplicated configuration and operation is omitted, and the description of the different configuration and operation is given below.
  • the indium phosphide 16 is, for example, as shown in FIG. 2B, Si 3 N 4 films 11 and 13 and SiO 2 films 12 and 17 (hereinafter collectively referred to as “coating layer”). Surrounded by. Accordingly, since the indium phosphide 16 can be indirectly heated by heating the coating layer, in this embodiment, the wavelength of the laser light emitted by the laser scanner 24 is set to a wavelength that is easily absorbed by the coating layer. Is done.
  • the absorption coefficient of indium phosphide or germanium is almost 0, while as shown in FIGS. 13 and 14, silicon nitride (Si 3 N 4 ) or silicon oxide (SiO 2 ). (2 ) is increased (in FIG. 13, the amount of light absorbed relative to the wave number (reciprocal of the wavelength) is shown, but the range of the wavelength from 7600 nm to 10600 nm is indicated by an arrow in the figure).
  • the laser light wavelength range is set to 7600 nm to 10600 nm and the laser light is irradiated to indium phosphide, germanium, silicon oxide or silicon nitride
  • the energy of the laser light is absorbed by silicon oxide or silicon nitride, and silicon oxide While silicon nitride is heated and the temperature rises, indium phosphide and germanium almost transmit laser light, so indium phosphide and germanium are not heated by the laser light.
  • the wavelength range of the laser light emitted by the laser scanner 24 is set to 7600 nm to 10600 nm.
  • the wavelength of the CO 2 laser light is approximately 9300 nm to 10600 nm, the laser scanner 24 irradiates the CO 2 laser light as the laser light L.
  • the laser light L irradiated to the surface of the single crystal silicon substrate 10 by the laser scanner 24 is absorbed and attenuated by these films when passing through the coating layer as shown in FIG.
  • the indium phosphide 16 when passing through the indium phosphide 16, it passes through the indium phosphide 16 with little absorption, and the single crystal silicon substrate 10 gradually absorbs and gradually decreases.
  • the coating layer is selectively heated by irradiation with the laser beam L, and the indium phosphide 16 is indirectly heated by the coating layer whose temperature has increased.
  • the lamp heater 25 starts heating the entire single crystal silicon substrate 10 placed on the susceptor 23, and the single crystal silicon substrate 10 The whole is heated to a temperature lower than the melting point of indium phosphide, for example, 800 ° C. (step S61).
  • the laser scanner 24 irradiates the surface of the single crystal silicon substrate 10 with the laser light L and starts heating the coating layer (step S62). At this time, the laser scanner 24 scans the single crystal silicon substrate 10 with the laser light L.
  • the laser scanner 24 has two laser light irradiation units 24a and 24b arranged along the scanning direction, and the laser light irradiated by the laser light irradiation unit 24a arranged forward in the scanning direction.
  • the intensity of L 1 is set to be larger than the intensity of the laser light L s irradiated by the laser light irradiation unit 24b disposed rearward in the scanning direction.
  • the coating layer When the coating layer is irradiated with the laser beam L 1 having a high intensity, the coating layer is sufficiently heated, and the indium phosphide 16 is indirectly heated by the coating layer whose temperature has been increased. As shown in the graph of the temperature gradient for the 16 depth directions, all temperatures of indium phosphide 16 exceed the melting point of indium phosphide. Thereby, all of the indium phosphide 16 filled in the trench 14 is melted.
  • the laser intensity in the coating layer by the laser scanner 24 is moved a small light L s is to be irradiated, the laser beam L s incident on the coating layer disappears in the middle of the attenuation to the coating layer.
  • the laser beam L s does not reach the Si 3 N 4 film 11
  • the temperature in the vicinity of the (001) crystal plane 15 of the coating layer decreases, and the temperature gradient in the depth direction of the indium phosphide 16 in FIG.
  • the temperature of indium phosphide 16 decreases in the vicinity of the (001) crystal plane 15, and the temperature gradient shifts to a lower temperature side than the temperature gradient in FIG. 8A. That is, slow cooling of the indium phosphide 16 by the laser scanner 24 is started (step S63).
  • the temperature of the coating layer decreases over the entire coating layer, and eventually the depth of the indium phosphide 16 in FIG.
  • the temperature gradient graph for the vertical direction all temperatures of indium phosphide 16 are below the melting point of indium phosphide. Thereby, the indium phosphide 16 is solidified and recrystallized as a whole. Thereafter, this process is terminated.
  • the laser beam irradiation units 24a and 24b of the laser scanner 24 sequentially irradiate the laser beams L l and L s to the coating layer, thereby gradually decreasing the amount of heating from the upper side of the coating layer. Since the temperature gradient in the depth direction of the indium phosphide 16 is shifted to the low temperature side and the molten indium phosphide 16 is gradually cooled from the (001) crystal face 15 side, the same effect as that of the first embodiment can be obtained. Can play.
  • the indium phosphide 16 is indirectly heated by heating the coating layer surrounding the indium phosphide 16, the entire indium phosphide 16 can be uniformly heated, and a part of the indium phosphide 16 is heated. It is possible to prevent the grains 16 from remaining as grains without being melted, or a part of the indium phosphorus 16 from being cooled first to produce grains.
  • the (001) crystal plane 15 is exposed at the bottom of the trench 14, but the Miller index of the exposed crystal plane is not limited to this, for example, (010), (011), (100 ), (101), (110) or (111).
  • the fin-type channel 20 obtained by each of the above embodiments can be suitably used for a MOSFET having a three-dimensional structure, a so-called FinFET, but can be used for a nanorod FET. , LED, semiconductor laser, photodetector, solar cell and other photonic devices.
  • the fin-type channel 20 of indium phosphide is formed using the trench 14.
  • the channel is provided in the Si 3 N 4 film 33 or the SiO 2 film 34.
  • Quantum dots or nanorods may be formed by filling the holes 35 with indium phosphide 16 and subjecting the indium phosphide 16 to the recrystallization process of FIG.
  • the dissimilar semiconductor filled in the trench 14 is not limited to indium phosphide. And at least one of germanium.
  • each trench 14 it is not necessary to fill each trench 14 with the same kind of different semiconductor.
  • one trench 14 is filled with indium phosphorus 16 and the other trench 14 is filled with germanium 36. Also good.
  • the absorption coefficient of germanium exceeds the absorption coefficient of indium phosphide in the range where the wavelength of the laser beam is 800 nm to 950 nm, the wavelength of the indium phosphide 16 and germanium 36 filled in each trench 14 is increased.
  • the entire single crystal silicon substrate 10 is heated by the lamp heater 25.
  • the laser scanner 24 and the LED lamp are not heated by the lamp heater 25.
  • the single crystal silicon substrate 10 may be heated only by 31 or the heating by the lamp heater 25 and the heating by the laser scanner 24 or the LED lamp 31 may be started simultaneously.
  • silicon nitride or silicon oxide for forming the cover layer is Si It is not limited to 3 N 4 or SiO 2 but may be Si x N y or SiO x (x and y are arbitrary natural numbers).
  • silicon nitride, silicon oxide, and a different kind of semiconductor that form the coating layer may contain impurities.
  • the heterogeneous semiconductor formed in each of the above embodiments may be used as a base film for adjusting the lattice constant.
  • an object of the present invention is to supply a storage medium storing software program codes for realizing the functions of the above-described embodiments to a computer (not shown) provided in the heat treatment apparatus 21 and the like, and the CPU of the computer stores the storage medium. It is also achieved by reading and executing the program code stored on the medium.
  • the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code and the storage medium storing the program code constitute the present invention.
  • Examples of the storage medium for supplying the program code include RAM, NV-RAM, floppy (registered trademark) disk, hard disk, magneto-optical disk, CD-ROM, CD-R, CD-RW, DVD (DVD). -ROM, DVD-RAM, DVD-RW, DVD + RW) and other optical disks, magnetic tapes, non-volatile memory cards, other ROMs, etc., as long as they can store the program code.
  • the program code may be supplied to the computer by downloading from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.
  • the function expansion is performed based on the instruction of the program code.
  • the form of the program code may be in the form of object code, program code executed by an interpreter, script data supplied to the OS, and the like.
  • LED lamp light 10 Single crystal silicon substrate 11, 13, 33 Si 3 N 4 film 12, 17, 34 SiO 2 film 14 Trench 16 Indium phosphide 20 Channel 24 Laser scanner 24a, 24b Laser Light irradiation unit 31 LED lamp 35 hole 36 germanium

Abstract

Provided is a microstructure forming method that enables a high-quality compound semiconductor microstructure to be formed on a substrate. A trench (14) is formed in a SiO2 film (12), etc., that is formed on the upper surface of a single-crystal silicon substrate (10), and a (001) crystal plane (15) of the single-crystal silicon substrate (10) is exposed at the bottom of the trench (14). The trench (14) is filled with indium phosphide (16), and the filled indium phosphide (16) is heated and melted. The melted indium phosphide (16) is slowly cooled, the (001) crystal plane (15) is used as a seed, and the indium phosphide (16) is recrystallized. The SiO2 film (12), etc., is removed. During the heating of the indium phosphide (16), the filled indium phosphide (16) is heated by a laser scanner (24) that is positioned to the upper-surface side of the single-crystal silicon substrate (10). During the slow cooling of the indium phosphide (16), the intensity of a laser beam (L) from the laser scanner (24) is gradually decreased.

Description

微細構造形成方法、半導体デバイスの製造方法、及びＣＭＯＳの形成方法Fine structure forming method, semiconductor device manufacturing method, and CMOS forming method
　本発明は、異種半導体の微細構造を基板に形成する微細構造形成方法、半導体デバイスの製造方法、及びＣＭＯＳの形成方法に関する。 The present invention relates to a fine structure forming method for forming a fine structure of a heterogeneous semiconductor on a substrate, a semiconductor device manufacturing method, and a CMOS forming method.
　ＩＩＩ族元素（アルミニウム（Ａｌ）、ガリウム（Ｇａ）、インジウム（Ｉｎ））及びＶ族元素（リン（Ｐ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ））の化合物や、ゲルマニウム（Ｇｅ）からなる異種半導体には、半導体として一般的なシリコン（Ｓｉ）よりもキャリアの移動度が高く、バンドギャップが小さいものがあるため、異種半導体を用いることによってシリコンの物性を超える半導体素子を作成することができる。 Group III elements (aluminum (Al), gallium (Ga), indium (In)) and group V elements (phosphorus (P), arsenic (As), antimony (Sb)) compounds, or different types of germanium (Ge) Some semiconductors have higher carrier mobility and smaller band gap than silicon (Si), which is common as a semiconductor, and therefore, semiconductor elements exceeding the physical properties of silicon can be created by using different types of semiconductors. .
　一方、長年に亘ってシリコンからなるウエハがＵＬＳＩ製造基板として用いられ、直径が３００ｍｍの大口径ウエハを扱う製造プロセス装置群は世界中の量産工場に数多く導入されている。 On the other hand, for many years, silicon wafers have been used as ULSI manufacturing substrates, and many manufacturing process equipment groups that handle large-diameter wafers with a diameter of 300 mm have been introduced into mass production plants around the world.
　したがって、大口径ウエハ上へ結晶欠陥が無い高品質なガリウムヒ素（ＧａＡｓ）、ガリウムアンチモン（ＧａＳｂ）、インジウムリン（ＩｎＰ）、インジウムヒ素（ＩｎＡｓ）、インジウムアンチモン（ＩｎＳｂ）、ヒ化インジウムガリウム（ＩｎＧａＡｓ）、ゲルマニウム等の異種半導体の微細構造を形成することができれば、今まで蓄積された半導体製造技術の大半を用い、既に数多く導入されている製造プロセス装置群を使用してシリコンの物性を凌駕する異種半導体のＵＬＳＩを製造することが可能となり、もって、量産コストの上昇を回避しながらＵＬＳＩの性能を向上させることができる。 Therefore, high quality gallium arsenide (GaAs), gallium antimony (GaSb), indium phosphide (InP), indium arsenide (InAs), indium antimony (InSb), indium gallium arsenide (InGaAs) without crystal defects on a large-diameter wafer. ) If the fine structure of different semiconductors such as germanium can be formed, most of the accumulated semiconductor manufacturing technology will be used and the physical properties of silicon will be surpassed by using a large number of manufacturing process equipment already introduced. It becomes possible to manufacture ULSIs of different types of semiconductors, and thus it is possible to improve ULSI performance while avoiding an increase in mass production costs.
　ところが、単にシリコン上に上述した異種半導体を堆積させて微細構造を形成すると、シリコンと異種半導体の格子定数の違いから異種半導体の微細構造中に多くの結晶欠陥が生じるため、異種半導体からなる微細構造、例えば、トランジスタのチャネルに期待した性能を発揮させることが困難である。 However, if a fine structure is formed by simply depositing the above-mentioned dissimilar semiconductor on silicon, many crystal defects are generated in the fine structure of the dissimilar semiconductor due to the difference in lattice constant between silicon and the dissimilar semiconductor. It is difficult to achieve the performance expected for the structure, for example, the channel of the transistor.
　ところで、結晶欠陥の少ない異種半導体、例えば、インジウムリンを成長させる方法の一つとして、ＬＰＥ（Ｌｉｑｕｉｄ　Ｐｈａｓｅ　Ｅｐｉｔａｘｙ）法が知られている。ＬＰＥ法では、結晶成長炉内において、ヒータが巻回されたルツボに満たされたわずかにリンを含んだ液相のインジウムを、スライダに設けられたインジウムリンの結晶基板に接触させ、その後、ヒータによって液相のインジウムとインジウムリンの結晶基板との間に温度差を発生させ且つ該温度差を維持し、結晶基板を種として、該結晶基板の結晶面から結晶欠陥の少ないインジウムリンの結晶をエピタキシャル成長させる（例えば、特許文献１参照。）。また、ＬＰＥ法を用いて、シリコン基板上にインジウムリンの結晶を成長させる試みも報告されている（例えば、非特許文献１乃至３参照）。 Incidentally, an LPE (Liquid Phase Epitaxy) method is known as one of the methods for growing a heterogeneous semiconductor with few crystal defects, for example, indium phosphide. In the LPE method, liquid indium slightly containing phosphorus filled in a crucible around which a heater is wound is brought into contact with a crystal substrate of indium phosphorus provided on a slider in a crystal growth furnace. To generate a temperature difference between the liquid phase indium and the crystal substrate of indium phosphide and maintain the temperature difference, and using the crystal substrate as a seed, crystals of indium phosphide with few crystal defects are formed from the crystal plane of the crystal substrate. Epitaxial growth is performed (for example, see Patent Document 1). There have also been reports of attempts to grow indium phosphide crystals on a silicon substrate using the LPE method (see, for example, Non-Patent Documents 1 to 3).
　ところで、ＵＬＳＩのトランジスタを三次元形状に加工する場合、インジウムリンからなるフィン構造のトランジスタのチャネルに期待した性能を発揮させるためにはフィン構造の幅を１０ｎｍ程度に抑える必要がある。微細構造である幅が狭いフィン構造を形成するには、シリコン基板上の絶縁膜に幅狭のトレンチを形成し、該トレンチ内へインジウム溶液を流し込み、トレンチ内にてインジウムリンの結晶を成長させるのが好ましい。 By the way, when processing a ULSI transistor into a three-dimensional shape, it is necessary to suppress the width of the fin structure to about 10 nm in order to exhibit the performance expected for the channel of the fin structure transistor made of indium phosphide. In order to form a fine fin structure with a narrow width, a narrow trench is formed in an insulating film on a silicon substrate, an indium solution is poured into the trench, and an indium phosphorus crystal is grown in the trench. Is preferred.
特開昭６３−１４４２００号公報JP 63-144200 A
　しかしながら、トレンチ内へインジウム溶液を流し込む場合、当該インジウム溶液をルツボ内に満たして保持することができないため、ルツボに巻回されたヒータによってインジウム溶液の温度を制御することができない。その結果、インジウムリンの結晶をエピタキシャル成長させる際に、インジウム溶液及びインジウムリンの結晶基板の境界近傍以外の箇所でもインジウム溶液の温度が低下し、当該箇所においてインジウムリンのグレインが生じる。グレインはインジウムリンの電気的特性、例えば、抵抗率を変化させるため、インジウムリンからなる微細構造に期待した性能を発揮させることが困難である。すなわち、高品質な異種半導体の微細構造をウエハに形成するのは困難である。 However, when the indium solution is poured into the trench, the temperature of the indium solution cannot be controlled by the heater wound around the crucible because the indium solution cannot be filled and held in the crucible. As a result, when the crystal of indium phosphide is epitaxially grown, the temperature of the indium solution is lowered at places other than the vicinity of the boundary between the indium solution and the crystal substrate of indium phosphide, and grains of indium phosphide are produced at the places. Since grains change the electrical characteristics of indium phosphide, for example, the resistivity, it is difficult to exhibit the performance expected of a fine structure made of indium phosphide. That is, it is difficult to form a high quality heterogeneous semiconductor microstructure on a wafer.
　本発明の課題は、高品質な異種半導体の微細構造を基板に形成することができる微細構造形成方法、半導体デバイスの製造方法、及びＣＭＯＳの形成方法を提供することにある。 An object of the present invention is to provide a fine structure forming method, a semiconductor device manufacturing method, and a CMOS forming method capable of forming a high quality heterogeneous semiconductor fine structure on a substrate.
　上記課題を解決するために、本発明によれば、シリコン基板の上面に形成された被覆層に凹部を形成し、該凹部の底において前記シリコン基板のシリコンの結晶面を露出させる凹部形成ステップと、前記凹部に異種半導体を充填する充填ステップと、前記充填された異種半導体を加熱して溶融させる加熱ステップと、前記溶融した異種半導体を冷却して前記シリコンの結晶面を種として前記異種半導体を再結晶させる冷却ステップと、前記被覆層を除去する除去ステップとを有し、前記加熱ステップでは、少なくとも前記シリコン基板の上面側に配置された上方熱源によって前記充填された異種半導体を加熱し、前記冷却ステップでは、前記上方熱源からの加熱量を低減させることによって前記溶融した異種半導体を冷却する微細構造形成方法が提供される。 In order to solve the above-described problem, according to the present invention, a recess forming step of forming a recess in a coating layer formed on an upper surface of a silicon substrate and exposing a silicon crystal plane of the silicon substrate at the bottom of the recess; A filling step of filling the concave portion with a different semiconductor, a heating step of heating and melting the filled different semiconductor, and cooling the molten different semiconductor to seed the different semiconductor using the silicon crystal plane as a seed. A cooling step for recrystallization, and a removal step for removing the coating layer. In the heating step, the filled dissimilar semiconductor is heated by at least an upper heat source arranged on the upper surface side of the silicon substrate, In the cooling step, a microstructure is formed to cool the molten dissimilar semiconductor by reducing the amount of heating from the upper heat source. The law is provided.
　本発明によれば、高品質な異種半導体の微細構造を基板に形成することができる。 According to the present invention, a high-quality heterogeneous semiconductor microstructure can be formed on a substrate.
　［図１Ａ乃至図１Ｅ］本発明の第１の実施の形態に係る微細構造形成方法を示す工程図である。
　［図２Ａ乃至図２Ｅ］本実施の形態に係る微細構造形成方法を示す工程図である。
　［図３］本実施の形態に係る微細構造形成方法で用いられる熱処理装置の構成を概略的に示す断面図である。
　［図４］インジウムリン、ゲルマニウム及びシリコンの吸光係数を示すグラフである。
　［図５］本実施の形態に係る微細構造形成方法における、インジウムリン、Ｓｉ３Ｎ４膜及びＳｉＯ２膜によるレーザ光の吸収形態を示す断面図である。
　［図６］本実施の形態に係る微細構造形成方法において図３の熱処理装置が実行するインジウムリンの再結晶化処理を示すフローチャートである。
　［図７］図６の再結晶化処理において行われるレーザ光によるトレンチの走査を説明するための図である。
　［図８Ａ乃至図８Ｃ］図６の再結晶化処理において行われるインジウムリンの深さ方向に関する温度勾配の制御を説明するための図である。
　［図９］本実施の形態に係る微細構造形成方法によって形成されるヒ化インジウムガリウム／ヒ化インジウムアルミニウム量子井戸チャネルの構成を概略的に示す断面図である。
　［図１０］本実施の形態に係る微細構造形成方法が適用される、ヒ化インジウムガリウム／ヒ化インジウムアルミニウム量子井戸チャネルを有するプレーナー型のチャネルの構成を概略的に示す断面図である。
　［図１１］本実施の形態に係る微細構造形成方法が適用される、積層構造のヒ化インジウムガリウム／ヒ化インジウムアルミニウム量子井戸チャネルの構成を概略的に示す断面図である。
　［図１２］本発明の第２の実施の形態に係る微細構造形成方法で用いられる熱処理装置の構成を概略的に示す断面図である。
　［図１３］波数に対する窒化珪素（Ｓｉ３Ｎ４）の吸光量を示すグラフである。
　［図１４］酸化珪素（ＳｉＯ２）の吸光係数を示すグラフである。
　［図１５］本発明の第３の実施の形態に係る微細構造形成方法における、インジウムリン、Ｓｉ３Ｎ４膜及びＳｉＯ２膜によるレーザ光の吸収形態を示す断面図である。
　［図１６］本実施の形態に係る微細構造形成方法によって形成される量子ドットやナノロッドの構成を概略的に示す断面図である。
　［図１７］各トレンチにおいてインジウムリン及びゲルマニウムを同時に再結晶化する場合を説明するための断面図である。 FIG. 1A to FIG. 1E are process diagrams showing a fine structure forming method according to a first embodiment of the present invention.
[FIGS. 2A to 2E] FIGS. 2A to 2E are process diagrams showing a fine structure forming method according to the present embodiment.
FIG. 3 is a cross-sectional view schematically showing a configuration of a heat treatment apparatus used in the microstructure forming method according to the present embodiment.
FIG. 4 is a graph showing extinction coefficients of indium phosphide, germanium and silicon.
FIG. 5 is a cross-sectional view showing how laser light is absorbed by indium phosphide, a Si 3 N 4 film, and a SiO 2 film in the microstructure forming method according to the present embodiment.
FIG. 6 is a flowchart showing indium phosphide recrystallization processing executed by the heat treatment apparatus of FIG. 3 in the microstructure forming method according to the present embodiment.
FIG. 7 is a diagram for explaining scanning of a trench by laser light performed in the recrystallization process of FIG.
[FIGS. 8A to 8C] FIGS. 8A to 8C are diagrams for explaining temperature gradient control in the depth direction of indium phosphide performed in the recrystallization process of FIG.
FIG. 9 is a cross-sectional view schematically showing a configuration of an indium gallium arsenide / indium aluminum arsenide quantum well channel formed by the microstructure forming method according to the present embodiment.
FIG. 10 is a cross-sectional view schematically showing the configuration of a planar channel having indium gallium arsenide / indium aluminum arsenide quantum well channels to which the microstructure forming method according to the present embodiment is applied.
[FIG. 11] A cross-sectional view schematically showing a configuration of a laminated indium gallium arsenide / indium aluminum arsenide quantum well channel to which the microstructure forming method according to the present embodiment is applied.
FIG. 12 is a cross-sectional view schematically showing a configuration of a heat treatment apparatus used in the microstructure forming method according to the second embodiment of the present invention.
FIG. 13 is a graph showing the amount of absorption of silicon nitride (Si 3 N 4 ) with respect to wave number.
FIG. 14 is a graph showing the extinction coefficient of silicon oxide (SiO 2 ).
FIG. 15 is a cross-sectional view showing how laser light is absorbed by indium phosphide, a Si 3 N 4 film, and a SiO 2 film in the microstructure forming method according to the third embodiment of the present invention.
FIG. 16 is a cross-sectional view schematically showing a configuration of quantum dots and nanorods formed by the microstructure forming method according to the present embodiment.
FIG. 17 is a cross-sectional view for explaining the case where indium phosphide and germanium are simultaneously recrystallized in each trench.
　以下、本発明の実施の形態について図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　まず、本発明の第１の実施の形態に係る微細構造形成方法について説明する。 First, the microstructure formation method according to the first embodiment of the present invention will be described.
　本実施の形態では、シリコン基板としてミラー指数が（００１）の結晶面（以下、「（００１）結晶面」という。）を有する半導体ウエハとしての単結晶シリコン基板１０を用い、異種半導体としてインジウムリンを用い、微細構造としてトランジスタのフィン型のチャネルを形成する場合について説明する。以下の図１Ａ~図１Ｅ及び図２Ａ~図２Ｅは、本実施の形態に係る微細構造形成方法を示す工程図であり、各図は当該微細構造形成方法が適用される単結晶シリコン基板１０の表面（上面）近傍の拡大断面図である。 In the present embodiment, a single crystal silicon substrate 10 as a semiconductor wafer having a crystal plane with a Miller index (001) (hereinafter referred to as “(001) crystal plane”) is used as a silicon substrate, and indium phosphide is used as a heterogeneous semiconductor. A case where a fin-type channel of a transistor is formed as a fine structure will be described. FIGS. 1A to 1E and FIGS. 2A to 2E are process diagrams showing a fine structure forming method according to the present embodiment. Each drawing shows a single crystal silicon substrate 10 to which the fine structure forming method is applied. It is an expanded sectional view near the surface (upper surface).
　まず、単結晶シリコン基板１０を準備し（図１Ａ）、該単結晶シリコン基板１０の表面に堆積法、例えば、熱ＣＶＤ法、プラズマＣＶＤ法、ＡＬＤ法やＳＯＤ（Ｓｐｉｎ　Ｏｎ　Ｄｉｅｌｅｃｔｒｉｃ）法によってＳｉ３Ｎ４膜１１を形成し（図１Ｂ）、さらに、Ｓｉ３Ｎ４膜１１上に堆積法によってＳｉＯ２膜１２及びＳｉ３Ｎ４膜１３を順に形成する（図１Ｃ）。本実施の形態では、Ｓｉ３Ｎ４膜１１、ＳｉＯ２膜１２及びＳｉ３Ｎ４膜１３の３層の膜によって被覆層を形成したが、被覆層は１層や２層の膜によって形成されてもよく、３層以上の膜によって形成されてもよい。 First, a single crystal silicon substrate 10 is prepared (FIG. 1A), and Si 3 is deposited on the surface of the single crystal silicon substrate 10 by a deposition method, for example, a thermal CVD method, a plasma CVD method, an ALD method, or an SOD (Spin On Dielectric) method. An N 4 film 11 is formed (FIG. 1B), and an SiO 2 film 12 and an Si 3 N 4 film 13 are sequentially formed on the Si 3 N 4 film 11 by a deposition method (FIG. 1C). In the present embodiment, the covering layer is formed by three layers of the Si 3 N 4 film 11, the SiO 2 film 12, and the Si 3 N 4 film 13, but the covering layer is formed by one or two layers. Alternatively, it may be formed of three or more layers.
　次いで、フォトリソグラフィによってＳｉ３Ｎ４膜１３及びＳｉＯ２膜１２を順次エッチングしてトレンチ１４（凹部）を形成し（図１Ｄ）、さらに、Ｓｉ３Ｎ４膜１１をエッチングしてトレンチ１４の底において単結晶シリコン基板１０の（００１）結晶面１５を露出させる（図１Ｅ）（凹部形成ステップ）。エッチングによるトレンチ１４の形成には、反応性イオンエッチングやウェットエッチングを用いてもよく、反応性イオンエッチングでは処理ガスとして、例えば、ＣＦｘガスを用い、ウェットエッチングではエッチャントとして、例えば、リン酸（Ｈ３ＰＯ４）を用いることができる。トレンチ１４は、例えば、幅が１０ｎｍ~５０ｎｍ、好ましくは１０ｎｍであって、深さが１０ｎｍ~１００ｎｍであり、且つアスペクト（深さ／幅）比が１以上、好ましくは３~１０である。 Next, the Si 3 N 4 film 13 and the SiO 2 film 12 are sequentially etched by photolithography to form a trench 14 (concave portion) (FIG. 1D), and the Si 3 N 4 film 11 is further etched to form the bottom of the trench 14. In FIG. 1E, the (001) crystal plane 15 of the single crystal silicon substrate 10 is exposed (FIG. 1E) (recess formation step). For the formation of the trench 14 by etching, reactive ion etching or wet etching may be used. For example, CFx gas is used as a processing gas in reactive ion etching, and phosphoric acid (H, for example, is used as an etchant in wet etching. 3 PO 4 ) can be used. The trench 14 has, for example, a width of 10 nm to 50 nm, preferably 10 nm, a depth of 10 nm to 100 nm, and an aspect (depth / width) ratio of 1 or more, preferably 3 to 10.
　次いで、トレンチ１４の底に露出した（００１）結晶面１５を薬液、例えば、硫酸過酸化水素水（ＳＰＭ）、塩酸過酸化水素水（ＳＣ２）、希弗酸（ＤＨＦ）を用いて洗浄し、（００１）結晶面１５における結晶方位を整える（図１Ｅ）。なお、（００１）結晶面１５の洗浄を、例えば、弗化水素（ＨＦ）及びアンモニア（ＮＨ３）の混合ガスによるドライエッチングによって行ってもよい。 Next, the (001) crystal face 15 exposed at the bottom of the trench 14 is cleaned using a chemical solution, for example, sulfuric acid hydrogen peroxide solution (SPM), hydrochloric acid hydrogen peroxide solution (SC2), dilute hydrofluoric acid (DHF), The crystal orientation in the (001) crystal plane 15 is adjusted (FIG. 1E). The cleaning of the (001) crystal plane 15 may be performed by dry etching using a mixed gas of hydrogen fluoride (HF) and ammonia (NH 3 ), for example.
　次いで、トレンチ１４に気相又は固相でインジウムリン（ＩｎＰ）１６を充填する（充填ステップ）。インジウムリン１６の充填には、化学気相成長（ＣＶＤ）法が用いられる。特に、有機金属化合物ガスを原料として用いる有機金属ＣＶＤ（ＭＯＣＶＤ）法を用いる場合について説明すると、ＣＶＤ成膜装置（図示しない）において、単結晶シリコン基板１０を加熱しながら、ＩＩＩ族化合物であるトリメチルインジウム（ＴＭＩｎ）及びＶ族化合物であるターシャリーブチルフォスフィン（ＴＢＰ）を用い、これらを化学反応させてインジウムリン１６を生成し、該インジウムリン１６をトレンチ１４に充填する。インジウムリン１６の充填時、単結晶シリコン基板１０の全体を、例えば、４００℃~６５０℃とするのが好ましく、特に、充填されたインジウムリン１６がアモルファス状態又は多結晶状態となった場合におけるグレインの大きさを小さくするために、４００℃~４５０℃とするのが好ましい。なお、インジウムリン１６の充填の際、雰囲気の圧力は、例えば、１０×１０４Ｐａ~１０×１０５Ｐａとするのが好ましい。 Next, the trench 14 is filled with indium phosphide (InP) 16 in a gas phase or a solid phase (filling step). A chemical vapor deposition (CVD) method is used for filling indium phosphide 16. In particular, the case of using a metal organic chemical vapor deposition (MOCVD) method using a metal organic compound gas as a raw material will be described. In a CVD film forming apparatus (not shown), a single crystal silicon substrate 10 is heated while trimethyl which is a group III compound. Using indium (TMIn) and group V compound tertiary butylphosphine (TBP), these are chemically reacted to form indium phosphide 16, and the indium phosphide 16 is filled in the trench 14. When the indium phosphide 16 is filled, the entire single crystal silicon substrate 10 is preferably set to, for example, 400 ° C. to 650 ° C. Particularly, the grain in the case where the filled indium phosphide 16 is in an amorphous state or a polycrystalline state. In order to reduce the size, the temperature is preferably set to 400 ° C. to 450 ° C. In addition, when filling indium phosphide 16, the pressure of the atmosphere is preferably 10 × 10 4 Pa to 10 × 10 5 Pa, for example.
　インジウムリン１６をトレンチ１４に充填する際、トレンチ１４の底には（００１）結晶面１５が露出する一方、単結晶シリコン基板１０の表面はＳｉ３Ｎ４膜１３で覆われるため、（００１）結晶面１５及びＳｉ３Ｎ４膜１３の表面の化学状態の差異に起因してインジウムリン１６はＳｉ３Ｎ４膜１３よりも（００１）結晶面１５において優先的に生成される。これにより、トレンチ１４にインジウムリン１６が優先的に充填される（図２Ａ）。なお、トレンチ１４へのインジウムリン１６の充填方法はＣＶＤ法に限られず、液相以外でインジウムリン１６をトレンチ１４へ充填する方法であればよい。例えば、インジウム、または、インジウムリンをターゲットとする物理気相成長（ＰＶＤ）法や原子層体積（ＡＬＤ）法を利用してもよい。若しくは、インジウムリンの微細粉末をトレンチ１４へ直接埋め込む方法を利用してもよい。なお、インジウムをターゲットとする場合は、リン雰囲気において処理を実行することによってインジウムリンを形成してもよく、又は、インジウムを形成後にリンをドーピングしてインジウムリンを形成してもよい。さらに、インジウムリン１６をトレンチ１４へ充填する方法として、複数の成膜法を組み合わせてもよい。 When indium phosphide 16 is filled in the trench 14, the (001) crystal plane 15 is exposed at the bottom of the trench 14, while the surface of the single crystal silicon substrate 10 is covered with the Si 3 N 4 film 13, so that (001) Due to the difference in chemical state between the crystal plane 15 and the surface of the Si 3 N 4 film 13, indium phosphide 16 is preferentially generated in the (001) crystal plane 15 over the Si 3 N 4 film 13. This preferentially fills the trench 14 with indium phosphide 16 (FIG. 2A). The method for filling the trench 14 with the indium phosphide 16 is not limited to the CVD method, and any method may be used as long as the indium phosphide 16 is filled into the trench 14 except for the liquid phase. For example, a physical vapor deposition (PVD) method or an atomic layer volume (ALD) method using indium or indium phosphorus as a target may be used. Alternatively, a method of directly embedding fine powder of indium phosphide into the trench 14 may be used. Note that when indium is used as a target, indium phosphorus may be formed by performing treatment in a phosphorus atmosphere, or indium phosphorus may be formed by doping phosphorus after forming indium. Furthermore, as a method of filling the indium phosphide 16 into the trench 14, a plurality of film forming methods may be combined.
　次いで、堆積法によってトレンチ１４に充填されたインジウムリン１６の頂部を含む単結晶シリコン基板１０の表面をＳｉＯ２膜１７で覆い（図２Ｂ）、その後、後述する図６の再結晶化処理を実行してインジウムリン１６を加熱し（加熱ステップ）、加熱によって溶融したインジウムリン１６を（００１）結晶面１５の近傍から徐冷すると、（００１）結晶面１５を種として結晶化インジウムリン１８が析出する（インジウムリン１６の再結晶化）（図２Ｃ）（冷却ステップ）。なお、インジウムリン１６を溶融する際、インジウムリンの融点が１０６２℃である一方、ＳｉＯ２の融点は１６５０℃であるため、インジウムリン１６が溶融する温度となっても、ＳｉＯ２膜１７は溶融しない。したがって、溶融したインジウムリン１６はＳｉＯ２膜１７によってトレンチ１４内に留められる。また、ＳｉＯ２膜１７はインジウムリン１６を覆うように形成されているため、インジウムリン１６からのリンの脱離を防止することができる。 Next, the surface of the single crystal silicon substrate 10 including the tops of the indium phosphines 16 filled in the trenches 14 is covered with a SiO 2 film 17 by a deposition method (FIG. 2B), and then a recrystallization process of FIG. Then, the indium phosphide 16 is heated (heating step), and when the indium phosphide 16 melted by the heating is gradually cooled from the vicinity of the (001) crystal face 15, the crystallized indium phosphide 18 is precipitated using the (001) crystal face 15 as a seed. (Recrystallization of indium phosphide 16) (FIG. 2C) (cooling step). It should be noted that in the melted indium phosphide 16, one melting point of indium phosphide is 1062 ° C., the melting point of SiO 2 is 1650 ° C., even if the temperature of the indium phosphide 16 melts, SiO 2 film 17 is melted do not do. Therefore, the melted indium phosphide 16 is retained in the trench 14 by the SiO 2 film 17. Further, since the SiO 2 film 17 is formed so as to cover the indium phosphorus 16, it is possible to prevent phosphorus from being detached from the indium phosphorus 16.
　結晶化インジウムリン１８が析出する際、当該結晶化インジウムリン１８はミラー指数（００１）の結晶性を引き継ぐが、シリコンとインジウムリンの格子定数は異なるため、（００１）結晶面１５から格子不整合に起因する貫通転位欠陥１９が発生する。ここで、貫通転位欠陥１９は（００１）結晶面１５に対して垂直ではなく、斜め、例えば、４５°の方向に沿って成長する。したがって、トレンチ１４のアスペクト比が１以上であれば、貫通転位欠陥１９がトレンチ１４の頂部に到達することはなく、同アスペクト比を２以上とすれば、結晶化インジウムリン１８において貫通転位欠陥１９が存在しない部分を十分に確保することができる。また、同アスペクト比を３~１０とすれば、結晶化インジウムリン１８において貫通転位欠陥１９が存在しない部分をより十分に確保することができる。 When crystallized indium phosphide 18 precipitates, the crystallized indium phosphide 18 inherits the crystallinity of the Miller index (001). However, since the lattice constants of silicon and indium phosphide are different, the lattice mismatch from (001) crystal plane 15 occurs. A threading dislocation defect 19 is generated due to the above. Here, the threading dislocation defect 19 is not perpendicular to the (001) crystal plane 15 but grows obliquely, for example, along a direction of 45 °. Therefore, if the aspect ratio of the trench 14 is 1 or more, the threading dislocation defect 19 does not reach the top of the trench 14. If the aspect ratio is 2 or more, the threading dislocation defect 19 in the crystallized indium phosphorus 18. It is possible to secure a sufficient portion where no exists. Further, if the aspect ratio is 3 to 10, a portion where the threading dislocation defect 19 does not exist in the crystallized indium phosphide 18 can be more sufficiently secured.
　次いで、トレンチ１４内が全て結晶化インジウムリン１８で満たされた後、ＳｉＯ２膜１７やＳｉ３Ｎ４膜１３をウェットエッチング、ドライエッチング、ＣＭＰ等によって除去する（図２Ｄ）。 Next, after the trench 14 is entirely filled with crystallized indium phosphide 18, the SiO 2 film 17 and the Si 3 N 4 film 13 are removed by wet etching, dry etching, CMP, or the like (FIG. 2D).
　次いで、ＳｉＯ２膜１２をウェットエッチング、または、ドライエッチングによって除去し、結晶化インジウムリン１８のフィン型のチャネル２０を得る（図２Ｅ）（除去ステップ）。得られたチャネル２０にはトレンチ１４の形状が反映されるため、チャネル２０のアスペクト比はトレンチ１４のアスペクト比とほぼ同じであり、１以上、好ましくは３~１０となる。次いで、チャネル２０を得た後、本実施の形態に係る微細構造形成方法を終了する。 Next, the SiO 2 film 12 is removed by wet etching or dry etching to obtain a fin-type channel 20 of crystallized indium phosphide 18 (FIG. 2E) (removal step). Since the shape of the trench 14 is reflected in the obtained channel 20, the aspect ratio of the channel 20 is substantially the same as the aspect ratio of the trench 14 and is 1 or more, preferably 3 to 10. Next, after obtaining the channel 20, the fine structure forming method according to the present embodiment is finished.
　ところで、上述したように、加熱によって溶融したインジウムリン１６を（００１）結晶面１５の近傍から徐冷する際、トレンチ１４に充填されたインジウムリン１６の深さ方向に関する温度勾配を制御しなければ、（００１）結晶面１５の近傍以外の箇所の温度が（００１）結晶面１５の近傍の温度よりも先に低下して当該箇所においてインジウムリン１６のグレインが生じる。 By the way, as described above, when the indium phosphide 16 melted by heating is gradually cooled from the vicinity of the (001) crystal plane 15, the temperature gradient in the depth direction of the indium phosphide 16 filled in the trench 14 must be controlled. , The temperature of the portion other than the vicinity of the (001) crystal plane 15 is lowered before the temperature of the vicinity of the (001) crystal plane 15, and the grains of indium phosphide 16 are generated at the location.
　本実施の形態に係る微細構造形成方法では、これに対応してインジウムリン１６を（００１）結晶面１５の近傍から徐冷する際、インジウムリン１６の深さ方向に関する温度勾配を制御する。 In the fine structure forming method according to the present embodiment, when the indium phosphide 16 is gradually cooled from the vicinity of the (001) crystal plane 15, the temperature gradient in the depth direction of the indium phosphide 16 is controlled.
　図３は、本実施の形態に係る微細構造形成方法で用いられる熱処理装置の構成を概略的に示す断面図である。図３の熱処理装置２１はトレンチ１４に充填されたインジウムリン１６の溶融、徐冷及び再結晶化に用いられる。 FIG. 3 is a cross-sectional view schematically showing a configuration of a heat treatment apparatus used in the fine structure forming method according to the present embodiment. The heat treatment apparatus 21 of FIG. 3 is used for melting, gradual cooling, and recrystallization of the indium phosphide 16 filled in the trench 14.
　図３において、熱処理装置２１は、単結晶シリコン基板１０を収容し、且つクォーツ（石英）からなるチャンバ２２と、該チャンバ２２内に配置されて単結晶シリコン基板１０を載置するテーブル状のサセプタ２３と、チャンバ２２内においてサセプタ２３の上方に配置されたレーザスキャナ２４（上方熱源、レーザ光照射装置）と、チャンバ２２の外の下方においてサセプタ２３を指向するように配置された複数のランプヒータ２５（下方熱源）とを備える。 In FIG. 3, a heat treatment apparatus 21 contains a single crystal silicon substrate 10, a chamber 22 made of quartz (quartz), and a table-like susceptor placed in the chamber 22 and on which the single crystal silicon substrate 10 is placed. 23, a laser scanner 24 (upper heat source, laser light irradiation device) disposed above the susceptor 23 in the chamber 22, and a plurality of lamp heaters disposed to face the susceptor 23 below the chamber 22 25 (downward heat source).
　レーザスキャナ２４はサセプタ２３に載置された単結晶シリコン基板１０に対向しながら、該単結晶シリコン基板１０の表面と平行に移動する（図中白抜き矢印参照）。また、レーザスキャナ２４は移動方向に沿って配列された２つのレーザ光照射部２４ａ、２４ｂ（一のレーザ光照射部、他のレーザ光照射部）を有する。２つのレーザ光照射部２４ａ、２４ｂはサセプタ２３に載置された単結晶シリコン基板１０の表面に向けてレーザ光を照射してトレンチ１４に充填されたインジウムリン１６を加熱する。 The laser scanner 24 moves in parallel with the surface of the single crystal silicon substrate 10 while facing the single crystal silicon substrate 10 placed on the susceptor 23 (see white arrows in the figure). The laser scanner 24 includes two laser light irradiation units 24a and 24b (one laser light irradiation unit and another laser light irradiation unit) arranged in the moving direction. The two laser light irradiation units 24 a and 24 b irradiate the surface of the single crystal silicon substrate 10 placed on the susceptor 23 with laser light to heat the indium phosphide 16 filled in the trench 14.
　ランプヒータ２５及びサセプタ２３の間に介在するチャンバ２２の底部には透過窓２６が嵌め込まれ、ランプヒータ２５は透過窓２６を透過するランプ光によってサセプタ２３に載置された単結晶シリコン基板１０を加熱する。 A transmission window 26 is fitted into the bottom of the chamber 22 interposed between the lamp heater 25 and the susceptor 23, and the lamp heater 25 causes the single crystal silicon substrate 10 placed on the susceptor 23 to be moved by the lamp light transmitted through the transmission window 26. Heat.
　トレンチ１４に充填されたインジウムリン１６を溶融する際、加熱によるトランジスタにおける電極や絶縁膜の破壊を防止するために、インジウムリン１６のみを選択的に加熱するのが好ましいので、２つのレーザ光照射部２４ａ、２４ｂが照射するレーザ光の波長はインジウムリン１６に吸収されやすい波長に設定される。 When the indium phosphide 16 filled in the trench 14 is melted, it is preferable to selectively heat only the indium phosphide 16 in order to prevent the breakdown of the electrodes and the insulating film in the transistor due to heating. The wavelength of the laser light irradiated by the parts 24a and 24b is set to a wavelength that is easily absorbed by the indium phosphide 16.
　図４は、インジウムリン、ゲルマニウム及びシリコンの吸光係数を示すグラフである。図４のグラフの横軸はインジウムリン等に照射されるレーザ光の波長であり、同縦軸は吸光係数である。 FIG. 4 is a graph showing the extinction coefficients of indium phosphide, germanium, and silicon. The horizontal axis of the graph of FIG. 4 is the wavelength of the laser light irradiated to indium phosphorus or the like, and the vertical axis is the extinction coefficient.
　図４のグラフにおいて、レーザ光の波長が８００ｎｍ~９５０ｎｍである範囲では、インジウムリンやゲルマニウムの吸光係数がシリコンの吸光係数に比べて一桁以上高くなる。また、図４のグラフには示されないが、酸化珪素（ＳｉＯ２）や窒化珪素（Ｓｉ３Ｎ４）の吸光係数はレーザ光の波長が８００ｎｍ~９５０ｎｍである範囲においてほぼ０であり、酸化珪素や窒化珪素は当該レーザ光を透過させる。 In the graph of FIG. 4, in the range where the wavelength of the laser light is 800 nm to 950 nm, the extinction coefficient of indium phosphide or germanium is higher by one digit or more than the extinction coefficient of silicon. Although not shown in the graph of FIG. 4, the absorption coefficient of silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ) is almost 0 in the range where the wavelength of the laser beam is 800 nm to 950 nm. And silicon nitride transmits the laser light.
　すなわち、レーザ光の波長の範囲を８００ｎｍ~９５０ｎｍに設定して当該レーザ光をインジウムリン、ゲルマニウム、シリコン、酸化珪素や窒化珪素に照射すると、レーザ光のエネルギーがインジウムリンやゲルマニウムに吸収されてインジウムリンやゲルマニウムが加熱される一方、シリコン、酸化珪素や窒化珪素はレーザ光をほぼ透過させてしまうため、シリコン、酸化珪素や窒化珪素はほとんど加熱されず、結果として、インジウムリンやゲルマニウムを選択的に加熱することができる。 That is, when the laser light wavelength range is set to 800 nm to 950 nm and the laser light is irradiated to indium phosphide, germanium, silicon, silicon oxide, or silicon nitride, the energy of the laser light is absorbed by indium phosphide or germanium. While phosphorus and germanium are heated, silicon, silicon oxide, and silicon nitride almost transmit laser light, so silicon, silicon oxide, and silicon nitride are hardly heated. As a result, indium phosphorus and germanium are selectively used. Can be heated.
　したがって、２つのレーザ光照射部２４ａ、２４ｂが照射するレーザ光の波長の範囲は８００ｎｍ~９５０ｎｍに設定される。このとき、２つのレーザ光照射部２４ａ、２４ｂが単結晶シリコン基板１０の表面へ向けて照射したレーザ光Ｌは、図５に示すように、インジウムリン１６を通過する際にインジウムリン１６に吸収されて減衰する一方、ＳｉＯ２膜１７、Ｓｉ３Ｎ４膜１３、ＳｉＯ２膜１２及びＳｉ３Ｎ４膜１１を通過する際に殆ど吸収されることなくこれらの膜を通過し、単結晶シリコン基板１０においても徐々に吸収されて漸減する。これにより、レーザ光Ｌの照射によってインジウムリン１６のみを選択的に加熱することができる。 Accordingly, the range of the wavelength of the laser light irradiated by the two laser light irradiation units 24a and 24b is set to 800 nm to 950 nm. At this time, the laser light L irradiated by the two laser light irradiation units 24a and 24b toward the surface of the single crystal silicon substrate 10 is absorbed by the indium phosphorus 16 when passing through the indium phosphorus 16 as shown in FIG. While passing through the SiO 2 film 17, Si 3 N 4 film 13, SiO 2 film 12 and Si 3 N 4 film 11, the film passes through these films with almost no absorption, and single crystal silicon. Even the substrate 10 is gradually absorbed and gradually decreased. Thereby, only the indium phosphide 16 can be selectively heated by irradiation with the laser beam L.
　図６は、本実施の形態に係る微細構造形成方法において図３の熱処理装置が実行するインジウムリンの再結晶化処理を示すフローチャートである。 FIG. 6 is a flowchart showing indium phosphide recrystallization processing executed by the heat treatment apparatus of FIG. 3 in the microstructure forming method according to the present embodiment.
　まず、トレンチ１４にインジウムリン１６が充填され、且つ表面がＳｉＯ２膜１７で覆われた単結晶シリコン基板１０がチャンバ２２内に搬入されてサセプタ２３に載置されると、ランプヒータ２５がランプ光（図示しない）によってサセプタ２３の下側を照射して単結晶シリコン基板１０の全体の加熱を開始し、単結晶シリコン基板１０の全体をインジウムリンの融点（１０６２℃）より低い温度、例えば、８００℃まで加熱する（ステップＳ６１）。 First, when the single crystal silicon substrate 10 in which the trench 14 is filled with indium phosphide 16 and the surface is covered with the SiO 2 film 17 is loaded into the chamber 22 and placed on the susceptor 23, the lamp heater 25 is moved to the lamp heater 25. The lower side of the susceptor 23 is irradiated with light (not shown) to start heating the entire single crystal silicon substrate 10, and the entire single crystal silicon substrate 10 is heated to a temperature lower than the melting point of indium phosphide (1062 ° C.), for example, Heat to 800 ° C. (step S61).
　次いで、レーザスキャナ２４が単結晶シリコン基板１０の表面に向けてレーザ光Ｌを照射してインジウムリン１６の加熱を開始する（ステップＳ６２）。このとき、レーザスキャナ２４は、図７に示すように、単結晶シリコン基板１０に形成された各トレンチ１４に沿って移動すること（図中白抜き矢印参照）により、各トレンチ１４をレーザ光で走査する。 Next, the laser scanner 24 irradiates the surface of the single crystal silicon substrate 10 with the laser light L and starts heating the indium phosphide 16 (step S62). At this time, as shown in FIG. 7, the laser scanner 24 moves along each trench 14 formed in the single crystal silicon substrate 10 (see the white arrow in the figure), so that each trench 14 is irradiated with laser light. Scan.
　上述したように、レーザスキャナ２４は移動（走査）方向に沿って配列された２つのレーザ光照射部２４ａ、２４ｂを有するが、走査方向に関して前方に配置されたレーザ光照射部２４ａが照射するレーザ光Ｌｌの強度は、走査方向に関して後方に配置されたレーザ光照射部２４ｂが照射するレーザ光Ｌｓの強度よりも大きく設定される。例えば、レーザ光Ｌｌの強度はレーザ光Ｌｓの強度の２倍に設定される。これにより、レーザスキャナ２４が移動する際、トレンチ１４における点Ａのインジウムリン１６には、まず、強度が大きいレーザ光Ｌｌが照射され、次いで、強度が小さいレーザ光Ｌｓが照射され、その後、いずれのレーザ光Ｌｌ、Ｌｓも照射されなくなる。 As described above, the laser scanner 24 includes the two laser light irradiation units 24a and 24b arranged along the movement (scanning) direction, but the laser beam irradiated by the laser light irradiation unit 24a disposed forward in the scanning direction. The intensity of the light L 1 is set to be larger than the intensity of the laser light L s irradiated by the laser light irradiation unit 24b disposed rearward in the scanning direction. For example, the intensity of the laser beam L 1 is set to twice the intensity of the laser beam L s . As a result, when the laser scanner 24 moves, the indium phosphide 16 at the point A in the trench 14 is first irradiated with the laser beam L 1 having a high intensity, and then irradiated with the laser beam L s having a low intensity. , Neither of the laser beams L 1 and L s is irradiated.
　点Ａのインジウムリン１６に強度が大きいレーザ光Ｌｌが照射されると、インジウムリン１６に入射したレーザ光Ｌｌは減衰しながらも（００１）結晶面１５まで到達し、インジウムリン１６全体が十分に加熱され、図８Ａのインジウムリン１６の深さ方向に関する温度勾配のグラフに示すように、インジウムリン１６の全ての温度がインジウムリンの融点を超える。これにより、トレンチ１４に充填されたインジウムリン１６の全てが溶融する。 When indium phosphide 16 strength is greater the laser beam L l of the point A is illuminated, the laser light L l incident on indium phosphide 16 while attenuating reached (001) crystal plane 15, the entire indium phosphide 16 Fully heated, all temperatures of indium phosphide 16 exceed the melting point of indium phosphide, as shown in the temperature gradient graph of indium phosphide 16 in the depth direction of FIG. 8A. Thereby, all of the indium phosphide 16 filled in the trench 14 is melted.
　次いで、レーザスキャナ２４が移動して点Ａのインジウムリン１６に強度が小さいレーザ光Ｌｌが照射されるようになると、インジウムリン１６に入射したレーザ光Ｌｓは減衰してインジウムリン１６の半ばで消滅する。このとき、レーザ光Ｌｓは（００１）結晶面１５まで到達しないので、図８Ｂのインジウムリン１６の深さ方向に関する温度勾配のグラフに示すように、インジウムリン１６の温度は（００１）結晶面１５の近傍において低下して温度勾配は図８Ａの温度勾配よりも低温側に移行する。すなわち、レーザスキャナ２４によるインジウムリン１６の徐冷が開始される（ステップＳ６３）。 Next, when the laser scanner 24 moves and the indium phosphide 16 at the point A is irradiated with the low intensity laser light L 1 , the laser light L s incident on the indium phosphide 16 is attenuated and is halfway in the indium phosphide 16. Disappears. At this time, since the laser beam L s does not reach the (001) crystal plane 15, the temperature of the indium phosphor 16 is the (001) crystal plane as shown in the graph of the temperature gradient in the depth direction of the indium phosphor 16 in FIG. 8B. The temperature gradient decreases in the vicinity of 15, and the temperature gradient shifts to a lower temperature side than the temperature gradient in FIG. 8A. That is, slow cooling of the indium phosphide 16 by the laser scanner 24 is started (step S63).
　図８Ｂでは、低温側に移行した温度勾配が融点と交差する点Ｐよりも下の部分に対応するインジウムリン１６は凝固し、結晶面１５を種として結晶化インジウムリン１８が析出する一方、点Ｐよりも上の部分に対応するインジウムリン１６は溶融したままである。 In FIG. 8B, the indium phosphide 16 corresponding to the portion below the point P where the temperature gradient that has shifted to the low temperature side intersects the melting point solidifies, and crystallized indium phosphide 18 precipitates using the crystal plane 15 as a seed. The indium phosphide 16 corresponding to the portion above P remains molten.
　次いで、さらにレーザスキャナ２４が移動して点Ａのインジウムリン１６にいずれのレーザ光Ｌｌ、Ｌｓも照射されなくなると、インジウムリン１６の温度はインジウムリン１６の全体において低下し、やがて図８Ｃのインジウムリン１６の深さ方向に関する温度勾配のグラフに示すように、インジウムリン１６の全ての温度がインジウムリンの融点を下回る。これにより、インジウムリン１６は凝固して全体的に再結晶化する。その後、本処理を終了する。 Next, when the laser scanner 24 further moves and the indium phosphide 16 at the point A is no longer irradiated with any of the laser beams L 1 and L s , the temperature of the indium phosphide 16 decreases over the entire indium phosphide 16, and eventually FIG. 8C As shown in the graph of the temperature gradient with respect to the depth direction of indium phosphide 16, all the temperatures of indium phosphide 16 are lower than the melting point of indium phosphide. Thereby, the indium phosphide 16 is solidified and recrystallized as a whole. Thereafter, this process is terminated.
　すなわち、図６の再結晶処理によれば、点Ａのインジウムリン１６にレーザスキャナ２４のレーザ光照射部２４ａ、２４ｂがレーザ光Ｌｌ、Ｌｓを順に照射することにより、インジウムリン１６への上方からの加熱量を漸減させてインジウムリン１６の深さ方向に関する温度勾配を低温側に移行させ、溶融したインジウムリン１６を（００１）結晶面１５側から徐冷する。これにより、トレンチ１４に充填されたインジウムリン１６の温度は（００１）結晶面１５の近傍から低下し、（００１）結晶面１５の近傍以外の箇所が（００１）結晶面１５の近傍よりも先に温度が低下することがない。その結果、（００１）結晶面１５を種としてインジウムリン１６を再結晶させる際、結晶化インジウムリン１８においてグレインが生じるのを防止することができ、もって、高品質な結晶化インジウムリン１８のチャネル２０を基板に形成することができる。 That is, according to the recrystallization process in FIG. 6, the laser light irradiation units 24 a and 24 b of the laser scanner 24 sequentially irradiate the indium phosphorus 16 at the point A with the laser light L 1 and L s in order. The amount of heating from above is gradually reduced to shift the temperature gradient in the depth direction of the indium phosphide 16 to the low temperature side, and the molten indium phosphide 16 is gradually cooled from the (001) crystal plane 15 side. As a result, the temperature of indium phosphide 16 filled in the trench 14 decreases from the vicinity of the (001) crystal plane 15, and locations other than the vicinity of the (001) crystal plane 15 are ahead of the vicinity of the (001) crystal plane 15. The temperature never drops. As a result, when the indium phosphide 16 is recrystallized using the (001) crystal plane 15 as a seed, it is possible to prevent the generation of grains in the crystallized indium phosphide 18, and thus the channel of the high quality crystallized indium phosphide 18 20 can be formed on the substrate.
　上述した図６の再結晶処理では、点Ａにおけるインジウムリン１６の溶融、徐冷及び再結晶化について説明したが、レーザスキャナ２４が各トレンチ１４をレーザ光で走査する際、レーザ光照射部２４ａ、２４ｂが各トレンチ１４に充填された全てのインジウムリン１６にレーザ光Ｌｌ、Ｌｓを順に照射することになるため、図６の再結晶処理は各トレンチ１４に充填された全てのインジウムリン１６に施され、全てのインジウムリン１６が再結晶化される。 In the recrystallization process of FIG. 6 described above, the melting, slow cooling, and recrystallization of the indium phosphide 16 at the point A has been described. However, when the laser scanner 24 scans each trench 14 with a laser beam, the laser beam irradiation unit 24a. , 24b irradiates all the indium phosphides 16 filled in the trenches 14 with the laser beams L 1 and L s in order, so that the recrystallization process of FIG. 16 and all the indium phosphide 16 is recrystallized.
　図６の再結晶処理では、レーザ光Ｌｌ、Ｌｓが照射される部分は単結晶シリコン基板１０の全体に比して非常に小さいため、レーザ光Ｌｌ、Ｌｓの照射によって温度が上昇する部分は非常に小さく、加熱時のサーマルショックによる単結晶シリコン基板１０の反りや割れを誘発することはなく、他の部位への熱影響を抑制することができる。また、当該部分の加熱に必要な熱量も少なくてよいため、レーザスキャナ２４の消費電力を削減することができる。 In the recrystallization process of FIG. 6, the portions irradiated with the laser beams L l and L s are very small as compared with the entire single crystal silicon substrate 10, so that the temperature rises due to the irradiation of the laser beams L l and L s The portion to be processed is very small and does not induce warping or cracking of the single crystal silicon substrate 10 due to thermal shock during heating, and can suppress the thermal influence on other parts. Further, since the amount of heat necessary for heating the portion may be small, the power consumption of the laser scanner 24 can be reduced.
　上述した図６の再結晶処理では、ランプヒータ２５のランプ光によって単結晶シリコン基板１０が加熱されるので、インジウムリン１６を溶融させるために必要なレーザスキャナ２４からのレーザ光Ｌｌ、Ｌｓの強度を低減することができ、もって、レーザスキャナ２４を高出力のレーザ照射装置によって構成する必要を無くし、レーザスキャナ２４の構成を簡素化することができる。さらに、レーザ光Ｌｌが分担する、インジウムリン１６を溶融させるために必要なインジウムリン１６の温度上昇幅が小さくなるので、レーザ光Ｌｌの強度を調整することにより、インジウムリン１６の温度が融点を越えるか否かを正確に制御することができる。 In the recrystallization process of FIG. 6 described above, since the single crystal silicon substrate 10 is heated by the lamp light of the lamp heater 25, the laser lights L 1 and L s from the laser scanner 24 necessary for melting the indium phosphide 16 are used. Therefore, it is not necessary to configure the laser scanner 24 with a high-power laser irradiation device, and the configuration of the laser scanner 24 can be simplified. Further, the laser beam L l takes charge, the temperature rise of indium phosphide 16 required to melt the indium phosphide 16 is reduced, by adjusting the intensity of the laser beam L l, the temperature of the indium phosphide 16 Whether or not the melting point is exceeded can be accurately controlled.
　また、上述した図６の再結晶処理では、レーザ光Ｌｌによるインジウムリン１６の溶融に先立ってランプヒータ２５のランプ光による単結晶シリコン基板１０の加熱が開始されるので、インジウムリン１６を溶融させる際に単結晶シリコン基板１０の温度が急変することがなく、単結晶シリコン基板１０の反りや割れの発生を防止することができる。 Further, recrystallization process in FIG. 6 described above, the heating of the single crystal silicon substrate 10 by the lamp light of the lamp heater 25 prior to melting of the indium phosphide 16 by the laser beam L l is initiated, the molten indium phosphide 16 In this case, the temperature of the single crystal silicon substrate 10 does not change suddenly, and warpage and cracking of the single crystal silicon substrate 10 can be prevented.
　上述した図６の再結晶処理では、インジウムリン１６に強度が小さいレーザ光Ｌｓを照射してインジウムリン１６の徐冷を開始する際、ランプヒータ２５による単結晶シリコン基板１０の加熱を継続してもよい。これにより、インジウムリン１６を再結晶させる際に単結晶シリコン基板１０の温度が急変することがなく、単結晶シリコン基板１０の反りや割れの発生を防止することができる。 In recrystallization of Figure 6 described above, strength indium phosphide 16 is irradiated with a small laser beam L s at the start of slow cooling indium phosphide 16, continued heating of the single crystal silicon substrate 10 by lamp heater 25 May be. Thereby, when the indium phosphide 16 is recrystallized, the temperature of the single crystal silicon substrate 10 does not change suddenly, and warpage and cracking of the single crystal silicon substrate 10 can be prevented.
　また、上述した図６の再結晶処理では、ランプヒータ２５からの単結晶シリコン基板１０への加熱量を低減させた後、インジウムリン１６に強度が小さいレーザ光Ｌｓを照射してインジウムリン１６の徐冷を開始してもよい。これにより、インジウムリン１６への下方からの加熱量を低減させてインジウムリン１６の温度を（００１）結晶面１５の近傍から確実に低下させることができる。 Further, in the recrystallization process of FIG. 6 described above, after the amount of heating from the lamp heater 25 to the single crystal silicon substrate 10 is reduced, the indium phosphide 16 is irradiated with laser light L s having a low intensity, and the indium phosphide 16 is irradiated. Slow cooling may be started. Thereby, the amount of heating from below to the indium phosphide 16 can be reduced, and the temperature of the indium phosphide 16 can be reliably lowered from the vicinity of the (001) crystal plane 15.
　さらに、上述した図６の再結晶処理では、インジウムリン１６に強度が小さいレーザ光Ｌｓを照射してインジウムリン１６の徐冷を開始した後に、ランプヒータ２５からの単結晶シリコン基板１０への加熱量を低減させてもよい。 Further, in the recrystallization process of FIG. 6 described above, the indium phosphide 16 is irradiated with laser light L s having a low intensity to start slow cooling of the indium phosphide 16, and then the lamp heater 25 applies the single crystal silicon substrate 10 to the single crystal silicon substrate 10. The amount of heating may be reduced.
　また、レーザスキャナ２４は走査方向に沿って配列された２つのレーザ光照射部２４ａ、２４ｂを有するが、レーザスキャナ２４を走査方向に沿って配列された３つ以上のレーザ光照射部で構成してもよく、または、レーザスキャナ２４を１つのレーザ光照射部によって構成してもよい。これらの場合も走査方向に関して前方から後方にかけて照射されるレーザ光の強度を低下させる。 The laser scanner 24 includes two laser light irradiation units 24a and 24b arranged along the scanning direction. The laser scanner 24 includes three or more laser light irradiation units arranged along the scanning direction. Alternatively, the laser scanner 24 may be configured by one laser light irradiation unit. In these cases also, the intensity of the laser beam irradiated from the front to the rear in the scanning direction is reduced.
　なお、上述した図６の再結晶処理では、ランプヒータ２５はサセプタ２３を介して単結晶シリコン基板１０の全体を加熱し、インジウムリン１６を選択的に加熱することがないため、ランプ光の波長に関しては特に制約がない。また、上述した図６の再結晶処理では、応答性を考慮した場合、ランプヒータ２５を用いるのが好ましいが、ランプヒータ２５の代わりに抵抗加熱ヒータを用いてもよい。 In the recrystallization process of FIG. 6 described above, the lamp heater 25 heats the entire single crystal silicon substrate 10 via the susceptor 23 and does not selectively heat the indium phosphorus 16. There are no particular restrictions on. In the recrystallization process of FIG. 6 described above, it is preferable to use the lamp heater 25 in consideration of responsiveness, but a resistance heater may be used instead of the lamp heater 25.
　上述した本実施の形態に係る微細構造形成方法によって形成されたフィン型のチャネル２０は、図９に示すように、下層バリアとしてのヒ化インジウムアルミニウム（ＩｎＡｌＡｓ）層２７、チャネル層としてのヒ化インジウムガリウム（ＩｎＧａＡｓ）層２８及び上層バリアとしてのインジウムリン層２９によって覆われてヒ化インジウムガリウム／ヒ化インジウムアルミニウム量子井戸チャネルを構成する。 As shown in FIG. 9, the fin-type channel 20 formed by the microstructure forming method according to the present embodiment described above includes an indium aluminum arsenide (InAlAs) layer 27 as a lower layer barrier and arsenic as a channel layer. Covered by an indium gallium (InGaAs) layer 28 and an indium phosphide layer 29 as an upper barrier constitutes an indium gallium arsenide / indium aluminum arsenide quantum well channel.
　なお、本実施の形態に係る微細構造形成方法は、図９に示すヒ化インジウムガリウム／ヒ化インジウムアルミニウム量子井戸チャネルの形成だけでなく、他の微細構造の形成にも適用される。 Note that the microstructure formation method according to the present embodiment is applied not only to the formation of the indium gallium arsenide / indium aluminum arsenide quantum well channel shown in FIG. 9, but also to the formation of other microstructures.
　図１０は、本実施の形態に係る微細構造形成方法が適用される、ヒ化インジウムガリウム／ヒ化インジウムアルミニウム量子井戸チャネルを有するプレーナー型のチャネルの構成を概略的に示す断面図である。 FIG. 10 is a cross-sectional view schematically showing the structure of a planar channel having an indium gallium arsenide / indium aluminum arsenide quantum well channel to which the microstructure forming method according to the present embodiment is applied.
　図１０において、本実施の形態に係る微細構造形成方法によって形成されたフィン形状の結晶化インジウムリン１８は、下層バリアとしてのヒ化インジウムアルミニウム層２７、チャネル層としてのヒ化インジウムガリウム層２８及び上層バリアとしてのインジウムリン層２９によって覆われ、結晶化インジウムリン１８の側面はＳｉＯ２膜１２によって覆われる。 In FIG. 10, the fin-shaped crystallized indium phosphide 18 formed by the microstructure forming method according to the present embodiment includes an indium aluminum arsenide layer 27 as a lower barrier, an indium gallium arsenide layer 28 as a channel layer, and The indium phosphide layer 29 as an upper barrier is covered, and the side surface of the crystallized indium phosphide 18 is covered with the SiO 2 film 12.
　図１１は、本実施の形態に係る微細構造形成方法が適用される、積層構造のヒ化インジウムガリウム／ヒ化インジウムアルミニウム量子井戸チャネルの構成を概略的に示す断面図である。 FIG. 11 is a cross-sectional view schematically showing a configuration of a laminated indium gallium arsenide / indium aluminum arsenide quantum well channel to which the microstructure forming method according to the present embodiment is applied.
　図１１において、本実施の形態に係る微細構造形成方法によって形成されたフィン形状の結晶化インジウムリン１８の上面は、下層バリアとしてのヒ化インジウムアルミニウム層２７、チャネル層としてのヒ化インジウムガリウム層２８及び上層バリアとしてのインジウムリン層２９によって覆われ、結晶化インジウムリン１８及びヒ化インジウムアルミニウム層２７の側面はＳｉＯ２膜１２によって覆われる。 In FIG. 11, the top surface of the fin-shaped crystallized indium phosphide 18 formed by the microstructure forming method according to the present embodiment is an indium aluminum arsenide layer 27 as a lower layer barrier and an indium gallium arsenide layer as a channel layer. 28 and an indium phosphide layer 29 as an upper barrier, and the side surfaces of the crystallized indium phosphide 18 and the indium arsenide aluminum layer 27 are covered with the SiO 2 film 12.
　次に、本発明の第２の実施の形態に係る微細構造形成方法について説明する。 Next, a microstructure forming method according to the second embodiment of the present invention will be described.
　本実施の形態は、その構成や作用が上述した第１の実施の形態と基本的に同じであり、用いられる熱処理装置の構成が上述した第１の実施の形態と異なる。したがって、重複した構成、作用については説明を省略し、以下に異なる構成、作用についての説明を行う。 This embodiment is basically the same in configuration and operation as the above-described first embodiment, and the configuration of the heat treatment apparatus used is different from that in the above-described first embodiment. Therefore, the description of the duplicated configuration and operation is omitted, and the description of the different configuration and operation is given below.
　図１２は、本実施の形態に係る微細構造形成方法で用いられる熱処理装置の構成を概略的に示す断面図である。 FIG. 12 is a cross-sectional view schematically showing a configuration of a heat treatment apparatus used in the fine structure forming method according to the present embodiment.
　図１２において、熱処理装置３０は、熱処理装置２１が備えるレーザスキャナ２４の代わりに、チャンバ２２の外の上方においてサセプタ２３に載置された単結晶シリコン基板１０を指向するように配置された複数のＬＥＤランプ３１（上方熱源）を備える。 In FIG. 12, the heat treatment apparatus 30 includes a plurality of heat exchangers arranged to face the single crystal silicon substrate 10 placed on the susceptor 23 above the outside of the chamber 22 instead of the laser scanner 24 included in the heat treatment apparatus 21. An LED lamp 31 (upper heat source) is provided.
　ＬＥＤランプ３１及びサセプタ２３の間に介在するチャンバ２２の天井部には透過窓３２が嵌め込まれ、ＬＥＤランプ３１は透過窓３２を透過するＬＥＤランプ光Ｒによってサセプタ２３に載置された単結晶シリコン基板１０の全体を上方から加熱する。本実施の形態でも、インジウムリン１６のみを選択的に加熱するために、ＬＥＤランプ３１が照射するＬＥＤランプ光Ｒの波長の範囲は８００ｎｍ~９５０ｎｍに設定される。 A transmissive window 32 is fitted into the ceiling portion of the chamber 22 interposed between the LED lamp 31 and the susceptor 23, and the LED lamp 31 is monocrystalline silicon placed on the susceptor 23 by the LED lamp light R that passes through the transmissive window 32. The entire substrate 10 is heated from above. Also in this embodiment, in order to selectively heat only the indium phosphide 16, the range of the wavelength of the LED lamp light R irradiated by the LED lamp 31 is set to 800 nm to 950 nm.
　本実施の形態に係る微細構造形成方法では、熱処理装置３０が図６のインジウムリンの再結晶化処理を実行する。具体的には、まず、ランプヒータ２５がサセプタ２３に載置された単結晶シリコン基板１０の全体の加熱を開始し、単結晶シリコン基板１０の全体をインジウムリンの融点より低い温度、例えば、８００℃まで加熱する（ステップＳ６１）。 In the fine structure forming method according to the present embodiment, the heat treatment apparatus 30 executes the recrystallization process of indium phosphide in FIG. Specifically, first, the lamp heater 25 starts heating the entire single crystal silicon substrate 10 placed on the susceptor 23, and the entire single crystal silicon substrate 10 is heated to a temperature lower than the melting point of indium phosphorus, for example, 800 Heat to ° C. (step S61).
　次いで、ＬＥＤランプ３１が単結晶シリコン基板１０の表面に向けてＬＥＤランプ光Ｒを照射してインジウムリン１６の加熱を開始する（ステップＳ６２）。このとき、ＬＥＤランプ３１は、図１２に示すように、単結晶シリコン基板１０のＬＥＤランプ光Ｒによって単結晶シリコン基板１０の全体を上方から照射し、インジウムリン１６に入射したＬＥＤランプ光Ｒは減衰しながらも（００１）結晶面１５まで到達し、図８Ａのインジウムリン１６の深さ方向に関する温度勾配のグラフに示すように、インジウムリン１６の全ての温度がインジウムリンの融点を超える。これにより、トレンチ１４に充填されたインジウムリン１６の全てが溶融する。 Next, the LED lamp 31 irradiates the LED lamp light R toward the surface of the single crystal silicon substrate 10 to start heating the indium phosphide 16 (step S62). At this time, the LED lamp 31 irradiates the entire single crystal silicon substrate 10 from above with the LED lamp light R of the single crystal silicon substrate 10 as shown in FIG. Although it is attenuated, it reaches the (001) crystal plane 15 and all the temperatures of the indium phosphide 16 exceed the melting point of the indium phosphide as shown in the graph of the temperature gradient in the depth direction of the indium phosphide 16 in FIG. 8A. Thereby, all of the indium phosphide 16 filled in the trench 14 is melted.
　次いで、ＬＥＤランプ３１は照射するＬＥＤランプ光Ｒの出力を漸減する。このとき、ＬＥＤランプ光Ｒは（００１）結晶面１５まで到達しないので、図８Ｂのインジウムリン１６の深さ方向に関する温度勾配のグラフに示すように、インジウムリン１６の温度は（００１）結晶面１５の近傍において低下して温度勾配は図８Ａの温度勾配よりも低温側に移行する。すなわち、ＬＥＤランプ３１によるインジウムリン１６の徐冷が開始される（ステップＳ６３）。 Next, the LED lamp 31 gradually reduces the output of the LED lamp light R to be irradiated. At this time, since the LED lamp light R does not reach the (001) crystal plane 15, the temperature of the indium phosphorus 16 is the (001) crystal plane as shown in the graph of the temperature gradient in the depth direction of the indium phosphorus 16 in FIG. 8B. The temperature gradient decreases in the vicinity of 15, and the temperature gradient shifts to a lower temperature side than the temperature gradient in FIG. 8A. That is, the slow cooling of the indium phosphide 16 by the LED lamp 31 is started (step S63).
　次いで、ＬＥＤランプ３１はＬＥＤランプ光Ｒの照射を停止する。このとき、インジウムリン１６の温度はインジウムリン１６の全体において低下し、やがて図８Ｃのインジウムリン１６の深さ方向に関する温度勾配のグラフに示すように、インジウムリン１６の全ての温度がインジウムリンの融点を下回る。これにより、インジウムリン１６は凝固して全体的に再結晶化する。その後、本処理を終了する。 Next, the LED lamp 31 stops the irradiation of the LED lamp light R. At this time, the temperature of the indium phosphide 16 is lowered throughout the indium phosphide 16, and eventually, as shown in the graph of the temperature gradient in the depth direction of the indium phosphide 16 in FIG. Below the melting point. Thereby, the indium phosphide 16 is solidified and recrystallized as a whole. Thereafter, this process is terminated.
　すなわち、本実施の形態では、ＬＥＤランプ３１がＬＥＤランプ光Ｒの出力を漸減することにより、インジウムリン１６への上方からの加熱量を漸減させてインジウムリン１６の深さ方向に関する温度勾配を低温側に移行させ、溶融したインジウムリン１６を（００１）結晶面１５側から徐冷するので、第１の実施の形態が奏する効果と同様の効果を奏することができる。 That is, in the present embodiment, the LED lamp 31 gradually reduces the output of the LED lamp light R, thereby gradually reducing the amount of heating from above to the indium phosphorus 16 and reducing the temperature gradient in the depth direction of the indium phosphorus 16 to a low temperature. Since the molten indium phosphide 16 is gradually cooled from the (001) crystal plane 15 side, the same effects as the effects of the first embodiment can be obtained.
　また、本実施の形態では、第１の実施の形態と異なり、各トレンチ１４に充填された全てのインジウムリン１６がＬＥＤランプ光Ｒによって同時に加熱されて溶融されるので、フィン型のチャネル２０の形成のスループットを向上することができる。 Further, in the present embodiment, unlike the first embodiment, all the indium phosphines 16 filled in the trenches 14 are simultaneously heated and melted by the LED lamp light R, so that the fin-type channel 20 The formation throughput can be improved.
　さらに、本実施の形態では、各ＬＥＤランプ３１が同時にＬＥＤランプ光Ｒの出力を漸減するが、各ＬＥＤランプ３１が異なるタイミングでＬＥＤランプ光Ｒの出力を漸減してもよい。 Furthermore, in this embodiment, each LED lamp 31 gradually decreases the output of the LED lamp light R at the same time, but each LED lamp 31 may gradually decrease the output of the LED lamp light R at different timings.
　また、本実施の形態では、上方熱源としてレーザスキャナ２４の代わりにＬＥＤランプ３１が用いられるが、ＬＥＤランプ３１は安価であるため、熱処理装置３０の製造コストを低減することができる。 In this embodiment, the LED lamp 31 is used as the upper heat source instead of the laser scanner 24. However, since the LED lamp 31 is inexpensive, the manufacturing cost of the heat treatment apparatus 30 can be reduced.
　なお、第１の実施の形態と同様に、本実施の形態では、ＬＥＤランプ光Ｒの出力を漸減してインジウムリン１６の徐冷を開始する際、ランプヒータ２５による単結晶シリコン基板１０の加熱を継続してもよく、ランプヒータ２５からの単結晶シリコン基板１０への加熱量を低減させた後、ＬＥＤランプ光Ｒの出力を漸減してインジウムリン１６の徐冷を開始してもよく、若しくは、ＬＥＤランプ光Ｒの出力を漸減してインジウムリン１６の徐冷を開始した後に、ランプヒータ２５からの単結晶シリコン基板１０への加熱量を低減させてもよい。 As in the first embodiment, in the present embodiment, when the indium phosphide 16 is gradually cooled by gradually decreasing the output of the LED lamp light R, the single crystal silicon substrate 10 is heated by the lamp heater 25. Or after the amount of heating from the lamp heater 25 to the single crystal silicon substrate 10 is reduced, the output of the LED lamp light R may be gradually decreased to start slow cooling of the indium phosphide 16. Alternatively, the heating amount of the single crystal silicon substrate 10 from the lamp heater 25 may be reduced after gradually decreasing the output of the LED lamp light R and starting the slow cooling of the indium phosphide 16.
　次に、本発明の第３の実施の形態に係る微細構造形成方法について説明する。 Next, a microstructure forming method according to the third embodiment of the present invention will be described.
　本実施の形態は、その構成や作用が上述した第１の実施の形態と基本的に同じであり、レーザスキャナ２４が照射するレーザ光によって加熱される対象がインジウムリン１６ではなくＳｉ３Ｎ４膜１１、１３やＳｉＯ２膜１２、１７である点で上述した第１の実施の形態と異なる。したがって、重複した構成、作用については説明を省略し、以下に異なる構成、作用についての説明を行う。 This embodiment is basically the same in configuration and operation as the first embodiment described above, and the object to be heated by the laser light emitted by the laser scanner 24 is not indium phosphide 16 but Si 3 N 4. It is different from the first embodiment described above in that the films 11 and 13 and the SiO 2 films 12 and 17 are used. Therefore, the description of the duplicated configuration and operation is omitted, and the description of the different configuration and operation is given below.
　単結晶シリコン基板１０において、インジウムリン１６は、例えば、図２Ｂに示すように、Ｓｉ３Ｎ４膜１１、１３やＳｉＯ２膜１２、１７（以下、これらをまとめて「被覆層」という。）によって囲まれる。したがって、被覆層を加熱することにより、インジウムリン１６を間接的に加熱することができるため、本実施の形態では、レーザスキャナ２４が照射するレーザ光の波長は被覆層へ吸収されやすい波長に設定される。 In the single crystal silicon substrate 10, the indium phosphide 16 is, for example, as shown in FIG. 2B, Si 3 N 4 films 11 and 13 and SiO 2 films 12 and 17 (hereinafter collectively referred to as “coating layer”). Surrounded by. Accordingly, since the indium phosphide 16 can be indirectly heated by heating the coating layer, in this embodiment, the wavelength of the laser light emitted by the laser scanner 24 is set to a wavelength that is easily absorbed by the coating layer. Is done.
　レーザ光の波長が７６００ｎｍ~１０６００ｎｍである範囲では、インジウムリンやゲルマニウムの吸光係数がほぼ０である一方、図１３や図１４に示すように、窒化珪素（Ｓｉ３Ｎ４）や酸化珪素（ＳｉＯ２）の吸光係数が大きくなる（なお、図１３では、波数（波長の逆数）に対する吸光量が示されるが、波長が７６００ｎｍ~１０６００ｎｍである範囲が図中矢印で示される。）。すなわち、レーザ光の波長の範囲を７６００ｎｍ~１０６００ｎｍに設定して当該レーザ光をインジウムリン、ゲルマニウム、酸化珪素や窒化珪素に照射すると、レーザ光のエネルギーが酸化珪素や窒化珪素に吸収されて酸化珪素や窒化珪素が加熱されて温度が上昇する一方、インジウムリンやゲルマニウムはレーザ光をほぼ透過させてしまうため、インジウムリンやゲルマニウムはレーザ光によって加熱されない。 In the range where the wavelength of the laser light is 7600 nm to 10600 nm, the absorption coefficient of indium phosphide or germanium is almost 0, while as shown in FIGS. 13 and 14, silicon nitride (Si 3 N 4 ) or silicon oxide (SiO 2 ). (2 ) is increased (in FIG. 13, the amount of light absorbed relative to the wave number (reciprocal of the wavelength) is shown, but the range of the wavelength from 7600 nm to 10600 nm is indicated by an arrow in the figure). That is, when the laser light wavelength range is set to 7600 nm to 10600 nm and the laser light is irradiated to indium phosphide, germanium, silicon oxide or silicon nitride, the energy of the laser light is absorbed by silicon oxide or silicon nitride, and silicon oxide While silicon nitride is heated and the temperature rises, indium phosphide and germanium almost transmit laser light, so indium phosphide and germanium are not heated by the laser light.
　したがって、本実施の形態では、レーザスキャナ２４が照射するレーザ光の波長の範囲が７６００ｎｍ~１０６００ｎｍに設定される。ここで、ＣＯ２レーザ光は波長が凡そ、９３００ｎｍ~１０６００ｎｍであるため、レーザスキャナ２４はレーザ光ＬとしてＣＯ２レーザ光を照射する。 Therefore, in the present embodiment, the wavelength range of the laser light emitted by the laser scanner 24 is set to 7600 nm to 10600 nm. Here, since the wavelength of the CO 2 laser light is approximately 9300 nm to 10600 nm, the laser scanner 24 irradiates the CO 2 laser light as the laser light L.
　本実施の形態では、レーザスキャナ２４が単結晶シリコン基板１０の表面へ向けて照射したレーザ光Ｌは、図１５に示すように、被覆層を通過する際にこれらの膜に吸収されて減衰する一方、インジウムリン１６を通過する際にほとんど吸収されることなくインジウムリン１６を通過し、単結晶シリコン基板１０においても徐々に吸収されて漸減する。これにより、レーザ光Ｌの照射によって被覆層を選択的に加熱し、温度が上昇した被覆層によってインジウムリン１６を間接的に加熱する。 In the present embodiment, the laser light L irradiated to the surface of the single crystal silicon substrate 10 by the laser scanner 24 is absorbed and attenuated by these films when passing through the coating layer as shown in FIG. On the other hand, when passing through the indium phosphide 16, it passes through the indium phosphide 16 with little absorption, and the single crystal silicon substrate 10 gradually absorbs and gradually decreases. Thereby, the coating layer is selectively heated by irradiation with the laser beam L, and the indium phosphide 16 is indirectly heated by the coating layer whose temperature has increased.
　本実施の形態では、図６のインジウムリンの再結晶化処理において、まず、ランプヒータ２５がサセプタ２３に載置された単結晶シリコン基板１０の全体の加熱を開始し、単結晶シリコン基板１０の全体をインジウムリンの融点より低い温度、例えば、８００℃まで加熱する（ステップＳ６１）。 In the present embodiment, in the recrystallization process of indium phosphide in FIG. 6, first, the lamp heater 25 starts heating the entire single crystal silicon substrate 10 placed on the susceptor 23, and the single crystal silicon substrate 10 The whole is heated to a temperature lower than the melting point of indium phosphide, for example, 800 ° C. (step S61).
　次いで、レーザスキャナ２４が単結晶シリコン基板１０の表面に向けてレーザ光Ｌを照射して被覆層の加熱を開始する（ステップＳ６２）。このとき、レーザスキャナ２４は、単結晶シリコン基板１０をレーザ光Ｌで走査する。 Next, the laser scanner 24 irradiates the surface of the single crystal silicon substrate 10 with the laser light L and starts heating the coating layer (step S62). At this time, the laser scanner 24 scans the single crystal silicon substrate 10 with the laser light L.
　本実施の形態においても、レーザスキャナ２４は走査方向に沿って配列された２つのレーザ光照射部２４ａ、２４ｂを有し、走査方向に関して前方に配置されたレーザ光照射部２４ａが照射するレーザ光Ｌｌの強度は、走査方向に関して後方に配置されたレーザ光照射部２４ｂが照射するレーザ光Ｌｓの強度よりも大きく設定される。これにより、レーザスキャナ２４が移動する際、単結晶シリコン基板１０の各箇所における被覆層には、まず、強度が大きいレーザ光Ｌｌが照射され、次いで、強度が小さいレーザ光Ｌｓが照射され、その後、いずれのレーザ光Ｌｌ、Ｌｓも照射されなくなる。 Also in the present embodiment, the laser scanner 24 has two laser light irradiation units 24a and 24b arranged along the scanning direction, and the laser light irradiated by the laser light irradiation unit 24a arranged forward in the scanning direction. The intensity of L 1 is set to be larger than the intensity of the laser light L s irradiated by the laser light irradiation unit 24b disposed rearward in the scanning direction. Thereby, when the laser scanner 24 moves, the coating layer in each part of the single crystal silicon substrate 10 is first irradiated with the laser beam L 1 having a high intensity, and then irradiated with the laser beam L s having a low intensity. Thereafter, neither of the laser beams L 1 and L s is irradiated.
　被覆層に強度が大きいレーザ光Ｌｌが照射されると、被覆層が十分に加熱され、さらに、温度が上昇した被覆層によってインジウムリン１６が間接的に加熱されるため、図８Ａのインジウムリン１６の深さ方向に関する温度勾配のグラフに示すように、インジウムリン１６の全ての温度がインジウムリンの融点を超える。これにより、トレンチ１４に充填されたインジウムリン１６の全てが溶融する。 When the coating layer is irradiated with the laser beam L 1 having a high intensity, the coating layer is sufficiently heated, and the indium phosphide 16 is indirectly heated by the coating layer whose temperature has been increased. As shown in the graph of the temperature gradient for the 16 depth directions, all temperatures of indium phosphide 16 exceed the melting point of indium phosphide. Thereby, all of the indium phosphide 16 filled in the trench 14 is melted.
　次いで、レーザスキャナ２４が移動して被覆層に強度が小さいレーザ光Ｌｓが照射されるようになると、被覆層に入射したレーザ光Ｌｓは減衰して被覆層の半ばで消滅する。このとき、レーザ光ＬｓはＳｉ３Ｎ４膜１１まで到達しないので、被覆層の（００１）結晶面１５の近傍における温度が低下し、図８Ｂのインジウムリン１６の深さ方向に関する温度勾配のグラフに示すように、インジウムリン１６の温度は（００１）結晶面１５の近傍において低下して温度勾配は図８Ａの温度勾配よりも低温側に移行する。すなわち、レーザスキャナ２４によるインジウムリン１６の徐冷が開始される（ステップＳ６３）。 Then, the laser intensity in the coating layer by the laser scanner 24 is moved a small light L s is to be irradiated, the laser beam L s incident on the coating layer disappears in the middle of the attenuation to the coating layer. At this time, since the laser beam L s does not reach the Si 3 N 4 film 11, the temperature in the vicinity of the (001) crystal plane 15 of the coating layer decreases, and the temperature gradient in the depth direction of the indium phosphide 16 in FIG. As shown in the graph, the temperature of indium phosphide 16 decreases in the vicinity of the (001) crystal plane 15, and the temperature gradient shifts to a lower temperature side than the temperature gradient in FIG. 8A. That is, slow cooling of the indium phosphide 16 by the laser scanner 24 is started (step S63).
　次いで、さらにレーザスキャナ２４が移動して被覆層にいずれのレーザ光Ｌｌ、Ｌｓも照射されなくなると、被覆層の温度は被覆層の全体において低下し、やがて図８Ｃのインジウムリン１６の深さ方向に関する温度勾配のグラフに示すように、インジウムリン１６の全ての温度がインジウムリンの融点を下回る。これにより、インジウムリン１６は凝固して全体的に再結晶化する。その後、本処理を終了する。 Next, when the laser scanner 24 further moves and the coating layer is not irradiated with any of the laser beams L 1 and L s , the temperature of the coating layer decreases over the entire coating layer, and eventually the depth of the indium phosphide 16 in FIG. As shown in the temperature gradient graph for the vertical direction, all temperatures of indium phosphide 16 are below the melting point of indium phosphide. Thereby, the indium phosphide 16 is solidified and recrystallized as a whole. Thereafter, this process is terminated.
　すなわち、本実施の形態では、被覆層にレーザスキャナ２４のレーザ光照射部２４ａ、２４ｂがレーザ光Ｌｌ、Ｌｓを順に照射することにより、被覆層への上方からの加熱量を漸減させてインジウムリン１６の深さ方向に関する温度勾配を低温側に移行させ、溶融したインジウムリン１６を（００１）結晶面１５側から徐冷するので、第１の実施の形態が奏する効果と同様の効果を奏することができる。また、本実施の形態では、インジウムリン１６を囲む被覆層を加熱することにより、インジウムリン１６を間接的に加熱するので、インジウムリン１６の全体を満遍なく加熱することができ、一部のインジウムリン１６が溶融せずにグレインとして残り、若しくは、一部のインジウムリン１６が先に冷却されてグレインが生じるのを防止することができる。 That is, in this embodiment, the laser beam irradiation units 24a and 24b of the laser scanner 24 sequentially irradiate the laser beams L l and L s to the coating layer, thereby gradually decreasing the amount of heating from the upper side of the coating layer. Since the temperature gradient in the depth direction of the indium phosphide 16 is shifted to the low temperature side and the molten indium phosphide 16 is gradually cooled from the (001) crystal face 15 side, the same effect as that of the first embodiment can be obtained. Can play. In the present embodiment, since the indium phosphide 16 is indirectly heated by heating the coating layer surrounding the indium phosphide 16, the entire indium phosphide 16 can be uniformly heated, and a part of the indium phosphide 16 is heated. It is possible to prevent the grains 16 from remaining as grains without being melted, or a part of the indium phosphorus 16 from being cooled first to produce grains.
　以上、本発明について、上記各実施の形態を用いて説明したが、本発明は上記各実施の形態に限定されるものではない。 As mentioned above, although this invention was demonstrated using said each embodiment, this invention is not limited to said each embodiment.
　例えば、上記各実施の形態では、トレンチ１４の底部において（００１）結晶面１５が露出したが、露出する結晶面のミラー指数はこれに限られず、例えば、（０１０）、（０１１）、（１００）、（１０１）、（１１０）又は（１１１）であってもよい。 For example, in each of the above embodiments, the (001) crystal plane 15 is exposed at the bottom of the trench 14, but the Miller index of the exposed crystal plane is not limited to this, for example, (010), (011), (100 ), (101), (110) or (111).
　また、上記各実施の形態により得られたフィン型のチャネル２０は、三次元構造のＭＯＳＦＥＴ、いわゆるＦｉｎＦＥＴに好適に用いることができるが、ナノロッドのＦＥＴに用いることができ、さらに、ＦＥＴ以外にも、ＬＥＤ、半導体レーザ、光検出器、太陽電池等のフォトニックデバイスに用いてもよい。 The fin-type channel 20 obtained by each of the above embodiments can be suitably used for a MOSFET having a three-dimensional structure, a so-called FinFET, but can be used for a nanorod FET. , LED, semiconductor laser, photodetector, solar cell and other photonic devices.
　さらに、上記各実施の形態では、トレンチ１４を用いてインジウムリンのフィン型のチャネル２０が形成されたが、図１６に示すように、Ｓｉ３Ｎ４膜３３やＳｉＯ２膜３４に設けられたホール３５にインジウムリン１６を充填し、該インジウムリン１６へ図６の再結晶化処理を施すことにより、量子ドットやナノロッドを形成してもよい。 Further, in each of the above-described embodiments, the fin-type channel 20 of indium phosphide is formed using the trench 14. However, as shown in FIG. 16, the channel is provided in the Si 3 N 4 film 33 or the SiO 2 film 34. Quantum dots or nanorods may be formed by filling the holes 35 with indium phosphide 16 and subjecting the indium phosphide 16 to the recrystallization process of FIG.
　また、トレンチ１４へ充填される異種半導体はインジウムリンに限られず、例えば、アルミニウムリン、アルミニウムヒ素、アルミニウムアンチモン、ガリウムリン、ガリウムヒ素、ガリウムアンチモン、インジウムヒ素、インジウムアンチモン、インジウムリン、ヒ化インジウムガリウム及びゲルマニウムの少なくとも１つであってもよい。 Further, the dissimilar semiconductor filled in the trench 14 is not limited to indium phosphide. And at least one of germanium.
　さらに、各トレンチ１４へ同種の異種半導体が充填される必要はなく、例えば、図１７に示すように、一のトレンチ１４へインジウムリン１６が充填され、他のトレンチ１４へゲルマニウム３６が充填されてもよい。図４に示すように、レーザ光の波長が８００ｎｍ~９５０ｎｍである範囲においてゲルマニウムの吸光係数はインジウムリンの吸光係数を上回るため、各トレンチ１４へ充填されたインジウムリン１６及びゲルマニウム３６へ、波長の範囲が８００ｎｍ~９５０ｎｍに設定されたレーザ光Ｌｌ、Ｌｓを用いて図６の再結晶化処理を施すことにより、インジウムリン１６だけでなくゲルマニウム３６の選択的な溶融、徐冷及び再結晶化を行うことができる。特に、図６の再結晶化処理では、再結晶化の際に、インジウムリン１６の深さ方向に関する温度勾配だけでなくゲルマニウム３６の深さ方向に関する温度勾配が制御されるので、再結晶化したインジウムリンとゲルマニウムにおいてグレインが生じるのを防止することができる。これにより、高品質なインジウムリンとゲルマニウムのチャネル２０を基板へ同時に形成することができる。このように形成されたインジウムリンとゲルマニウムのチャネル２０は、ＣＭＯＳに用いることができる。 Further, it is not necessary to fill each trench 14 with the same kind of different semiconductor. For example, as shown in FIG. 17, one trench 14 is filled with indium phosphorus 16 and the other trench 14 is filled with germanium 36. Also good. As shown in FIG. 4, since the absorption coefficient of germanium exceeds the absorption coefficient of indium phosphide in the range where the wavelength of the laser beam is 800 nm to 950 nm, the wavelength of the indium phosphide 16 and germanium 36 filled in each trench 14 is increased. By performing the recrystallization process of FIG. 6 using the laser beams L 1 and L s set in the range of 800 nm to 950 nm, selective melting, slow cooling and recrystallization of germanium 36 as well as indium phosphorus 16 is performed. Can be made. In particular, in the recrystallization process of FIG. 6, not only the temperature gradient in the depth direction of indium phosphide 16 but also the temperature gradient in the depth direction of germanium 36 is controlled during the recrystallization. Generation of grains in indium phosphide and germanium can be prevented. Thus, high-quality indium phosphide and germanium channels 20 can be simultaneously formed on the substrate. The indium phosphide and germanium channel 20 formed in this way can be used in a CMOS.
　また、上述した各実施の形態における図６の再結晶化処理では、ランプヒータ２５によって単結晶シリコン基板１０の全体を加熱したが、ランプヒータ２５による加熱を行うことなく、レーザスキャナ２４やＬＥＤランプ３１のみによって単結晶シリコン基板１０を加熱してもよく、また、ランプヒータ２５による加熱とレーザスキャナ２４やＬＥＤランプ３１による加熱を同時に開始してもよい。 In the recrystallization process of FIG. 6 in each of the above-described embodiments, the entire single crystal silicon substrate 10 is heated by the lamp heater 25. However, the laser scanner 24 and the LED lamp are not heated by the lamp heater 25. The single crystal silicon substrate 10 may be heated only by 31 or the heating by the lamp heater 25 and the heating by the laser scanner 24 or the LED lamp 31 may be started simultaneously.
　さらに、上述した各実施の形態では、被覆層を形成する窒化珪素としてＳｉ３Ｎ４を用い、酸化珪素としてＳｉＯ２を用いる場合について説明したが、被覆層を形成する窒化珪素や酸化珪素はＳｉ３Ｎ４やＳｉＯ２に限られず、ＳｉｘＮｙやＳｉＯｘ（ｘ、ｙは任意の自然数）であればよい。また、被覆層を形成する窒化珪素や酸化珪素及び異種半導体は、不純物を含んでいてもよい。なお、上述した各実施の形態で形成された異種半導体は、格子定数を調整するための下地膜として用いてもよい。 Further, in each of the above-described embodiments, the case where Si 3 N 4 is used as silicon nitride for forming the cover layer and SiO 2 is used as silicon oxide has been described. However, silicon nitride or silicon oxide for forming the cover layer is Si It is not limited to 3 N 4 or SiO 2 but may be Si x N y or SiO x (x and y are arbitrary natural numbers). In addition, silicon nitride, silicon oxide, and a different kind of semiconductor that form the coating layer may contain impurities. Note that the heterogeneous semiconductor formed in each of the above embodiments may be used as a base film for adjusting the lattice constant.
　また、本発明の目的は、上述した各実施の形態の機能を実現するソフトウェアのプログラムコードを記録した記憶媒体を、熱処理装置２１等が備えるコンピュータ（図示しない）に供給し、コンピュータのＣＰＵが記憶媒体に格納されたプログラムコードを読み出して実行することによっても達成される。 In addition, an object of the present invention is to supply a storage medium storing software program codes for realizing the functions of the above-described embodiments to a computer (not shown) provided in the heat treatment apparatus 21 and the like, and the CPU of the computer stores the storage medium. It is also achieved by reading and executing the program code stored on the medium.
　この場合、記憶媒体から読み出されたプログラムコード自体が上述した各実施の形態の機能を実現することになり、プログラムコード及びそのプログラムコードを記憶した記憶媒体は本発明を構成することになる。 In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code and the storage medium storing the program code constitute the present invention.
　また、プログラムコードを供給するための記憶媒体としては、例えば、ＲＡＭ、ＮＶ−ＲＡＭ、フロッピー（登録商標）ディスク、ハードディスク、光磁気ディスク、ＣＤ−ＲＯＭ、ＣＤ−Ｒ、ＣＤ−ＲＷ、ＤＶＤ（ＤＶＤ−ＲＯＭ、ＤＶＤ−ＲＡＭ、ＤＶＤ−ＲＷ、ＤＶＤ＋ＲＷ）等の光ディスク、磁気テープ、不揮発性のメモリカード、他のＲＯＭ等の上記プログラムコードを記憶できるものであればよい。或いは、上記プログラムコードは、インターネット、商用ネットワーク、若しくはローカルエリアネットワーク等に接続される不図示の他のコンピュータやデータベース等からダウンロードすることによりコンピュータに供給されてもよい。 Examples of the storage medium for supplying the program code include RAM, NV-RAM, floppy (registered trademark) disk, hard disk, magneto-optical disk, CD-ROM, CD-R, CD-RW, DVD (DVD). -ROM, DVD-RAM, DVD-RW, DVD + RW) and other optical disks, magnetic tapes, non-volatile memory cards, other ROMs, etc., as long as they can store the program code. Alternatively, the program code may be supplied to the computer by downloading from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.
　また、コンピュータが読み出したプログラムコードを実行することにより、上記各実施の形態の機能が実現されるだけでなく、そのプログラムコードの指示に基づき、ＣＰＵ上で稼動しているＯＳ（オペレーティングシステム）等が実際の処理の一部又は全部を行い、その処理によって上述した各実施の形態の機能が実現される場合も含まれる。 Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) running on the CPU based on the instruction of the program code. Includes a case where part or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.
　更に、記憶媒体から読み出されたプログラムコードが、コンピュータに挿入された機能拡張ボードやコンピュータに接続された機能拡張ユニットに備わるメモリに書き込まれた後、そのプログラムコードの指示に基づき、その機能拡張ボードや機能拡張ユニットに備わるＣＰＵ等が実際の処理の一部又は全部を行い、その処理によって上述した各実施の形態の機能が実現される場合も含まれる。 Further, after the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. This includes a case where the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.
　上記プログラムコードの形態は、オブジェクトコード、インタプリタにより実行されるプログラムコード、ＯＳに供給されるスクリプトデータ等の形態から成ってもよい。 The form of the program code may be in the form of object code, program code executed by an interpreter, script data supplied to the OS, and the like.
　本出願は、２０１３年６月１０日に出願された日本出願第２０１３−１２１８２１号に基づく優先権を主張するものであり、当該日本出願に記載された全内容を本出願に援用する。 This application claims priority based on Japanese Patent Application No. 2013-121821 filed on June 10, 2013, the entire contents of which are incorporated in this application.
Ｌ、Ｌｌ、Ｌｓ　レーザ光
Ｒ　ＬＥＤランプ光
１０　単結晶シリコン基板
１１、１３、３３　Ｓｉ３Ｎ４膜
１２、１７、３４　ＳｉＯ２膜
１４　トレンチ
１６　インジウムリン
２０　チャネル
２４　レーザスキャナ
２４ａ、２４ｂ　レーザ光照射部
３１　ＬＥＤランプ
３５　ホール
３６　ゲルマニウム L, L l , L s Laser light R LED lamp light 10 Single crystal silicon substrate 11, 13, 33 Si 3 N 4 film 12, 17, 34 SiO 2 film 14 Trench 16 Indium phosphide 20 Channel 24 Laser scanner 24a, 24b Laser Light irradiation unit 31 LED lamp 35 hole 36 germanium

Claims (21)

  1. 　シリコン基板の上面に形成された被覆層に凹部を形成し、該凹部の底において前記シリコン基板のシリコンの結晶面を露出させる凹部形成ステップと、
    　前記凹部に異種半導体を充填する充填ステップと、
    　前記充填された異種半導体を加熱して溶融させる加熱ステップと、
    　前記溶融した異種半導体を冷却して前記シリコンの結晶面を種として前記異種半導体を再結晶させる冷却ステップと、
    　前記被覆層を除去する除去ステップとを有し、
    　前記加熱ステップでは、少なくとも前記シリコン基板の上面側に配置された上方熱源によって前記充填された異種半導体を加熱し、
    　前記冷却ステップでは、前記上方熱源からの加熱量を低減させることによって前記溶融した異種半導体を冷却することを特徴とする微細構造形成方法。     Forming a recess in the coating layer formed on the upper surface of the silicon substrate, and exposing the silicon crystal surface of the silicon substrate at the bottom of the recess; and
    A filling step of filling the recess with a different semiconductor;
    A heating step of heating and melting the filled heterogeneous semiconductor;
    Cooling the molten dissimilar semiconductor to recrystallize the dissimilar semiconductor using the silicon crystal plane as a seed; and
    A removal step of removing the coating layer,
    In the heating step, the filled dissimilar semiconductor is heated by at least an upper heat source disposed on the upper surface side of the silicon substrate,
    In the cooling step, the melted heterogeneous semiconductor is cooled by reducing the amount of heating from the upper heat source.
  2. 　前記加熱ステップでは、前記シリコン基板の下面側に配置された下方熱源によって前記シリコン基板を加熱することを特徴とする請求項１記載の微細構造形成方法。 The method for forming a microstructure according to claim 1, wherein, in the heating step, the silicon substrate is heated by a lower heat source disposed on a lower surface side of the silicon substrate.
  3. 　前記加熱ステップでは、前記下方熱源が前記シリコン基板を前記異種半導体の融点より低い温度まで加熱した後、前記上方熱源が前記充填された異種半導体を当該異種半導体の融点以上の温度へ加熱することを特徴とする請求項２記載の微細構造形成方法。 In the heating step, the lower heat source heats the silicon substrate to a temperature lower than the melting point of the dissimilar semiconductor, and then the upper heat source heats the filled dissimilar semiconductor to a temperature equal to or higher than the melting point of the dissimilar semiconductor. The fine structure forming method according to claim 2, wherein:
  4. 　前記冷却ステップでは、前記下方熱源による前記シリコン基板の加熱を継続したまま、前記上方熱源からの加熱量のみを低減させることを特徴とする請求項２又は３記載の微細構造形成方法。 4. The method of forming a microstructure according to claim 2, wherein, in the cooling step, only the amount of heating from the upper heat source is reduced while the heating of the silicon substrate by the lower heat source is continued.
  5. 　前記冷却ステップでは、前記下方熱源からの加熱量を低減させた後、前記上方熱源からの加熱量を低減させることを特徴とする請求項２又は３記載の微細構造形成方法。 4. The microstructure forming method according to claim 2, wherein, in the cooling step, after the amount of heating from the lower heat source is reduced, the amount of heating from the upper heat source is reduced.
  6. 　前記冷却ステップでは、前記上方熱源からの加熱量を低減させた後、前記下方熱源からの加熱量を低減させることを特徴とする請求項２又は３記載の微細構造形成方法。 The method for forming a microstructure according to claim 2 or 3, wherein, in the cooling step, after the amount of heating from the upper heat source is reduced, the amount of heating from the lower heat source is reduced.
  7. 　前記上方熱源はレーザ光照射装置であり、
    　前記加熱ステップでは、前記レーザ光照射装置はレーザ光で前記凹部を走査することを特徴とする請求項１乃至６のいずれか１項に記載の微細構造形成方法。     The upper heat source is a laser beam irradiation device,
    7. The microstructure forming method according to claim 1, wherein in the heating step, the laser beam irradiation device scans the concave portion with a laser beam.
  8. 　前記レーザ光照射装置は、前記レーザ光の走査方向に沿って配置された少なくとも２つのレーザ光照射部を有し、
    　前記走査方向に関して前方に配置された一の前記レーザ光照射部が照射する前記レーザ光の強度は、前記走査方向に関して後方に配置された他の前記レーザ光照射部が照射する前記レーザ光の強度よりも大きいことを特徴とする請求項７記載の微細構造形成方法。     The laser beam irradiation apparatus has at least two laser beam irradiation units arranged along the scanning direction of the laser beam,
    The intensity of the laser beam irradiated by one laser beam irradiation unit arranged in front of the scanning direction is the intensity of the laser beam irradiated by another laser beam irradiation unit arranged rearward in the scanning direction. The fine structure forming method according to claim 7, wherein the fine structure forming method is larger.
  9. 　前記異種半導体はインジウムリンであり、前記他のレーザ光照射部が照射するレーザ光の波長は８００ｎｍ~９５０ｎｍであることを特徴とする請求項８記載の微細構造形成方法。 9. The method for forming a microstructure according to claim 8, wherein the heterogeneous semiconductor is indium phosphide, and the wavelength of the laser beam irradiated by the other laser beam irradiation unit is 800 nm to 950 nm.
  10. 　前記上方熱源はＬＥＤランプであることを特徴とする請求項１乃至６のいずれか１項に記載の微細構造形成方法。 The method for forming a microstructure according to any one of claims 1 to 6, wherein the upper heat source is an LED lamp.
  11. 　前記異種半導体はインジウムリンであり、前記ＬＥＤランプが照射するランプ光の波長は８００ｎｍ~９５０ｎｍであることを特徴とする請求項１０記載の微細構造形成方法。 11. The method for forming a microstructure according to claim 10, wherein the dissimilar semiconductor is indium phosphide, and the wavelength of the lamp light irradiated by the LED lamp is 800 nm to 950 nm.
  12. 　前記加熱ステップでは、前記上方熱源によって前記被覆層を加熱して前記充填された異種半導体を間接的に加熱することを特徴とする請求項１記載の微細構造形成方法。 The fine structure forming method according to claim 1, wherein, in the heating step, the covering layer is heated by the upper heat source to indirectly heat the filled dissimilar semiconductor.
  13. 　前記被覆層は少なくとも酸化珪素を含み、前記上方熱源は波長が７６００ｎｍ~１０６００ｎｍの光を前記被覆層に照射することを特徴とする請求項１２記載の微細構造形成方法。 13. The microstructure forming method according to claim 12, wherein the coating layer contains at least silicon oxide, and the upper heat source irradiates the coating layer with light having a wavelength of 7600 nm to 10600 nm.
  14. 　前記異種半導体は、アルミニウムリン、アルミニウムヒ素、アルミニウムアンチモン、ガリウムリン、ガリウムヒ素、ガリウムアンチモン、インジウムヒ素、インジウムアンチモン、インジウムリン、ヒ化インジウムガリウム及びゲルマニウムの少なくとも１つを含むことを特徴とする請求項１乃至１３のいずれか１項に記載の微細構造形成方法。 The dissimilar semiconductor includes at least one of aluminum phosphorus, aluminum arsenic, aluminum antimony, gallium phosphorus, gallium arsenide, gallium antimony, indium arsenic, indium antimony, indium phosphide, indium gallium arsenide, and germanium. Item 14. The method for forming a microstructure according to any one of Items 1 to 13.
  15. 　前記凹部はトレンチであることを特徴とする請求項１乃至１４のいずれか１項に記載の微細構造形成方法。 The method for forming a microstructure according to any one of claims 1 to 14, wherein the recess is a trench.
  16. 　前記凹部はホールであることを特徴とする請求項１乃至１４のいずれか１項に記載の微細構造形成方法。 The method for forming a microstructure according to any one of claims 1 to 14, wherein the concave portion is a hole.
  17. 　前記充填ステップと前記加熱ステップの間に、前記充填された異種半導体の上部にさらなる被覆層を形成する被覆ステップをさらに備えることを特徴とする請求項１乃至１６のいずれか１項に記載の微細構造形成方法。 17. The fine structure according to claim 1, further comprising a coating step of forming a further coating layer on the filled heterogeneous semiconductor between the filling step and the heating step. Structure formation method.
  18. 　異種半導体をシリコン基板上に備える半導体デバイスの製造方法であって、
    　前記シリコン基板の上面に形成された凹部に充填された前記異種半導体を加熱して溶融させる加熱ステップと、
    　前記溶融した異種半導体を冷却して再結晶させる冷却ステップとを有し、
    　前記加熱ステップでは、少なくとも前記シリコン基板の上面側に配置された上方熱源によって前記充填された異種半導体を加熱し、
    　前記冷却ステップでは、前記上方熱源からの加熱量を低減させることによって前記溶融した異種半導体を冷却することを特徴とする半導体デバイスの製造方法。     A method of manufacturing a semiconductor device comprising a heterogeneous semiconductor on a silicon substrate,
    A heating step of heating and melting the dissimilar semiconductor filled in the recess formed on the upper surface of the silicon substrate;
    A cooling step of cooling and recrystallizing the melted dissimilar semiconductor,
    In the heating step, the filled dissimilar semiconductor is heated by at least an upper heat source disposed on the upper surface side of the silicon substrate,
    In the cooling step, the molten dissimilar semiconductor is cooled by reducing the amount of heating from the upper heat source.
  19. 　前記シリコン基板上には前記異種半導体からなる２つのチャネルが形成され、一の前記チャネルは前記異種半導体としてインジウムリンを含み、他の前記チャネルは前記異種半導体としてゲルマニウムを含むことを特徴とする請求項１８記載の半導体デバイスの製造方法。 Two channels made of the dissimilar semiconductor are formed on the silicon substrate, one of the channels includes indium phosphide as the dissimilar semiconductor, and the other channel includes germanium as the dissimilar semiconductor. Item 19. A method for manufacturing a semiconductor device according to Item 18.
  20. 　前記加熱ステップにおいて、前記異種半導体の上部は被覆されていることを特徴とする請求項１８又は１９記載の半導体デバイスの製造方法。 20. The method of manufacturing a semiconductor device according to claim 18 or 19, wherein, in the heating step, an upper portion of the dissimilar semiconductor is covered.
  21. 　シリコン基板上に形成されたインジウムリンとゲルマニウムをそれぞれ含む２つのチャネルを有するＣＭＯＳの形成方法であって、
    　前記インジウムリンと前記ゲルマニウムを同時に加熱し、さらに同時に冷却することによって再結晶させることを特徴とするＣＭＯＳの形成方法。     A method of forming a CMOS having two channels each containing indium phosphide and germanium formed on a silicon substrate,
    A method for forming a CMOS, wherein the indium phosphide and the germanium are recrystallized by simultaneously heating and simultaneously cooling.
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