WO2014196175A1 - Circuit board and led module - Google Patents
Circuit board and led module Download PDFInfo
- Publication number
- WO2014196175A1 WO2014196175A1 PCT/JP2014/002861 JP2014002861W WO2014196175A1 WO 2014196175 A1 WO2014196175 A1 WO 2014196175A1 JP 2014002861 W JP2014002861 W JP 2014002861W WO 2014196175 A1 WO2014196175 A1 WO 2014196175A1
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- WIPO (PCT)
- Prior art keywords
- electrode
- base
- wiring board
- solder material
- groove portion
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the first substrate electrode 12 and the second substrate electrode 22 correspond to the pad member in the present invention.
- the 1st groove part 14 and the 2nd groove part 24 are corresponded to the groove part in this invention.
- the solder materials 16 and 26 correspond to the bonding material in the present invention.
- the 1st base material electrode 12 and the 2nd base material electrode 22 should just be provided at least 1 each on the base material 1, and may be provided with two or more. Thereby, even if it is the LED chip 2 which has a p-type semiconductor layer and an n-type semiconductor layer, the stable joining state is implement
- 1st groove part 14 is formed with the 1st substrate electrode 12 which is a mounting electrode. Thereby, the 1st groove part 14 can be formed only by an electrode formation process.
- the shape of the bonding material forming portion and the shape of the solder material 46 before bonding the wiring substrate 40 and the LED chip 2 are similar to the first base electrode 42 on the first base electrode 42. Is formed. That is, as shown in FIG. 4, the bonding material forming portion and the solder material 46 have the same shape as the first base electrode 42 and a small area, and are located a predetermined distance from the periphery of the first base electrode 42. It is formed in an intrusive shape.
- the LED element mounting structure for mounting the LED element on the wiring board is illustrated.
- the present invention is not limited to the LED element and is used for a mounting structure for mounting other light emitting elements on the wiring board. Also good.
- other light emitting elements other solid light emitting elements such as a semiconductor light emitting element such as a semiconductor laser, an EL element such as an organic EL (Electro Luminescence) or an inorganic EL may be used.
Abstract
A circuit board (1) having an LED chip (2) mounted by fusion bonding, wherein the circuit board (1) is provided with: a first substrate electrode (12) and a second substrate electrode (22) formed on a substrate (10), the first and second substrate electrodes (21, 22) being electroconductive pads for joining the LED chip (2); solder (16, 26) disposed on the first and second substrate electrodes (21, 22); and a first channel (14) and a second channel (24) into which molten solder is poured when the LED chip (2) is joined to the first and second substrate electrodes (21, 22), the first and second channels (14, 24) being formed on the substrate (10).
Description
本発明は、配線基板及びＬＥＤモジュールに関し、特に、発光素子を実装する配線基板及びＬＥＤモジュールに関する。
The present invention relates to a wiring board and an LED module, and more particularly to a wiring board and an LED module on which a light emitting element is mounted.
従来、配線基板やサブマウント基板上にＬＥＤチップ等の発光素子を搭載する技術が開示されている。
Conventionally, a technique for mounting a light emitting element such as an LED chip on a wiring board or a submount board has been disclosed.
発光素子は、温度が高くなるほど発光効率が低下するため、発光素子の発光効率を向上するためには、発光素子での温度上昇を抑制する必要がある。
Since the luminous efficiency of the light emitting element decreases as the temperature increases, it is necessary to suppress the temperature rise in the light emitting element in order to improve the luminous efficiency of the light emitting element.
発光素子で発生した熱は、大部分が実装基板への伝熱により放熱される。したがって、発光素子を高熱伝導な材料に大面積で実装することにより、発熱量が大きくても発光素子の温度上昇を抑制することができる。
Most of the heat generated in the light emitting element is dissipated by heat transfer to the mounting board. Therefore, by mounting the light-emitting element on a high thermal conductivity material in a large area, the temperature rise of the light-emitting element can be suppressed even if the heat generation amount is large.
高熱伝導な材料によって発光素子を配線基板に大面積で実装する技術としては、例えばＡｕＳｎなどの金属材料を用いた溶融接合により発光素子を配線基板に実装する技術が開示されている（例えば、特許文献１、２参照）。
As a technology for mounting a light emitting element on a wiring board with a large thermal conductivity material, a technique for mounting the light emitting element on the wiring board by fusion bonding using a metal material such as AuSn is disclosed (for example, a patent). References 1 and 2).
特許文献１に記載の発光装置では、基板上に溝を形成することにより、ＬＥＤ素子を基板に接合するための溶融金属がＬＥＤ素子の外部へはみ出すことを抑制している。この発光装置では、ＬＥＤ素子の外部への溶融金属のはみ出しに対しては対応できるが、ＬＥＤ素子の同一面に設けられた異なる電極（例えば、ｐ型電極とｎ型電極）の間での短絡を防止することは困難である。
In the light emitting device described in Patent Document 1, by forming a groove on the substrate, the molten metal for joining the LED element to the substrate is prevented from protruding to the outside of the LED element. This light-emitting device can cope with the protrusion of molten metal to the outside of the LED element, but a short circuit between different electrodes (for example, a p-type electrode and an n-type electrode) provided on the same surface of the LED element. It is difficult to prevent.
また、特許文献２に記載の技術では、ＬＥＤチップを搭載する被搭載部が接合材料であるはんだ材をはじく材料により形成されている。したがって、ＬＥＤチップと基板との接合状態が安定せず、１つのＬＥＤチップの同一面に存在する異なる電極間の短絡を防止することは困難である。
Further, in the technique described in Patent Document 2, the mounted portion on which the LED chip is mounted is formed of a material that repels a solder material that is a bonding material. Therefore, the bonding state between the LED chip and the substrate is not stable, and it is difficult to prevent a short circuit between different electrodes existing on the same surface of one LED chip.
したがって、上記した技術では、フリップチップ型発光素子の接合においてチップの同一面に存在する電極が短絡する可能性があり、接合状態が安定せず動作が不安定になるという問題がある。
Therefore, in the above-described technique, there is a possibility that the electrodes existing on the same surface of the chip may be short-circuited when the flip-chip type light emitting element is bonded, and the bonding state is not stable and the operation becomes unstable.
上記課題に鑑み、本発明は、安定した接合状態を実現することができる配線基板及びＬＥＤモジュールを提供することを目的とする。
In view of the above problems, an object of the present invention is to provide a wiring board and an LED module capable of realizing a stable bonded state.
上記目的を達成するために、本発明に係る配線基板の一態様は、溶融接合によりＬＥＤ素子が実装される配線基板であって、基材上に形成され、前記ＬＥＤ素子を接合する、導電性を有するパッド部と、前記パッド部の上に配置された接合材料と、前記基材上に形成され、前記ＬＥＤ素子を前記パッド部に接合する時に、溶融した前記接合材料が流れ込む溝部とを備える。
In order to achieve the above object, one aspect of a wiring board according to the present invention is a wiring board on which an LED element is mounted by melt bonding, and is formed on a base material and joins the LED element. A pad portion, a bonding material disposed on the pad portion, and a groove portion formed on the base material into which the molten bonding material flows when the LED element is bonded to the pad portion. .
また、本発明に係るＬＥＤモジュールの一態様において、上記した特徴を有する配線基板と、前記配線基板に実装された前記ＬＥＤ素子とを備えるとしてもよい。
Moreover, in one aspect of the LED module according to the present invention, a wiring board having the above-described characteristics and the LED element mounted on the wiring board may be provided.
本発明によれば、安定した接合状態を実現することができる配線基板及びＬＥＤモジュールを提供することができる。
According to the present invention, it is possible to provide a wiring board and an LED module that can realize a stable bonded state.
以下、実施の形態について、図面を参照しながら説明する。なお、以下に説明する実施の形態は、いずれも本発明の好ましい一具体例を示すものである。したがって、以下の実施の形態で示される数値、形状、材料、構成要素、構成要素の配置位置及び接続形態、工程、工程の順序などは、一例であって本発明を限定する主旨ではない。よって、以下の実施の形態における構成要素のうち、本発明の最上位概念を示す独立請求項に記載されていない構成要素については、任意の構成要素として説明される。
Hereinafter, embodiments will be described with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present invention. Therefore, the numerical values, shapes, materials, constituent elements, arrangement positions and connecting forms of constituent elements, processes, order of processes, and the like shown in the following embodiments are merely examples and do not limit the present invention. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements.
なお、各図は、模式図であり、必ずしも厳密に図示されたものではない。また、各図において、実質的に同一の構成に対しては同一の符号を付しており、重複する説明は省略又は簡略化する。
Each figure is a schematic diagram and is not necessarily shown strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.
（実施の形態１）
まず、実施の形態１に係る配線基板及びＬＥＤモジュールについて、図１および図２を用いて説明する。図１は、実施の形態１に係る配線基板の構成を示す概略図であり、（ａ）は配線基板の上面図、（ｂ）は（ａ）のＡＡ’線における配線基板の断面図である。図２は、実施の形態１に係るＬＥＤモジュールを示す断面図であり、（ａ）はＬＥＤ素子の実装前の断面図、（ｂ）はＬＥＤ素子の実装後の断面図である。 (Embodiment 1)
First, the wiring board and LED module according toEmbodiment 1 will be described with reference to FIGS. 1 and 2. 1A and 1B are schematic views showing the configuration of the wiring board according to the first embodiment, where FIG. 1A is a top view of the wiring board, and FIG. . 2A and 2B are cross-sectional views showing the LED module according to Embodiment 1, wherein FIG. 2A is a cross-sectional view before mounting the LED element, and FIG. 2B is a cross-sectional view after mounting the LED element.
まず、実施の形態１に係る配線基板及びＬＥＤモジュールについて、図１および図２を用いて説明する。図１は、実施の形態１に係る配線基板の構成を示す概略図であり、（ａ）は配線基板の上面図、（ｂ）は（ａ）のＡＡ’線における配線基板の断面図である。図２は、実施の形態１に係るＬＥＤモジュールを示す断面図であり、（ａ）はＬＥＤ素子の実装前の断面図、（ｂ）はＬＥＤ素子の実装後の断面図である。 (Embodiment 1)
First, the wiring board and LED module according to
図１の（ａ）及び（ｂ）に示すように、本実施の形態に係る配線基板１は、基材１０と、第１の基材電極１２と、第１の溝部１４と、はんだ材１６と、第２の基材電極２２と、第２の溝部２４と、はんだ材２６とで構成されている。第１の基材電極１２と、第１の溝部１４と、はんだ材１６とにより、ｐ型電極が構成され、第２の基材電極２２と、第２の溝部２４と、はんだ材２６とにより、ｎ型電極が構成されている。
As shown in FIGS. 1A and 1B, the wiring board 1 according to the present embodiment includes a base material 10, a first base material electrode 12, a first groove portion 14, and a solder material 16. And a second base electrode 22, a second groove 24, and a solder material 26. The first base electrode 12, the first groove portion 14, and the solder material 16 constitute a p-type electrode, and the second base electrode 22, the second groove portion 24, and the solder material 26 The n-type electrode is configured.
ここで、第１の基材電極１２及び第２の基材電極２２は、本発明におけるパッド部材に相当する。第１の溝部１４及び第２の溝部２４は、本発明における溝部に相当する。はんだ材１６及び２６は、本発明における接合材料に相当する。また、第１の基材電極１２及び第２の基材電極２２は、基材１の上に少なくとも１つずつ設けられていればよく、複数設けられていてもよい。これにより、ｐ型半導体層とｎ型半導体層を有するＬＥＤチップ２であっても、安定した接合状態を実現してＬＥＤチップ２の短絡を抑制することができる。
Here, the first substrate electrode 12 and the second substrate electrode 22 correspond to the pad member in the present invention. The 1st groove part 14 and the 2nd groove part 24 are corresponded to the groove part in this invention. The solder materials 16 and 26 correspond to the bonding material in the present invention. Moreover, the 1st base material electrode 12 and the 2nd base material electrode 22 should just be provided at least 1 each on the base material 1, and may be provided with two or more. Thereby, even if it is the LED chip 2 which has a p-type semiconductor layer and an n-type semiconductor layer, the stable joining state is implement | achieved and the short circuit of the LED chip 2 can be suppressed.
基材１０は、例えば、シリコン基板により構成されている。なお、基材１０の材料は、シリコンに限られず、窒化アルミニウム、または、炭化ケイ素等であってもよい。また、単一の材料で構成された基板に限らず、複数の材料層で構成された基板やインターポーザ等であってもよい。
The base material 10 is composed of, for example, a silicon substrate. The material of the base material 10 is not limited to silicon, but may be aluminum nitride, silicon carbide, or the like. Further, the substrate is not limited to a single material, and may be a substrate or an interposer formed of a plurality of material layers.
基材１０上には、絶縁膜（図示せず）が設けられている。絶縁膜としては、例えば二酸化シリコン膜（ＳｉＯ２膜）等を用いることができる。絶縁膜は、基材１０上の全面に形成されている。例えば、Ｓｉ基材の場合は、熱酸化等で形成される。絶縁膜は、第１の基材電極１２が形成される領域と第２の基材電極２２が形成される領域とに分離して形成されている。
An insulating film (not shown) is provided on the base material 10. As the insulating film, for example, a silicon dioxide film (SiO 2 film) or the like can be used. The insulating film is formed on the entire surface of the base material 10. For example, in the case of a Si base material, it is formed by thermal oxidation or the like. The insulating film is formed separately into a region where the first base electrode 12 is formed and a region where the second base electrode 22 is formed.
絶縁膜の上には、第１の基材電極１２及び第２の基材電極２２が形成されている。
A first base electrode 12 and a second base electrode 22 are formed on the insulating film.
第１の基材電極１２は、配線基板１に対向して配置されるＬＥＤチップ２のｐ型半導体層に接続されるｐ型電極である。第１の基材電極１２は、例えば、銅箔上にニッケルと金を積層して構成されている。
The first base electrode 12 is a p-type electrode connected to the p-type semiconductor layer of the LED chip 2 disposed to face the wiring board 1. The first base electrode 12 is configured, for example, by laminating nickel and gold on a copper foil.
第２の基材電極２２は、ＬＥＤチップ２のｎ型半導体層に接続されるｎ型電極である。第２の基材電極２２は、例えば、銅箔上にニッケルと金を積層して構成されている。
The second base electrode 22 is an n-type electrode connected to the n-type semiconductor layer of the LED chip 2. The second substrate electrode 22 is configured by, for example, laminating nickel and gold on a copper foil.
なお、図２の（ａ）に示すように、第１の基材電極１２は、絶縁膜の上面のうち、少なくともＬＥＤチップ２においてｐ型半導体層に接続されるｐ型電極である第１の電極３４と対向して形成されている。
2A, the first base electrode 12 is a first p-type electrode that is connected to the p-type semiconductor layer in at least the LED chip 2 on the upper surface of the insulating film. It is formed to face the electrode 34.
また、第２の基材電極２２は、絶縁膜の上面のうち、少なくともＬＥＤチップ２においてｎ型半導体層に接続されるｎ型電極である第２の電極３６と対向して形成されている。
The second base electrode 22 is formed on the upper surface of the insulating film so as to face at least the second electrode 36 which is an n-type electrode connected to the n-type semiconductor layer in the LED chip 2.
第１の溝部１４は、実装電極である第１の基材電極１２で形成されている。これにより、第１の溝部１４は、電極形成プロセスのみで形成することができる。
1st groove part 14 is formed with the 1st substrate electrode 12 which is a mounting electrode. Thereby, the 1st groove part 14 can be formed only by an electrode formation process.
詳細には、図１の（ｂ）に示すように、第１の基材電極１２は、基材１０上の絶縁膜の上に実装された第１の実装電極１２ａと、第１の実装電極１２ａの上に所定のパターンに形成された第２の実装電極１２ｂとの段差で構成される。すなわち、第１の溝部１４の底面は第１の実装電極１２ａで構成され、第１の溝部１４の側面は第２の実装電極１２ｂで構成される。配線基板１の上の第１の基材電極１２の上には、接合材料であるはんだ材１６が形成されており、第１の溝部１４は、接合時に溶融したはんだ材１６を溜めおくことができる。これにより、ＬＥＤチップ２を配線基板１に接合する溶融接合において、ＬＥＤチップ２を短絡させることなく接合することができる。なお、第１の基材電極１２を形成するために必要な領域の大きさは、例えば８００μｍ×８００μｍであり、このときの第１の溝部１４の幅は、例えば２０μｍである。
Specifically, as shown in FIG. 1B, the first substrate electrode 12 includes a first mounting electrode 12a mounted on an insulating film on the substrate 10, and a first mounting electrode. It is comprised by the level | step difference with the 2nd mounting electrode 12b formed in the predetermined pattern on 12a. That is, the bottom surface of the first groove portion 14 is composed of the first mounting electrode 12a, and the side surface of the first groove portion 14 is composed of the second mounting electrode 12b. A solder material 16 that is a bonding material is formed on the first base electrode 12 on the wiring board 1, and the first groove portion 14 can store the molten solder material 16 at the time of bonding. it can. Thereby, in the melt | fusion joining which joins the LED chip 2 to the wiring board 1, it can join, without short-circuiting the LED chip 2. FIG. Note that the size of the region necessary for forming the first base electrode 12 is, for example, 800 μm × 800 μm, and the width of the first groove 14 at this time is, for example, 20 μm.
第２の溝部２４は、実装電極である第２の基材電極２２で形成されている。これにより、第２の溝部２４は、電極形成プロセスのみで形成することができる。
The second groove 24 is formed by the second base electrode 22 that is a mounting electrode. Thereby, the 2nd groove part 24 can be formed only by an electrode formation process.
詳細には、図１の（ｂ）に示すように、第２の基材電極２２は、基材１０上の絶縁膜の上に実装された第１の実装電極２２ａと、第１の実装電極２２ａの上に形成された第２の実装電極２２ｂとで構成される。すなわち、第２の溝部２４の底面は第１の実装電極２２ａで構成され、第２の溝部２４の側面は第２の実装電極２２ｂで構成される。配線基板１の上の第２の基材電極２２の上には、接合材料であるはんだ材２６が形成されており、第２の溝部２４は、接合時に溶融したはんだ材２６を溜めおくことができる。これにより、ＬＥＤチップ２を配線基板１に接合する溶融接合において、ＬＥＤチップ２を短絡させることなく接合することができる。なお、上記したように、第１の基材電極１２を形成するために必要な領域の大きさが、例えば、８００μｍ×８００μｍであるとき、第２の溝部２４の幅は、例えば２０μｍである。
Specifically, as shown in FIG. 1B, the second base electrode 22 includes a first mounting electrode 22a mounted on an insulating film on the base 10 and a first mounting electrode. And a second mounting electrode 22b formed on 22a. That is, the bottom surface of the second groove portion 24 is composed of the first mounting electrode 22a, and the side surface of the second groove portion 24 is composed of the second mounting electrode 22b. A solder material 26, which is a bonding material, is formed on the second base electrode 22 on the wiring board 1, and the second groove 24 can store the molten solder material 26 at the time of bonding. it can. Thereby, in the melt | fusion joining which joins the LED chip 2 to the wiring board 1, it can join, without short-circuiting the LED chip 2. FIG. Note that, as described above, when the size of the region necessary for forming the first base electrode 12 is, for example, 800 μm × 800 μm, the width of the second groove portion 24 is, for example, 20 μm.
また、図１の（ａ）に示すように、第２の溝部２４は、第２の基材電極２２が形成される接合材料形成部の外周部に形成されている。接合材料形成部は、第２の基材電極２２において、溶融前のはんだ材２６が配置される部分をいう。これにより、接合時にはんだ材２６は第２の溝部２４に流れ込むため、はんだ材２６を第２の基材電極２２の全面に濡れ広げることができる。
Further, as shown in FIG. 1A, the second groove portion 24 is formed on the outer peripheral portion of the bonding material forming portion where the second base electrode 22 is formed. The bonding material forming portion refers to a portion in the second base electrode 22 where the solder material 26 before melting is disposed. Accordingly, the solder material 26 flows into the second groove portion 24 at the time of joining, so that the solder material 26 can be spread over the entire surface of the second substrate electrode 22.
ここで、本実施の形態に係るＬＥＤモジュールは、上記した配線基板１にＬＥＤチップ２を実装した構成である。これにより、ＬＥＤチップ２と配線基板１との安定した接合状態を実現できる。
Here, the LED module according to the present embodiment has a configuration in which the LED chip 2 is mounted on the wiring board 1 described above. Thereby, the stable joining state of LED chip 2 and wiring board 1 is realizable.
ＬＥＤチップ２は、直流電力が通電されることによって単色の可視光を発するベアチップであり、青色光を発する青色ＬＥＤチップ、赤色光を発する赤色ＬＥＤチップ又は緑色光を発する緑色ＬＥＤチップの可視域波長帯の光を発するＬＥＤチップ等である。なお、ＬＥＤチップ２には、これらの可視光によるものだけではなく、例えば、紫外線発光のＬＥＤチップを用いることもできる。
The LED chip 2 is a bare chip that emits monochromatic visible light when DC power is applied, and is a visible wavelength of a blue LED chip that emits blue light, a red LED chip that emits red light, or a green LED chip that emits green light. LED chips that emit band light. The LED chip 2 is not limited to those using visible light, but may be, for example, an ultraviolet light emitting LED chip.
ＬＥＤチップ２は、絶縁基板３０と、半導体層３２と、第１の電極３４と、第２の電極３６とを備えている。
The LED chip 2 includes an insulating substrate 30, a semiconductor layer 32, a first electrode 34, and a second electrode 36.
絶縁基板３０は、例えば、サファイア（Ａｌ２Ｏ３）等の絶縁物で構成されている。
The insulating substrate 30 is made of an insulator such as sapphire (Al 2 O 3 ), for example.
絶縁基板３０の上には、半導体層３２が形成されている。半導体層３２は、例えば、ＧａＮ等の窒化物半導体で構成され、ｐ型層、活性層及びｎ型層が順に積層されている。
A semiconductor layer 32 is formed on the insulating substrate 30. The semiconductor layer 32 is made of, for example, a nitride semiconductor such as GaN, and a p-type layer, an active layer, and an n-type layer are sequentially stacked.
また、半導体層３２の最上層であるｐ型層上には、第１の電極３４が形成されている。
Further, a first electrode 34 is formed on the p-type layer that is the uppermost layer of the semiconductor layer 32.
さらに、半導体層３２において、ｐ型層と活性層とがエッチングされることにより露出したｎ型層上には、第２の電極３６が形成されている。すなわち、第１の電極３４が形成されたＬＥＤチップ２の主面の一部に対し、第２の電極３６が形成されたＬＥＤチップ２の主面の他の一部は、窪んで形成されている。つまり、図２の（ａ）に示すように、ＬＥＤチップ２の半導体層３２は、段差を有する構成である。
Further, a second electrode 36 is formed on the n-type layer exposed by etching the p-type layer and the active layer in the semiconductor layer 32. That is, the other part of the main surface of the LED chip 2 on which the second electrode 36 is formed is formed to be recessed with respect to the part of the main surface of the LED chip 2 on which the first electrode 34 is formed. Yes. That is, as shown in FIG. 2A, the semiconductor layer 32 of the LED chip 2 has a step.
ＬＥＤチップ２は、図２の（ｂ）に示すように、半導体層３２が配置された側を配線基板１に対向させた状態で、配線基板１上に配置される。すなわち、第１の基材電極１２と第１の電極３４とが対向し、第２の基材電極２２と第２の電極３６とが対向するように配置される。
The LED chip 2 is arranged on the wiring board 1 with the side on which the semiconductor layer 32 is arranged facing the wiring board 1 as shown in FIG. That is, the first base electrode 12 and the first electrode 34 are opposed to each other, and the second base electrode 22 and the second electrode 36 are opposed to each other.
ＬＥＤチップ２を配線基板１の上に載置すると、ｐ型電極である第１の基材電極１２と第１の電極３４とがはんだ材１６を介して接続され、ｎ型電極である第２の基材電極２２と第２の電極３６とがはんだ材２６を介して接続される。第１の基材電極１２と第１の電極３４との接合、及び、第２の基材電極２２及び第２の電極３６との接合は、後に詳述するように、加熱溶融（溶融接合）により行われる。
When the LED chip 2 is placed on the wiring substrate 1, the first base electrode 12 that is a p-type electrode and the first electrode 34 are connected via the solder material 16, and the second base that is an n-type electrode. The base electrode 22 and the second electrode 36 are connected via the solder material 26. The joining of the first base electrode 12 and the first electrode 34 and the joining of the second base electrode 22 and the second electrode 36 are performed by heat melting (melt joining) as will be described in detail later. Is done.
はんだ材１６は、本発明における接合材料に相当し、第１の基材電極１２の上に形成されている。はんだ材１６は、図１の（ｂ）に示すように、ＬＥＤチップ２の第２の電極３６に接触しない範囲、すなわち、第１の基材電極１２から第２の基材電極２２へとはみ出さない範囲に形成されている。また、はんだ材１６が溶融時に第１の基材電極１２の上からはみ出したとしても、はみ出したはんだ材１６は第１の溝部１４に流れ込むので、はんだ材１６が第１の基材電極１２から第２の基材電極２２へと流れ出すことはない。これにより、はんだ材１６による、ｐ型電極である第１の電極３４とｎ型電極である第２の電極３６との間の短絡を防ぐことができる。
The solder material 16 corresponds to the bonding material in the present invention, and is formed on the first base electrode 12. As shown in FIG. 1 (b), the solder material 16 protrudes from the first base electrode 12 to the second base electrode 22 in a range where it does not contact the second electrode 36 of the LED chip 2. It is formed in a range that does not. Further, even if the solder material 16 protrudes from the first base electrode 12 at the time of melting, the solder material 16 that protrudes flows into the first groove portion 14, so that the solder material 16 comes from the first base electrode 12. There is no flow out to the second substrate electrode 22. Thereby, the short circuit between the 1st electrode 34 which is a p-type electrode, and the 2nd electrode 36 which is an n-type electrode by the solder material 16 can be prevented.
はんだ材１６は、配線基板１とＬＥＤチップ２の接合前においては、第１の基材電極１２上において、第１の基材電極１２と相似形に形成されている。すなわち、図１の（ａ）に示すように、はんだ材１６は、第１の基材電極１２と同一の形状で面積が小さく、第１の基材電極１２の周縁から所定の距離内側に入り込んだ形状に形成されている。はんだ材１６の形成形状を第１の基材電極１２の外形を縮小した相似形にすることにより、接合後に、第１の基材電極１２の外形に対し、はんだ材１６が第１の基材電極１２の全面に濡れ広がることが可能となる。
The solder material 16 is formed on the first base electrode 12 in a similar shape to the first base electrode 12 before the wiring substrate 1 and the LED chip 2 are joined. That is, as shown in FIG. 1A, the solder material 16 has the same shape as the first base electrode 12 and a small area, and enters the inner side of the predetermined distance from the periphery of the first base electrode 12. It is formed into a shape. By forming the solder material 16 into a similar shape in which the outer shape of the first base material electrode 12 is reduced, the solder material 16 becomes the first base material with respect to the outer shape of the first base material electrode 12 after joining. It becomes possible to spread over the entire surface of the electrode 12.
はんだ材２６は、本発明における接合材料に相当し、第２の基材電極２２の上に形成されている。はんだ材２６もはんだ材１６と同様、第２の基材電極２２から第１の基材電極１２へとはみ出さない範囲に形成されている。また、はんだ材２６が溶融時に第２の基材電極２２の上からはみ出したとしても、はみ出したはんだ材２６は第２の溝部２４に流れ込むので、はんだ材２６が第２の基材電極２２から第１の基材電極１２へと流れ出すことはない。これにより、はんだ材２６によるｐ型電極である第１の電極３４とｎ型電極である第２の電極３６との間の短絡を防ぐことができる。
The solder material 26 corresponds to the bonding material in the present invention, and is formed on the second substrate electrode 22. Similarly to the solder material 16, the solder material 26 is formed in a range that does not protrude from the second base material electrode 22 to the first base material electrode 12. Even if the solder material 26 protrudes from the second base material electrode 22 at the time of melting, the solder material 26 that protrudes flows into the second groove portion 24, so that the solder material 26 extends from the second base material electrode 22. There is no flow out to the first substrate electrode 12. Thereby, the short circuit between the 1st electrode 34 which is a p-type electrode by the solder material 26, and the 2nd electrode 36 which is an n-type electrode can be prevented.
はんだ材１６及び２６には、４００℃以下で溶融可能な材料が用いられる。これにより、はんだ材１６は、後に述べる実装工程において、加熱溶融により第１の基材電極１２上のほぼ全面に溶融する。溶融したはんだ材１６により、第１の基材電極１２とＬＥＤチップ２の第１の電極３４とは、はんだ材１６を介在してほぼ全面で溶融接合される。同様に、はんだ材２６は、加熱溶融により第２の基材電極２２上のほぼ全面に溶融する。溶融したはんだ材２６により、第２の基材電極２２とＬＥＤチップ２の第２の電極３６とは、はんだ材２６を介在してほぼ全面で溶融接合される。このとき、はんだ材１６及び２６の溶融後の高さは異なるため、後に詳述するように、ＬＥＤチップ２における、第１の電極３４が形成されたＬＥＤチップ２の主面の一部と第２の電極３６が形成されたＬＥＤチップの主面の他の一部との段差を吸収しつつ、第１の基材電極１２と第１の電極３４、及び、第２の基材電極２２と第２の電極３６とを接合することができる。
As the solder materials 16 and 26, materials that can be melted at 400 ° C. or lower are used. As a result, the solder material 16 is melted on almost the entire surface of the first base material electrode 12 by heating and melting in a mounting process described later. With the molten solder material 16, the first base electrode 12 and the first electrode 34 of the LED chip 2 are melt-bonded on almost the entire surface with the solder material 16 interposed therebetween. Similarly, the solder material 26 is melted on almost the entire surface of the second base material electrode 22 by heating and melting. Due to the molten solder material 26, the second base electrode 22 and the second electrode 36 of the LED chip 2 are melt-bonded on almost the entire surface with the solder material 26 interposed therebetween. At this time, since the heights after melting of the solder materials 16 and 26 are different, as described later in detail, a part of the main surface of the LED chip 2 on which the first electrode 34 is formed and The first base electrode 12, the first electrode 34, and the second base electrode 22, while absorbing a step with the other part of the main surface of the LED chip on which the second electrode 36 is formed, The second electrode 36 can be joined.
はんだ材１６及び２６には、例えば、Ａｕ－Ｓｎはんだが用いられる。Ａｕ－Ｓｎはんだ以外のはんだ材では、Ａｕ－Ａｇ－Ｃｕ、Ａｕ－Ｇｅ、ＳｎやＳｎ－Ａｇ系等の従来の電子部品に汎用されるはんだ材を使用してもよい。これにより、はんだ材１６及び２６の低コスト化を実現することができる。
For the solder materials 16 and 26, for example, Au—Sn solder is used. As the solder material other than the Au—Sn solder, a solder material generally used for conventional electronic parts such as Au—Ag—Cu, Au—Ge, Sn, Sn—Ag, etc. may be used. Thereby, the cost reduction of the solder materials 16 and 26 is realizable.
このように、はんだ材１６とはんだ材２６とにより配線基板１とＬＥＤチップ２とを接合することで、放熱性に大きく影響するｐ型電極（第１の基材電極１２と第１の電極３４）の接合については、はんだ材１６によってほぼ全面に溶融接合を行うことができる。これにより、放熱性を向上することができる。
Thus, the p-type electrode (the 1st base electrode 12 and the 1st electrode 34 which influences heat dissipation greatly by joining wiring board 1 and LED chip 2 with solder material 16 and solder material 26. ) Can be melt-bonded almost over the entire surface by the solder material 16. Thereby, heat dissipation can be improved.
また、第２の基材電極２２と第２の電極３６との間のギャップが第１の基材電極１２と第１の電極３４との間のギャップより大きいｎ型電極（第２の基材電極２２と第２の電極３６）の接合については、余分な量のはんだ材１６及び２６が第１の溝部１４及び第２の溝部２４に流れ込むので、ＬＥＤチップ２における、第１の電極３４が形成されたＬＥＤチップ２の主面の一部と第２の電極３６が形成されたＬＥＤチップの主面の他の一部との段差を吸収しつつ、第１の基材電極１２と第１の電極３４、及び、第２の基材電極２２と第２の電極３６とを接合することができる。
Further, an n-type electrode (second base material) in which the gap between the second base material electrode 22 and the second electrode 36 is larger than the gap between the first base material electrode 12 and the first electrode 34. Regarding the joining of the electrode 22 and the second electrode 36), since an excessive amount of solder material 16 and 26 flows into the first groove portion 14 and the second groove portion 24, the first electrode 34 in the LED chip 2 is While absorbing a step between a part of the main surface of the formed LED chip 2 and another part of the main surface of the LED chip on which the second electrode 36 is formed, the first base electrode 12 and the first base electrode 12 The electrode 34 and the second base electrode 22 and the second electrode 36 can be joined.
ここで、本実施の形態に係るＬＥＤモジュールにおける、配線基板１とＬＥＤチップ２との接合手順について説明する。
Here, the joining procedure of the wiring board 1 and the LED chip 2 in the LED module according to the present embodiment will be described.
はじめに、図２の（ａ）及び（ｂ）に示すように、第１の基材電極１２及び第２の基材電極２２上に接合材料であるはんだ材１６及び２６がそれぞれ形成される、接合材料形成工程が行われる。はんだ材１６及び２６は、第１の基材電極１２及び第２の基材電極２２それぞれの接合材料形成部に形成される。ここで、はんだ材１６及び２６は、これらの面積及び高さを所定の条件にする必要がある場合には、条件に合わせてはんだ材１６及び２６が形成される。
First, as shown in FIGS. 2A and 2B, solder materials 16 and 26, which are bonding materials, are formed on the first base electrode 12 and the second base electrode 22, respectively. A material formation process is performed. The solder materials 16 and 26 are formed in the bonding material forming portions of the first base material electrode 12 and the second base material electrode 22, respectively. Here, when it is necessary for the solder materials 16 and 26 to have these areas and heights in predetermined conditions, the solder materials 16 and 26 are formed according to the conditions.
なお、はんだ材１６及び２６は第１の基材電極１２及び第２の基材電極２２に限らず、第１の電極３４及び第２の電極３６に形成されてもよい。
The solder materials 16 and 26 are not limited to the first base electrode 12 and the second base electrode 22 but may be formed on the first electrode 34 and the second electrode 36.
次に、図２の（ａ）及び（ｂ）に示すように、配線基板１のはんだ材１６とＬＥＤチップ２の第１の電極３４とが対向し、配線基板１のはんだ材２６とＬＥＤチップ２の第２の電極３６とが対向するように、配線基板１の上にＬＥＤチップ２が配置される。
Next, as shown in FIGS. 2A and 2B, the solder material 16 of the wiring board 1 and the first electrode 34 of the LED chip 2 face each other, and the solder material 26 of the wiring board 1 and the LED chip. The LED chip 2 is disposed on the wiring board 1 so that the second electrode 36 of the second electrode faces the second electrode 36.
次に、配線基板１の上にＬＥＤチップ２が配置されたＬＥＤモジュールを加熱し、はんだ材１６及び２６を溶融する溶融工程が行われる。溶融工程では、第１の基材電極１２及び第２の基材電極２２上の全面にはんだ材１６及び２６が濡れ広がるように、はんだ材１６及び２６の融点以上の温度下ではんだ材１６及び２６を溶融させる。これにより、はんだ材１６及び２６は、加熱前の高さよりも低くなるように溶融される。
Next, a melting process is performed in which the LED module in which the LED chip 2 is disposed on the wiring board 1 is heated to melt the solder materials 16 and 26. In the melting step, the solder material 16 and the solder material 16 and 26 at a temperature equal to or higher than the melting point of the solder materials 16 and 26 so that the solder materials 16 and 26 spread over the entire surface of the first base material electrode 12 and the second base material electrode 22. 26 is melted. Thereby, the solder materials 16 and 26 are melted so as to be lower than the height before heating.
次に、図２の（ｂ）に示すように、第１の基材電極１２と第１の電極３４、及び、第２の基材電極２２と第２の電極３６とを接合する接合工程が行われる。接合工程では、はんだ材１６及び２６の融点以上の温度下において加熱溶融されたはんだ材１６及び２６に第１の電極３４及び第２の電極３６を当接させる。
Next, as shown in FIG. 2B, a bonding step of bonding the first base electrode 12 and the first electrode 34, and the second base electrode 22 and the second electrode 36 is performed. Done. In the joining step, the first electrode 34 and the second electrode 36 are brought into contact with the solder materials 16 and 26 heated and melted at a temperature equal to or higher than the melting point of the solder materials 16 and 26.
具体的には、溶融工程において、はんだ材１６は、第１の基材電極１２上のほぼ全面に溶融する。溶融したはんだ材１６に第１の電極３４を当接することにより、第１の基材電極１２とＬＥＤチップ２の第１の電極３４とは、はんだ材１６を介在してほぼ全面で接合される。
Specifically, in the melting step, the solder material 16 is melted on almost the entire surface of the first base electrode 12. By bringing the first electrode 34 into contact with the molten solder material 16, the first base material electrode 12 and the first electrode 34 of the LED chip 2 are joined almost entirely with the solder material 16 interposed therebetween. .
このとき、余分な量のはんだ材１６は、第１の溝部１４に流れ込むため、はんだ材１６が第１の基材電極１２から第２の基材電極２２へと流れ出すことはない。これにより、はんだ材１６によるｐ型電極である第１の電極３４とｎ型電極である第２の電極３６との間の短絡を防ぐことができる。
At this time, since an excessive amount of the solder material 16 flows into the first groove portion 14, the solder material 16 does not flow out from the first base material electrode 12 to the second base material electrode 22. Thereby, the short circuit between the 1st electrode 34 which is a p-type electrode by the solder material 16, and the 2nd electrode 36 which is an n-type electrode can be prevented.
同様に、溶融工程において、はんだ材２６は、第２の基材電極２２上のほぼ全面に溶融する。溶融したはんだ材２６に第２の電極３６を当接することにより、第２の基材電極２２とＬＥＤチップ２の第２の電極３６とは、はんだ材２６を介在してほぼ全面で溶融接合される。
Similarly, in the melting step, the solder material 26 is melted on almost the entire surface of the second base electrode 22. By bringing the second electrode 36 into contact with the molten solder material 26, the second base electrode 22 and the second electrode 36 of the LED chip 2 are melt-bonded on almost the entire surface with the solder material 26 interposed therebetween. The
このとき、余分な量のはんだ材２６は、第２の溝部２４に流れ込むため、はんだ材２６が第２の基材電極２２から第１の基材電極１２へと流れ出すことはない。これにより、はんだ材２６によるｐ型電極である第１の電極３４とｎ型電極である第２の電極３６との間の短絡を防ぐことができる。
At this time, since an excessive amount of the solder material 26 flows into the second groove portion 24, the solder material 26 does not flow from the second base material electrode 22 to the first base material electrode 12. Thereby, the short circuit between the 1st electrode 34 which is a p-type electrode by the solder material 26, and the 2nd electrode 36 which is an n-type electrode can be prevented.
なお、第１の溝部１４及び第２の溝部２４は、側面及び底面に、Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｎｉ、Ｔｉ、Ｓｎの少なくともいずれかで構成され、側面と底面に跨って形成された導電層を有してもよい。すなわち、第１の溝部１４及び第２の溝部２４のそれぞれの側面及び底面には、Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｎｉ、Ｔｉ、Ｓｎの少なくともいずれかで構成される導電層が形成されていてもよい。
The first groove portion 14 and the second groove portion 24 are formed of at least one of Au, Ag, Cu, Pt, Ni, Ti, and Sn on the side surface and the bottom surface, and are formed across the side surface and the bottom surface. You may have a conductive layer. That is, a conductive layer composed of at least one of Au, Ag, Cu, Pt, Ni, Ti, and Sn is formed on the side surface and the bottom surface of each of the first groove portion 14 and the second groove portion 24. Also good.
詳細には、図３に示すように、配線基板１は、基材１０の上に形成された第１の基材電極２２及び第２の基材電極２２にそれぞれ設けられた第１の溝部１４及び第２の溝部２４の側面及び底面に、例えばＡｕで構成される導電層３８を有する。
Specifically, as shown in FIG. 3, the wiring substrate 1 includes a first groove portion 14 provided on each of the first base material electrode 22 and the second base material electrode 22 formed on the base material 10. In addition, a conductive layer 38 made of, for example, Au is provided on the side surface and the bottom surface of the second groove portion 24.
導電層３８は、例えばスパッタリングにより第１の基材電極１２及び第２の基材電極２２の上に形成されている。導電層３８の厚さは、一例として２μｍである。
The conductive layer 38 is formed on the first base electrode 12 and the second base electrode 22 by sputtering, for example. The thickness of the conductive layer 38 is 2 μm as an example.
Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｎｉ、Ｔｉ、Ｓｎは、はんだ材１６又は２６を構成するＡｕＺｎに対する濡れ性がよい。したがって、上記した構成とすることにより、はんだ材１６及び２６が第１の基材電極１２及び第２の基材電極２２の上に濡れ広がる際にボイドが入らず、第１の基材電極１２及び第２の基材電極２２の全面にはんだ材１６及び２６を効率よく濡れ広げることができる。
Au, Ag, Cu, Pt, Ni, Ti, and Sn have good wettability with respect to AuZn constituting the solder material 16 or 26. Therefore, with the above-described configuration, when the solder materials 16 and 26 wet and spread on the first base material electrode 12 and the second base material electrode 22, voids do not enter and the first base material electrode 12. In addition, the solder materials 16 and 26 can be efficiently spread over the entire surface of the second base electrode 22.
なお、導電層３８は、第１の溝部１４及び第２の溝部２４の底面及び側面に限らず、第１の基材電極１２第２の基材電極２２の上面にも形成されていてもよい。
The conductive layer 38 is not limited to the bottom surface and the side surface of the first groove portion 14 and the second groove portion 24, but may be formed on the upper surface of the first base material electrode 12 and the second base material electrode 22. .
以上、本実施の形態に係る配線基板によれば、基材１０上に形成され、ＬＥＤチップ２を接合する、導電性を有する第１の基材電極１２及び第２の基材電極２２と、第１の基材電極１２及び第２の基材電極２２の上に配置されたはんだ材１６及び２６と、基材１０上に形成され、ＬＥＤチップ２を第１の基材電極１２及び第２の基材電極２２に接合する時に、溶融した接合材料が流れ込む第１の溝部１４及び第２の溝部２４とを備える。また、第１の基材電極１２は、ＬＥＤチップ２のｐ型半導体層に接続され、第２の基材電極２２は、ＬＥＤチップ２のｎ型半導体層に接続される。
As described above, according to the wiring substrate according to the present embodiment, the first base electrode 12 and the second base electrode 22 having conductivity, which are formed on the base material 10 and join the LED chip 2, Solder materials 16 and 26 disposed on the first base electrode 12 and the second base electrode 22 and the base material 10, the LED chip 2 is formed on the first base electrode 12 and the second base electrode 12. The first groove portion 14 and the second groove portion 24 into which the molten bonding material flows when bonding to the base electrode 22 are provided. The first base electrode 12 is connected to the p-type semiconductor layer of the LED chip 2, and the second base electrode 22 is connected to the n-type semiconductor layer of the LED chip 2.
これにより、ｐ型半導体層とｎ型半導体層を有するＬＥＤチップ２であっても、配線基板１とＬＥＤチップ２との安定した接合状態を実現してＬＥＤチップ２の短絡を抑制することができる。
Thereby, even if it is the LED chip 2 which has a p-type semiconductor layer and an n-type semiconductor layer, the stable joining state of the wiring board 1 and the LED chip 2 is implement | achieved, and the short circuit of the LED chip 2 can be suppressed. .
（実施の形態１の変形例）
次に、実施の形態１の変形例について図４～図６を参照して説明する。図４～図６は、本変形例に係る配線基板の構成を示す上面図である。 (Modification of Embodiment 1)
Next, a modification of the first embodiment will be described with reference to FIGS. 4 to 6 are top views showing the configuration of the wiring board according to this modification.
次に、実施の形態１の変形例について図４～図６を参照して説明する。図４～図６は、本変形例に係る配線基板の構成を示す上面図である。 (Modification of Embodiment 1)
Next, a modification of the first embodiment will be described with reference to FIGS. 4 to 6 are top views showing the configuration of the wiring board according to this modification.
本変形例では、第１の溝部は、第１の基材電極が形成される接合材料形成部の外周部に形成されている。これにより、接合時に第１の電極材料から接合材料であるはんだ材がはみ出しても、はみ出したはんだ材は第１の溝部に流れ込むため、はんだ材を第１の基材電極の全面に濡れ広げることができる。
In the present modification, the first groove is formed on the outer peripheral portion of the bonding material forming portion where the first base electrode is formed. As a result, even if the solder material, which is the bonding material, protrudes from the first electrode material during bonding, the protruding solder material flows into the first groove, so that the solder material spreads over the entire surface of the first base electrode. Can do.
図４に示す配線基板４０では、第１の基材電極４２の上に接合材料であるはんだ材４６が形成される接合材料形成部の外周を囲むように、第１の溝部４４が形成されている。なお、接合材料形成部は、第１の基材電極１２において、溶融前のはんだ材１６が配置される部分をいう。
In the wiring board 40 shown in FIG. 4, the first groove 44 is formed so as to surround the outer periphery of the bonding material forming portion where the solder material 46 as the bonding material is formed on the first base electrode 42. Yes. The bonding material forming portion refers to a portion where the solder material 16 before melting is disposed in the first base electrode 12.
ここで、接合材料形成部の形状、及び、配線基板４０とＬＥＤチップ２の接合前におけるはんだ材４６の形状は、第１の基材電極４２上において、第１の基材電極４２と相似形に形成されている。すなわち、図４に示すように、接合材料形成部及びはんだ材４６は、第１の基材電極４２と同一の形状で面積が小さく、第１の基材電極４２の周縁から所定の距離内側に入り込んだ形状に形成されている。
Here, the shape of the bonding material forming portion and the shape of the solder material 46 before bonding the wiring substrate 40 and the LED chip 2 are similar to the first base electrode 42 on the first base electrode 42. Is formed. That is, as shown in FIG. 4, the bonding material forming portion and the solder material 46 have the same shape as the first base electrode 42 and a small area, and are located a predetermined distance from the periphery of the first base electrode 42. It is formed in an intrusive shape.
また、接合材料形成部の外周を囲むように形成された第１の溝部４４の形状は、第１の基材電極４２と相似形に形成されている。はんだ材４６の形成形状を第１の基材電極４２の外形を縮小した相似形にすることにより、接合後に、第１の基材電極４２の外形に対し、はんだ材４６を第１の基材電極４２の全面に濡れ広げることが可能となる。
The shape of the first groove 44 formed so as to surround the outer periphery of the bonding material forming portion is similar to that of the first base electrode 42. By forming the solder material 46 into a similar shape obtained by reducing the outer shape of the first base material electrode 42, the solder material 46 is changed from the outer shape of the first base material electrode 42 to the first base material after joining. It becomes possible to spread over the entire surface of the electrode 42.
また、第１の溝部４４が接合材料形成部の外周に形成されることにより、はんだ材４６が第１の基材電極４２からはみ出したとしても、はみ出したはんだ材４６は第１の溝部４４に流れ込むので、はんだ材４６が第１の基材電極４２から第２の基材電極２２へと流れ出すことがない。これにより、はんだ材４６によるｐ型電極である第１の電極３４とｎ型電極である第２の電極３６との間の短絡を防ぐことができる。
Further, since the first groove portion 44 is formed on the outer periphery of the bonding material forming portion, even if the solder material 46 protrudes from the first base material electrode 42, the protruding solder material 46 enters the first groove portion 44. Since it flows in, the solder material 46 does not flow out from the first base electrode 42 to the second base electrode 22. Thereby, the short circuit between the 1st electrode 34 which is a p-type electrode by the solder material 46, and the 2nd electrode 36 which is an n-type electrode can be prevented.
図５に示す配線基板５０では、ＬＥＤチップ２の実装前のはんだ材５６は、円形の形状に形成されている。したがって、第１の基材電極５２の上面から見たときのはんだ材５６の面積は、第１の基材電極５２の面積よりも小さく形成されている。
In the wiring board 50 shown in FIG. 5, the solder material 56 before mounting the LED chip 2 is formed in a circular shape. Therefore, the area of the solder material 56 when viewed from the upper surface of the first base electrode 52 is formed smaller than the area of the first base electrode 52.
また、はんだ材５６が形成される接合材料形成部の外周には、第１の溝部５４が形成されている。加熱溶融時においては、はんだ材５６は、円形の形状の中心から外側に向かって溶融し、第１の基材電極５２上に均一に広がる。第２の基材電極２２上に形成されたはんだ材２６は、第２の基材電極２２上に均一に溶融する。
Further, a first groove 54 is formed on the outer periphery of the bonding material forming portion where the solder material 56 is formed. At the time of heating and melting, the solder material 56 is melted outward from the center of the circular shape and spreads uniformly on the first substrate electrode 52. The solder material 26 formed on the second base electrode 22 is uniformly melted on the second base electrode 22.
このとき、第１の溝部５４が接合材料形成部の外周に形成されることにより、はんだ材５６が第１の基材電極５２からはみ出したとしても、はみ出したはんだ材５６は第１の溝部５４に流れ込むので、はんだ材５６が第１の基材電極５２から第２の基材電極５２へと流れ出すことがない。これにより、はんだ材５６によるｐ型電極である第１の電極３４とｎ型電極である第２の電極３６との間の短絡を防ぐことができる。
At this time, even if the solder material 56 protrudes from the first base electrode 52 by forming the first groove portion 54 on the outer periphery of the bonding material forming portion, the protruding solder material 56 remains in the first groove portion 54. Therefore, the solder material 56 does not flow out from the first base electrode 52 to the second base electrode 52. Thereby, the short circuit between the 1st electrode 34 which is a p-type electrode by the solder material 56, and the 2nd electrode 36 which is an n-type electrode can be prevented.
図６に示す配線基板６０では、ＬＥＤチップ２の実装前のはんだ材６６は、十字の形状に形成されている。したがって、第１の基材電極５２の上面から見たときのはんだ材６６の面積は、第１の基材電極５２の面積よりも小さく形成されている。
In the wiring board 60 shown in FIG. 6, the solder material 66 before mounting the LED chip 2 is formed in a cross shape. Therefore, the area of the solder material 66 when viewed from the upper surface of the first base electrode 52 is formed to be smaller than the area of the first base electrode 52.
また、はんだ材６６が形成される接合材料形成部の外周には、第１の溝部６４が形成されている。加熱溶融時においては、はんだ材６６は、十字の形状の中心から外側に向かって溶融し、第１の基材電極６２上に均一に広がる。第２の基材電極２２上に形成されたはんだ材２６は、第２の基材電極２２上に均一に溶融する。
Also, a first groove 64 is formed on the outer periphery of the bonding material forming portion where the solder material 66 is formed. At the time of heating and melting, the solder material 66 is melted outward from the center of the cross shape and spreads uniformly on the first substrate electrode 62. The solder material 26 formed on the second base electrode 22 is uniformly melted on the second base electrode 22.
このとき、第１の溝部６４が接合材料形成部の外周に形成されることにより、はんだ材６６が第１の基材電極６２からはみ出したとしても、はみ出したはんだ材６６は第１の溝部６４に流れ込むので、はんだ材６６が第１の基材電極６２から第２の基材電極６２へと流れ出すことがない。これにより、はんだ材６６によるｐ型電極である第１の電極３４とｎ型電極である第２の電極３６との間の短絡を防ぐことができる。
At this time, even if the solder material 66 protrudes from the first base material electrode 62 by forming the first groove portion 64 on the outer periphery of the bonding material forming portion, the protruding solder material 66 remains in the first groove portion 64. Therefore, the solder material 66 does not flow out from the first base electrode 62 to the second base electrode 62. Thereby, the short circuit between the 1st electrode 34 which is a p-type electrode by the solder material 66, and the 2nd electrode 36 which is an n-type electrode can be prevented.
（実施の形態２）
次に、実施の形態２に係る配線基板及びＬＥＤモジュールについて、図７を用いて説明する。図７は、本実施の形態に係る配線基板の構成を示す断面図である。 (Embodiment 2)
Next, the wiring board and LED module according to Embodiment 2 will be described with reference to FIG. FIG. 7 is a cross-sectional view showing the configuration of the wiring board according to the present embodiment.
次に、実施の形態２に係る配線基板及びＬＥＤモジュールについて、図７を用いて説明する。図７は、本実施の形態に係る配線基板の構成を示す断面図である。 (Embodiment 2)
Next, the wiring board and LED module according to Embodiment 2 will be described with reference to FIG. FIG. 7 is a cross-sectional view showing the configuration of the wiring board according to the present embodiment.
本実施の形態に係る配線基板７０が実施の形態１に係る配線基板１と異なる点は、溝部（第１の溝部及び第２の溝部）７４が配線基板７０を構成する第１の基材電極及び第２の基材電極と、基材１０の一部とを掘り込んで形成されている点である。また、溝部７４の側面と底面に、Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｎｉ、Ｔｉ、Ｓｎの少なくともいずれかで構成され、側面と底面に跨って形成された導電層７８を有している。
The wiring board 70 according to the present embodiment is different from the wiring board 1 according to the first embodiment in that a groove portion (first groove portion and second groove portion) 74 is a first base material electrode that constitutes the wiring substrate 70. And the second base electrode and a part of the base 10 are dug. In addition, the side surface and the bottom surface of the groove 74 have a conductive layer 78 that is made of at least one of Au, Ag, Cu, Pt, Ni, Ti, and Sn and is formed across the side surface and the bottom surface.
詳細には、図７に示すように、基材１０には溝部７４を構成するためのパターンが掘り込んで形成され、溝部７４の側面及び底面には、例えば、スパッタリング法により導電層７８が形成されている。また、基材１０の上には、電極７２がパターン形成されている。
Specifically, as shown in FIG. 7, the base material 10 is formed by digging a pattern for forming the groove portion 74, and the conductive layer 78 is formed on the side surface and the bottom surface of the groove portion 74 by, for example, sputtering. Has been. An electrode 72 is formed on the base material 10 in a pattern.
この構成によれば、基材１０に溝部（第１の溝部及び第２の溝部）７４を構成するためのパターンを掘り込んだ後、第１の基材電極及び第２の基材電極を構成するための、電極７２を形成するプロセスを１回行うのみで、第１の溝部及び第２の溝部を形成することができる。
According to this configuration, the first substrate electrode and the second substrate electrode are configured after digging a pattern for forming the groove portion (first groove portion and second groove portion) 74 in the substrate 10. Therefore, the first groove portion and the second groove portion can be formed only by performing the process of forming the electrode 72 once.
また、Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｎｉ、Ｔｉ、Ｓｎは、はんだ材１６又は２６を構成するＡｕＺｎに対する濡れ性がよい。したがって、上記した構成とすることにより、はんだ材１６及び２６が第１の基材電極１２及び第２の基材電極２２の上に濡れ広がる際にボイドが入らず、第１の基材電極１２及び第２の基材電極２２の全面にはんだ材１６及び２６を効率よく濡れ広げることができる。
Further, Au, Ag, Cu, Pt, Ni, Ti, and Sn have good wettability with respect to AuZn constituting the solder material 16 or 26. Therefore, with the above-described configuration, when the solder materials 16 and 26 wet and spread on the first base material electrode 12 and the second base material electrode 22, voids do not enter and the first base material electrode 12. In addition, the solder materials 16 and 26 can be efficiently spread over the entire surface of the second base electrode 22.
なお、基材１０に掘り込んだ溝部のパターンの側面と底面に形成される導電層７８は、電極７２を形成した後に形成されてもよいし、基材１０に溝部（第１の溝部及び第２の溝部）７４を構成するためのパターンを掘り込んだ後に形成されてもよい。また、導電層７８に代えて、Ａｇ、Ｃｕ等Ａｕ以外の導電材料により、基材１０に掘り込んだ溝部のパターンの側面と底面に導電層が形成されてもよい。
The conductive layer 78 formed on the side surface and the bottom surface of the groove pattern dug into the base material 10 may be formed after the electrode 72 is formed, or the base material 10 may be formed with the groove portions (the first groove portion and the first groove portion). (2 groove portions) 74 may be formed after digging a pattern. Instead of the conductive layer 78, a conductive layer may be formed on the side and bottom surfaces of the groove pattern dug in the base material 10 using a conductive material other than Au, such as Ag or Cu.
（その他の変形例）
以上、本発明に係る配線基板及びＬＥＤモジュールについて、実施の形態に基づいて説明したが、本発明は、上記実施の形態に限定されるものではない。 (Other variations)
As mentioned above, although the wiring board and LED module which concern on this invention were demonstrated based on embodiment, this invention is not limited to the said embodiment.
以上、本発明に係る配線基板及びＬＥＤモジュールについて、実施の形態に基づいて説明したが、本発明は、上記実施の形態に限定されるものではない。 (Other variations)
As mentioned above, although the wiring board and LED module which concern on this invention were demonstrated based on embodiment, this invention is not limited to the said embodiment.
例えば、上記した実施の形態では、ＬＥＤ素子を配線基板に実装するＬＥＤ素子の実装構造について例示したが、ＬＥＤ素子に限らず他の発光素子を配線基板に実装する実装構造に本発明を用いてもよい。他の発光素子としては、半導体レーザ等の半導体発光素子、有機ＥＬ（Ｅｌｅｃｔｒｏ Ｌｕｍｉｎｅｓｃｅｎｃｅ）又は無機ＥＬ等のＥＬ素子等、その他の固体発光素子を用いてもよい。
For example, in the above-described embodiment, the LED element mounting structure for mounting the LED element on the wiring board is illustrated. However, the present invention is not limited to the LED element and is used for a mounting structure for mounting other light emitting elements on the wiring board. Also good. As other light emitting elements, other solid light emitting elements such as a semiconductor light emitting element such as a semiconductor laser, an EL element such as an organic EL (Electro Luminescence) or an inorganic EL may be used.
その他、各実施の形態及び変形例に対して当業者が思いつく各種変形を施して得られる形態や、本発明の趣旨を逸脱しない範囲で各実施の形態及び変形例における構成要素及び機能を任意に組み合わせることで実現される形態も本発明に含まれる。
In addition, the form obtained by making various modifications conceived by those skilled in the art with respect to each embodiment and modification, and the components and functions in each embodiment and modification are arbitrarily set within the scope of the present invention. Forms realized by combining them are also included in the present invention.
１、４０、５０、６０、７０ 配線基板
２ ＬＥＤチップ（ＬＥＤ素子）
１０ 基材
１２ 第１の基材電極（パッド部）
１２ａ、２２ａ 第１の実装電極（溝部）
１４ 第１の溝部（溝部）
１６、２６、４６、５６、６６ はんだ材（接合材料）
２２ 第２の基材電極（パッド部）
１２ｂ、２２ｂ 第２の実装電極（溝部）
２４ 第２の溝部（溝部）
３０ 絶縁基板
３２ 半導体層
３４ 第１の電極
３６ 第２の電極
３８、７８ 導電層 1, 40, 50, 60, 70 Wiring board 2 LED chip (LED element)
10substrate 12 first substrate electrode (pad portion)
12a, 22a First mounting electrode (groove)
14 First groove (groove)
16, 26, 46, 56, 66 Solder material (joining material)
22 Second substrate electrode (pad part)
12b, 22b Second mounting electrode (groove)
24 Second groove (groove)
30 Insulatingsubstrate 32 Semiconductor layer 34 First electrode 36 Second electrode 38, 78 Conductive layer
２ ＬＥＤチップ（ＬＥＤ素子）
１０ 基材
１２ 第１の基材電極（パッド部）
１２ａ、２２ａ 第１の実装電極（溝部）
１４ 第１の溝部（溝部）
１６、２６、４６、５６、６６ はんだ材（接合材料）
２２ 第２の基材電極（パッド部）
１２ｂ、２２ｂ 第２の実装電極（溝部）
２４ 第２の溝部（溝部）
３０ 絶縁基板
３２ 半導体層
３４ 第１の電極
３６ 第２の電極
３８、７８ 導電層 1, 40, 50, 60, 70 Wiring board 2 LED chip (LED element)
10
12a, 22a First mounting electrode (groove)
14 First groove (groove)
16, 26, 46, 56, 66 Solder material (joining material)
22 Second substrate electrode (pad part)
12b, 22b Second mounting electrode (groove)
24 Second groove (groove)
30 Insulating
Claims (7)
- 溶融接合によりＬＥＤ素子が実装される配線基板であって、
基材上に形成され、前記ＬＥＤ素子を接合する、導電性を有するパッド部と、
前記パッド部の上に配置された接合材料と、
前記基材上に形成され、前記ＬＥＤ素子を前記パッド部に接合する時に、溶融した前記接合材料が流れ込む溝部とを備える
配線基板。 A wiring board on which LED elements are mounted by melt bonding,
A conductive pad portion that is formed on a substrate and joins the LED elements;
A bonding material disposed on the pad portion;
A wiring board comprising: a groove portion formed on the base material and into which the molten bonding material flows when the LED element is bonded to the pad portion. - 前記パッド部は、前記ＬＥＤ素子のｐ型半導体層に接続される第１の基材電極と、前記ＬＥＤ素子のｎ型半導体層に接続される第２の基材電極とを、それぞれ少なくとも１つ有する
請求項１に記載の配線基板。 The pad section includes at least one first base electrode connected to the p-type semiconductor layer of the LED element and at least one second base electrode connected to the n-type semiconductor layer of the LED element. The wiring board according to claim 1. - 前記パッド部は、溶融前の前記接合材料が配置される接合材料形成部を有し、
前記溝部は、前記接合材料形成部の外周に形成されている
請求項１又は２に記載の配線基板。 The pad portion has a bonding material forming portion in which the bonding material before melting is disposed,
The wiring substrate according to claim 1, wherein the groove portion is formed on an outer periphery of the bonding material forming portion. - 前記溝部は、前記溝部の底面を構成する第１の実装電極と、前記溝部の側面を構成する第２の実装電極とで構成されている
請求項１～３のいずれか１項に記載の配線基板。 The wiring according to any one of claims 1 to 3, wherein the groove portion includes a first mounting electrode constituting a bottom surface of the groove portion and a second mounting electrode constituting a side surface of the groove portion. substrate. - 前記溝部は、前記パッド部と前記基材の一部とを掘り込んで形成されている
請求項１～３のいずれか１項に記載の配線基板。 The wiring board according to any one of claims 1 to 3, wherein the groove portion is formed by digging out the pad portion and a part of the base material. - 前記溝部は、側面及び底面に、Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｎｉ、Ｔｉ、Ｓｎの少なくともいずれかで構成され、前記側面と前記底面に跨って形成された導電層を有する
請求項１～５のいずれか１項に記載の配線基板。 The groove includes a conductive layer formed on at least one of Au, Ag, Cu, Pt, Ni, Ti, and Sn on a side surface and a bottom surface and formed across the side surface and the bottom surface. The wiring board according to any one of the above. - 請求項１～６のいずれか１項に記載の配線基板と、
前記配線基板に実装された前記ＬＥＤ素子とを備える
ＬＥＤモジュール。 The wiring board according to any one of claims 1 to 6,
An LED module comprising the LED element mounted on the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015521291A JP6103401B2 (en) | 2013-06-07 | 2014-05-29 | Wiring board and LED module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013121312 | 2013-06-07 | ||
| JP2013-121312 | 2013-06-07 |
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| PCT/JP2014/002861 WO2014196175A1 (en) | 2013-06-07 | 2014-05-29 | Circuit board and led module |
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| JP (1) | JP6103401B2 (en) |
| WO (1) | WO2014196175A1 (en) |
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| KR20190019745A (en) * | 2017-08-18 | 2019-02-27 | 주식회사 루멘스 | light emitting element and method for making the same |
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|---|---|---|---|---|
| JP2003101121A (en) * | 2001-09-27 | 2003-04-04 | Matsushita Electric Ind Co Ltd | Semiconductor light emitting device |
| JP2005038892A (en) * | 2003-07-15 | 2005-02-10 | Matsushita Electric Ind Co Ltd | Semiconductor light emitting device and its manufacturing method |
| JP2005123439A (en) * | 2003-10-17 | 2005-05-12 | Matsushita Electric Ind Co Ltd | Light emitting device |
| JP2005174998A (en) * | 2003-12-08 | 2005-06-30 | Kyocera Corp | Package for storing light emitting element and light emitting device |
| JP2006147675A (en) * | 2004-11-17 | 2006-06-08 | Matsushita Electric Works Ltd | Semiconductor device and its evaluation method |
| JP2006313897A (en) * | 2005-05-07 | 2006-11-16 | Samsung Electronics Co Ltd | Submount for light emitting package |
| JP2007243193A (en) * | 2006-03-09 | 2007-09-20 | Samsung Electro-Mechanics Co Ltd | Light-emitting diode package |
| JP2008053423A (en) * | 2006-08-24 | 2008-03-06 | Hitachi Cable Ltd | Connector, and optical transceiver module |
-
2014
- 2014-05-29 JP JP2015521291A patent/JP6103401B2/en active Active
- 2014-05-29 WO PCT/JP2014/002861 patent/WO2014196175A1/en active Application Filing
Patent Citations (8)
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|---|---|---|---|---|
| JP2003101121A (en) * | 2001-09-27 | 2003-04-04 | Matsushita Electric Ind Co Ltd | Semiconductor light emitting device |
| JP2005038892A (en) * | 2003-07-15 | 2005-02-10 | Matsushita Electric Ind Co Ltd | Semiconductor light emitting device and its manufacturing method |
| JP2005123439A (en) * | 2003-10-17 | 2005-05-12 | Matsushita Electric Ind Co Ltd | Light emitting device |
| JP2005174998A (en) * | 2003-12-08 | 2005-06-30 | Kyocera Corp | Package for storing light emitting element and light emitting device |
| JP2006147675A (en) * | 2004-11-17 | 2006-06-08 | Matsushita Electric Works Ltd | Semiconductor device and its evaluation method |
| JP2006313897A (en) * | 2005-05-07 | 2006-11-16 | Samsung Electronics Co Ltd | Submount for light emitting package |
| JP2007243193A (en) * | 2006-03-09 | 2007-09-20 | Samsung Electro-Mechanics Co Ltd | Light-emitting diode package |
| JP2008053423A (en) * | 2006-08-24 | 2008-03-06 | Hitachi Cable Ltd | Connector, and optical transceiver module |
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| Publication number | Publication date |
|---|---|
| JPWO2014196175A1 (en) | 2017-02-23 |
| JP6103401B2 (en) | 2017-03-29 |
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