WO2014193254A1

WO2014193254A1 - Modular generator for bipolar or unipolar pulses with correction of voltage decay integrated in power semiconductor modules

Info

Publication number: WO2014193254A1
Application number: PCT/PT2014/000035
Authority: WO
Inventors: José Fernando ALVES DA SILVA; Hiren CANACSINH; Luís Manuel DOS SANTOS REDONDO
Original assignee: Instituto Superior Tecnico; Instituto Superior De Engenharia De Lisboa
Priority date: 2013-05-28
Filing date: 2014-05-28
Publication date: 2014-12-04
Also published as: PT106971B; PT106971A

Abstract

This invention refers to modular generators to output bipolar or unipolar voltage pulses with corrected pulse voltage decay and respective process. The pulse correction and the respective process are integrated in p modules, of the n+p generator modules, using power semiconductors (24A), (24B), (25), (26A), (26B), (27A), (27B), (28A), (28B) and (29). The n+p generator modules contain power semiconductors with turn-on and turn-off capability (1A), (4A), (6A), (7A), (8A), (14A), (16A), (17A), (18A), (24A), (26A), (27A), (28A) and non controlled power semiconductors (IB), (2), (4B), (5), (6B), (7B), (8B), (9), (14B), (15), (16B), (17B), (18B), (19), (24B), (25), (26B), (27B), (28B), (29). The n+p generator modules are supplied from a constant voltage source V_dc (11) and apply to resistive, inductive or capacitive loads (12), bipolar or unipolar voltage pulses with amplitude nV_dc, being V_dc the no load voltage of capacitors (3), (10), (13), (20), (30). The p modules use variable frequency pulse width modulation and filtering inductor L_f(31) and capacitor C_f(32) to correct the voltage decay of the pulse plateau.

Description

DESCRIPTION

MODULAR GENERATOR FOR BIPOLAR OR UNIPOLAR PULSES WITH CORRECTION OF VOLTAGE DECAY INTEGRATED IN POWER SEMICONDUCTOR MODULES

Field of invention

This invention presents a Marx type high voltage bipolar pulse modular generator, containing n+p modules, all similar, from which p are used on the pulse decay correction, using the power semiconductors (24A) , (24B) , (25), (26A) , (26B) , (27A) , (27B) , (28A), (28B) , and (29), for example.

Considering solid-state electronics, different techniques are known to generate bipolar high voltage pulses. Some circuit topologies use two independent continuous voltage power supplies, with series assembled power semiconductors to hold the high voltage, connected in such a way to independently obtain negative and/or positive high voltage pulses. Further existing topologies use static power converters that can associate a high voltage transformer, to increase the output voltage.

Alternatively, Marx type generators can be used, where the capacitors are charged in parallel, by a constant voltage power supply, and subsequently discharged in series through the load. This type of circuits is limited by the amount of capacitor stored energy regarding the energy required by the load during the pulse. Considering the situation where the energy delivered to the load, during the pulse, has a similar order of magnitude compared to the capacitor stored energy, then the pulse shape is no longer rectangular and presents an evident time decay of the top voltage.

A simple solution, to circumvent this problem, would be to increase the capacitance of the storage capacitors, but this technique increases the size, the weight and the cost of the circuit. Several authors developed techniques for compensating the high voltage pulse decay on the unipolar Marx generator circuits, which include a resonant circuit in each stage. This resonant circuit algebraically adds the quasi linear part of the resonant sinusoidal voltage to the main capacitor voltage, to nearly compensate the voltage decay, thus providing circuits with smaller dimensions.

This invention provides a new solid-state topology for a modular Marx generator that allows the generation of high voltage unipolar and/or bipolar pulses with flat top, namely, it corrects the pulse top voltage decay. The time decay during the unipolar/bipolar pulse is corrected using pulse width modulation in the p extra modules. In addition, a filter with coil (31) and capacitor C (32) removes the modulation components from the pulse top.

State of the Art

High voltage pulse generators, capable of generating bipolar pulses, are increasingly being used in industrial applications, as in the surface treatment of metals and semiconductors, plasma immersion ion implantation, food sterilization, waste treatment, pollution control, medical diagnostic and treatment, for example.

Quality requirements, weight and cost have led to the development of circuits to generate high voltage bipolar pulses, taking advantage of power semiconductors ( solid—state) [1-4] .

Using solid-state technology, a frequent method to generate high voltage bipolar pulses uses two power supplies and power semiconductors, operating as switches to generate negative and/or positive pulses. Considering the industrial processes required high voltages (from dozens to hundreds of kV) , and the semiconductor voltage limitations (up to 6 kV) , each switch consists of a series stack of power semiconductors [1,3]. Alternatively, equivalent topologies developed from power electronic converters, use a pulse transformer to increase the voltage applied to the load [2-3,5-6]. The transformer is a critical component in the pulse waveform shaping, being also heavy and difficult to design and assemble. For these reasons other approaches, such as the multi-level converter type, have been used to generate high voltage bipolar pulses [7] .

The Marx generator topology, described originally by E. Marx in 1924, is one of the most important in the generation of high voltage pulses, requiring only one constant voltage power supply with relatively low voltage value. The Marx generator uses switch type devices to charge parallel connected capacitors, and subsequently discharge them, series connected, through a load. A transient voltage is thus generated with amplitude close to the number of the series capacitors multiplied by the constant voltage source value.

Recently several works have been published with Marx type generators, intensively using power semiconductors, capable of applying high voltage pulse into the load, positive and/or negative. It was proposed in [4], a high voltage bipolar pulse modulator based in the Marx concept, which uses two high voltage power supplies. In [8] it was presented a topology capable of generating unipolar and/or bipolar pulses based on the Marx generator concept using only a power supply. There is an increasingly need to build high-voltage generators with better performance, increased compactness and reliablity.

However, the Marx type generators are limited by the ratio between the energy stored in the capacitors and the energy delivered to the load during the pulse. If the pulse energy is in the same order of magnitude of the energy stored in the capacitors, the pulse is no longer quasi rectangular, the voltage at the end of the pulse decreasing significantly, due to the discharge of the capacitors. One solution would be to increase the capacitance of capacitors, but this would increase the size and cost of the generator.

The requirement for pulse voltage decay correction, leveling the pulse top, can be achieved adding one or more modules (p modules) like the remaining, linked to a switching process. For example, it is shown in figure 1, a high voltage bipolar pulse generator based on the Marx generator concept, with pulse voltage decay correction performed in one or several modules.

Detailed description of the invention

The invention here reported is related to a modular generator for unipolar or bipolar pulses (Marx generator type) with pulse voltage decay correction, and respective operating process, integrated in modules of power semiconductors with turn-on and turn-off capability (1A), (4A), (6A), (7A) , (8A), (14A), (16A), (17A), (18A), (24A), (26A), (27A) , (28A) , non controlled power semiconductors, hereinafter referred as diodes, (IB), (2), (4B), (5), (6B), (7B), (8B), (9), (14B) , (15), (16B) , (17B), (18B), (19), (24B), (25), (26B), (27B) , (28B) , (29). It applies bipolar and/or unipolar voltage pulses into resistive, inductive or capacitive loads (12) , with amplitude nVdc, where V_dc is the power supply (11) voltage and the open load voltage of capacitors C_j (3), (10), (13), (20).

Figure 1 showns the bipolar pulse generator circuit based on high-voltage modules with power semiconductors with turn-on and turn-off capability, with n levels, where power semiconductors based electronic switches are used. For explanation clearness of the process of the bipolar pulses generation, the pulse voltage decay correction, the filter with coil L_f (31) and capacitor C_f (32), will be included and discussed later.

The power semiconductors with turn-on and turn-off capability operating as switches, T_a (1A) , T_di (4A), (14A), T_ei (6A), (16A), T_fi (7A), (17A) and T_hi (8A) , (18A) with ie { 1 , 2 , ... , n } are in the preferred embodiment, metal oxide semiconductor field effect transistors (MOSFET) (with anti- parallel intrinsic diode) , but equivalent power semiconductors with turn-on and turn-off capability can be used, such as insulated gate bipolar transistors (IGBT), gate turn-off thyristors (GTO) , bipolar junction transistors (BJT) , junction field effect transistors ( JFET) , vertical junction field effect transistors (VFET) , static induction transistor (SIT), bipolar mode static induction transistors (BSIT) , insulated gate thyristor (MCT) , field controlled thyristor (FCTh) or any equivalent device with a similar function, in Silicon, in Silicon Carbide or in equivalent materials, with or without anti- parallel non controlled power semiconductors, diode types, according to the load needs, which can have resistive, inductive or capacitive behaviour.

To describe the operation of the circuit of figure 1, it is considered that the circuit operates under periodic regime.

To charge the capacitors C_j, j e {1,2,..., n+1}, (3), (10), (13), (20) of the figure 1 circuit, the power semiconductors MOSFET type with turn-on and turn-off capability, or equivalent with similar behavior, hereinafter referred as MOSFETs T_a (1A), di (4A), (14A) and T_hi (8A) , (18A) are driven to the ON state and MOSFETs T_ei (6A ), (16A), T_fi (7A) , (17A) to the OFF state. The diodes D_b (2) D_ci (5), (15) and D_gi (9), (19) are forward biased and conducting. In this situation the topology shown in Figure 1 becomes equivalent to the circuit shown in Figure 2, where MOSFETs T_a (1A), T_di (4A) , (14A) and T_hi (8A), (18A) , and diodes D_b (2), D_ci (5), (15) and D_gi (9), (19) are conducting. In this mode of operation the energy, previously delivered by capacitors Cj (3), (10), (13), (20), is re-stored by the constant voltage source Vd_C (H) (with the r internal resistance (21) , figure 2) through OSFETs T_a (1A), T_di (4A) , _. (14A) and T_hi (8A), (18A), and diodes D_b (2), D_ci (5), (15) and D_gi (9), (19).

During the energy recharging (re-storage) of capacitors Cj (3),

(10) , (13), (20), the voltage v_Q applied to the load (12), referenced to ground, is a residual voltage of conducting MOSFETs T_hi (8A), (18A) and diodes D_gi (9), (19) being approximately zero.

The internal resistance (21) from constant voltage source

(11) , together with the voltage drop across the conducting MOSFETs T_a (1A), T_di (4A), (14A) and T_hi (8A), (18A) and the eguivalent series resistance of capacitors C_j (3), (10), (13), (20) limit the capacitor recharging currents i_lr i₂, i_n,

±2 = _c2 + Ϊ3, (ID

(III) i-n+l — -l_c(n+l) (IV)

In the capacitors C_j (3), (10), (13), (20) recharging process, the recharging current depends on the voltage variation Av_Cj of the capacitor j (intended to be small v_Cj∞V_dc) and on recharge time At:

<, -c,-£ (V)

This current can be high in the transient regime, especially during the operating initial instants, a current limiter being necessary. During the recharging of the capacitors, the recharging time constant is cj - ^ j (VI ) where R_tj is the total series equivalent resistance of the circuit. Since R_tj includes the internal resistance of the source, the equivalent voltage drop of the conducting power semiconductors and the equivalent series resistance of the capacitors, the value of x_Cj can be very low, to easily obtain operating frequencies above tens of kHz.

One method to limit the value of the recharging currents (especially during the first charging process of the capacitors from zero to V_dc) is to use an impedance in series with the DC voltage source V_dc (11) . This impedance is short-circuited in steady state, to minimize power loss and to reduce recharging times. Alternatively, it can be used a constant voltage source (11) having soft voltage start to limit charging voltage rate on the capacitors (3), (10), (13), (20), thus preventing the damage of the power semiconductors during the process of capacitor recharging.

The second operating mode corresponds to the application of the voltage pulse into the load (12) . The sequence of application of this load (12) voltage pulse into is processor programmed by the user by setting the driving signals of the MOSFETs . Thus, the signals of the MOSFETs can be set to:

• apply only positive pulses into the load (unipolar pulses);

• apply only negative pulses into the load (unipolar pulses) ;

• apply positive and negative or negative and positive pulses to the load (bipolar pulses) .

To accomplish the first option (positive unipolar pulses) MOSFETs T_di (4A), (14A) and T_fi (7A), (17A) are ON state driven, and the MOSFETs T_a (1A) , T_ei (6A) (16A) and T_hi (8A), (18A) are OFF state driven. Thus, to apply positive voltage pulses to the load (12), the circuit of Figure 1 a s ^sumes the topology of Figure 3, where the MOSFETs T_di (4A), (14A) and T_fi (7A) , (17A) are conducting.

During positive pulse mode operation, all capacitors C_j (3) , (10), (13), (20) (except the capacitor C_(n+i) (20) because it is not used in this mode) are series connected and the open circuit voltage in the load (12), is

assuming that capacitors (3), (10), (13), are all charged at Va_c voltage value, and null residual voltage drops. To apply negative unipolar voltage pulses to the load (12) MOSFETs T_ei (6A), (16A) and T_hi (8A) , (18A) are ON state driven and MOSFETs T_a (1A.), T_di (4A) , (14A) and T_fi (7A) , (17A) are OFF state driven. Then, the circuit of Figure 1, for negative pulses assumes the topology shown in Figure 4, where the MOSFETs T_ei (6A), (16A) and T_hi (8A) , (18A) are conducting.

During this period, the capacitors C_j, (10) (13) (20) (with the exception of the capacitor C_\ (3) , as it is not used in this mode) are series connected and the open circuit voltage in the load (12), is

assuming null residual voltage drops and capacitors (10), (13), (20) all charged at the V_dc voltage.

According to the previously described and looking into Figure 1, the number of capacitors C_j is bigger by one unit regarding the number of modules of power semiconductors (n) required to generate the voltage nV_dc. When applying positive pulses, capacitor C_n+i (20) does not contribute to the process of application of voltage to the load, while for applying negative pulses, the capacitor Ci (3) does not contribute also. The generation of bipolar pulses is obtained using the above described, now including both the driving signals for the positive pulse and for the negative pulse. The sequence in which the MOSFETs are turned ON and OFF depends on the pulse type. To apply negative followed by positive pulses to the load (12), first MOSFETs T_ei ( 6A ) , (16A) and T_hi (8A), (18A) are ON state driven and MOSFETs T_a (1A), T_di ( 4A ) , (14A) and T_fi (7A), (17A) are OFF state driven, followed by MOSFETs T_di (4A), (14A) and T_fi (7A), (17A) being ON state driven and MOSFETs T_a (1A) , T_ei (6A) (16A) and T_hi (8A), (18A) being OFF state driven.

These conditions however depend on:

• the physical characteristics of components;

• the circuit operating frequency;

• the capacitors charging time is considerably higher than the discharging time, therefore, the MOSFETs T_ei <6A), (16A) and _fi (7A), (17A) should operate with a small duty cycle while MOSFETs T_a (1A), T_di (4A), (14A) and T_hi (8A), (18A) should operate with high duty cycle.

When applying the negative pulse, the capacitors (10) , (13) , (20), are not short-circuited by MOSFETs T_ei (6A), (16A) and T_hi (8A), (18A) because MOSFETs T_di (4A) , (14A) and T_fi (7A) , (17A), are OFF state driven and diodes D_gi (9), (19) are reverse biased. Likewise, regarding the positive pulse, capacitors (3), (10), (13) are not short-circuited through MOSFETs T_di (4A) , (14A) and T_fi (7A), (17A), since MOSFETs T_ei (6A), (16A) and T_hi (8A), (18A) are OFF state driven and diodes D_ci (5), (15) are reverse biased.

The MOSFET T_a (1A) is OFF state driven during the second mode of operation, shuting down the voltage source V_dc current, i.e., all the energy for the pulses is supplied entirely by capacitors (3), (10), (13), (20). Also, the reverse biased diode D_b (2) prevents the capacitor Ci discharge (3) . The circuit of Figure 1 requires MOSFET gate driving circuits operating at floating potentials. This fact requires all the MOSFET gate driving circuits being insulated from the ground potential. Since each controlled semiconductor in all the generator modules of Figure 1 is at a high and floating potential, the driving signals of the OSFETs are transmitted using optical fibers in order to guarantee the galvanic electrical insulation of each circuit. Similarly, the power supply for each semiconductor driving circuit is generated using galvanic insulation. The control system for driving the MOSFETs has to drive them all synchronously, except T_dl (4A) , T_hi (8A) and T_fn (17A) (in this example) . MOSFETs T_di (4A) and T_fn (17A) do not contribute to establish a zero voltage either into capacitive loads, after the negative pulse, or in establishing a zero average voltage value into inductive loads, after the positive pulse. Also the semiconductor T_hi (8A) does not contribute to establish a zero average voltage value in inductive loads, after negative pulse. The topology of Figure 1 has the ability to handle capacitive loads, as is the case of plasma or gas applications where it is required to establish a zero voltage in the load after the pulse application. After applying the positive pulse, it is necessary to establish a near zero voltage at the load (12) . This is achieved by ON state driving MOSFETs T_hi (8A) , (18A) , as can be seen in Figure 5.

After the negative pulse, to establish a zero voltage at the load, ON state driven MOSFETs T_di (4A), (14A) (except T_di (4A) ) , T_fn (17A) , are used together with diodes D_Ci (5) , (15) (except D_ci (5)) and anti-parallel diodes (8B) and (6B), as can be seen in Figure 6. After the negative pulse, a zero voltage at the load can also be established using MOSFETs T_di (4A) , (14A) , and diodes Dci (5), (15) and capacitors (3) and (20), as shown in figure 17. The use of MOSFET T_a (1A) (OFF state driven during the capacitors discharge) is intended to disconnect the constant voltage source V_dc (11) from the circuit, during the discharge of the capacitors, preventing the constant voltage supply V_dc (11) to withstand the high current pulse, therefore all the pulse energy is stored in capacitors C_j (3), (10) (13) (20).

The circuit of Figure 1 can also supply inductive type loads, or with pulse transformers to raise the voltage level (with zero average value) applied to the load (12) , by using the diodes conduction after applying positive or negative pulses.

Thus, when applying positive pulses into an inductive load, considering the current with the direction specified in Figure 3, the zero average voltage in the load is accomplished by applying the negative voltage according to the loop constituted by diodes (8B) , (18B) , (6B) and (16B) and the capacitors C₂ (10) to C_n+i (20), as shown in Figure 7.

During this period, the load (12) is subject to a symmetrical voltage with amplitude equal to the amplitude of a negative pulse. This means that two pulses with equal amplitudes are applied to the load (12), but with symmetrical polarities. However the circuit of Figure 1 provides an alternative to establish zero average voltages into the load, using the antiparallel diodes (8B) and (6B) of the MOSFE s T_hi and T_ei, ON state driven MOSFE s T_di (4A) , (14A) (except T_di (4A)) and only T_fn (17A), and diodes D_ci (5), (15) (except D_ci (5)) and capacitor C₂ (10), as shown in figure 8.

In this discussed alternative, it is chosen the capacitor (capacitor (10) in the case presented) to recover the energy of the inductive load. Similarly, the application of negative pulses to an inductive load, considering the current direction specified in Figure 4, the the load zero voltage average value is accomplished by applying a positive voltage accordingly to the loop including the diodes (4B), (14B) , ( IB ) , (17B) and capacitors ¾ (3) to C_n (13), as shown in Figure 9.

In the same way, during this period the load is subjected to a symmetrical voltage with amplitude equalling the amplitude of the negative pulse. Yet the circuit of Figure 1 provides an alternative to establish a load voltage zero average value, after the negative pulse, using ON state driven MOSFETs T_hi (8A), (18A) (except T_hi (8A) ) and diodes D_gi (9), (19) (except D_gl (9)), MOSFET T_di and T_fi anti-parallel diodes, respectively (4B) and (7B) and capacitor Ci (3), as shown in figure 10.

Likewise, the presented alternative allows choosing the capacitor (capacitor (3) in the presented case) that will recover the energy still in the inductive load.

As seen, the circuit of Figure 1 modules uses two power semiconductors in all the operating modes. Thus, for the charging mode MOSFETs T_di (4A) , (14A) and T_hi (8A) , (18A) are used; for positive pulse MOSFETs T_di (4A), (14A) and T_fi (7A) , (17A) are driven ON; and for negative pulse MOSFETs T_ei (6A), (16A) and T_hi (8A), (18A) are used. Thus, it is clear that MOSFETs T_di (4A) , (14A) and T_hi (8A), (18A) operate in the charging and load (12) positive and negative pulse respectively, which requires MOSFETs with. higher ratings.

Marx type generators are limited by the ratio between the stored energy in the capacitors Cj (3), (10), (13), (20) and the energy delivered to the load (12) during the pulse. During the pulse time into the load, the voltage on the capacitors C (3), (10) (13) (20) might not decrease to values that could result in a significant decrease of the pulse voltage. One way to achieve this, considering the energy stored in the capacitors, given as:

E, capacitors (ix) where v_c is the voltage in each of the n capacitors that contribute to the pulse (positive and/or negative), is to make the stored energy 50 to 100 times greater than the energy of the pulse voltage:

= nV_dci₀t_d (X) where t_d is the pulse duration time and o the pulse current,

assuming that the load (12) is resistive and capacitors C_j (3), (10) (13) (20) are all charged at the V_dc voltage.

This solution has the disadvantage of increasing the volume and cost of the generator.

For resistive loads, the voltage pulse decreases exponentially according to

where C_eq is the equivalent capacitance of the series connected capacitors C_j (3), (10), (13), (20), and R_eq is the equivalent resistance of the circuit in this mode of operation.

In cases where the pulse energy has the order of magnitude of the stored energy in the capacitors C_j (3), (10), (13), (20), the pulse no longer presents a near rectangular shape, and by the pulse end the voltage into the capacitors contributing to the the pulse Cj (3), (10), (13) decreases significantly, as shown in figure 11.

Figure 12 shows an innovative topology to make the correction of the negative and/or positive pulse voltage decay without increasing the capacitance of capacitors C_j (3) , (10) , (13) , (20) . Taking into account the modularity of the bipolar Marx generator circuit shown in Figure 1 and without losing this valuable characteristic, one or more modules (p modules) , which are identical to the Marx based modules, are added to correct the pulse voltage decay. Each of the p correction modules comprises four MOSFETs T_d(n+p) (24A) , T_e(n_+P> (26A) , T_f(n+p) (27A) , T_h(n₊p) (28A), two diodes D_c(n+p) (25) and D_g(n+p) (29) and capacitors C(n+ ) (30) and C_(n+i) (20) to correct the negative and positive pulses voltage decay respectively, being the latter capacitor (20) shared with module n. The p modules differ from Marx modules only in the process of driving the MOSFETs. The topology contains an output filter coil L_f (31) and capacitor C_f (32) to smooth the plateau of the output voltage.

The circuit of Figure 12 has essentially two modes of operation corresponding to the charge of the capacitors (3), (10), (13), (20) and (30) and to the application of high voltage pulse into the load. Said capacitors (3), (10) (13) (20) and (30) are charged using the ON state driven MOSFETs T_a (1A) , T_di (4A), (14A), (24A) and T_hi (8A) (18A), (28A) and diodes D_b (2) D_ci (5), (15), (25) and D_gi (9), (19), (29), as shown in figure 13.

The second mode of operation corresponds to the application of high voltage pulse in the load (12) . Thus, considering initially the positive pulse (without correction), MOSFETs T_di (4A), (14A), (24A) and T_fi (7A) , (17A) , (27A) (except T_fn (17A) ) are ON state driven and MOSFETs T_a (1A) , T_ei (6A), (16A) , (26A) and T_hi (8A) , (18A) , (28A) , are OFF state driven as shown in figure 14. When correction is not required, capacitor C_n+i (20) is by-passed by diode D_cn (15) .

To apply a negative pulse into the load (12), MOSFETs T_ei (6A) , (16A), (26A) (except Te (n+p) (26A) ) and T_hi (8A) , (18A) , (28A) are ON state driven and MOSFETs T_a (1A), T_di (4A) , (14A) , (24A) and T_fi (7a) , (17A) , (27A) are OFF state driven, as shown in figure 15. When the correction module is not operating, the capacitor C_(n+P) (30) is by-passed by diode D_g(n+P) (29) .

The driving signals for MOSFETs T_e(_n+p) (26A) and T_fn (17A) are obtained using a closed loop hysteretic control of the average voltage. The error value between the output voltage and the reference voltage is integrated (averaged) giving a triangular waveform which is compared with an hysteresis band of the comparator, which generates the driving signals to the MOSFETs (17A) and (26A) of the correction modules as in figure 16. The positive pulse with correction is implemented accordingly with Figure 14. When the output voltage starts to decrease from its initial value, the hysteresis voltage controller sets to drive ON the semiconductor MOSFETs T_fn (17A), thus reducing the error between the voltage output and the reference voltage by connecting in series the capacitor C_n+i (20) with the capacitors (3), (10) and (13) of the Marx generator, as can be seen in Figure 14, in the dashed line.

The negative pulse with correction is carried out accordingly to Figure 15. When the output voltage starts to be higher than its initial value, the hysteresis voltage controller reduces the error between the output voltage and the reference voltage by modulating the semiconductor T_e{n+P) (26A), which connects the capacitor C_(n+p) (30) in series with the capacitors (10), (13) and (20) of the Marx generator in accordance with figure 15, in the dashed line.

The correction generates a pulse width modulation voltage waveform, which is superimposed to the waveform of the uncorrected output voltage, requiring a filter with coil L_f (31) and capacitor C_f (32) to smooth the waveform output voltage. The absolut value of the total output voltage equals

approximately n times the voltage of each module, i.e., the constant voltage source, V_dC (11) . Description of the drawings

Figure 1 shows the electrical circuit concept of the modular high-voltage bipolar pulse generator, based on the Marx type generator, with n modules, using capacitors (3), (10), (13),

(20) and MOSFETs (1A) , (4A) , (6A), (7A) , (8A) , (14A), (16A), (17A), (18A), (24A), (26A) , (27A) , (28A) and diodes (IB), (4B), (6B), (7B), (8B), (14B), (16B) , (17B), (18B), (2), (5), (9), (15), (19), (24B) , (25), (26B) , (27B) , (28B) , (29), a constant voltage power supply (11), a power supply internal resistance

(21) and the load (12) . It also shows diodes (29), and capacitors (30) and (20), capacitor (32) and the filter coil L_f (31) .

Figure 2 shows the charging loop of capacitors (3), (10), (13), (20) from the constant voltage power supply (11) and MOSFETs (1A), (4A), (8A), (14A), (18A), and diodes (2), (5), (9), (15), (19), (IB), (4B) , (8B) and (18B), the load (12), and the power supply internal resistance (21) .

Figure 3 shows the positive pulse operating mode, connecting capacitors (3), (10), (13) in series with the load (12) through MOSFETs (4A), (7A) , (14A), (17A) and diodes (4B), (7B) , (14B), (17B) .

Figure 4 shows the negative pulse operating mode, connecting capacitors (10), (13), (20) in series with the load (12) through MOSFETs (6A), (8A) , (16A), (18A) and diodes (6B), (8B) , (16B), (18B). Figure 5 shows the discharging mode for the load capacitors (12) after the positive pulse, through MOSFETs (8A) , (18A), and diodes (9), (19), (8B) , (18B) .

Figure 6 shows the discharging mode for the load capacitors (12) after the negative pulse, through MOSFETs (14A) , (17A) and diodes (8B) , (6B), (14B), (17B).

Figure 7 shows the path to establish the zero average voltage mode into inductive type loads (12), after the positive pulse, applying a voltage of the same amplitude as the pulse but with symmetrical polarity, through the diodes (8B) , (6B), (18B), (16B) and capacitors (10), (13), (20).

Figure 8 shows the path to establish the zero average voltage mode into inductive type loads (12), after the positive pulse, with a voltage having the amplitude of a cell and symmetrical polarity, through the MOSFETs (14A), (17A) and diodes (8B) , (6B), (14B), (17B) and capacitor (10).

Figure 9 shows the path to establish the zero average voltage mode into inductive type loads (12) , after the negative pulse, with a voltage of the same amplitude as the pulse but with symmetrical polarity, through the diodes (4B) , (7B) , (14B), (17B) and capacitors (3), (10), (13).

Figure 10 shows the path to establish the zero average voltage mode into inductive type loads (12) , after the negative pulse, with a voltage having the amplitude of a cell and symmetrical polarity, through the MOSFET (18A) and diodes (4B), (7B) , (18B) , (19) and capacitor (3) . Figure 11 shows the circuit of figure 1, operating with 4 cells, with a voltage V_dc=100V and a resistive load of 15 Ω. The primary Y-axis, identified as v₀(V), refers to the output voltage, expressed in Volt; the secondary Y-axis, identified as i₀(A), refers to the output current, expressed in Ampere; the X-axis, identified as t(ps), refers to time, expressed in μ≤, for a scale of 5μ≤ per division. The curves (a) and (b) represent the load voltage (lOOV/div) and the load current (lOA/div) respectively, where it is shown that the pulses exhibit a voltage decay of about 150V with pulse widths of about 10 s.

Figure 12 shows the electrical circuit concept of the Marx type high voltage bipolar pulse generator, with unipolar/bipolar pulse voltage decay correction circuit, using n+p modules, and capacitors (3), (10), (13), (20), (30) and MOSFETs (1A) , (4A), (6A), (7A), (8A), (14A), (16A), (17A) , (18A) , (24A) , (26A) , (27A), (28A) and diodes (IB), (4B) , (6B), (7B), (8B), (14B), (16B), (17B), (18B), (24B) , (26B) , (27B) , (28B) , (2), (5), (9), (15), (19), (25), (29) one constant voltage power supply (11), power supply internal resistance (21) and filter with coil _f (31) and capacitor C_f (32) and load (12) .

Figure 13 shows the charging loop for the capacitors (3) , (10) ,

(13), (20), (30) through the constant voltage power supply (11), MOSFETs (1A), (4A), (8A), (14A), (18A), (24A) , (28A) , power supply internal resistance (21) and diodes (IB), (4B), (8B) ,

(14B), (18B), (24B), (28B) , (2), (5), (9), (15), (19), (25), (29), filter with coil L_f (31) and capacitor C_f (32) and load (12) . Figure 14 shows the positive pulse mode, without correction, connecting capacitors (3), (10), (13) in series with the load (12) through MOSFETs (4A) , (7A) , (14A) , (24A) , (27A) and diode (15) . The positive pulse with correction is generated by driving ON the MOSFET T_fn (17A) in order to reduce the error between the output voltage and the reference voltage, connecting in series capacitor C_n+i (20) with capacitors (3), (10), (13), in the dashed line, and filter with coil L_f (31) and capacitor C_f (32) .

Figure 15 shows the negative pulse mode, without correction, connecting capacitors (10), (13), (20) in series with the load (12) through MOSFETs (6A), (8A), (16A), (18A), (28A) and diode (29) . The negative pulse with correction is generated by driving ON the MOSFET T_e(_n+P) (26A) in order to reduce the error between the output voltage and the reference voltage, connecting in series capacitor C_n+P (30) with capacitors (10), (13), (20), in the dashed line, and filter with coil L_f (31) and capacitor C_f (32) .

Figure 16 shows the diagram of the hysteretic voltage control system. The error value between the output voltage and the reference voltage is integrated (average value) resulting in a triangular wave that is compared with a hysteretic window in the comparator, which generates the driving signals for the MOSFETs T_fn (17A) and T_e(n+P) (26A) .

Figure 17 shows the discharging mode of the load (12) capacitors after the negative pulse through MOSFETs T_di (4A) , (14A) , diodes D_ei (5), (15) and capacitors (3) and (20). References

[1] M. P. J Gaudreau, T. Hawkey, J. Petry and M. Kempkes, "Pulsed Power systems for Food and Wastewater processing", in Twenty Third International Power Modulator Symposium, Rancho Mirage, CA June 1998.

[2] S. Y. Tseng, T. F . Wu, S. S. Chen and M. W. Wu, "A Combined Wide and Narrow Pulse Generator for Food Processing Microbes", in 36th IEEE Annual Power Electronics Specialists Conference, pp. 375 - 381, June 2005. [3] C. Wang, Q. H. Zhang and C. Streaker, "A 12 kV solid state high voltage pulse generator for a bench top PEF machine", in IEEE Power Electronics and Motion Control Conference, 15-18 August, Beijing, China, 2000, vol. 3, pp. 1347-1352.

[4] S. V. G. Vardigans and D. de Cogan, "A Bipolar Pulse Tester for Semiconductor Devices", in J. Phys. E: Sci. Instrum. , Vol. 19, pp. 1016-1019, 1986.

[5] J. H. Kim, I. W. Jeong, H. J. Ryoo, S. S. Kim and G. H. Rim, "Semiconductor switch based fast high voltage pulse generators", in 14^th Pulsed Power Conference, 15-18 June, 2003, vol. 1, pp. 665-668.

[6] J. H. Kim, S. C. Lee, B. K. Lee and S. V. Shenderey, "A high voltage bi-polar pulse generator using push-pull inverter", in IEE Industrial Electronics Society Conference, 2-6 November, Virginia US, 2003, vol. 1, pp. 102-106. [7] M. Petkovsek, P. Zajec, J. Nastran and D. Voncina, "Multilevel bipolar high voltage pulse source - Interlock dead time reduction", in EUROCON-Computer as a Tool, 2003, 22-24 September Slovenia, vol. 2, pp. 240-243.

[8] L. M. Redondo, H. Canacsinh and J. Fernando Silva, "Generalized Solid-State Marx Modulator Topology", in IEEE Transactions on Dielectrics and Electrical Insulation, Vol. 1 No. 4, pp. 1037-1042.

Claims

1. Modular generator for bipolar or unipolar pulses with correction of voltage decay integrated in power semicondutors modules, being the rectangular bipolar pulses with positive and negative voltage or unipolar pulses with positive voltage or negative voltage, at high frequency and high amplitude, using n+p equal modules, where n and p are greater than or equal to one, based on MOSFETs (4A) , (6A), (7A) , (8A) and diodes (4B) , (5), (6B) , (7B), (8B) and (9), characterized in that it contains p modules, each with MOSFETs (24A) , (26A) , (27A) , (28A) and diodes (24B) , (25), (26B) , (27B) , (28B) , (29), associated with coil L_f (31) and a capacitor C_f (32) making the correction of the voltage decay of the bipolar or unipolar pulses.

2. Process for the correction of the voltage decay integrated in modules of power semiconductors for the modular generator of bipolar pulses, as defined in claim 1, characterized in that it switches on and off the MOSFET (26A) , during the negative pulse, and switches on and off the MOSFET (17A) , during the positive pulse, obtaining a maximum module output voltage equal to n times the constant voltage power supply, V_dc (11) .

3. Process for the correction of the voltage decay integrated in modules of power semiconductors, according to the previous claim, characterized in that it generates negative pulses using MOSFETs (6A), (8A) , (16A) , (18A), (28A) ON state driven, and conducting non controlled power semiconductor (29), and capacitors (10), (13) and (20), being the correction of the voltage decay in the negative voltage pulses made by high frequency switching of MOSFETs (26A) of the p modules and capacitors (30), correcting to zero the average value of the error between the voltage plateau and the pulse voltage.

4. Process for the correction of the voltage decay integrated in modules of power semiconductors, according to the previous claims, characterized in that it generates positive pulses using MOSFETs (4A), (7A) , (14A), (24A) , (27A) ON state driven, and conducting non controlled power semiconductor (15), ON state driven and capacitors (3), (10) and (13), being the correction of the voltage decay in the positive voltage pulses made by high frequency switching of MOSFETs (17A) of the p modules and capacitors (20), correcting to zero the average value of the error between the voltage plateau and the pulse voltage.

5. Process for the correction of the voltage decay integrated in power semicondutors modules, according to the previous claims, characterized in that, after the positive pulse voltage, it supplies the coil L_f (31), and capacitor C_f (32) and inductive loads with a negative voltage with amplitude equalling the sum of the capacitor (10), (13), (20) and (30) voltages, using diodes (6B), (8B) , (16B) , (18B), (26B) and (28B) , and capacitors (10), (13), (20) and (30), or alternatively supplies a negative voltage with amplitude equal- to the capacitor (10) voltage, using ON state driven MOSFETs (14A), (24A) and (27A) and diodes (6B), (8B) and capacitor (10).

6. Process for the correction of the voltage decay integrated in power semicondutors modules, according to claims 3 to 5, characterized in that, after the negative pulse voltage, it supplies the filter with coil L_f (31) , capacitor C_f (32) and inductive loads with a positive voltage with amplitude equal to the sum of the capacitor (3), (10), (13) and (20) voltages, using diodes (4B), (7B) , (14B), (17B) , (24B) and (27B) , and capacitors (3), (10), (13) and (20), or alternatively supplies a positive voltage with amplitude equal to the capacitor (3) voltage, using ON state driven MOSFETs (18A) , (28A) and diodes ((19), (29), (4B) and (7B) and capacitor (3).