WO2014192762A1

WO2014192762A1 - Display device

Info

Publication number: WO2014192762A1
Application number: PCT/JP2014/064008
Authority: WO
Inventors: 繁田　光浩
Original assignee: 堺ディスプレイプロダクト株式会社
Priority date: 2013-05-29
Filing date: 2014-05-27
Publication date: 2014-12-04

Abstract

Provided is a display device capable of maintaining substantially constant the voltage waveforms of the control voltage and the signal voltage supplied via a scanning line and a signal line. This display device is provided with multiple display elements, signal lines for supplying signal voltages to be applied to said display elements, switching elements provided corresponding to the display elements and for controlling conduction or non-conduction between the display elements and the signal lines by being opened and closed, and a scanning line for supplying a control voltage for controlling the opening and closing of the switching elements, wherein the display device is also provided with one or multiple auxiliary scanning lines electrostatically coupled to the scanning line, and a means for applying to said one or multiple auxiliary scanning lines a voltage of the opposite polarity of the control voltage.

Description

Display device

The present invention relates to a display device capable of keeping a voltage waveform of a control voltage and a signal voltage supplied via a scanning line and a signal line substantially constant.

Liquid crystal display devices are widely used for computer displays, television receivers, information displays for displaying various information, and the like. For example, in an active matrix liquid crystal display device, a thin film transistor (TFT) provided for each pixel functions as a switching element, and a signal voltage (grayscale voltage) is applied to the pixel electrode during a period in which the switching element is on. Thus, the light transmittance of each pixel is controlled, and there is no crosstalk between pixels, and high-definition and multi-gradation display is possible.

Generally, a liquid crystal display device is composed of two transparent substrates made of a thin glass plate and a liquid crystal sealed between these substrates. On one substrate (TFT substrate), a pixel electrode and a TFT are formed for each pixel, and on the other substrate (CF substrate), a color filter facing the pixel electrode, a common electrode (counter electrode) common to each pixel, and Is formed.

A plurality of gate wirings extending in the horizontal direction and a plurality of source wirings extending in the vertical direction are formed on the TFT substrate. Each rectangular area defined by the gate wiring and the source wiring is a pixel area. In each pixel region, a TFT as a switching element and a pixel electrode are formed. In addition, the liquid crystal display device includes a gate driver connected to the gate wiring and a source driver connected to the source wiring in order to control image display in each pixel.

The source driver outputs display data to each source wiring at a timing synchronized with the data clock signal within one horizontal synchronization period. On the other hand, the gate driver sequentially outputs scanning signals to the gate wiring at a timing synchronized with the gate clock signal within one vertical synchronization period. The TFT of the pixel connected to the gate wiring supplied with the scanning signal is turned on, and the display data supplied to the source wiring is written to the pixel electrode. Thereby, the direction of the liquid crystal molecules in the pixel changes, and the light transmittance of the pixel changes accordingly. Display data is written to each pixel within one vertical synchronization period, and a desired image is displayed on the liquid crystal display device.

Japanese Patent Laid-Open No. 9-16128

In recent years, there has been a demand for larger liquid crystal display devices. However, when the liquid crystal display device is increased in size, the lengths of the gate wiring and the source wiring formed on the TFT substrate are increased, and the wiring resistance and the like are increased. For this reason, a relatively large voltage drop occurs in the gate wiring and the source wiring. For example, the same display data is given to a pixel connected near the source driver and a pixel far from the source driver. Regardless, there may be differences in color and brightness. In extreme cases, a predetermined voltage cannot be supplied by a signal output from a gate driver or a source driver, and the display quality of an image may be remarkably deteriorated.

The present invention has been made in view of such circumstances, and even in a liquid crystal display device having a large number of pixels, each pixel is driven without causing distortion of a signal waveform or a decrease in signal intensity. An object of the present invention is to provide a display device that can reliably supply signals necessary for the above.

The display device of the present application is provided corresponding to each of a plurality of display elements, a signal line for supplying a signal voltage to be applied to the display element, and the display element, and is opened and closed between the display element and the signal line. One or more auxiliary devices electrostatically coupled to the scanning line in a display device comprising a switching element that controls conduction / non-conduction of the scanning line and a scanning line that supplies a control voltage for controlling opening and closing of the switching element A scanning line and means for applying a voltage having a polarity opposite to that of the control voltage to the one or more auxiliary scanning lines are provided.

The display device of the present application has a first wiring layer that constitutes the scanning line and a second wiring layer that constitutes the auxiliary scanning line, and an insulating layer is provided between the first and second wiring layers. It is characterized by that.

The display device of the present application is provided corresponding to each of a plurality of display elements, a signal line for supplying a signal voltage to be applied to the display element, and the display element, and is opened and closed between the display element and the signal line. One or a plurality of auxiliary devices electrostatically coupled to the signal line in a display device including a switching element that controls conduction / non-conduction of the scanning line and a scanning line that supplies a control voltage for controlling opening and closing of the switching element A signal line and means for applying a voltage having a polarity opposite to that of the signal voltage to the one or more auxiliary signal lines are provided.

The display device of the present application has a first wiring layer that constitutes the signal line and a second wiring layer that constitutes the auxiliary signal line, and an insulating layer is provided between the first and second wiring layers. It is characterized by that.

In the present application, the control voltage is supplied to the switching element included in each pixel through the scanning line, and a voltage having a polarity opposite to the control voltage is applied to the auxiliary scanning line electrostatically coupled to the scanning line. Charge flows from the scanning line to the scanning line, and the voltage waveform of the control voltage in the scanning line is maintained.

In the present application, the signal voltage to be applied to the display element through the signal line is supplied, and the auxiliary signal line electrostatically coupled to the signal line is configured to apply a voltage having a polarity opposite to that of the signal voltage. Charge flows from the auxiliary signal line into the signal line, and the voltage waveform of the signal voltage in the signal line is maintained.

According to the present application, even in a liquid crystal display device having a large number of pixels, a signal necessary for driving each pixel is reliably supplied without causing distortion of the signal waveform or a decrease in signal strength. Can do.

It is a figure which shows schematic structure of the display apparatus which concerns on this Embodiment. It is a schematic diagram which shows the structure of each pixel in a liquid crystal display panel. It is a schematic diagram which shows the equivalent circuit of each pixel. It is sectional drawing which shows the structural example of a liquid crystal display panel roughly. It is sectional drawing which shows the other structural example of a liquid crystal display panel roughly. It is a wave form diagram which shows the voltage waveform of the control voltage used with the conventional liquid crystal display panel. 4 is a waveform diagram showing a voltage waveform of a control voltage used in the liquid crystal display panel of Embodiment 1. FIG. It is a wave form diagram which shows the modification of the voltage waveform of a control voltage. 6 is a schematic diagram illustrating a configuration of each pixel in a liquid crystal display panel according to Embodiment 2. FIG. It is a schematic diagram which shows the equivalent circuit of each pixel. 6 is a waveform diagram showing a voltage waveform of a signal voltage used in the liquid crystal display panel of Embodiment 2. FIG. 6 is a schematic diagram illustrating a configuration of each pixel in a liquid crystal display panel according to Embodiment 3. FIG. It is a schematic diagram which shows the equivalent circuit of each pixel. 6 is a waveform diagram showing a voltage waveform of a control voltage used in the liquid crystal display panel of Embodiment 3. FIG.

The present invention will be specifically described with reference to the drawings showing the embodiments thereof.
Embodiment 1 FIG.
FIG. 1 is a diagram showing a schematic configuration of a display device according to the present embodiment. The display device according to the present embodiment is, for example, a liquid crystal display device including a liquid crystal display panel 1, a gate driver 2, a source driver 3, a power supply circuit 4, an image memory 5, a control circuit 6, and the like.

The liquid crystal display panel 1 includes a plurality of

pixels

10, 10, 10,... Configured by a display element 11 and a switching element 12 (see FIG. 2). These

pixels

10, 10, 10,... Are arranged in a matrix (for example, 1024 in the row direction and 768 in the column direction) in the liquid crystal display panel 1.

Each pixel 10 of the liquid crystal display panel 1 includes a liquid crystal layer 120 sealed between the pixel electrode 111 and the counter electrode 131 (see FIG. 4). In this embodiment mode, the voltage applied to the liquid crystal layer 120 is controlled by grounding the counter electrode 131 and controlling the voltage applied to the pixel electrode 111. At this time, the control circuit 6 controls the operation of the display element 11 and the switching element 12 of each pixel 10 through the gate driver 2 and the source driver 3, thereby applying a voltage (application to the liquid crystal layer 120) to the pixel electrode 111. Voltage). By controlling the voltage applied to the pixel electrode 111, the light transmittance of the liquid crystal layer 120 in each pixel 10 is adjusted, and the display luminance of each pixel 10 is determined.

The control circuit 6 controls a voltage applied to the liquid crystal layer 120 in each pixel 10 based on a synchronization signal input from the outside, a memory control signal, a power supply control signal, a source driver control signal, and a gate driver control signal. And the generated control signals are output to the image memory 5, the power supply circuit 4, the source driver 3, and the gate driver 2, respectively.

The image memory 5 temporarily stores input display data, and outputs pixel data to be displayed on the liquid crystal display panel 1 to the source driver 3 in synchronization with a memory control signal input from the control circuit 6. The image memory 5 may be built in the control circuit 6 and output image data to the source driver 3 through internal processing of the control circuit 6.

Here, the synchronization signal and display data that are input include the LCD signal output from the CPU or LCD control IC mounted on the mobile phone, portable game machine, etc., and the CRT output signal of the personal computer (PC) as A / D. The converted signal and the signal obtained by the control circuit 6 directly controlling the video RAM mounted on the PC or the like are included.

The power supply circuit 4 generates a drive voltage for the gate driver 2 and a drive voltage for the source driver 3 in synchronization with the power supply control signal input from the control circuit 6, and outputs them to the gate driver 2 and the source driver 3, respectively. To do.

The gate driver 2 sequentially outputs a control voltage Vg for controlling on / off of the switching element 12 in synchronization with the gate driver control signal input from the control circuit 6 and applies it to the gate main wiring 20 which is a scanning line. In the first embodiment, the gate driver 2 sequentially outputs a voltage −Vg having a polarity opposite to the control voltage applied to the gate main wiring 20 in synchronization with the gate driver control signal input from the control circuit 6. Then, it is applied to the gate sub-wiring 21 which is a sub-scanning line.

The source driver 3 takes in the pixel data output from the image memory 5 in synchronization with the source driver control signal input from the control circuit 6, and sequentially outputs the signal voltage Vs corresponding to the pixel data. The signal voltage Vs output from the source driver 3 is displayed on the display element of each pixel 10 via the source line (source main line) 30 that is a signal line of the liquid crystal display panel 1 when the corresponding switching element 12 is on. 11 (pixel electrode 111).

FIG. 2 is a schematic diagram showing the configuration of each pixel 10 in the liquid crystal display panel 1. As described above, the liquid crystal display panel 1 includes a plurality of

pixels

10, 10, 10,... Arranged in a matrix. In FIG. 2, for simplification, a part of the

pixels

10, 10, 10,... Constituting one row is shown.

The control voltage Vg from the gate driver 2 is sequentially supplied to the

pixels

10, 10, 10,... Constituting one row through the gate main wiring 20 formed corresponding to each row. While the control voltage Vg from the gate driver 2 is applied to the switching element 12, the switching element 12 is turned on, and the corresponding display element 11 is conducted to the source line 30. At this time, by supplying the signal voltage Vs output from the source driver 3 to the display element 11 via the source line 30, the desired signal voltage Vs can be applied to the display element 11 (pixel electrode 111). it can.

In the first embodiment, a gate sub-wiring 21 electrostatically coupled to the gate main wiring 20 is provided, and a voltage −Vg having a polarity opposite to the control voltage Vg supplied by the gate main wiring 20 is applied to the gate sub-wiring 21. That is, the gate main wiring 20 and the gate sub wiring 21 are configured to form a balanced wiring.

FIG. 3 is a schematic diagram showing an equivalent circuit of each pixel 10. In each pixel 10, the switching element 12 can be represented by, for example, a TFT 12a (see FIG. 10), and the display element 11 can be represented as a liquid crystal capacitor 11a between the pixel electrode 111 and the counter electrode 131.

The gate terminal of the TFT 12 a is connected to the gate main wiring 20, and the source terminal of the TFT 12 a is connected to the source wiring 30. The drain terminal of the TFT 12a is connected to one end side (pixel electrode 111) of the liquid crystal capacitor 11a. In the present embodiment, the other end side (counter electrode 131) of the liquid crystal capacitor 11a is grounded.

The TFT 12a is ON / OFF controlled by applying a control voltage Vg supplied line-sequentially from the gate driver 2 through the gate main wiring 20. During the on period of the TFT 12a, the signal voltage Vs supplied from the source driver 3 through each source line 30 is applied to the liquid crystal capacitor 11a. By controlling the magnitude of the signal voltage Vs, the light transmittance of the liquid crystal layer 120 in each pixel 10 (display luminance of each pixel 10) can be controlled.

In FIG. 3, electrostatic coupling between the gate main wiring 20 and the gate sub-wiring 21 is shown by capacitive coupling. A voltage −Vg having a polarity opposite to the control voltage Vg supplied by the gate main wiring 20 is applied to the gate sub wiring 21, whereby charges are supplied to the gate main wiring 20 from the gate sub wiring 21 through the capacitor 25. The potential (voltage waveform) of the gate main wiring 20 can be maintained.
In FIG. 3, the electrostatic coupling between the gate main wiring 20 and the gate sub-wiring 21 is shown by capacitive coupling, but may be coupled by capacitance and resistance.

FIG. 4 is a cross-sectional view schematically showing a configuration example of the liquid crystal display panel 1. The liquid crystal display panel 1 includes a TFT substrate 110 in which each pixel 10 is formed in a matrix, a liquid crystal layer 120 formed by enclosing a liquid crystal substance, and a CF substrate 130 on which a color filter and the like are formed. The TFT substrate 110 and the CF substrate 130 are, for example, glass substrates, and pixel electrodes 111 corresponding to the respective pixels 10 are formed on one surface side of the TFT substrate 110. Further, a counter electrode 131 is formed on one surface side of the CF substrate 130 facing the pixel electrode 111.

On the other surface side of the TFT substrate 110, a protective film 112, a source wiring layer 113, a semiconductor layer 114, and an insulating layer 115 are laminated. In addition, the gate main wiring layer 116 constituting the gate main wiring 20 and the gate sub wiring layer 117 constituting the gate sub wiring 21 are formed inside the insulating layer 115. In the configuration example shown in FIG. 4, the gate main wiring layer 116 and the gate sub wiring layer 117 are formed in a state of being physically separated in the stacking direction, and an insulating layer 115 is provided between them. With such a configuration, the gate main wiring 20 and the gate sub-wiring 21 are electrostatically coupled to each other, and charge is transferred through the insulating layer 115.

FIG. 5 is a cross-sectional view schematically showing another configuration example of the liquid crystal display panel 1. The configuration example shown in FIG. 5 is different from the configuration example shown in FIG. 4 in that the gate main wiring layer 116 and the gate sub wiring layer 117 are juxtaposed in the in-plane direction inside the insulating layer 115. The gate main wiring layer 116 and the gate sub wiring layer 117 are formed in a state of being physically separated in the in-plane direction, and an insulating layer 115 is provided therebetween. With such a configuration, the gate main wiring 20 and the gate sub-wiring 21 are electrostatically coupled to each other, and charge is transferred through the insulating layer 115.

In the configuration example shown in FIG. 5, the gate main wiring layer 116 and the gate sub wiring layer 117 can be formed in the same process. Further, there is a concern that the aperture ratio may be reduced by juxtaposing the gate main wiring layer 116 and the gate sub-wiring layer 117. However, in the balanced wiring, the wiring can be thinned, so that the reduction in the aperture ratio is suppressed. Can do.

Hereinafter, the voltage waveform of the control voltage supplied through the gate main wiring 20 and the gate sub-wiring 21 will be described.

FIG. 6 is a waveform diagram showing a voltage waveform of a control voltage used in a conventional liquid crystal display panel. The voltage waveform of the control voltage output from the gate driver is, for example, a rectangular wave as shown in FIG. A signal having a voltage waveform substantially the same as the voltage waveform shown in FIG. 6A is input to the display element at a position where the transmission distance of the signal from the gate driver is short.

However, the signal having the voltage waveform is affected by circuit resistance, stray capacitance, etc. while being transmitted through the gate wiring. The longer the signal transmission distance, the greater the influence of circuit resistance, stray capacitance, etc., so the display element located at a position away from the gate driver has a distorted waveform as shown in FIG. A control voltage with a reduced signal strength is applied. For this reason, even when a control voltage having a constant voltage waveform is output from the gate driver, it is applied between the display element located near the gate driver and the display element located away from the gate driver. There is a clear difference in the magnitude of the control voltage.

FIG. 7 is a waveform diagram showing voltage waveforms of control voltages used in the liquid crystal display panel 1 of the first embodiment. The liquid crystal display panel 1 according to Embodiment 1 includes a gate main wiring 20 and a gate sub-wiring 21 that are electrostatically coupled for each row, and the gate main wiring 20 has a control voltage for controlling on / off of the switching element 12. One characteristic is that Vg is applied and a voltage −Vg having a polarity opposite to that of the control voltage Vg is applied to the gate sub-wiring 21.

When the voltage waveform of the control voltage supplied to the gate main wiring 20 by the gate driver 2 is a rectangular wave as shown in the lower part of FIG. 7A, the gate sub-wiring 21 includes, for example, the upper part of FIG. As shown in FIG. 6, a voltage waveform obtained by inverting the positive / negative of the voltage waveform of the control voltage supplied to the gate main wiring 20 is applied.

When control voltages having these voltage waveforms are applied to the gate main wiring 20 and the gate sub wiring 21, respectively, charges from the gate sub wiring 21 flow into the gate main wiring 20 through electrostatic coupling, and the respective voltages. The effect of maintaining the waveform is obtained. As a result, as shown in FIG. 7B, the distortion of the voltage waveform in the gate main wiring 20 and the gate sub-wiring 21 is small even at a location separated from the gate driver 2, and a decrease in signal strength is also suppressed.

FIG. 8 is a waveform diagram showing a modification of the voltage waveform of the control voltage. In the example shown in FIG. 7, the voltage waveform obtained by inverting the positive / negative voltage waveform of the control voltage supplied to the gate main wiring 20 is applied to the gate sub-wiring 21. However, when a voltage having a polarity opposite to the control voltage supplied to the gate main wiring 20 is applied to the gate sub-wiring 21, charges from the gate sub-wiring 21 flow into the gate main wiring 20 through electrostatic coupling. The effect is obtained. For this reason, it is not necessary to completely invert the voltage waveform including the phase and amplitude intensity. For example, a control voltage having a rectangular wave voltage waveform shown in the lower part of FIG. 8A is applied to the gate main wiring 20, and the phase and the signal amplitude are slightly different as shown in the upper part of FIG. 8A. A configuration in which a waveform control voltage is applied to the gate sub-wiring 21 may be adopted.

When a control voltage having a reverse polarity is applied to the gate main wiring 20 and the gate sub-wiring 21 that are electrostatically coupled to each other, charges from the gate sub-wiring 21 flow into the gate main wiring 20 via the electrostatic coupling, The effect of maintaining each voltage waveform is obtained. As a result, even at a location separated from the gate driver 2, as shown in FIG. 8B, the distortion of the voltage waveform in the gate main wiring 20 and the gate sub wiring 21 is small, and the decrease in signal strength is also suppressed.

As described above, in the first embodiment, even when a large number of

pixels

10, 10, 10,... Are arranged in the row direction, these

pixels

10, 10, 10,. It can be controlled by a control voltage. For this reason, even if the wiring resistance is high, the potential change can be reduced, and the wiring can be made thinner or thinner.

Embodiment 2. FIG.
In the first embodiment, a gate sub-wiring 21 electrostatically coupled to the gate main wiring 20 is provided, and a voltage −Vg having a polarity opposite to the control voltage Vg supplied from the gate main wiring 20 is applied to the gate sub-wiring 21. However, a configuration may be adopted in which a wiring electrostatically coupled to the source main wiring 30 is provided and a voltage −Vs having a polarity opposite to the signal voltage Vs supplied from the source main wiring 30 is applied to the wiring.
In the second embodiment, an application example to the source main wiring 30 will be described. Note that the configuration of the drive system in the liquid crystal display device is the same as that in Embodiment 1, and thus the description thereof is omitted.

FIG. 9 is a schematic diagram showing the configuration of each pixel 10 in the liquid crystal display panel 1 of the second embodiment. The liquid crystal display panel 1 includes a plurality of

pixels

10, 10, 10,... Arranged in a matrix. In FIG. 9, for simplification, a part of the

pixels

10, 10, 10,... Constituting one column is shown.

The signal voltage Vs from the source driver 3 is sequentially supplied to the

pixels

10, 10, 10,... Constituting one column through the source main wiring 30 formed corresponding to each column. While the control voltage Vg from the gate driver 2 is applied to the switching element 12, the switching element 12 is turned on, and the corresponding display element 11 is conducted to the source main wiring 30. At this time, by applying the signal voltage Vs output from the source driver 3 to the display element 11 via the source main wiring 30, the desired signal voltage Vs is applied to the display element 11 (pixel electrode 111). Can do.

In the second embodiment, a source sub-wiring 31 electrostatically coupled to the source main wiring 30 is provided, and a voltage −Vs having a polarity opposite to the signal voltage Vs supplied by the source main wiring 30 is applied to the source sub-wiring 31. That is, the source main wiring 30 and the source sub-wiring 31 are configured to form a balanced wiring.

FIG. 10 is a schematic diagram showing an equivalent circuit of each pixel 10. In each pixel 10, the switching element 12 can be represented by, for example, a TFT 12a, and the display element 11 can be represented as a liquid crystal capacitor 11a between the pixel electrode 111 and the counter electrode 131.

The gate terminal of the TFT 12 a is connected to the gate main wiring 20, and the source terminal of the TFT 12 a is connected to the source main wiring 30. The drain terminal of the TFT 12a is connected to one end side (pixel electrode 111) of the liquid crystal capacitor 11a. In the present embodiment, the other end side (counter electrode 131) of the liquid crystal capacitor 11a is grounded.

The TFT 12a is ON / OFF controlled by applying a control voltage Vg supplied line-sequentially from the gate driver 2 through the gate main wiring 20. During the ON period of the TFT 12a, the signal voltage Vs supplied from the source driver 3 through each source main wiring 30 is applied to the liquid crystal capacitor 11a. By controlling the magnitude of the signal voltage Vs, the light transmittance of the liquid crystal layer 120 in each pixel 10 (display luminance of each pixel 10) can be controlled.

In FIG. 10, electrostatic coupling between the source main wiring 30 and the source sub-wiring 31 is shown by capacitive coupling. By applying a voltage −Vs having a polarity opposite to that of the signal voltage Vs supplied from the source main wiring 30 to the source sub wiring 31, electric charges are supplied to the source main wiring 30 from the source sub wiring 31 through the capacitor 35. The potential (voltage waveform) of the source main wiring 30 can be maintained.
In FIG. 10, the electrostatic coupling between the source main wiring 30 and the source sub-wiring 31 is shown by capacitive coupling, but may be coupled by capacitance and resistance.

FIG. 11 is a waveform diagram showing voltage waveforms of signal voltages used in the liquid crystal display panel 1 of the second embodiment. The liquid crystal display panel 1 according to Embodiment 2 includes a source main line 30 and a source sub-line 31 that are electrostatically coupled to each column, and a signal voltage Vs supplied to the display element 11 is applied to the source main line 30. One feature is that a voltage −Vs having a polarity opposite to that of the signal voltage Vs is applied to the source sub-wiring 31.

When the voltage waveform of the signal voltage supplied to the source main wiring 30 by the source driver 3 is a rectangular wave as shown in the lower part of FIG. 11A, the source sub-wiring 31 includes, for example, the upper part of FIG. As shown, a voltage waveform obtained by inverting the positive / negative of the voltage waveform of the signal voltage supplied to the source main wiring 30 is applied.

When signal voltages having these voltage waveforms are respectively applied to the source main wiring 30 and the source sub-wiring 31, charges from the source sub-wiring 31 flow into the source main wiring 30 through electrostatic coupling, and the respective voltages The effect of maintaining the waveform is obtained. As a result, even at a location separated from the source driver 3, as shown in FIG. 11B, the distortion of the voltage waveform in the source main wiring 30 and the source sub wiring 31 is small, and the decrease in signal strength is also suppressed.

As described above, in the second embodiment, even when a large number of

pixels

10, 10, 10,... Are arranged in the column direction, substantially the same voltage waveform is applied to these

pixels

10, 10, 10,. A signal voltage can be provided. Therefore, the potential of the pixel electrode 111 corresponding to each pixel 10 can be made substantially constant, and variations in display luminance between pixels can be suppressed. Further, even when the wiring resistance is high, the potential change can be reduced, so that the wiring can be made thinner or thinner.

In the second embodiment, the signal voltage obtained by inverting the positive / negative of the voltage waveform of the signal voltage supplied to the source main wiring 30 is applied to the source sub wiring 31. However, by applying a voltage having a polarity opposite to that of the signal voltage supplied to the source main wiring 30 to the source sub wiring 31, charges from the source sub wiring 31 flow into the source main wiring 30 through electrostatic coupling. The effect is obtained. For this reason, it is not necessary to completely invert the voltage waveform including the phase and amplitude intensity. For example, a signal voltage having a rectangular wave voltage waveform shown in the lower part of FIG. 11A is applied to the source main wiring 30, and a signal voltage having a slightly different phase and signal amplitude and a reverse polarity is applied to the gate sub-wiring 21. It is good also as a structure to apply.

Embodiment 3 FIG.
In the first embodiment, a gate sub-wiring 21 electrostatically coupled to the gate main wiring 20 is provided, and a voltage −Vg having a polarity opposite to the control voltage Vg supplied from the gate main wiring 20 is applied to the gate sub-wiring 21. However, a configuration in which a plurality of gate subwirings are provided may be employed.
In Embodiment 3, a configuration in which a plurality of gate sub-wirings are provided will be described. Note that the configuration of the drive system in the liquid crystal display device is the same as that in Embodiment 1, and thus the description thereof is omitted.

FIG. 12 is a schematic diagram showing the configuration of each pixel 10 in the liquid crystal display panel 1 of the third embodiment. As described above, the liquid crystal display panel 1 includes a plurality of

pixels

10, 10, 10,... Constituting one row is shown.

The control voltage Vg from the gate driver 2 is sequentially supplied to the

pixels

The third embodiment includes two gate sub-wirings 21 (first gate sub-wiring 21a and second gate sub-wiring 21b) that are electrostatically coupled to the gate main wiring 20, and the control voltage supplied by the gate main wiring 20 A voltage −Vg having a polarity opposite to that of Vg is applied to the first gate sub-wiring 21a and the second gate sub-wiring 21b, respectively. That is, the gate main wiring 20, the first gate sub-wiring 21a, and the second gate sub-wiring 21b are configured to form a balanced wiring.

FIG. 13 is a schematic diagram showing an equivalent circuit of each pixel 10. In each pixel 10, the switching element 12 can be represented by, for example, a TFT 12a, and the display element 11 can be represented as a liquid crystal capacitor 11a between the pixel electrode 111 and the counter electrode 131.

In FIG. 13, electrostatic coupling between the gate main wiring 20 and the first gate sub-wiring 21a and electrostatic coupling between the gate main wiring 20 and the second gate sub-wiring 21b are shown by capacitive coupling. A voltage −Vg having a polarity opposite to the control voltage Vg supplied from the gate main wiring 20 is applied to the first and second gate sub-wirings 21 a and 21 b, respectively, so that the

capacitors

25 a and 25 b are connected to the gate main wiring 20. Thus, charges from the first and

second gate sub-wirings

21a and 21b flow in, and the potential (voltage waveform) of the gate main wiring 20 can be held.
In FIG. 13, the electrostatic coupling between the gate main wiring 20 and the first and

second gate subwirings

21a and 21b is shown by capacitive coupling, but may be coupled by capacitance and resistance.

FIG. 14 is a waveform diagram showing a voltage waveform of a control voltage used in the liquid crystal display panel 1 of the third embodiment. The liquid crystal display panel 1 according to Embodiment 3 includes a gate main wiring 20 and first and

second gate sub-wirings

21a and 21b that are electrostatically coupled to each row, and the switching element 12 is turned on / off in the gate main wiring 20. One of the features is that a control voltage Vg for off control is applied, and a voltage −Vg having a polarity opposite to that of the control voltage Vg is applied to the first and

second gate sub-wirings

21a and 21b.

When the voltage waveform of the control voltage supplied to the gate main wiring 20 by the gate driver 2 is a rectangular wave as shown in the lower part of FIG. 14A, the first and

second gate sub-wirings

21a and 21b include, for example, As shown in the upper part and interruption of FIG. 14A, a voltage waveform obtained by inverting the positive / negative of the voltage waveform of the control voltage supplied to the gate main wiring 20 is applied.

When control voltages having these voltage waveforms are respectively applied to the gate main wiring 20 and the first and

second gate subwirings

21a and 21b, the gate main wiring 20 is connected to the first and second gates via electrostatic coupling. Charges from the sub-wirings 21a and 21b flow in, and the operation of maintaining the respective voltage waveforms is obtained. As a result, even at a location separated from the gate driver 2, as shown in FIG. 14B, the distortion of the voltage waveform in the gate main wiring 20 and the first and second

gate sub wirings

21a and 21b is small, and the signal strength is reduced. The decrease is also suppressed.

In the third embodiment, the control voltage obtained by inverting the positive / negative of the voltage waveform of the control voltage supplied to the gate main wiring 20 is applied to the first and

second gate sub-wirings

21a and 21b. However, by applying a voltage having a polarity opposite to the control voltage supplied to the gate main wiring 20 to the first and

second gate sub-wirings

21a and 21b, the gate main wiring 20 is connected to the first via the electrostatic coupling. In addition, an effect that charges flow from the second source sub-wirings 31a and 31b is obtained. For this reason, it is not necessary to completely invert the voltage waveform including the phase and amplitude intensity. For example, a control voltage having a rectangular wave voltage waveform shown in the lower part of FIG. 14A is applied to the gate main wiring 20, and the signal voltages having slightly different phases and signal amplitudes and having opposite polarities are applied to the first and second signal voltages. It may be configured to be applied to the gate sub-wirings 21a and 21b.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. In addition, the technical features described in each embodiment can be combined with each other.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 2 Gate driver 3 Source driver 4 Power supply circuit 5 Image memory 6 Control circuit 10 Pixel 11 Display element 12 Switching element 20 Gate main wiring 21 Gate sub wiring 30 Source main wiring 31 Source sub wiring

Claims

A plurality of display elements, a signal line for supplying a signal voltage to be applied to the display element, and a display line are provided corresponding to each of the display elements, and conduction / non-conduction between the display element and the signal line is achieved by opening and closing. In a display device comprising a switching element to be controlled and a scanning line for supplying a control voltage for controlling opening and closing of the switching element,
One or more auxiliary scan lines electrostatically coupled to the scan lines;
And a means for applying a voltage having a polarity opposite to that of the control voltage to the one or more auxiliary scanning lines.
A first wiring layer constituting the scanning line and a second wiring layer constituting the auxiliary scanning line are provided, and an insulating layer is provided between the first and second wiring layers. Item 4. The display device according to Item 1.
A plurality of display elements, a signal line for supplying a signal voltage to be applied to the display element, and a display line are provided corresponding to each of the display elements, and conduction / non-conduction between the display element and the signal line is achieved by opening and closing. In a display device comprising a switching element to be controlled and a scanning line for supplying a control voltage for controlling opening and closing of the switching element,
One or more auxiliary signal lines electrostatically coupled to the signal lines;
And a means for applying a voltage having a polarity opposite to that of the signal voltage to the one or more auxiliary signal lines.
A first wiring layer constituting the signal line and a second wiring layer constituting the auxiliary signal line are provided, and an insulating layer is provided between the first and second wiring layers. Item 4. The display device according to Item 3.