JP2011186239A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device that reduces punch-through voltage generated at a pixel simply and suppresses generation of flickers. <P>SOLUTION: The liquid crystal display device includes: an array substrate including a plurality of signal lines, a plurality of scanning lines, a plurality of auxiliary capacitance lines, and a plurality of pixel electrodes overlaid on a plurality of TFTs and the plurality of scanning lines; a counter substrate; and a liquid crystal layer. The pixel electrode PE overlaid on the scanning line Yn at the nth row is electrically connected to TFT 14 which is connected to the scanning line Yn+1 at the (n+1)th row and forms the same pixel PX along with the TFT. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device.

  In general, a liquid crystal display device is known as a lightweight, small, and high-definition display device. In a liquid crystal display device, polarity inversion driving is performed in order to prevent liquid crystal deterioration caused by continuous application of a unidirectional DC electric field during driving. Every time the TFT (Thin Film Transistor) of the pixel performs a switching operation, the charge is redistributed between the pixel electrode and the auxiliary capacitance element connected to the pixel electrode, so that the pixel potential fluctuates (punch-through voltage). To do. As a result, the positive / negative magnitude of the AC electric field is shifted, the transmittance of the liquid crystal layer is periodically changed, and the display screen flickers (hereinafter referred to as flicker).

  In general, in a liquid crystal display device, the potential of the common electrode of the counter substrate is adjusted so that the voltage applied to the liquid crystal layer becomes equal in both cases of positive and negative AC electric fields, thereby suppressing flicker. However, the punch-through voltage differs within the display screen due to the influence of parasitic capacitance between the scan line and the pixel electrode due to the overlap of the scan line and the pixel electrode.

  Specifically, when the level of the switching signal supplied from the scanning line driver circuit to the scanning line is switched from the level at which the TFT is turned on (on potential) to the level at which the TFT is turned off (off potential), the scanning line and the pixel By coupling with the electrode, a punch-through voltage is generated in the pixel. Focusing on the moment when the TFT is turned off, it takes time until the TFT is turned off after the punch-through voltage is generated due to the dullness of the waveform of the switching signal.

  For this reason, the TFT continues to pass a current so as to neutralize the potential difference between the pixel electrode and the signal line caused by the penetration voltage, and eventually the TFT is completely turned off when the gate voltage of the TFT exceeds the threshold voltage. As the waveform of the switching signal becomes duller, the TFT is turned off more slowly, so that neutralization proceeds and the punch-through voltage becomes smaller. The dullness of the gate line increases as the distance from the scanning line driving circuit (power feeding unit) increases. For this reason, for example, when the scanning line driving circuit is connected to both ends of the scanning line, the punch-through voltage generated at the left and right pixels of the display screen is large, and the punch-through voltage generated at the center pixel is large. Get smaller.

  By the way, the value obtained by adding the punch-through voltage to the center value of the voltage of the signal line is the optimum value of the potential of the common electrode. For this reason, the potential of the common electrode for suppressing flicker also varies within the display screen. When the potential of the common electrode deviates from the optimum value, for example, when a gray raster screen is displayed, light and dark flicker due to polarity reversal is visually recognized. Although flicker can be suppressed locally within the display screen, flicker cannot be suppressed over the entire display screen only by adjusting the potential of the common electrode.

  That is, flicker occurs in the display screen in the direction along the scanning line. The flicker is particularly noticeable when the display screen is horizontally long (when the scanning line is long). Therefore, in order to suppress flicker, a technique for devising the setting of the resistance value of the source region and the drain region of the TFT so as not to cause a difference in the effective voltage applied to the liquid crystal layer of each pixel (for example, Patent Document 1) has been proposed.

JP 2002-98990 A

In the liquid crystal display device, in order to suppress the occurrence of flicker, the resistance value of the source region of the TFT and the resistance value of the drain region are devised. Since there are a plurality of types of liquid crystal display devices, it is necessary to devise setting of the resistance value of the source region and the drain region of the TFT for each type. Moreover, there is a possibility that the punch-through voltage generated in the pixel cannot be sufficiently reduced.
The present invention has been made in view of the above points, and an object of the present invention is to provide a liquid crystal display device that can easily reduce a punch-through voltage generated in a pixel and suppress occurrence of flicker. is there.

In order to solve the above-described problem, a liquid crystal display device according to an aspect of the present invention includes:
A plurality of signal lines extending in the column direction, a plurality of scanning lines extending in the row direction, a plurality of auxiliary capacitance lines extending in the row direction with an interval between the plurality of scanning lines, and the plurality of signal lines And a plurality of switching elements connected to the plurality of scanning lines, and a plurality of pixel electrodes disposed in a region partitioned by the plurality of signal lines and the plurality of auxiliary capacitance lines and superimposed on the plurality of scanning lines. An array substrate;
A counter substrate disposed opposite to the array substrate with a gap;
A liquid crystal layer sandwiched between the array substrate and the counter substrate,
The pixel electrode superimposed on the n-th scanning line is electrically connected to the switching element connected to the (n−1) -th or n + 1-th scanning line, and forms the same pixel together with the switching element. It is characterized by being.

  According to the present invention, it is possible to provide a liquid crystal display device that can easily reduce a punch-through voltage generated in a pixel and suppress occurrence of flicker.

1 is a perspective view schematically showing a part of a liquid crystal display device according to an embodiment of the present invention. It is a schematic block diagram which shows the said liquid crystal display device. FIG. 3 is an enlarged plan view showing a wiring structure of pixels of the array substrate shown in FIGS. 1 and 2. It is a figure which expands and shows on the same plane the sectional view along line AB of Drawing 3, the sectional view along line BC, and the sectional view along line CD. FIG. 5 is an equivalent circuit diagram of the pixel shown in FIGS. 2 to 4. 4 is a timing chart showing signal waveforms of the liquid crystal display device, (1) a scanning line driving signal SYn-1, (2) a scanning line driving signal SYn, (3) a scanning line driving signal SYn + 1, and (4) a video signal SXi, (5) It is a figure which shows the electric potential Vpx of the pixel of n row i column. It is a schematic block diagram which shows the liquid crystal display device which concerns on other embodiment of this invention. FIG. 8 is an enlarged plan view showing a pixel wiring structure of the array substrate shown in FIG. 7. FIG. 9 is an equivalent circuit diagram of the pixel shown in FIGS. 7 and 8. 12 is a timing chart showing signal waveforms of a liquid crystal display device according to another embodiment, wherein (1) scanning line driving signal SYn, (2) scanning line driving signal SYn + 1, (3) scanning line driving signal SYn + 2, (4 FIG. 5 is a diagram illustrating a video signal SXi and (5) a potential Vpx of a pixel in an n-th row and an i-th column.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to the drawings.
As shown in FIGS. 1 and 2, the liquid crystal display device includes a liquid crystal display panel P, scanning line driving circuits YD1, YD2, a signal line driving circuit XD, an external driving circuit 5, and a backlight unit BU.

The liquid crystal display panel P includes an array substrate 1, a counter substrate 2 disposed to face the array substrate, and a liquid crystal layer 3 sandwiched between the two substrates. The liquid crystal display panel P has a display region R1 in which the array substrate 1 and the counter substrate 2 overlap. The array substrate 1 has a plurality of pixels PX arranged in a matrix in the display region R1. The pixel PX will be described later.
As shown in FIG. 4, the array substrate 1 includes, for example, a glass substrate 10 as a transparent insulating substrate. The counter substrate 2 includes, for example, a glass substrate 50 as a transparent insulating substrate.

  As shown in FIG. 2, the scanning line drive circuits YD1, YD2 and the signal line drive circuit XD are formed on the glass substrate 10 outside the display region R1. The scanning line drive circuits YD1 and YD2 are respectively connected to both ends of a plurality of scanning lines Y and a plurality of auxiliary capacitance lines Z, which will be described later, extending outside the display region R1. The scanning line driving circuits YD1 and YD2 output a scanning line driving signal as a switching signal to the scanning line Y, and give a predetermined voltage to the auxiliary capacitance line Z.

  The signal line drive circuit XD is connected to a plurality of signal lines X, which will be described later, extending outside the display region R1. The signal line drive circuit XD has an analog switch circuit that selectively connects an external video signal to the signal line X, and outputs the video signal to the selected signal line X.

  The external drive circuit 5 includes a control IC 6. The external drive circuit 5 is connected to one side edge of the array substrate 1 via a plurality of flexible wiring boards 7. A driving IC 8 is installed on each flexible wiring board 7.

  The one side edge portion of the array substrate 1 will be described in detail. The one side edge portion of the glass substrate 10 includes a plurality of first wires 81, a plurality of second wires 82, a plurality of third wires 83, and an OLB (outer not shown). lead bonding) pad groups are formed. The flexible wiring board 7 is connected to the OLB pad group.

  The first wiring 81 is obliquely connected to connect between the scanning line driving circuit YD1 and the OLB pad group, and between the scanning line driving circuit YD2 and the OLB pad group. The second wiring 82 and the third wiring 83 are obliquely connected to connect the signal line driving circuit XD and the OLB pad group.

  The external drive circuit 5 generates a scan line drive circuit control signal for controlling the scan line drive circuits YD1 and YD2, and a signal line drive circuit control signal for controlling the analog switch circuit in the signal line drive circuit XD. To do.

  The external driving circuit 5 transmits the scanning line driving circuit control signal to the scanning line driving circuits YD1 and YD2 via the flexible wiring board 7 and the first wiring 81. The external drive circuit 5 transmits the signal line drive circuit control signal to the signal line drive circuit XD via the flexible wiring board 7 and the second wiring 82. Furthermore, the external drive circuit 5 transmits a video signal given from the outside to the signal line drive circuit XD via the flexible wiring board 7 and the third wiring 83.

  As shown in FIGS. 1 to 5, in the display region R1, on the glass substrate 10, a plurality of scanning lines Y extending along the row direction d1 and a column direction d2 orthogonal to the row direction are extended. A plurality of signal lines X are arranged. On the glass substrate 10, a plurality of auxiliary capacitance lines Z parallel to the scanning lines Y are formed at intervals with respect to the scanning lines Y. In this embodiment, the signal line X and the auxiliary capacitance line Z function as a black matrix (light shielding portion). A pixel electrode PE, which will be described later, is formed in an area partitioned by the plurality of signal lines X and the plurality of auxiliary capacitance lines Z.

  Here, there are m scanning lines Y (scanning lines Y2,..., Ym, Ym + 1). Note that the scanning line Y1 is a dummy scanning line. There are m auxiliary capacitance lines Z (auxiliary capacitance lines Z1,..., Zm-1, Zm). There are h signal lines X (signal lines X1,..., Xh-1, Xh).

  The liquid crystal display panel P of this embodiment is an XGA liquid crystal display panel. For this reason, the number of scanning lines Y and auxiliary capacitance lines Z is 768 (m = 768), and the number of signal lines X is 1024 × 3 = 3072 (h = 3072).

  The liquid crystal display panel P has m × h pixels PX arranged in a matrix in the display region R1. Focusing on the direction along the column direction d2, m pixel electrodes PE are arranged in the column direction d2 (pixel electrodes PE1,..., PEm-1, PEm). Next, one pixel PX is taken out and described.

  The pixel PX includes a TFT (thin film transistor) 14 as a switching element provided in the vicinity of the intersection of the signal line X and the scanning line Y, a pixel electrode PE that is electrically connected to the TFT 14 and overlaps the scanning line Y, and a pixel electrode And an auxiliary capacitance element Cs electrically connected to the PE. Each TFT 14 is a double gate type PMOS transistor.

  More specifically, the semiconductor layer 15, the connection electrode 16, and the auxiliary capacitance electrode 17 are formed on the glass substrate 10. The semiconductor layer 15, the connection electrode 16, and the auxiliary capacitance electrode 17 may be formed after forming an undercoating film (not shown) on the glass substrate 10. The semiconductor layer 15, the connection electrode 16, and the auxiliary capacitance electrode 17 are simultaneously formed of the same material by patterning a semiconductor film formed on the glass substrate 10. In this embodiment, the semiconductor layer 15, the connection electrode 16, and the auxiliary capacitance electrode 17 are made of polysilicon. Further, the semiconductor layer 15, the connection electrode 16, and the auxiliary capacitance electrode 17 are integrally formed.

  A gate insulating film 18 is formed on the glass substrate 10, the semiconductor layer 15, the connection electrode 16, and the auxiliary capacitance electrode 17. On the gate insulating film 18, a plurality of scanning lines Y, a plurality of gate electrodes 20 extending a part of these scanning lines, and a plurality of auxiliary capacitance lines Z are formed.

  Each gate electrode 20 is formed so as to overlap each semiconductor layer 15. Here, since the semiconductor layer 15 is formed in an L shape, a part of the scanning line Y overlapping the semiconductor layer 15 also functions as the gate electrode 20. Each auxiliary capacitance line Z is formed so as to overlap the plurality of auxiliary capacitance electrodes 17. The auxiliary capacitance electrode 17 and the auxiliary capacitance line Z that are arranged to face each other via the gate insulating film 18 form an auxiliary capacitance element Cs.

  The scanning line Y, the gate electrode 20 and the storage capacitor line Z are simultaneously formed of a light-shielding low resistance material such as aluminum or molybdenum-tungsten. In this embodiment, the scanning line Y, the gate electrode 20 and the auxiliary capacitance line Z are made of molybdenum-tungsten.

  An interlayer insulating film 22 is formed on the gate insulating film 18, the scanning line Y, the gate electrode 20, and the auxiliary capacitance line Z. A plurality of signal lines X and a plurality of contact electrodes 30 are formed on the interlayer insulating film 22.

  The signal line X overlaps part of the plurality of semiconductor layers 15. The signal line X is electrically connected to the source region RS of the semiconductor layer 15 through a contact hole that penetrates part of the gate insulating film 18 and the interlayer insulating film 22.

  The contact electrode 30 is electrically connected to the drain region RD of the semiconductor layer 15 through another contact hole that penetrates part of the gate insulating film 18 and the interlayer insulating film 22. The contact electrode 30 is electrically connected to the auxiliary capacitance electrode 17 through the drain region RD of the semiconductor layer 15.

  The signal line X and the contact electrode 30 are simultaneously formed of a light-shielding low resistance material such as aluminum or molybdenum-tungsten. In this embodiment, the signal line X and the contact electrode 30 are made of aluminum.

  An interlayer insulating film 31 as a protective film is formed on the interlayer insulating film 22, the signal line X, and the contact electrode 30. A color filter CF is formed on the interlayer insulating film 31. The color filter CF has a plurality of red colored layers, a plurality of green colored layers, and a plurality of blue colored layers. Each colored layer is formed in a stripe shape and extends in a direction along the signal line X. Both side edges of each colored layer overlap the signal line X.

  On the color filter CF, a plurality of pixel electrodes PE are formed of a transparent conductive material such as ITO (indium tin oxide). The pixel electrodes PE are arranged in a matrix. The pixel electrode PE is electrically connected to the contact electrode 30 through a contact hole 40 penetrating a part of the interlayer insulating film 31 and the color filter CF. The pixel electrode PE is formed such that the periphery is overlapped with two adjacent signal lines X and two adjacent auxiliary capacitance lines Z.

  As described above, a plurality of columnar spacers (not shown) are formed on the glass substrate 10 on which the color filter CF and the pixel electrode PE are formed. An alignment film 37 is formed on the color filter CF and the pixel electrode PE on which columnar spacers are formed.

  In the array substrate 1, the scanning line Y is supplied from the scanning line driving circuits YD 1 and YD 2 and transmits a scanning line driving signal SY (SY 2,..., SYm, SYm + 1) as a switching signal for switching the open / close state of the TFT 14 to the TFT 14. To do. As described above, since the scanning line Y1 is a dummy scanning line, no scanning line drive signal is given to the scanning line Y1. A predetermined voltage is applied to the auxiliary capacitance line Z from the scanning line driving circuits YD1 and YD2. The video signal SX (SX1,..., SXi,..., SXh) is given to the signal line X from the signal line driving circuit XD.

Next, the counter substrate 2 will be described.
As shown in FIGS. 1, 2, and 4, the counter substrate 2 includes the glass substrate 50. On the glass substrate 50, a common electrode 51 is formed of a transparent conductive material such as ITO. An alignment film 52 is formed on the common electrode 51.

  The array substrate 1 and the counter substrate 2 are arranged to face each other with a predetermined gap by a plurality of columnar spacers. The array substrate 1 and the counter substrate 2 are joined by a sealing material 60 disposed between both substrates on the outer periphery of the display region R1. The liquid crystal layer 3 is formed in a region surrounded by the array substrate 1, the counter substrate 2, and the sealing material 60. The pixel electrode PE forms a liquid crystal capacitance Clc between the pixel electrode PE and the common electrode 51 positioned with the liquid crystal layer 3 interposed therebetween. A liquid crystal inlet 61 is formed in a part of the sealing material 60, and the liquid crystal inlet is sealed with a sealing material 62.

  A polarizing plate 71 is disposed on the outer surface of the glass substrate 10. A polarizing plate 72 is disposed on the outer surface of the glass substrate 50. In this embodiment, the outer surface of the polarizing plate 72 is a display surface.

  The backlight unit BU includes a light guide plate Ba, and a light source and a reflection plate (not shown) arranged to face one side edge of the light guide plate. The light guide plate Ba is disposed to face the polarizing plate 71. The liquid crystal display device also has a bezel and the like (not shown).

Next, the pixel PX of this embodiment will be described in detail.
The dummy scanning line Y1 overlaps the pixel electrode PE1. The m-th scanning line Ym overlaps the pixel electrode PEm. The (m + 1) th row scanning line Ym + 1 is located away from the pixel electrode PE (PEm).

Here, n is an integer of 2 or more and m-1 or less (2 ≦ n ≦ m−1).
The pixel electrode PEn superimposed on the n-th scanning line Yn is electrically connected to the TFT 14 connected to the (n + 1) -th scanning line Yn + 1, and the auxiliary capacitive element formed by the n-th auxiliary capacitance line Zn. The same pixel PX is formed together with the TFT 14 and the auxiliary capacitance element Cs. The pixel electrode PE, TFT 14, and auxiliary capacitance element Cs of each pixel PX are located in the same column.

Next, coupling between the pixel electrode PE and the scanning line Y will be described.
The coupling is divided into the following two elements. Focusing on the pixel PXn in the n-th row, the above elements are due to the coupling between the gate and the source of the TFT 14 connected to the scanning line Yn + 1 and the parasitic capacitance Cp between the pixel electrode PEn and the scanning line Yn. .

Next, the punch-through voltage ΔV will be described.
Focusing on the pixel PXn in the n-th row, for convenience, elements that can become the punch-through voltage ΔV are as follows: potential fluctuation of the scanning line Yn that overlaps the pixel electrode PEn of the pixel PXn (change in parasitic capacitance Cp). ) And a potential variation (ΔV2) due to coupling between the gate and the source of the TFT 14 connected to the scanning line Yn + 1.

  The elements that can be the punch-through voltage ΔV are given for convenience, because the punch-through voltage ΔV is not actually equal to the sum of the potential fluctuation of ΔV1 and the potential fluctuation of ΔV2 (ΔV ≠ ΔV1 + ΔV2). ).

  Next, a method for driving the liquid crystal display device will be described. Here, focusing on the pixel PX in the n-th row and the i-th column, the driving of the pixel PX will be described as a representative. The pixel PX in the n-th row and the i-th column includes a pixel electrode PEn superimposed on the n-th row scanning line Yn, a TFT 14 connected to the (n + 1) -th row scanning line Yn + 1 and the i-th row signal line Xi, and an n-th row. And an auxiliary capacitance element Cs formed of the auxiliary capacitance line Zn of the eye.

  As shown in FIGS. 2, 5, and 6, when the driving of the liquid crystal display device is started, the scanning line driving circuits YD1 and YD2 are controlled every one horizontal scanning period (1H) under the control of the external driving circuit 5. The scanning line driving signal SY is sequentially given to the scanning line Y while changing the row. Specifically, a cycle for turning on the TFT 14 (on potential), in this case, a low level scanning line drive signal SY in order from the second scanning line Y2 to the (m + 1) th scanning line Ym + 1 is repeated. .

  For example, when a low-level scanning line drive signal SYn-1 is given to the scanning line Yn-1 during a certain horizontal scanning period, the low-level scanning line driving signal SYn is applied to the scanning line Yn during a continuous horizontal scanning period. In addition, a low-level scanning line driving signal SYn + 1 is applied to the scanning line Yn + 1 in one continuous horizontal scanning period.

  In addition, under the control of the external drive circuit 5, the signal line drive circuit XD performs one horizontal scanning of the video signal SX having a high level, here a positive voltage, and the video signal having a low level, here, a negative voltage. The signal line X is alternately applied to each period.

  For example, when a video signal SX having a positive voltage is applied to the i-th signal line Xi in one horizontal scanning period, a video signal SX having a negative voltage is applied to the signal line Xi in one continuous horizontal scanning period. Further, a video signal SX having a positive voltage is applied to the signal line Xi in one continuous horizontal scanning period.

The common electrode 51 is grounded. For this reason, the liquid crystal display device performs polarity inversion driving in which the polarity is inverted once every horizontal scanning period.
As described above, the liquid crystal display device is driven.

  As described above, the TFT 14 of the pixel PX in the n-th row and i-th column is in an open state while the scanning line drive signal SYn + 1 is at the low level, and a video signal having a positive voltage is applied to the pixel electrode PEn of the pixel PX in the n-th row and i-th column. SXi is given. As a result, the potential Vpx of the pixel PX in the n-th row and i-th column is set to a value at which this pixel is in a light transmission state, and the light transmission state of this pixel is maintained.

  Here, in one horizontal scanning period immediately before the light transmission period of the pixel PX in the n-th row and the i-th column, the potential variation occurs by ΔV1 in the potential Vpx of the pixel PX. The potential fluctuation of ΔV1 is caused by the potential fluctuation (change in parasitic capacitance Cp) of the scanning line Yn that overlaps the pixel electrode PEn of the pixel PXn in the n-th row and i-th column. However, since the potential fluctuation of ΔV1 occurs before the light transmission period, it does not contribute as the punch-through voltage ΔV. In addition, since the period in which the potential variation of ΔV1 occurs is one horizontal scanning period (1H / 768H) of the 768 horizontal scanning periods and a short period, the potential variation of ΔV1 has no adverse effect on the image display. is there.

  Further, a potential variation of ΔV2 occurs in the potential Vpx of the pixel PX from the latter half of the first one horizontal scanning period to the second one horizontal scanning period of the light transmission period of the pixel PX in the nth row and ith column. The potential fluctuation of ΔV2 is caused by the coupling between the gate and the source of the TFT 14 of the pixel PXn in the n-th row and the i-th column. Since the potential fluctuation of ΔV2 occurs within the light transmission period, it contributes as a punch-through voltage ΔV.

  According to the liquid crystal display device configured as described above, the liquid crystal display panel P includes the array substrate 1, the counter substrate 2, and the liquid crystal layer 3. The array substrate 1 includes a plurality of signal lines X, a plurality of scanning lines Y, a plurality of auxiliary capacitance lines Z, a plurality of TFTs 14, and a plurality of pixel electrodes PE. The pixel electrode PE is disposed in a region partitioned by the signal line X and the auxiliary capacitance line Z and overlaps the scanning line Y.

  The pixel electrode PEn superimposed on the n-th scanning line Yn is electrically connected to the TFT 14 connected to the (n + 1) -th scanning line Yn + 1, and forms the same pixel PX together with the TFT 14.

Thereby, although the potential fluctuation of ΔV2 contributes to the punch-through voltage ΔV, the potential fluctuation of ΔV1 does not contribute to the punch-through voltage ΔV. Since the penetration voltage ΔV of each pixel PX can be reduced, the occurrence of flicker can be suppressed. Needless to say, it is possible to prevent the occurrence of a punch-through voltage due to the potential fluctuation of ΔV1, and to suppress the occurrence of flicker without devising the setting of the resistance value of the source region and the drain region of the TFT. There is no.
From the above, it is possible to obtain a liquid crystal display device that can easily reduce the punch-through voltage generated in the pixel and can suppress the occurrence of flicker.

Next, a liquid crystal display device according to another embodiment of the present invention will be described in detail. In this embodiment, other configurations are the same as those of the above-described embodiment, and the same portions are denoted by the same reference numerals and detailed description thereof is omitted.
As shown in FIG. 7, the liquid crystal display device includes a liquid crystal display panel P, scanning line drive circuits YD1, YD2, a signal line drive circuit XD, an external drive circuit 5, and a backlight unit BU.

  There are m scanning lines Y (scanning lines Y1, ..., Ym-1, Ym). The scanning line Ym + 1 is a dummy scanning line. There are m auxiliary capacitance lines Z (auxiliary capacitance lines Z1,..., Zm-1, Zm). There are h signal lines X (signal lines X1,..., Xh-1, Xh). The liquid crystal display panel P of this embodiment is an XGA liquid crystal display panel. For this reason, the number of scanning lines Y and auxiliary capacitance lines Z is 768 (m = 768), and the number of signal lines X is 1024 × 3 = 3072 (h = 3072).

  As shown in FIGS. 7 to 9, the scanning line Y transmits the scanning line driving signals SY (SY1,..., SYm-1, SYm) given from the scanning line driving circuits YD1 and YD2 to the TFT. Since the scanning line Ym + 1 is a dummy scanning line, no scanning line drive signal is given to the scanning line Ym + 1. A predetermined voltage is applied to the auxiliary capacitance line Z from the scanning line driving circuits YD1 and YD2. The video signal SX (SX1,..., SXi,..., SXh) is given to the signal line X from the signal line driving circuit XD.

Next, the pixel PX of this embodiment will be described in detail.
The scanning line Y1 in the first row is located away from the pixel electrode PE (PE1). The scanning line Y2 in the second row overlaps with the pixel electrode PE1. The (m + 1) th scanning line Ym + 1 overlaps the pixel electrode PE (PEm).

Here, n is an integer of 2 or more and m or less (2 ≦ n ≦ m).
The pixel electrode PEn-1 superimposed on the nth scanning line Yn is electrically connected to the TFT 14 connected to the n-1th scanning line Yn-1, and the n-1th auxiliary capacitance line. The same pixel PX is formed together with the TFT 14 and the auxiliary capacitive element Cs by being electrically connected to the auxiliary capacitive element Cs formed of Zn-1. The pixel electrode PE, TFT 14, and auxiliary capacitance element Cs of each pixel PX are located in the same column.

Next, coupling between the pixel electrode PE and the scanning line Y will be described.
The coupling is divided into the following two elements. Focusing on the pixel PXn in the n-th row, the above elements are due to the coupling between the gate and the source of the TFT 14 connected to the scanning line Yn and the parasitic capacitance Cp between the pixel electrode PEn and the scanning line Yn + 1. .

Next, the punch-through voltage ΔV will be described.
Focusing on the pixel PXn in the n-th row, for convenience, elements that can become the punch-through voltage ΔV are as follows: potential fluctuation of the scanning line Yn + 1 that overlaps the pixel electrode PEn of the pixel PXn (change in parasitic capacitance Cp). ) And a potential variation (ΔV2) due to coupling between the gate and source of the TFT 14 connected to the scanning line Yn−1.

  The elements that can be the punch-through voltage ΔV are given for convenience, because the punch-through voltage ΔV is not actually equal to the sum of the potential fluctuation of ΔV1 and the potential fluctuation of ΔV2 (ΔV ≠ ΔV1 + ΔV2). ).

  Next, a method for driving the liquid crystal display device will be described. Here, focusing on the pixel PX in the n-th row and the i-th column, the driving of the pixel PX will be described as a representative. The pixel PX in the n-th row and the i-th column includes a pixel electrode PEn superimposed on the (n + 1) -th scanning line Yn + 1, a TFT 14 connected to the n-th scanning line Yn and the i-th signal line Xi, and the (n + 1) th row. And an auxiliary capacitance element Cs formed by the auxiliary capacitance line Zn + 1 of the eye.

  As shown in FIGS. 7, 9 and 10, when driving of the liquid crystal display device is started, the scanning line driving circuits YD1 and YD2 are controlled every one horizontal scanning period (1H) under the control of the external driving circuit 5. The scanning line driving signal SY is sequentially given to the scanning line Y while changing the row. More specifically, a cycle for turning on the TFT 14 (on potential), in this case, a low-level scanning line driving signal SY in order from the first scanning line Y1 to the m-th scanning line Ym is repeated. .

  For example, when a low-level scanning line drive signal SYn-1 is given to the scanning line Yn-1 during a certain horizontal scanning period, the low-level scanning line driving signal SYn is applied to the scanning line Yn during a continuous horizontal scanning period. In addition, a low-level scanning line driving signal SYn + 1 is applied to the scanning line Yn + 1 in one continuous horizontal scanning period.

  In addition, under the control of the external drive circuit 5, the signal line drive circuit XD performs one horizontal scanning of the video signal SX having a high level, here a positive voltage, and the video signal having a low level, here, a negative voltage. The signal line X is alternately applied to each period.

  For example, when a video signal SX having a positive voltage is applied to the i-th signal line Xi in one horizontal scanning period, a video signal SX having a negative voltage is applied to the signal line Xi in one continuous horizontal scanning period. Further, a video signal SX having a positive voltage is applied to the signal line Xi in one continuous horizontal scanning period.

The common electrode 51 is grounded. For this reason, the liquid crystal display device performs polarity inversion driving in which the polarity is inverted once every horizontal scanning period.
As described above, the liquid crystal display device is driven.

  From the above, during the period when the scanning line drive signal SYn is at a low level, the TFT 14 of the pixel PX in the n-th row and i-th column is opened, and the video signal having a positive voltage is applied to the pixel electrode PEn of the pixel PX in the n-th row and i-th column. SXi is given. As a result, the potential Vpx of the pixel PX in the n-th row and i-th column is set to a value at which this pixel is in a light transmission state, and the light transmission state of this pixel is maintained.

  Here, from the second half of the first horizontal scanning period of the light transmission period of the pixel PX in the n-th row and i-th column to the second one horizontal scanning period, the potential variation of the pixel PX is caused by ΔV2. The potential fluctuation of ΔV2 is caused by the coupling between the gate and the source of the TFT 14 of the pixel PXn in the n-th row and the i-th column. Since the potential fluctuation of ΔV2 occurs within the light transmission period, it contributes as a punch-through voltage ΔV.

  Further, in one horizontal scanning period immediately after the light transmission period of the pixel PX in the n-th row and the i-th column, the potential variation occurs by ΔV1 in the potential Vpx of the pixel PX. The potential fluctuation of ΔV1 is caused by the potential fluctuation (change in parasitic capacitance Cp) of the scanning line Yn + 1 that overlaps the pixel electrode PEn of the pixel PXn in the n-th row and i-th column. However, since the potential fluctuation of ΔV1 is a negligible level, it contributes as the punch-through voltage ΔV, but does not adversely affect the display image. In addition, since the period in which the potential variation of ΔV1 occurs is one horizontal scanning period (1H / 768H) of the 768 horizontal scanning periods and a short period, the potential variation of ΔV1 has no adverse effect on the image display. is there.

  According to the liquid crystal display device configured as described above, the liquid crystal display panel P includes the array substrate 1, the counter substrate 2, and the liquid crystal layer 3. The array substrate 1 includes a plurality of signal lines X, a plurality of scanning lines Y, a plurality of auxiliary capacitance lines Z, a plurality of TFTs 14, and a plurality of pixel electrodes PE. The pixel electrode PE is disposed in a region partitioned by the signal line X and the auxiliary capacitance line Z and overlaps the scanning line Y.

  The pixel electrode PEn superimposed on the nth scanning line Yn is electrically connected to the TFT 14 connected to the (n-1) th scanning line Yn-1, and forms the same pixel PX together with the TFT14. Yes.

As a result, the punch-through voltage ΔV of each pixel PX can be reduced, and the occurrence of flicker can be suppressed. Needless to say, it is possible to prevent the occurrence of a punch-through voltage due to the potential fluctuation of ΔV1, and to suppress the occurrence of flicker without devising the setting of the resistance value of the source region and the drain region of the TFT. There is no.
From the above, it is possible to obtain a liquid crystal display device that can easily reduce the punch-through voltage generated in the pixel and can suppress the occurrence of flicker.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some components may be deleted from all the components shown in the embodiment.

  The pixel electrode PEn superimposed on the n-th scanning line Yn only needs to be electrically connected to the TFT 14 connected to the scanning line Yn−1 or the scanning line Yn + 1 and form the same pixel together with the TFT 14. .

  The dummy scanning line may not be provided. The TFT 14 is not limited to a double gate type TFT but may be a single gate type TFT. The TFT 14 is not limited to a PMOS TFT but may be an NMOS TFT.

  DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Opposite substrate, 3 ... Liquid crystal layer, 10 ... Glass substrate, 14 ... TFT, 15 ... Semiconductor layer, 17 ... Auxiliary capacity electrode, 20 ... Gate electrode, P ... Liquid crystal display panel, YD1, YD2 ... Scanning line drive circuit, XD ... signal line drive circuit, BU ... backlight unit, R1 ... display area, PX ... pixel, PE ... pixel electrode, Cs ... auxiliary capacitance element, Y ... scanning line, Z ... auxiliary capacitance line, X ... signal line, d1 ... row direction, d2 ... column direction.

Claims (4)

A plurality of signal lines extending in the column direction, a plurality of scanning lines extending in the row direction, a plurality of auxiliary capacitance lines extending in the row direction with an interval between the plurality of scanning lines, and the plurality of signal lines And a plurality of switching elements connected to the plurality of scanning lines, and a plurality of pixel electrodes disposed in a region partitioned by the plurality of signal lines and the plurality of auxiliary capacitance lines and superimposed on the plurality of scanning lines. An array substrate;
A counter substrate disposed opposite to the array substrate with a gap;
A liquid crystal layer sandwiched between the array substrate and the counter substrate,
The pixel electrode superimposed on the n-th scanning line is electrically connected to the switching element connected to the (n−1) -th or n + 1-th scanning line, and forms the same pixel together with the switching element. A liquid crystal display device.   The liquid crystal display device according to claim 1, wherein the pixel electrode and the switching element of the pixel are located in the same column. The number of the scanning lines is m,
The liquid crystal display device according to claim 1, wherein the first scanning line or the m-th scanning line is located away from the pixel electrode.   The liquid crystal display device according to claim 1, wherein the scanning line transmits a switching signal for switching an open / close state of the switching element to the switching element.

Images