KR102004844B1 - Liquid crystal display having high aperture ratio - Google Patents

Abstract

The present invention relates to a liquid crystal display device in which two gate wirings are arranged so as to overlap each other to increase the aperture ratio and implement a narrow bezel in a structure driven by a zigzag inversion to reduce the number of data wirings. A liquid crystal display device according to the present invention includes a plurality of data lines, a plurality of gate lines crossing the data lines, pixel electrodes arranged in a matrix, and a plurality of gate lines crossing the data lines and the gate lines The thin film transistors being formed; Two pixel electrodes are disposed between two neighboring data lines; At least two pixel electrodes in a row are connected to the same data line; Two neighboring gate wirings are disposed between the pixel electrodes of two neighboring rows; And the two neighboring gate wirings are vertically overlapped with each other with an insulating film interposed therebetween.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device having a high aperture ratio,

The present invention relates to a liquid crystal display device driven by dot inversion using a source driver integrated circuit (IC) which outputs a data voltage whose polarity is inverted with a column inversion. Particularly, the present invention relates to a liquid crystal display device in which two gate wirings are arranged so as to overlap each other in a zigzag-in version to reduce the number of data wirings, thereby increasing the aperture ratio and realizing a narrow bezel.

A liquid crystal display device of an active matrix driving type displays a moving image by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. The liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, and the like, and is rapidly applied to a television, thereby quickly replacing a cathode ray tube.

The liquid crystal display device includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying a data voltage to the data lines of the liquid crystal display panel, A gate drive IC for supplying a gate pulse (or a scan pulse) to scan lines (or scan lines), a control circuit for controlling the ICs, a light source driving circuit for driving a light source of the backlight unit, and the like.

Due to the process technology of the liquid crystal display device and the breakthrough of the driving technology, the manufacturing cost of the liquid crystal display device is lowered and the image quality is greatly improved. It is necessary to further improve the power consumption, image quality, and manufacturing cost of the liquid crystal display device in accordance with the requirements of the information terminal with low power consumption and low cost.

As a technical requirement, a double rate drive (DRD) for transferring information to two pixels connected to different gate lines through a single data line has been proposed. Further, a liquid crystal display device which drives a liquid crystal display panel in dot-inversion using a source drive integrated circuit that outputs a data voltage whose polarity is inverted with a column inversion is proposed.

1 is a schematic view showing the structure of a conventional liquid crystal display device. 2 is a circuit diagram showing a connection of a pixel array driven by a conventional double-rate drive method. FIG. 3 is an enlarged plan view showing the structure of a pixel array driven by a double-rate drive method according to the circuit diagram of FIG. 2. FIG.

1, a conventional liquid crystal display device includes a liquid crystal display panel (DPL), a source drive IC 12, and a timing controller 11 in which a pixel array 10 is formed. A backlight unit (not shown) for uniformly irradiating light to the liquid crystal display panel may be disposed under the liquid crystal display panel DPL.

The liquid crystal display panel DPL includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. A pixel array 10 is formed in the liquid crystal display panel DPL. The pixel array 10 includes liquid crystal cells arranged in a matrix form by an intersection structure of data lines and gate lines to display video data. A storage capacitor Cst connected to the data lines, the gate lines, the thin film transistors, the pixel electrode of the liquid crystal cell connected to the thin film transistor, and the pixel electrode of the liquid crystal cell is formed on the lower glass substrate of the pixel array 10, And the like. Each of the liquid crystal cells of the pixel array 10 is driven by a voltage difference between a pixel electrode for charging a data voltage through a thin film transistor and a common electrode to which a common voltage is applied so as to adjust the amount of light transmitted, do. The specific structure of the pixel array 10 will be described in detail later with reference to FIGS. 2 and 3. FIG.

On the upper glass substrate of the liquid crystal display panel, a black matrix, a color filter, and a common electrode are formed. The common electrode is formed on the upper glass substrate in the case of a vertical field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. In the IPS (In-Plane Switching) mode and the FFS (Fringe Field Switching) And is formed on the lower glass substrate together with the pixel electrode in the case of the same horizontal electric field driving method.

An alignment film is formed on each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel to attach a polarizing plate and set a pre-tilt angle of the liquid crystal.

The liquid crystal display of the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The source drive ICs 12 are mounted on a TCP (Tape Carrier Package) 15 and bonded to a lower glass substrate of a liquid crystal display panel by a TAB (Tape Automated Bonding) process. A source PCB (Printed Circuit Board) Respectively. The source drive ICs 12 may be bonded on the lower glass substrate of the liquid crystal display panel by a COG (Chip On Glass) process. The data output channels of each of the source drive ICs 12 are connected to the data lines of the pixel array 10 in a 1: 1 relationship.

Each of the source drive ICs 12 receives digital video data from the timing controller 11. The source driver ICs 12 convert the digital video data into positive / negative analog data voltages in response to the source timing control signal from the timing controller 11 and output the data lines of the pixel array 10 through the output channels . The source drive ICs 12 supply data voltages of opposite polarities to neighboring data lines under the control of the timing controller 11 and supply the polarities of the data voltages supplied to the respective data lines to the same .

The gate driving circuit 13 sequentially supplies gate pulses to the gate wirings of the pixel array in response to a gate timing control signal transmitted from the timing controller 11. [ The gate driver circuit 13 is mounted on the TCP and bonded to the lower glass substrate of the liquid crystal display panel by the TAB process or directly formed on the lower glass substrate by the GIP (Gate In Panel) . The gate drive circuit 13 may be disposed on one side of the pixel array 10 or on both sides of the pixel array 10 as shown in Fig.

The timing controller 11 supplies the source drive ICs 12 with digital video data input from an external system board. The timing controller 11 generates a source timing control signal for controlling the operation timing of the source drive ICs 12 and a gate timing control signal for controlling the operation timing of the gate drive circuit 13. [ The timing controller 11 is mounted on the control PCB 16. The control PCB 16 and the source PCB 14 are connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

Hereinafter, the structure of a liquid crystal display device driven by a double-rate scheme will be described with further reference to Figs. 2 and 3. Fig. 2 and 3, the pixel array 10 includes data wirings D1, D2, D3, D4, ... and gate wirings G1, G2, G3, G4, Thin film transistors T11 and T12 for supplying the pixel electrodes P11, P12, P13, P14, ..., Pij to the data lines D1, D2, D3, D4, T12, T13, T14, ... Tij.

During the Nth (N is a positive integer) frame period, only positive polarity analog data voltages are supplied from the source drive ICs 12 to the odd data lines D1, D3 ... D2m-1, D2m + 1 , Only the negative analog data voltage is supplied from the source drive ICs 12 to the even-numbered data lines D2, D4 ... D2m. During the (N + 1) -th frame period, only the negative analog data voltage is supplied from the source drive ICs 12 to the odd data lines D1, D3 ... D2m-1, D2m + Only the positive analog data voltage is supplied from the source drive ICs 12 to the data lines D2, D4, ..., D2m.

Due to the data voltage in which the polarity is inverted in the column-inversion manner and the connection of the thin film transistors and the data lines, the same polarity is continuously supplied to each of the data lines for one frame period. And the data voltages charged in the liquid crystal cells of the pixel array are inverted into a version whose polarity is horizontal 2 dot and vertical 1 dot.

In each of the data lines D1, D2, D3, D4, ... in the odd horizontal display lines LINE1, LINE3, ..., LINE2p-1 of the pixel array 10, The electrodes are connected to sequentially charge data voltages of the same polarity supplied from the same data line. The two data lines D1, D2, D3, D4, ... in the horizontal horizontal display lines LINE2, LINE4, ..., LINE2p of the pixel array 10 are provided with two pixel electrodes And sequentially charges data voltages of the same polarity supplied from the same data line.

The thin film transistors T11, T12, T13, T14, ..., Tij assigned to the pixel electrodes P11, P12, P13, P14, The connection relation of the wirings (D1, D2, D3, D4, ...) will be described in more detail as follows. Here, m (related to the data line number), n (related to the gate line number), p (related to the display line number), i (related to the row number), j (related to the column number) Referring to FIG. 2, a plurality of data lines are arranged and pixel electrodes of two rows are arranged between neighboring data lines. On the other hand, the gate wirings G1, G2, G3, G4, ... have a structure in which two wirings are arranged between neighboring pixels in the vertical direction.

Now, since it is described with reference to the image information displayed in the case of one frame, consideration will be given to which data wire each pixel receives information in a state in which all the gate wirings are sequentially selected.

Thin film transistors and pixel electrodes existing between the m-th data line and the (m + 1) -th data line in each of the odd-numbered horizontal display lines LINE1, LINE3, ..., LINE2p- As shown in Fig. In addition, the pixel electrodes existing between the m-th (m is a positive integer) data line and the (m-1) -th data line in each of the excellent horizontal display lines LINE2, LINE4, And charges the data voltage sequentially supplied from the data line. That is, the pixel electrodes connected to the m-th data line are connected to P (2p-1, 2m-1) and P (2p- 1) -1 and P (2p, 2 (m-1)).

Thin film transistors for switching the current path between these pixel electrodes and the mth data line are connected. (2p-1, 2m-1) and T (2p-1, 2m) Thin film transistors. For example, P15 through T15, P16 through T16, P35 through T35, P36 through T36, P23 through T23, P24 through T24, P43 through T43, P44 through T44, etc. are supplied with the data voltage. Here, when the matrix position is calculated, if the value is less than '0', it means that there is no connection.

In a liquid crystal display device having such a structure, since the polarities of data voltages charged in the liquid crystal cells connected to one data line are the same, the power consumption of the source drive IC can be reduced and the data charge amount of each liquid crystal cell can be uniformly can do. Therefore, deterioration in image quality such as luminance unevenness and color distortion caused by unevenness of the data charging amount caused by the inversion method of the non-double-rate driving method can be prevented. Further, the number of data lines and the number of channels of the source drive ICs can be reduced by using the thin film transistor connection relationship in which the liquid crystal cells adjacent to the left and right sides share one data line, and further, the manufacturing cost of the liquid crystal display device can be reduced .

In the structure for such a double rate driving, as can be seen in Fig. 3, two gate wirings are arranged between two pixel electrodes adjacent in the vertical direction. Therefore, there may arise a problem that the opening area becomes smaller.

An object of the present invention is to provide a liquid crystal display device capable of improving power consumption and image quality. It is another object of the present invention to provide a pixel structure in which information is transferred to two pixels connected to different gate lines by one data line in order to improve power consumption, And to provide a liquid crystal display device capable of eliminating the decrease in luminance. It is a further object of the present invention to provide a double-rate driving method in which a gate signal is applied at the top and / or bottom of a display panel through a vertical gate wiring, thereby increasing the ratio of the opening area and minimizing the width of the bezel area And a liquid crystal display device having a narrow bezel structure.

According to an aspect of the present invention, there is provided a liquid crystal display device including a plurality of data lines, a plurality of gate lines crossing the data lines, pixel electrodes arranged in a matrix, Thin film transistors formed at intersections of the gate wirings; Two pixel electrodes are disposed between two neighboring data lines; At least two pixel electrodes in a row are connected to the same data line; Two neighboring gate wirings are disposed between the pixel electrodes of two neighboring rows; And the two neighboring gate wirings are vertically overlapped with each other with an insulating film interposed therebetween.

The two neighboring gate wirings include a first gate wiring formed of the same material in the same layer as the gate electrode of the thin film transistor; And a second gate wiring formed on the insulating film covering the first gate wiring.

The first gate wiring is extended and connected to the gate electrode of the thin film transistor and the second gate wiring is in contact with the gate electrode of the thin film transistor through a gate contact hole passing through the insulating film.

The second gate line includes a transparent conductive material and a metal material formed on the same layer as the pixel electrode connected to the drain electrode of the thin film transistor on a protective film covering the thin film transistor.

And gate vertical interconnections arranged one by one between the two pixel electrodes disposed between the two neighboring data interconnections.

And the gate vertical interconnections are connected to any one of the neighboring two gate interconnections.

The two neighboring gate wirings include a first gate wiring formed of the same material in the same layer as the gate electrode of the thin film transistor; And a second gate wiring formed on the insulating film covering the first gate wiring, wherein the gate vertical wiring includes: a first gate vertical wiring connected to the first gate wiring; And a second gate vertical wiring connected to the second gate wiring.

And the gate vertical wirings are formed of the same material in the same layer as the data wiring.

The present invention can control the polarities of the data voltages charged in the liquid crystal cells connected to one data line equally to equalize the amount of data charges of the liquid crystal cells and reduce the power consumption of the source drive IC. Further, the present invention can realize a high aperture ratio by enlarging the aperture region by arranging the two gate wirings allocated to one pixel row on the different layers and overlapping each other. Further, in the present invention, by arranging a vertical gate wiring which is electrically connected to a horizontal gate wiring which is arranged in a horizontal direction and overlaps with each other and which is overlapped with one pixel row between the pixel columns where no data wiring is arranged, The bezel area occupying space can be minimized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a structure of a liquid crystal display device according to a related art; FIG.
2 is a circuit diagram showing a connection of a pixel array driven by a conventional double-rate drive method;
3 is a plan enlarged view showing in detail the structure of a pixel array driven by a double-rate drive method according to the circuit diagram of FIG.
4 is a plan enlarged view showing the structure of a pixel array driven by a double-rate drive method according to the first embodiment of the present invention in detail.
5 is a cross-sectional view showing a superposition structure of a gate wiring in a pixel array according to the first embodiment of the present invention, which is cut along a perforated line I-I 'in FIG. 4;
6 is a cross-sectional view showing the structure of a thin film transistor in the pixel array according to the first embodiment of the present invention, which is cut into a perforated line II-II 'in FIG.
FIG. 7 is a plan enlarged view showing a detailed structure of a pixel array driven by a double-rate drive method according to a second embodiment of the present invention; FIG.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured.

4 is a plan enlarged view showing the structure of a pixel array driven by a double-rate drive method according to the first embodiment of the present invention. 5 is a cross-sectional view showing a superposition structure of a gate wiring in a pixel array according to the first embodiment of the present invention, which is cut along a perforated line I-I 'in FIG. The basic structure of the liquid crystal display panel according to the present invention is not greatly different from the conventional structure. In the description of the present invention, only the pixel array portion of the liquid crystal display panel, which clearly differs from the prior art, will be described.

Referring to FIG. 4, the pixel array of the liquid crystal display according to the first embodiment of the present invention includes data lines D1, D2, D3, D4, ... and gate lines G1, G2, The pixel electrodes P11, P12, P13, P14, ..., Pij are supplied to the data lines D1, D2, D3, D4, ... in response to gate pulses (T11, T12, T13, T14, ... Tij). Particularly, in the pixel array of the liquid crystal display device according to the first embodiment of the present invention, the gate wirings arranged two by two for each pixel row have a structure in which they are overlapped in different layers.

For example, the second gate wiring G2 and the third gate wiring G3 may be formed in different layers with the planarizing film interposed therebetween. That is, the second gate wiring G2 may be formed in the same layer as the gate electrode G assigned to the P12 pixel electrode, and the gate electrode G may have a shape branched off from the second gate wiring. On the other hand, the third gate wiring G3 is formed on the layer higher than the second gate wiring G2 with the insulating film interposed therebetween, and through the gate contact hole GH exposing a part of the gate electrode G of P22 Can be connected to each other.

4, since the second gate wiring G2 and the third gate wiring G3 are formed so as to overlap with each other, as compared with FIG. 3 showing a pixel array according to the prior art, The area can be significantly reduced. The pixel electrodes P11, P12, P13, P14, ... P21, P22, P23, P24, ... are formed in a manner that the area occupied by the gate wirings G2, G3, G4, G5, Can be formed larger. As a result, the aperture ratio, which is the area ratio occupied by the pixel electrodes in the entire area of the display panel, can be further secured.

Hereinafter, the sectional structure of the pixel array according to the present invention will be described in more detail with reference to FIGS. 5 and 6. FIG. FIG. 6 is a cross-sectional view showing the structure of a thin film transistor in the pixel array according to the first embodiment of the present invention, which is cut along a perforated line II-II 'in FIG.

First, the structure of a thin film transistor will be described with reference to FIG. A gate electrode G is formed on the substrate SUB. On the gate electrode G, a gate insulating film GI is applied over the entire surface of the substrate SUB. A semiconductor channel layer A is formed so as to overlap the gate electrode G on the gate insulating film GI.

A source electrode S which is in contact with one side of the semiconductor channel layer A and a drain electrode which is in contact with the other side of the semiconductor channel layer A with a certain distance from the source electrode S D are formed. Then, the planarization film PAC covering the thin film transistor T is applied to the entire surface of the substrate SUB. A contact hole exposing a part of the drain electrode (D) is formed in the planarization film (PAC). On the planarization film PAC, pixel electrodes PXL and P12 are formed which are in contact with the drain electrode D through the contact hole.

A protective film PAS covering the entire surface of the substrate SUB is coated on the pixel electrodes PXL and P12. A common electrode COM that overlaps the pixel electrode PXL is formed on the passivation film PAS.

Hereinafter, with reference to FIG. 5, a lamination structure of two gate wirings G2 and G3 disposed between two vertically adjacent pixel electrodes P12 and P22 will be described. Here, a representative example of a plurality of pixel electrodes and a plurality of gate wirings will be described, and the same concept is applied to the entire substrate.

A gate electrode G (P22) assigned to the P22 pixel electrode on the substrate SUB and a gate electrode G (P12) assigned to the P12 pixel electrode and a second gate G (P12) connected to the gate electrode G A wiring G2 is formed. At this time, the third gate wiring G1 connected to the gate electrode G (P22) assigned to the P22 pixel electrode is not formed.

A gate insulating film GI is applied over the entire substrate SUB over the gate electrodes G (P12) and G (P22) and the second gate wiring G2. A channel layer A, a source electrode S and a drain electrode D of the thin film transistor T are formed on the gate insulating film GI as shown in FIG. On the thin film transistor T, a planarization film (PAC) is applied to the entire surface of the substrate SUB.

A part of the planarization film PAC and the gate insulating film GI is patterned to form a gate contact hole GH exposing a part of the gate electrode G (P22) assigned to the P22 pixel electrode. A third gate wiring G3 which overlaps with the second gate wiring G2 is formed when the pixel electrode P12 which is in contact with the drain electrode D of the first gate wiring T is formed. G3 are connected to the gate electrode G (P22) assigned to the P22 pixel electrode through the gate contact hole GH.

The third gate wiring G3 is formed to be long across the substrate SUB. As the size of the liquid crystal display panel increases, the length of the third gate wiring G3 becomes longer. Therefore, it is preferable that the third gate wiring G3 includes a material having a low resistivity value. However, in the present invention, the third gate wiring G3 is formed in the same layer as the pixel electrode P12 in the same step. That is, the third gate wiring G3 must be formed of a transparent conductive material used for the pixel electrode P12. Indium Tin Oxide or Indium Zinc Oxide is a material having a non- Since it is larger than a material, it is not suitable as a wiring material.

In order to lower the line resistance of the third gate wiring G3, the third gate wiring preferably has a structure in which a transparent conductive material layer IT and a low-resistance metal material layer ME are laminated. For example, a transparent conductive material layer (IT) such as indium tin oxide (ITO) or indium zinc oxide (ITO) is formed on the planarization layer (PAC), and a conductive layer made of aluminum, tantalum, A layer of low resistance metal material (ME) such as nickel, silver (Ag) is continuously applied. Then, using the half-tone mask, the pixel electrode P12 is formed of only the transparent conductive material layer IT and the third gate wiring G3 is formed of the transparent conductive material layer IT and the low- ME) are stacked.

The protective film PAS is applied to the entire surface of the substrate SUB on which the third gate wiring G3 and the pixel electrode P12 are formed. A common electrode COM overlapping the pixel electrode P12 is formed on the protective film PAS.

As described above, in the case of the flat panel display device using the double-rate driving method, since the thin film transistors connected to the two gate wirings can be driven by one data wiring, the number of data wirings can be reduced to 1/2. Since the two pixel columns are arranged between two neighboring data lines, it is possible to have a structure in which the spaces where the data lines are arranged are left one by one compared to the general driving method.

Generally, in a rectangular display device of 16: 9 or more, the number of data lines is much larger than the number of gate lines. Particularly, when the resolution is exceeded and the ultra high resolution display device is implemented in the double-rate driving method, the number of data lines is often more than twice the number of gate lines. Therefore, in the double-rate driving method, the positions of the erased data lines remain as vacant spaces and occupy only the black matrix. In such a structure, if the gate vertical wiring for applying the gate signal to the gate wiring is disposed at the position of the empty vertical wiring, the gate driving circuit can be arranged above and below the left / right side of the substrate. As a result, a narrow bezel structure in which the left and right bezel areas of the display panel are minimized can be realized.

In the second embodiment of the present invention, an example is shown in which a gate driver for applying a scan signal to gate wirings extending in the horizontal direction of the substrate is applied to a liquid crystal display device disposed on the upper portion or the lower portion of the substrate. That is, in the double-rate driving method, in order to supply a scan signal to the gate wiring, a gate vertical wiring extending in the longitudinal direction of the substrate is disposed in an empty space between two neighboring pixel lines disposed between neighboring data wirings Structure. Particularly, two gate wirings extending in the horizontal direction are arranged for each pixel row. By vertically overlapping these two gate wirings, a liquid crystal display device having a larger opening region per pixel region is provided.

The structure of the liquid crystal display device according to the second embodiment is basically similar to that according to the first embodiment. If there is a difference, the gate driver is located on the upper or lower side of the substrate, and a gate vertical wiring for applying a scan signal to the gate wiring connects the gate driver with the gate wiring. The gate vertical wiring is disposed between two pixel region columns disposed between two neighboring data wirings.

Will be described in more detail with reference to FIG. FIG. 7 is an enlarged plan view showing the structure of a pixel array driven by a double-rate drive method according to a second embodiment of the present invention. The pixel array of the liquid crystal display according to the second embodiment of the present invention includes data lines D1, D2, D3, D4, ... and gate lines G1, G2, G3, G4, ) For supplying the pixel electrodes P11, P12, P13, P14, ..., Pij to the data lines D1, D2, D3, D4, T11, T12, T13, T14, ...). Particularly, in the pixel array of the liquid crystal display device according to the second embodiment of the present invention, the gate wirings arranged two by two for each pixel row have a structure in which they are overlapped in different layers.

For example, the second gate wiring G2 and the third gate wiring G3 may be formed in different layers with the planarizing film interposed therebetween. The second gate wiring G2 may be formed in the same layer as the gate electrode G allocated to the P12 pixel electrode so that the gate electrode G is branched at the second gate wiring G2 . On the other hand, the third gate wiring G3 is formed on the layer higher than the second gate wiring G2 with the insulating film therebetween, and the gate contact hole GH exposing a part of the gate electrode G of P21 Can be connected to each other.

Since the second gate wiring G2 and the third gate wiring G3 are formed so as to overlap with each other as in the first embodiment, the area occupied by the gate wirings can be remarkably reduced as compared with the pixel array of the related art . P21, P12, P13, P14, ... P21, P22, P23, P24, ... so that the area occupied by the gate lines G1, G2, G3, G4, G5, ... can be formed larger. As a result, the aperture ratio, which is the area ratio occupied by the pixel electrodes in the entire area of the display panel, can be further secured.

In particular, in the second embodiment, gate vertical wiring lines (GV1, GV2, ...) are further included between the pixel columns of two columns arranged between two neighboring data wirings. The gate vertical interconnections GV1, GV2, ... may be formed of the same material in the same layer as the data interconnections D1, D2, .... Therefore, it is possible to arrange the gate vertical interconnections GV1, GV2, ... one by one between the adjacent data interconnections. The gate wirings G1, G2, ... can be connected to the respective gate vertical wirings GV1, GV2, ... through the gate wiring contact holes GLH.

For example, as shown in Fig. 7, the second gate wiring G2 is formed of the same material as the gate electrode G in the same layer. In other words, the gate electrode G assigned to the P12 pixel electrode has a form directly branched from the second gate wiring G2. Further, the second gate vertical wiring GV2 can be arranged between the P11 pixel electrode and the P12 pixel electrode, instead of the data wiring.

The second vertical gate wiring GV2 is connected to the second gate wiring G2 through a gate wiring contact hole GVH exposing a part of the second gate wiring G2. In particular, it is preferable that the gate wiring contact hole GVH is formed at a position slightly protruding toward the pixel region from the second gate wiring G2 so that interference with the third gate wiring G3 is prevented.

On the other hand, the third gate wiring G3 overlaps the second gate wiring G2 when forming the pixel electrode P12 in contact with the drain electrode D of the thin film transistor T on the planarizing film, SUB in the lateral direction. The third gate wiring G3 is connected to the gate electrode G (P23) assigned to the P23 pixel electrode through the gate contact hole GH. In addition, the third gate vertical wiring GV3 can be disposed between the P13 pixel electrode and the P14 pixel electrode instead of the data wiring.

The third gate wiring G3 is formed on the planarizing film and the third gate vertical wiring GV3 is formed on the same layer as the data lines D1, D2, ... on the gate insulating film GI. Therefore, the planarizing film covering the third gate vertical wiring GV3 is patterned to form the third gate wiring G3 and the third gate wiring G3 via the gate wiring contact hole GVH exposing a part of the third gate vertical wiring GV3. Gate vertical wiring (GV3) can be connected.

In the second embodiment, the gate vertical wirings are formed of the same material in the same layer as the data wiring. However, it may be formed in another layer depending on the convenience of manufacture. For example, it may be formed on the uppermost layer where the common electrode is formed, and further, a layer for the gate vertical wiring may be further formed.

The connection structure of the thin film transistors in the pixel array according to the second embodiment is slightly different from that of the first embodiment. This is to facilitate formation of gate vertical wiring between neighboring data wirings. That is, Fig. 7 shows an example of a connection structure suitable for avoiding interference with data lines when the gate vertical wiring is formed of the same material in the same layer as the data wiring.

As described above, in the second embodiment, the gate vertical wiring that goes parallel to the data wiring can be disposed at the position of the data wiring deleted in the liquid crystal display device using the double-rate driving method. Thereby, the data driving IC that supplies the voltage to the data wiring is disposed on the upper side of the substrate, while the gate driving IC which supplies the voltage to the gate vertical wiring can be disposed on the lower side of the substrate. As a result, the gate driving ICs and / or the wirings connected to the gate driving ICs disposed on the left and right sides of the substrate can be omitted. That is, it is possible to provide a liquid crystal display device in which the bezel area occupying the left and right sides of the substrate is minimized.

Further, by vertically overlapping two gate wirings disposed between adjacent two pixel rows, it is possible to secure a wider pixel region. According to the second embodiment, a narrow-bezel liquid crystal display device having a high aperture ratio can be realized.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: Pixel array 11: Timing controller
12: Source drive IC 13: Gate drive circuit
14: Source PCB 15: Source drive IC
16: control PCB 17: flexible circuit board
D1, D2, D3, D4, DL: Data lines G1, G2, G3, G4,
T11, T12, T13, T14, TFT: Thin film transistor
P11, P12, P13, P14, and PXL:
GV2, GV3, GV4, GV5: Gate vertical wiring
GH: Gate contact hole GVH: Gate wiring contact hole

Claims (11)

A plurality of data lines, a plurality of gate lines crossing the data lines, pixel electrodes arranged in a matrix, and thin film transistors formed at intersections of the data lines and the gate lines;
Two pixel electrodes are disposed between two neighboring data lines;
At least two pixel electrodes in a row are connected to the same data line;
Two neighboring gate wirings are disposed between the pixel electrodes of two neighboring rows; And
The two neighboring gate wirings are vertically overlapped with each other with an insulating film interposed therebetween,
Further comprising gate vertical interconnections arranged one-by-one between the two pixel electrodes disposed between the two neighboring data interconnections.
The method according to claim 1,
The two neighboring gate wirings,
A first gate wiring formed of the same material in the same layer as the gate electrode of the thin film transistor; And
And a second gate wiring formed on the insulating film covering the first gate wiring.
3. The method of claim 2,
Wherein the first gate wiring is extended and connected to a gate electrode of the thin film transistor,
Wherein the second gate wiring is in contact with a gate electrode of the thin film transistor through a gate contact hole passing through the insulating film.
3. The method of claim 2,
Wherein the second gate wiring comprises:
And a transparent conductive material and a metal material formed on the same layer as the pixel electrode connected to the drain electrode of the thin film transistor on a protective film covering the thin film transistor.
delete The method according to claim 1,
And the gate vertical interconnections are connected to any one of the neighboring two gate interconnections.
The method according to claim 6,
The two neighboring gate wirings,
A first gate wiring formed of the same material in the same layer as the gate electrode of the thin film transistor; And
And a second gate wiring formed on the insulating film covering the first gate wiring,
The gate vertical interconnects,
A first gate vertical wiring connected to the first gate wiring; And
And a second gate vertical wiring connected to the second gate wiring.
8. The method of claim 7,
Wherein the gate vertical wirings are formed of the same material in the same layer as the data wiring. The method according to claim 6,
Wherein the first gate wiring is connected to the first gate vertical wiring via a first gate wiring contact hole passing through the insulating film and the second gate wiring is connected to the first gate wiring via a second gate wiring contact hole passing through the insulating film, 2-gate vertical wiring.
10. The method of claim 9,
Wherein the first gate wiring has a first protrusion extending in the same direction as the extending direction of the first gate wiring with the gate electrode of the thin film transistor,
And the second gate wiring has a second protrusion extending in the same direction as the extending direction of the second gate wiring with the gate electrode of the thin film transistor.
11. The method of claim 10,
Wherein the first gate wiring contact hole is disposed at the first projection and the second gate wiring contact hole is disposed at the second projection.

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