WO2014189360A1 - A cmos method of fabricating a combination of an ion sensitive field effect transistor (isfet) and mosfet device - Google Patents

A cmos method of fabricating a combination of an ion sensitive field effect transistor (isfet) and mosfet device Download PDF

Info

Publication number
WO2014189360A1
WO2014189360A1 PCT/MY2014/000091 MY2014000091W WO2014189360A1 WO 2014189360 A1 WO2014189360 A1 WO 2014189360A1 MY 2014000091 W MY2014000091 W MY 2014000091W WO 2014189360 A1 WO2014189360 A1 WO 2014189360A1
Authority
WO
WIPO (PCT)
Prior art keywords
pattern
silicon
isfet
metal
oxide
Prior art date
Application number
PCT/MY2014/000091
Other languages
French (fr)
Inventor
Muhamad Ramdzan Buyong
Zain Azlina MOHD
Zaini Khairil Mazwan MOHD
Sharaifah Kamariah WAN SABLI
Mohd Rofei Mat Hussin
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2014189360A1 publication Critical patent/WO2014189360A1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G01N27/4148—Integrated circuits therefor, e.g. fabricated by CMOS processing

Definitions

  • the present invention relates to a method of fabricating ion-sensitive field-effect transistor (ISFET) device by using Complementary metal-oxide-semiconductor (CMOS) compatible.
  • ISFET ion-sensitive field-effect transistor
  • CMOS Complementary metal-oxide-semiconductor
  • Chemical sensors are micro devices that connect chemical and electrical domains (i.e. transduction of the chemical information into electric signal ⁇ -
  • the response of the sensors should be fast and selective and sensitive for the anal te.
  • the construction of chemical sensors requires the integration of a sensing receptor and a transducing element into a defined chemical system Field effect transistors (FETs) are very interesting because they can be made very sma!l with current planar iC technology and have the advantage of a fast response time.
  • FETs Field effect transistors
  • ISFET is an integrated device that is similar to Meial-Oxide-Semiconductor Field Effect Transistor (MOSFET) except the gate part, Unlike !vlOSFET, metal gate of MOSFET is replaced by a pH sensing membrane which is Silicon Nitride (SI 3 N In ISFET design, Si ? ,N 4 as a sensing membrane is use to detect Ion response in pH buffer solution by exposing the membrane layer to the solution, The pH sensitivity is one of the most Important characteristic parameters of ISFET devices.
  • MOSFET Meial-Oxide-Semiconductor Field Effect Transistor
  • the response of an ISFET is generally determined by the type of the sensing membrane used. Therefore the sensing membrane material plays a significant role.
  • the pH sensitivity can be determined by extracting the threshold voltage (VTH) of ISFET device in various pH solutions.
  • VTH of MOSFET is usually defined as the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor.
  • VTH refer to the minimum gate voltage required to induce a conducting channel at the surface of ISFET.
  • the standard fabrication process produces an unstable threshold voltage thai can affect yield of wafer fabrication. There is also a large metal etch process variation between center and edge of wafer that would also affect the yield of fabrication. It Is also not possible to determine performance at wafer level testing.
  • a method of fabricating ion-sensitive tleid-effect transistor (iSFET) device by using Complementary meia!-oxide-semiconductor (CMOS) compatible includes the steps of marking and etching a silicon layer, depositing an oxide layer, implanting a p-well pattern on the silicon and oxide layers, implanting a channel pattern onto the silicon and oxide layers, implanting N+ source and drain pattern onto the silicon and oxide layers, implanting P+ diffusion pattern onto the silicon and oxide layers, removing the oxide layer, adding a bottom oxidation layer, depositing a silicon nitride layer, adding a contact hole pattern, sputtering metal 1 onto contact hole pattern, silicon nitride layer and the bottom oxidation layer and etching a metal 1 pattern on the sputtered metal such that the method forms a mask design includes a combination of ISFET and metal- oxide-semiconductor field-effect transistor ( OSFET) dice on a single site. .
  • OSFET metal- oxide
  • Figure 1 shows a h!ock diagram of a method of method of fabricating ion-sensitive field- effect transistor (1SF6T) device by using Complementary metah-oxide-semiconductor (CMOS) compatible in the present embodiment of the invention
  • CMOS Complementary metah-oxide-semiconductor
  • Figure 2 shows a cross section of a device fabricated using the method in the present embodiment of the invention:
  • Figure 3 shows a cross section of a MOSFET device to be used as test structure In the method:
  • Figure 4 shows a cross section of a die Including 1 ISFET devices and 1 MOSFET device;
  • Figure 5 shows contact points of SSFET and MOSFET devices;
  • Figure 8 shows a layout design of an ISFET device with a window opening for sensing area;
  • Figure 7 shows an enlarged view of an ISFET sensing area; and
  • Figure 8 shows a wafer map with 125 dice.
  • the present invention reiates to a method of fabricating ion-sensitive field-effect transistor (ISFET) device by using Complementary metai-oxide-semlconductor (CMOS) compatible.
  • ISFET ion-sensitive field-effect transistor
  • CMOS Complementary metai-oxide-semlconductor
  • Figure 1 illustrates a method of fabricating Ion-sensitive field-effect transistor (iSFET) device by using Complementary metai-oxide-semiconductor (CMOS) compatible.
  • CMOS Complementary metai-oxide-semiconductor
  • the method includes the steps of marking and etching a silicon layer (101), depositing an oxide layer (102), implanting a p-vveli pattern on the silicon and oxide layers (101 , 102), implanting a channel pattern onto the silicon and oxide layers (101 , 102), implanting N+ source and dram pattern onto the silicon and oxide layers (101 , 102), implanting P+ diffusion pattern onto the silicon and oxide layers (101 , 02), removing the oxide layer (102), adding a bottom oxidation layer (103), depositing a silicon nitride layer (104), adding a contact hole pattern (105), sputtering metal 1 onto contact ho!e pattern (105), silicon nitride iayer (104) and the bottom oxidation iayer (103) and etching a metal 1 pattern on the sputtered metal such that the method forms a mask design includes a combination of ISFET and metai-oxide- semiconductor field-effect transistor ( OSFET) dice on a single site.
  • OSFET
  • the fabrication method uses 8 lithography mask layers which include siiicon mark etch pattern, P-weii implant pattern, N* source and drain pattern, P+ diffusion pattern, contact hoie pattern and Metal 1 pattern.
  • the method as described above uses a CMOS compatibie process rlow, The additional steps of low pressure chemical vapor deposition (LPCVD) bottom oxidation and LPCVD silicon nitride deposition together with post nitride deposition with nitrogen annealing ensures t si the fabrication is CMOS compatible.
  • LPCVD low pressure chemical vapor deposition
  • An ISFET sensing membrane includes a thin layer film less than 1000 Angstrom deposited by low pressure chemical vapour deposition (LPCVD) high temperature silicon nitride and a thin layer film !ess than 1000 Angstrom deposited by LPCVD high temperature bottom silicon oxide.
  • LPCVD low pressure chemical vapour deposition
  • the rneta! etching process Is done on the silicon nitride sensing membrane which is done In a reactive ion etcher.
  • the metal is etched at a pressure between 8 and 18 m ' T in a plasma containing Ci* gas at a flow rate about 50 and 120 seem, BCL 3 gas at flow rate about 30 and 50 seem, CHF gas at flow rate about 5 seem and Argon gas at flow rate about 50 seem.
  • the method as described above uses MOSFET as a test structure in each image lithography shot.
  • electric current flows from source to drain via channel.
  • channel resistance depends on electric field perpendicular to the direction of the current.
  • Channel resistance also depends on potential difference over silicon nitride gate. Therefore, source-drain current, id, is influenced by the interface potential at the silicon nitride/aqueous solution.
  • Vds source-drain potential
  • changes in the gate potential can be compensated by modu!ation of the Vgs.
  • This adjustment should be carried out in such a way that the changes in Vgs applied to the reference electrode are exactly opposite to the changes in the gate oxide potential.
  • This is automatically performed by !SFET amplifier with feedback which aiiows obtaining constant source-drain current, !n this particular case, the gate-source potential is determined by the surface potential at the insulator/electrolyte interface.
  • the selectivity and chemical sensitivity of the ISFET are completely controlled by the properties of the electrolyte/insulator interface.
  • Figure 2 shows a complete ISFET device as fabricated by the method described above in comparison to Figure 3 that shows a complete MOSFET device.
  • Figure 4 shows a mask design which is a combination of ISFET and metal-oxide- semiconductor field-effect transistor (MOSFET) dice on a single site.
  • MOSFET metal-oxide- semiconductor field-effect transistor
  • Figure 5 shows contact points of ISFET and MOSFET devices.
  • Figure 6 shows a layout design of ISFET which has a window opening for sensing area after encapsulation to facilitate sensing process.
  • Figure 7 specifically points to an ISFET sensing area.
  • Figure 8 shows an example of a wafer map that includes 125 dice. It is to be appreciated that the method as decribed herein improves existing fabrication process flow of ISFET devices by using CMOS compatible by optimizing metal etch recipe and including MOSFET test structures.

Abstract

A method of fabricating ion-sensitive field-effect transistor (ISFET) device by using Complementary metal-oxide-semiconductor (CMOS) compatible is provided, the method includes the steps of marking and etching a silicon layer (101), depositing an oxide layer (102), as well as implanting doping patterns on the silicon and oxide layers (101, 102), depositing a silicon nitride layer (104), sputtering and etching metal.

Description

A CMOS METHOD OF FABRICATING A COMBINATION OF AN ION SENSITIVE FIELD EFFECT TRANSISTOR (ISFET) AND MOSFET DEVICE
FIELD OF INVENTION
The present invention relates to a method of fabricating ion-sensitive field-effect transistor (ISFET) device by using Complementary metal-oxide-semiconductor (CMOS) compatible.
BACKGROUND OF INVENTION
Chemical sensors are micro devices that connect chemical and electrical domains (i.e. transduction of the chemical information into electric signal}- The response of the sensors should be fast and selective and sensitive for the anal te. The construction of chemical sensors requires the integration of a sensing receptor and a transducing element into a defined chemical system Field effect transistors (FETs) are very interesting because they can be made very sma!l with current planar iC technology and have the advantage of a fast response time.
!SFET was first explored by P. Bergveld in 1972 (Bergveld, 1972), In recent years, many researchers have done to characterize ISFET based on MOSFET technology up until now. ISFET is an integrated device that is similar to Meial-Oxide-Semiconductor Field Effect Transistor (MOSFET) except the gate part, Unlike !vlOSFET, metal gate of MOSFET is replaced by a pH sensing membrane which is Silicon Nitride (SI3N In ISFET design, Si?,N4 as a sensing membrane is use to detect Ion response in pH buffer solution by exposing the membrane layer to the solution, The pH sensitivity is one of the most Important characteristic parameters of ISFET devices. The response of an ISFET is generally determined by the type of the sensing membrane used. Therefore the sensing membrane material plays a significant role. The pH sensitivity can be determined by extracting the threshold voltage (VTH) of ISFET device in various pH solutions. The VTH of MOSFET is usually defined as the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor. As for ISFET device, VTH refer to the minimum gate voltage required to induce a conducting channel at the surface of ISFET.
The standard fabrication process produces an unstable threshold voltage thai can affect yield of wafer fabrication. There is also a large metal etch process variation between center and edge of wafer that would also affect the yield of fabrication. It Is also not possible to determine performance at wafer level testing.
US 7,019..343 82 describes an ISFET device, manufacturing method. However, this solution is only partially CMOS compatible,
Therefore, there is a need for an improvement over the existing fabrication process of ISFET.
SUMMARY OF INVENTION
Accordingly, there is provided a method of fabricating ion-sensitive tleid-effect transistor (iSFET) device by using Complementary meia!-oxide-semiconductor (CMOS) compatible, the method includes the steps of marking and etching a silicon layer, depositing an oxide layer, implanting a p-well pattern on the silicon and oxide layers, implanting a channel pattern onto the silicon and oxide layers, implanting N+ source and drain pattern onto the silicon and oxide layers, implanting P+ diffusion pattern onto the silicon and oxide layers, removing the oxide layer, adding a bottom oxidation layer, depositing a silicon nitride layer, adding a contact hole pattern, sputtering metal 1 onto contact hole pattern, silicon nitride layer and the bottom oxidation layer and etching a metal 1 pattern on the sputtered metal such that the method forms a mask design includes a combination of ISFET and metal- oxide-semiconductor field-effect transistor ( OSFET) dice on a single site. .
The present invention consists of several novel features and a combination of parts hereinafter fully described and illustrated in the accompanying description and drawings, it being understood that various changes In the details may be made without departing from the scope of the invention or sacrificing any of the advantages of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be fui!y understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration oniy, and thus are not limitative of the present invention, wherein:
Figure 1 shows a h!ock diagram of a method of method of fabricating ion-sensitive field- effect transistor (1SF6T) device by using Complementary metah-oxide-semiconductor (CMOS) compatible in the present embodiment of the invention;
Figure 2 shows a cross section of a device fabricated using the method in the present embodiment of the invention:
Figure 3 shows a cross section of a MOSFET device to be used as test structure In the method:
Figure 4 shows a cross section of a die Including 1 ISFET devices and 1 MOSFET device; Figure 5 shows contact points of SSFET and MOSFET devices;
Figure 8 shows a layout design of an ISFET device with a window opening for sensing area; Figure 7 shows an enlarged view of an ISFET sensing area; and Figure 8 shows a wafer map with 125 dice. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention reiates to a method of fabricating ion-sensitive field-effect transistor (ISFET) device by using Complementary metai-oxide-semlconductor (CMOS) compatible. Hereinafter, this specification will describe the present invention according to the preferred embodiment of the present Invention. However, it is to be understood that limiting the description to the preferred embodiment of the invention is merely to facilitate discussion of the present invention and it Is envisioned that those skilled in the art may devise various modifications and equivalents without departing from the scope of the appended claims.
The following detailed description of the preferred embodiment will now be described in accordance with the attached drawings, either individually or in combination, Figure 1 illustrates a method of fabricating Ion-sensitive field-effect transistor (iSFET) device by using Complementary metai-oxide-semiconductor (CMOS) compatible. The method includes the steps of marking and etching a silicon layer (101), depositing an oxide layer (102), implanting a p-vveli pattern on the silicon and oxide layers (101 , 102), implanting a channel pattern onto the silicon and oxide layers (101 , 102), implanting N+ source and dram pattern onto the silicon and oxide layers (101 , 102), implanting P+ diffusion pattern onto the silicon and oxide layers (101 , 02), removing the oxide layer (102), adding a bottom oxidation layer (103), depositing a silicon nitride layer (104), adding a contact hole pattern (105), sputtering metal 1 onto contact ho!e pattern (105), silicon nitride iayer (104) and the bottom oxidation iayer (103) and etching a metal 1 pattern on the sputtered metal such that the method forms a mask design includes a combination of ISFET and metai-oxide- semiconductor field-effect transistor ( OSFET) dice on a single site. . The fabrication method uses 8 lithography mask layers which include siiicon mark etch pattern, P-weii implant pattern, N* source and drain pattern, P+ diffusion pattern, contact hoie pattern and Metal 1 pattern. The method as described above uses a CMOS compatibie process rlow, The additional steps of low pressure chemical vapor deposition (LPCVD) bottom oxidation and LPCVD silicon nitride deposition together with post nitride deposition with nitrogen annealing ensures t si the fabrication is CMOS compatible.
An ISFET sensing membrane includes a thin layer film less than 1000 Angstrom deposited by low pressure chemical vapour deposition (LPCVD) high temperature silicon nitride and a thin layer film !ess than 1000 Angstrom deposited by LPCVD high temperature bottom silicon oxide.
The rneta! etching process Is done on the silicon nitride sensing membrane which is done In a reactive ion etcher. The metal is etched at a pressure between 8 and 18 m'T in a plasma containing Ci* gas at a flow rate about 50 and 120 seem, BCL3 gas at flow rate about 30 and 50 seem, CHF gas at flow rate about 5 seem and Argon gas at flow rate about 50 seem.
The method as described above uses MOSFET as a test structure in each image lithography shot. In ISFET devices, electric current (Id) flows from source to drain via channel. Like in MOSFET, channel resistance depends on electric field perpendicular to the direction of the current. Channel resistance also depends on potential difference over silicon nitride gate. Therefore, source-drain current, id, is influenced by the interface potential at the silicon nitride/aqueous solution. Although the electric resistance of the channel provides a measure for the silicon nitride potential, the direct measurement of this resistance gives no indication of the absolute value of this potential. However at a fixed source-drain potential (Vds), changes in the gate potential can be compensated by modu!ation of the Vgs. This adjustment should be carried out in such a way that the changes in Vgs applied to the reference electrode are exactly opposite to the changes in the gate oxide potential. This is automatically performed by !SFET amplifier with feedback which aiiows obtaining constant source-drain current, !n this particular case, the gate-source potential is determined by the surface potential at the insulator/electrolyte interface. The selectivity and chemical sensitivity of the ISFET are completely controlled by the properties of the electrolyte/insulator interface.
Figure 2 shows a complete ISFET device as fabricated by the method described above in comparison to Figure 3 that shows a complete MOSFET device.
Figure 4 shows a mask design which is a combination of ISFET and metal-oxide- semiconductor field-effect transistor (MOSFET) dice on a single site. In this example In Figure 4, there are 14 ISFET and 1 MOSFET die on a single site. Figure 5 shows contact points of ISFET and MOSFET devices.
Figure 6 shows a layout design of ISFET which has a window opening for sensing area after encapsulation to facilitate sensing process. Figure 7 specifically points to an ISFET sensing area. Figure 8 shows an example of a wafer map that includes 125 dice. It is to be appreciated that the method as decribed herein improves existing fabrication process flow of ISFET devices by using CMOS compatible by optimizing metal etch recipe and including MOSFET test structures.

Claims

1. A method of fabricating ion-sensitive field-effect transistor (ISFET) device by using Complementary mefal-~oxlde~semiconductor (CMOS) compatible, the method includes the steps of:
i. marking and etching a silicon layer (101);
ii. depositing an oxide layer (102):
iii. implanting a p-wel! pattern on the silicon and oxide layers (101. 102);
iv. implanting a channel pattern onto the silicon and oxide layers (101 , 102);
v. implanting + source and drain pattern onto the silicon and oxide layers (101 , 102):
vi. implanting P+ diffusion pattern onto the silicon and oxide layers (101 , 102);
vis. removing the oxide layer (102);
viii. adding a bottom oxidation layer (103);
ix. depositing a silicon nitride layer (104);
x. adding a contact hole pattern (105);
xi. sputtering metal 1 onto contact hole pattern (105), silicon nitride layer (104) and the bottom oxidation layer (103); and
xii. etching a metal 1 pattern on the sputtered metal;
such that the method forms a mask design includes a combination of ISFET and metal-oxide-semiconductor field-effect transistor (MOSFET) dice on a single site.
2, The method as claimed in claim 1. wherein the method uses 8 lithography mask layers which include silicon mark etch pattern, P-vveli implant pattern, N+ source and drain pattern, P+ diffusion pattern, contact hole pattern and Metal 1 pattern,
3. The method as claimed in claim 1 , wherein the method further includes steps of low pressure chemical vapor deposition (LPCVD) bottom oxidation and LPCVD silicon nitride deposition together with post nitride deposition with nitrogen annealing ensures that fabrication is CMOS compatible.
The method as claimed in claim 1 , wherein the metal etching step is done on the silicon nitride sensing membrane which is done in a reactive ion etcher.
The method as claimed in claim 1 , wherein MOSFET is used as a test structure In each image lithography shot.
The method as claimed in claim 1 , wherein selectivity and chemical sensitivity of the !SFET are completely controlled by properties of electrolyte/insulator interface.
The method as claimed in claim 1 , wherein the method further includes adding a window opening for sensing area after encapsulation.
PCT/MY2014/000091 2013-05-21 2014-05-05 A cmos method of fabricating a combination of an ion sensitive field effect transistor (isfet) and mosfet device WO2014189360A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI2013700830 2013-05-21
MYPI2013700830A MY163969A (en) 2013-05-21 2013-05-21 A method of fabricating ion sensitive field effect transistor (isfet) device

Publications (1)

Publication Number Publication Date
WO2014189360A1 true WO2014189360A1 (en) 2014-11-27

Family

ID=51261196

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/MY2014/000091 WO2014189360A1 (en) 2013-05-21 2014-05-05 A cmos method of fabricating a combination of an ion sensitive field effect transistor (isfet) and mosfet device

Country Status (2)

Country Link
MY (1) MY163969A (en)
WO (1) WO2014189360A1 (en)

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
BOUSSE L ET AL: "A process for the combined fabrication of ion sensors and CMOS circuits", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 9, no. 1, 1 January 1988 (1988-01-01), pages 44 - 46, XP011406588, ISSN: 0741-3106, DOI: 10.1109/55.20408 *
CANE C ET AL: "Compatibility of ISFET and CMOS technologies for smart sensors", TRANSDUCERS. SAN FRANCISCO, JUNE 24 - 27, 1991; [PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON SOLID STATE SENSORS AND ACTUATORS], NEW YORK, IEEE, US, vol. CONF. 6, 24 June 1991 (1991-06-24), pages 225 - 228, XP010037246, ISBN: 978-0-87942-585-2, DOI: 10.1109/SENSOR.1991.148843 *
HASHIM U ET AL: "Silicon nitride gate ISFET fabrication based on four mask layers using standard MOSFET technology", SEMICONDUCTOR ELECTRONICS, 2008. ICSE 2008. IEEE INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 25 November 2008 (2008-11-25), pages 626 - 628, XP031415503, ISBN: 978-1-4244-3873-0 *
KWON D H ET AL: "A very large integrated pH-ISFET sensor array chip compatible with standard CMOS processes", SENSORS AND ACTUATORS B: CHEMICAL: INTERNATIONAL JOURNAL DEVOTED TO RESEARCH AND DEVELOPMENT OF PHYSICAL AND CHEMICAL TRANSDUCERS, ELSEVIER S.A, CH, vol. 44, no. 1-3, 1 October 1997 (1997-10-01), pages 434 - 440, XP004117157, ISSN: 0925-4005, DOI: 10.1016/S0925-4005(97)00207-4 *

Also Published As

Publication number Publication date
MY163969A (en) 2017-11-15

Similar Documents

Publication Publication Date Title
US11008611B2 (en) Double gate ion sensitive field effect transistor
CN103296027B (en) Using the simulation floating gate memory manufacturing process of N-channel and P channel MOS transistor
TW586228B (en) Method for fabricating a titanium nitride sensing membrane on an EGFET
US20060035400A1 (en) Apparatus of ion sensitive thin film transistor and method of manufacturing of the same
CN104950023A (en) TFT ion sensor and TFT ion sensor apparatus using the same
US20050186697A1 (en) Fabrication method of an ion sensitive field effect transistor
CN104614430A (en) Fet sensing cell and method of improving sensitivity of the same
US7009376B2 (en) SnO2 ISFET device, manufacturing method, and methods and apparatus for use thereof
Khanna Fabrication of ISFET microsensor by diffusion-based Al gate NMOS process and determination of its pH sensitivity from transfer characteristics
US20180340901A1 (en) Gas sensor platform and the method of making the same
US6867059B2 (en) A-C:H ISFET device manufacturing method, and testing methods and apparatus thereof
JP2016103577A (en) Semiconductor biosensor device
CN104051512B (en) The back side sensing biological field effect transistor of performance enhancement
CN101022105B (en) Semiconductor device testing device and substrate for producing tester
Mahfoz-Kotb et al. Air-gap polycrystalline silicon thin-film transistors for fully integrated sensors
WO2014189360A1 (en) A cmos method of fabricating a combination of an ion sensitive field effect transistor (isfet) and mosfet device
WO2009064166A2 (en) An integrated ion sensitive field effect transistor sensor
CN108732225B (en) Ion sensitive field effect transistor and forming method thereof
Sinha et al. Simulation, fabrication and characterization of Dual-Gate MOSFET test structures
Chaudhary et al. Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si 3 N 4 ISFET
JPH06288972A (en) Ion sensor and ion measuring method
US11567026B2 (en) PH sensor
Zhang et al. Cmos 3d-extended metal gate isfets with near nernstian ion sensitivity
KR100958623B1 (en) Method for measuring depth of depletion region in trasistor, pattern for measuring the depth, and method for manufacturing the pattern
WO2011049428A1 (en) Inverted isfet

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14745243

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14745243

Country of ref document: EP

Kind code of ref document: A1