WO2014182120A1

WO2014182120A1 - Method for forming through-electrode of interposer substrate, and semiconductor package including interposer substrate

Info

Publication number: WO2014182120A1
Application number: PCT/KR2014/004151
Authority: WO
Inventors: 조수제; 전인균
Original assignee: 주식회사 옵토레인
Priority date: 2013-05-09
Filing date: 2014-05-09
Publication date: 2014-11-13
Also published as: KR101468680B1; KR20140133022A

Abstract

Disclosed are a method for forming a through-electrode of an interposer substrate, and a semiconductor package including the interposer substrate. The method for forming a through-electrode of an interposer substrate, according to the present invention, comprises the steps of: preparing a photosensitive glass substrate having a hole; and forming a through-electrode by filling the hole with a molten metal.

Description

A method of forming a through electrode of an interposer substrate and a semiconductor package including an interposer substrate

The present invention relates to a method of forming a through electrode of an interposer substrate and a semiconductor package including an interposer substrate.

The recent trend of the electronics industry is to manufacture products with high reliability and low cost, which are becoming lighter, smaller, faster, more versatile, and more efficient. One important technology that enables this is the semiconductor package assembly technology. In order to cope with these recent trends, development of 3D packaging technology for three-dimensional stacking of semiconductor chips has been actively performed. In particular, a stacking technology for electrically connecting semiconductor chips using an interposer substrate including a through electrode has been attracting attention as an advantageous technology for implementing high performance and miniaturization of electronic products.

Conventional interposer substrates are mainly implemented in silicon. However, when silicon is used as the interposer substrate, it takes a long time and a cost to form the through electrode.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor package including a method of forming a through electrode of an interposer substrate using photosensitive glass and an interposer substrate using photosensitive glass.

A method of forming a through electrode of an interposer substrate according to an embodiment of the present invention includes preparing a photosensitive glass substrate having a hole formed therein, and forming a through electrode by filling a molten metal into the hole.

The method of forming a through electrode of the interposer substrate may further include protruding the through electrode by etching at least one of a front surface and a rear surface of the photosensitive glass substrate.

The photosensitive glass substrate may include photosensitive glass in a crystalline state.

The photosensitive glass substrate may be crystallized by being exposed to ultraviolet rays and heat treated at 570 degrees Celsius to 800 degrees Celsius.

The molten metal may be a metal or alloy including at least one of tin, lead, silver, copper, gold, zinc, and aluminum.

Melting temperature of the molten metal may be more than 200 degrees Celsius or less than 600 degrees Celsius.

The filling of the molten metal into the hole may further include forming a metal thin film in the hole before filling the molten metal into the hole.

The metal thin film may be a metal, an alloy, or a multilayer film including at least one of nickel, copper, gold, silver, tin, and aluminum.

The method of forming a through electrode of the interposer substrate may further include polishing at least one of a front surface and a rear surface of the photosensitive glass substrate filled with the holes before protruding the through electrode.

Etching at least one of the front and rear surfaces of the photosensitive glass substrate to protrude the through electrode may include etching at least one of the front and rear surfaces of the photosensitive glass substrate with an aqueous hydrofluoric acid solution.

The method of forming a through electrode of the interposer substrate may further include protruding the through electrode and then applying heat to the through electrode to round the protruding portion of the through electrode.

According to another aspect of the present invention, a method of forming a through electrode of an interposer substrate includes filling a metal material into a hole of a photosensitive glass substrate on which a hole is formed to form a through electrode, and at least one of a front surface and a rear surface of the photosensitive glass substrate. Etching to protrude the through electrode.

The filling of the metal material in the hole may include cooling the molten metal after filling the molten metal in which the metal material is molten.

A method of forming a ball grid array according to another embodiment of the present invention may include the method of forming a through electrode.

According to another embodiment of the present invention, a semiconductor package includes a printed circuit board, at least one or more semiconductor chips, and a plurality of semiconductor chips, interposed between the plurality of semiconductor chips, or between the semiconductor chip and the printed circuit board. And an interposer layer interposed therebetween, wherein the interposer layer may include at least one interposer substrate.

The interposer layer may be interposed between the semiconductor chip and the printed circuit board, and the interposer substrate included in the interposer layer may be a ball grid array.

According to the embodiment of the present invention, the through electrode can be more easily formed by using the photosensitive glass as the interposer substrate, and the time and cost required for packaging can be reduced.

1 illustrates a semiconductor package according to an embodiment of the present invention.

2 to 8 are cross-sectional views sequentially illustrating an embodiment of forming a through electrode in the interposer substrate of FIG. 1.

9 through 16 are cross-sectional views sequentially illustrating another embodiment of forming a through electrode on the interposer substrate of FIG. 1.

17 is a flowchart illustrating a method of forming a through electrode of an interposer substrate according to embodiments of the present invention.

18 illustrates a semiconductor package according to another embodiment of the present invention.

19 illustrates a semiconductor package according to another embodiment of the present invention.

20 illustrates a semiconductor package according to another embodiment of the present invention.

21 illustrates a semiconductor package according to another embodiment of the present invention.

Specific structural or functional descriptions of the embodiments according to the inventive concept disclosed herein are provided for the purpose of describing the embodiments according to the inventive concept only. It may be embodied in various forms and is not limited to the embodiments described herein.

Embodiments according to the inventive concept may be variously modified and have various forms, so embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments in accordance with the concept of the invention to the specific forms disclosed, it includes all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The terms are only for the purpose of distinguishing one component from another, for example, without departing from the scope of the rights according to the inventive concept, the first component may be named a second component, and similarly The second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If a layer is said to be "on" another layer or substrate, or if a layer is said to be bonded or bonded to another layer or substrate, it may be formed directly on the other layer or substrate or a third layer therebetween. This may be intervened. Portions denoted by like reference numerals denote like elements throughout the specification.

The terms top, bottom, top, bottom, front, back, or top, bottom, etc. are used to distinguish relative positions in the components. For example, in the case of naming the upper part on the drawing as the upper part and the lower part on the drawing for convenience, the upper part may be called the lower part and the lower part may be named the upper part without departing from the scope of the present invention. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, the semiconductor package 1 may include a first chip 30, a second chip 40, and an interposer substrate 10.

The first chip 30 and the second chip 40 may be semiconductor chips, for example, a dynamic random access memory (DRAM), a NAND flash memory, a NOR flash memory, a CMOS image sensor ( CMOS Image Sensor (CIS), Digital Signal Processor (DSP), Backside Illuminated CIS, Radio Frequency (RF) System, Analog System, Microelectromechanical Systems (MEMS), Microprocessor Unit (Micro Processor Unit; MPU), Application Specific Integrated Circuit (ASIC), and the like.

The first chip 30 and the second chip 40 may be stacked to increase the storage capacity of the semiconductor package 1.

When the sizes of the first chip 30 and the second chip 40 are different from each other, it is difficult to directly connect the first chip 30 and the second chip 40 using conductive wires. Therefore, the interposer substrate 10 may be interposed between the first chip 30 and the second chip 40 to electrically connect the first chip 30 and the second chip 40.

The interposer substrate 10 may be a photosensitive glass substrate. The interposer substrate 10 may include at least one through electrode 20. The first chip 30 and the second chip 40 may be electrically connected by the through electrode 20.

In FIG. 1, the through electrode 20 protrudes in the front and rear directions of the interposer substrate 10, and the interposer substrate 10, the first chip 30, and the second chip 40 are formed by the through electrode 20. ) Is shown to be combined, but the scope of the present invention is not limited thereto. In some embodiments, the through electrode 20 may protrude only in one of the front and rear surfaces of the interposer substrate 10, and in some embodiments, the through electrode 20 may not protrude in the front and rear directions. have. The interposer substrate 10, the first chip 30, and the second chip 40 may be connected through a bump electrically connected to the through electrode 20.

In addition, although the interposer substrate 10 is illustrated to be interposed between the first chip 30 and the second chip 40 in FIG. 1, the scope of the present invention is not limited thereto. In some embodiments, the interposer substrate may be interposed between the chip and the ball grid array (BGA). According to another embodiment, the interposer substrate may be implemented as a ball grid array, and may be interposed between the chip and the printed circuit board (PCB).

Referring to FIG. 2, a photosensitive glass substrate 100 having at least one through hole 110 is provided. Photosensitive glass is generally a transparent glassy state, but the crystal state may be made opaque due to exposure and heat treatment processes. The photosensitive glass substrate 100 may include photosensitive glass in a glass state or a crystalline state.

The method of forming the through hole 110 in the photosensitive glass substrate 100 may vary. According to the exemplary embodiment, after the crystallization is performed by exposing and heat-treating the region to form the through hole 110 in the glass photosensitive glass substrate 100, the through region may be formed by removing the crystal region. An aqueous hydrofluoric acid solution containing hydrogen fluoride (HF) may be used to remove the crystal region.

Assuming that the through-hole is formed in the silicon substrate, since the silicon is a semiconductor, the silicon must be insulated. Through-holes must be formed individually using a laser, which requires a lot of time and requires expensive process equipment.

In the present invention, since the photosensitive glass substrate is used, the through hole can be made small by crystallizing a region in which the through hole is to be formed and then removing it using an aqueous solution containing hydrogen fluoride (HF). In addition, through-holes can be formed at one time, and no additional insulation treatment is required, thereby reducing the time and cost required for packaging.

Referring to FIG. 3, the photosensitive glass substrate 100 may be exposed to ultraviolet rays and then heat-treated to crystallize. The temperature during the heat treatment may be 570 degrees Celsius to 800 degrees Celsius. When heat treated at about 580 degrees Celsius, the photosensitive glass substrate 100 may be in a metastable crystal state. When heat-treated at 750 degrees Celsius or more, the photosensitive glass substrate 100 may be in a stable crystal state.

However, according to the embodiment, the photosensitive glass substrate 100 may be crystallized, and the subsequent process may be performed using the photosensitive glass substrate in a glass state.

Referring to FIG. 4, a metal seed layer 120 is formed on the surface of the photosensitive glass substrate 100. Since it is difficult to directly adhere the metal material to the photosensitive glass or the like, the metal seed layer 120 is used to fill the metal material with no empty space in the through-hole 110. In some embodiments, the metal seed layer 120 may be an alloy or a multilayer including one or more kinds of nickel, copper, gold, silver, tin, and the like. When the molten metal to be filled in the through hole 110 includes aluminum, the metal seed layer 120 may be an aluminum thin film or an alloy including the same.

The metal seed layer 120 may be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Physical vapor deposition is a method of coating a gasified material in a vacuum on a base surface, which is divided into vacuum deposition and sputtering. Vacuum deposition is a method of forming a thin film by attaching metal particles to a substrate, which are heated after heating the metal under high vacuum. Sputtering refers to a process of forming a thin film on an object surface by applying an ion bombardment to a material, which causes the atoms or molecules constituting the material to stick out and adhere to the object surface around the material.

Chemical vapor deposition is a method of forming a thin film by reacting chemical bonds, source gas decomposition, etc. by applying external energy by flowing source gas on a substrate to be coated in a manufacturing process.

4 and 5, a through electrode 130 is formed by filling a metal material in the through hole 110 in which the metal seed layer 120 is formed.

According to one embodiment, the metal material may be a molten metal. After filling the molten metal into the through hole 110, the molten metal may be cooled to form the through electrode 130.

The melting temperature of the molten metal is 200 degrees Celsius or more, so that the through electrode 130 may not be affected by a subsequent process. On the other hand, the melting temperature of the molten metal can be set to 600 degrees Celsius or less so that the molten metal does not affect the photosensitive glass substrate 100.

The metal material may be a metal or an alloy containing at least one of tin, lead, silver, copper, gold, zinc, and aluminum. When using an eutectic alloy as the metal material, a low melting temperature can be obtained.

When the through electrode is formed on the silicon substrate, the SiO ₂ thin film is formed by first oxidizing the wall surface to insulate the silicon substrate. Thereafter, when the molten metal is filled in the through hole of the silicon substrate, problems such as peeling off of the SiO ₂ thin film may occur.

In the present invention, since the photosensitive glass substrate 100 is used instead of the silicon substrate, it is easy to form a through electrode by filling molten metal. Therefore, the formation cost of the through electrode is reduced, and there is an effect that various metal materials can be used as the through electrode 130.

According to another embodiment, the metal material may be filled in the through hole 110 by electroplating.

According to another exemplary embodiment, the metal materials may be silver electrical conductive pastes or solder pastes, and the through electrodes 130 may be formed by filling the metal materials in the through holes 110 and performing heat treatment.

According to another embodiment, the through hole 110 may be filled by sputtering without separately filling the metal material.

5 and 6, after filling the through hole 110 with a metal material to form the through electrode 130, the front and rear surfaces of the photosensitive glass substrate 100 may be polished and planarized. Accordingly, the metal seed layer and the metal part 140 formed on the front and rear surfaces of the photosensitive glass substrate 100 may be removed.

6 and 7, at least one of the front and rear surfaces of the photosensitive glass substrate 100 may be etched to protrude the through electrode 130. In this case, the protruding through electrode 130 may have a uniform height.

In some embodiments, an aqueous hydrofluoric acid solution may be added to at least one of the front and rear surfaces of the photosensitive glass substrate 100 to etch.

According to another embodiment, sanding may be performed on at least one of the front and rear surfaces of the photosensitive glass substrate 100. Sanding, also known as sand blasting, is a technique used to clean or polish the surface deposits by blowing sand at high speed through compressed air. Since the photosensitive glass substrate 100 is etched at a faster speed than the through electrode 130 according to the difference in the sanding resistance of the metal material and the photosensitive glass, the through electrode 130 may protrude.

Referring to FIG. 8, the protrusion of the through electrode 130 may be rounded by applying heat to the through electrode 130. According to an embodiment, the protrusion of the through electrode 130 may be hemispherical.

The photosensitive glass substrate 100 of FIG. 8 may correspond to the interposer substrate 10 of FIG. 1, and the through electrode 130 of FIG. 8 may correspond to the through electrode 20 of FIG. 1. In the subsequent process, the first chip 30 and the second chip 40 are coupled to the upper and lower portions of the photosensitive glass substrate 100, and the first chip 30 and the second chip 40 are connected to the through electrode 130. Can be electrically connected via

9, a photosensitive glass substrate 200 in a glass state may be provided. A portion 210 of the photosensitive glass substrate 200 to form at least one through electrode may be crystallized by UV exposure and heat treatment.

9 and 10, a hole 220 is formed in the photosensitive glass substrate 200. For example, an aqueous hydrofluoric acid solution may be added to the front or rear surface of the photosensitive glass substrate 200 for etching. Accordingly, the crystallized portion 210 may be etched to form a hole 220 in the photosensitive glass substrate 200.

10 and 11, the photosensitive glass substrate 200 may be exposed to ultraviolet rays and then heat-treated to crystallize. The temperature during the heat treatment may be 570 degrees Celsius to 800 degrees Celsius. However, according to the exemplary embodiment, the process may be performed without crystallizing the photosensitive glass substrate 200.

Referring to FIG. 12, the metal seed layer 240 is formed on a surface on which the hole 220 of the crystallized photosensitive glass substrate 230 is formed. In some embodiments, the metal seed layer 240 may be an alloy or a multilayer including one or more kinds of nickel, copper, gold, silver, tin, and the like. When the molten metal to be filled in the hole 220 includes aluminum, the metal seed layer 240 may be an aluminum thin film or an alloy including the same.

The metal seed layer 240 may be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

12 and 13, a through electrode 250 is formed by filling a metal material into a hole 220 in which the metal seed layer 240 is formed.

According to one embodiment, the metal material may be a molten metal. After the molten metal is filled in the hole 220, the molten metal may be cooled to form the through electrode 250.

The melting temperature of the molten metal may be 200 degrees Celsius or more and 600 degrees Celsius or less.

According to another embodiment, the metal material may be filled in the hole 220 by electroplating.

According to another embodiment, the metal materials may be silver electrical conductive pastes or solder pastes, and the through-electrodes 250 may be formed by filling the metal material in the holes 220 and performing heat treatment.

According to another embodiment, the hole 220 may be filled by sputtering without separately filling the metal material.

Referring to FIGS. 13 and 14, the front and rear surfaces of the crystallized photosensitive glass substrate 230 may be polished and planarized. In this case, the front and rear surfaces of the through electrode 250 may be exposed to the outside.

The front and back portions 260 of the photosensitive glass substrate 230 may be removed by polishing, such as a chemical mechanical polishing (CMP) process.

Referring to FIGS. 14 and 15, at least one of the front and rear surfaces of the photosensitive glass substrate 230 may be etched to protrude the through electrode 250. In this case, the protruding through electrode 250 may have a uniform height.

In some embodiments, an aqueous hydrofluoric acid solution may be added to at least one of the front and rear surfaces of the photosensitive glass substrate 230 to etch. According to another embodiment, sanding may be performed on at least one of the front and rear surfaces of the photosensitive glass substrate 230.

Referring to FIG. 16, the protrusion of the through electrode 250 may be rounded by applying heat to the through electrode 250. According to an embodiment, the protrusion of the through electrode 250 may be hemispherical.

The photosensitive glass substrate 230 of FIG. 16 may correspond to the interposer substrate 10 of FIG. 1, and the through electrode 250 of FIG. 16 may correspond to the through electrode 20 of FIG. 1. In the subsequent process, the first chip 30 and the second chip 40 are coupled to the upper and lower portions of the photosensitive glass substrate 230, and the first chip 30 and the second chip 40 are connected to the through electrode 250. Can be electrically connected via

1 and 17, the interposer substrate may be a photosensitive glass substrate 10. A through electrode 20 is formed by filling a metal material in the hole of the photosensitive glass substrate 10 (S301). The hole may be formed to penetrate the photosensitive glass substrate 10, but may also be formed so as not to penetrate the photosensitive glass substrate 10.

At least one of the upper and lower surfaces of the photosensitive glass substrate 10 is etched to protrude the through electrode 20 (S303). In the subsequent process, the plurality of

chips

30 and 40 may be coupled to the photosensitive glass substrate 10 and electrically connected to each other through the through electrode 20.

18 illustrates a semiconductor package according to another embodiment of the present invention. Since the configuration of FIG. 18 is largely the same as that shown in FIG. 1, the following description will focus on differences for convenience of description.

Referring to FIG. 18, the semiconductor package 400 may include a third chip 430, a PCB substrate 440, and a ball grid array 410.

The third chip 430 may be a single semiconductor chip, or may be a result of stacking a plurality of semiconductor chips.

The PCB substrate 440 may be a substrate on which an electronic circuit is formed of a thin copper foil on an entire surface of an insulator.

The ball grid array 410 is interposed between the third chip 430 and the PCB substrate 440, and electrically connects the third chip 430 and the PCB substrate 440 through at least one through electrode 420. do. The ball grid array 410 may be the interposer substrate shown in FIG. 8 or 16.

Referring to FIG. 19, the semiconductor package 500 may include a fourth chip 510, a fifth chip 520, a first interposer substrate 530, and a second interposer substrate 550.

Each of the fourth chip 510 and the fifth chip 520 may be a single semiconductor chip, or may be a result of stacking a plurality of semiconductor chips. The pads (not shown) of each of the fourth chip 510 and the fifth chip 520 may have different sizes.

The first interposer substrate 530 may be coupled to the fourth chip 510. The first interposer substrate 530 may include at least one through electrode 540 having a thickness corresponding to the size of a pad (not shown) of the fourth chip 510.

The second interposer substrate 550 may be coupled to the fifth chip 520. The second interposer substrate 550 may include at least one through electrode 560 having a thickness corresponding to the size of a pad (not shown) of the fifth chip 520.

The first interposer substrate 530 and the second interposer substrate 550 may be the interposer substrate illustrated in FIG. 8 or 16.

The connection circuit unit 570 may be disposed on one surface of the first interposer substrate 530. The connection circuit unit 570 may electrically connect the through

electrodes

540 and 560 of each of the first interposer substrate 530 and the second interposer substrate 550.

Therefore, pads (not shown) of each of the fourth chip 510 and the fifth chip 520 may be electrically connected through the through

electrodes

540 and 560 and the connection circuit unit 570.

Referring to FIG. 20, the semiconductor package 600 may include a sixth chip 610, a PCB substrate 620, a third interposer substrate 630, and a fourth interposer substrate 650.

The sixth chip 610 may be a single semiconductor chip, or may be a result of stacking a plurality of semiconductor chips. The PCB substrate 620 may be a substrate on which an electronic circuit is formed of a thin copper foil on an entire surface of an insulator. The pads (not shown) of each of the sixth chip 610 and the PCB substrate 620 may have different sizes.

The third interposer substrate 630 may be coupled to the sixth chip 610. The third interposer substrate 630 may include at least one through electrode 640 having a thickness corresponding to the size of a pad (not shown) of the sixth chip 610.

The fourth interposer substrate 650 may be coupled to the PCB substrate 620. The fourth interposer substrate 650 may include at least one through electrode 660 having a thickness corresponding to the size of a pad (not shown) of the PCB substrate 620.

The third interposer substrate 630 and the fourth interposer substrate 650 may be the interposer substrate illustrated in FIG. 8 or 16. The fourth interposer substrate 650 may be a ball grid array.

The connection circuit unit 670 may be disposed on one surface of the third interposer substrate 630. The connection circuit unit 670 may electrically connect the through

electrodes

640 and 660 of each of the third interposer substrate 630 and the fourth interposer substrate 650.

Therefore, pads (not shown) of each of the sixth chip 610 and the PCB substrate 620 may be electrically connected through the through

electrodes

640 and 660 and the connection circuit unit 670.

Referring to FIG. 21, the semiconductor package 700 may include a seventh chip 710, an eighth chip 720, a PCB substrate 730, a fifth interposer substrate 740, a sixth interposer substrate 760, and the like. The seventh interposer substrate 790 may be included.

The seventh chip 710 and the eighth chip 720 may be a single semiconductor chip, or may be a result of stacking a plurality of semiconductor chips. The PCB substrate 730 may be a substrate on which an electronic circuit is formed of a thin copper foil on an entire surface of an insulator. The pads (not shown) of the seventh chip 710, the eighth chip 720, and the PCB substrate 730 may have different sizes.

The fifth interposer substrate 740 may be coupled to the seventh chip 710. The fifth interposer substrate 740 may include at least one through electrode 750 having a thickness corresponding to the size of a pad (not shown) of the seventh chip 710.

The sixth interposer substrate 760 may be coupled to the eighth chip 720. The sixth interposer substrate 760 may include at least one through electrode 770 having a thickness corresponding to the size of a pad (not shown) of the eighth chip 720.

The connection circuit unit 780 may be disposed on one surface of the fifth interposer substrate 740. The connection circuit unit 780 may electrically connect the through

electrodes

750 and 770 of each of the fifth interposer substrate 740 and the sixth interposer substrate 760.

The seventh interposer substrate 790 is interposed between the eighth chip 720 and the PCB substrate 730, and electrically connects the third chip 430 and the PCB substrate 440 through at least one through electrode 795. Connect with

The fifth interposer substrate 740, the sixth interposer substrate 760, and the seventh interposer substrate 790 may be the interposer substrate illustrated in FIG. 8 or 16. The seventh interposer substrate 790 may be a ball grid array.

Accordingly, pads (not shown) of each of the seventh chip 710, the eighth chip 720, and the PCB substrate 730 may be electrically connected through the through

electrodes

740, 760, and 795 and the connection circuit unit 780. have.

21 illustrates an interposer layer in which a plurality of interposer substrates are stacked between a semiconductor chip and a semiconductor chip, and one interposer substrate is interposed between the semiconductor chip and the PCB substrate. It is not limited to this. An interposer layer in which one interposer substrate or a plurality of interposer substrates are stacked may be interposed between the semiconductor chip and the semiconductor chip. In addition, an interposer layer in which one interposer substrate or a plurality of interposer substrates are stacked may be interposed between the semiconductor chip and the PCB substrate.

Although the preferred embodiments have been illustrated and described above, the invention is not limited to the specific embodiments described above, and does not depart from the gist of the invention as claimed in the claims. Of course, various modifications can be made by the operator, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

The invention is applicable to industries related to semiconductor manufacturing and assembly.

Claims

Providing a photosensitive glass substrate having holes formed thereon; And

Forming a through electrode by filling a molten metal into the hole;
The method of claim 1, wherein the through electrode forming method of the interposer substrate is performed.

And etching the at least one of the front and rear surfaces of the photosensitive glass substrate to protrude the through electrode.
The method of claim 1, wherein the photosensitive glass substrate

A method of forming a through electrode of an interposer substrate comprising photosensitive glass in a crystalline state.
The method of claim 3, wherein the photosensitive glass substrate

A method of forming a through electrode of an interposer substrate, wherein the interposer substrate is exposed to ultraviolet rays and heat-treated at 570 degrees Celsius to 800 degrees Celsius.
The method of claim 1, wherein the molten metal

A method of forming a through electrode of an interposer substrate, which is a metal or an alloy comprising at least one of tin, lead, silver, copper, gold, zinc and aluminum.
The method of claim 5, wherein the melting temperature of the molten metal is

A method of forming a through electrode of an interposer substrate of 200 degrees Celsius or more and 600 degrees Celsius or less.
The method of claim 1, wherein filling the hole with molten metal

The method of forming a through electrode of an interposer substrate further comprises forming a metal thin film in the hole before the molten metal is filled in the hole.
The method of claim 7, wherein the metal thin film

A method for forming a through-electrode of an interposer substrate, which is a metal, alloy or multilayer film containing at least one of nickel, copper, gold, silver, tin and aluminum.
The method of claim 2, wherein the through-electrode forming method of the interposer substrate

And grinding at least one of a front surface and a rear surface of the photosensitive glass substrate filled with the holes before protruding the through electrode.
The method of claim 2, wherein etching the at least one of the front side and the rear side of the photosensitive glass substrate to protrude the through electrode comprises:

And etching at least one of the front and rear surfaces of the photosensitive glass substrate with an aqueous hydrofluoric acid solution.
The method of claim 2, wherein the through-electrode forming method of the interposer substrate

And protruding the through electrode and applying heat to the through electrode to round the protruding portion of the through electrode.
Forming a through electrode by filling a metal material in the hole of the photosensitive glass substrate on which the hole is formed; And

And etching at least one of a front surface and a rear surface of the photosensitive glass substrate to protrude the through electrode.
The method of claim 12, wherein filling the hole with a metal material

And filling the hole with the molten metal in which the metal material is molten, and then cooling the molten metal.
Printed circuit board;

At least one semiconductor chip; And

When the number of the semiconductor chip is a plurality of interposed between the plurality of semiconductor chips, or between the semiconductor chip and the printed circuit board includes an interposer layer,

The interposer layer is

A semiconductor package comprising at least one interposer substrate of claim 1.
15. The method of claim 14, wherein the interposer layer is

Interposed between the semiconductor chip and the printed circuit board,

The interposer substrate included in the interposer layer

A semiconductor package that is a ball grid array.