WO2014172895A1

WO2014172895A1 - Deinterleaving method and communications system

Info

Publication number: WO2014172895A1
Application number: PCT/CN2013/074805
Authority: WO
Inventors: 金丽丽; 喻凡; 肖治宇; 常德远
Original assignee: 华为技术有限公司
Priority date: 2013-04-26
Filing date: 2013-04-26
Publication date: 2014-10-30
Also published as: CN103718490A

Abstract

The present invention provides a deinterleaving method and a communications system. The method comprises: an analog-to-digital converter performing analog-to-digital conversion on first symbol information sent by a sending end, so as to obtain second symbol information; a deinterleaver deinterleaving the second symbol information by using the symbol as a unit, so as to obtain third symbol information; a demodulator demodulating the third symbol information, so as to obtain floating point information represented in bit mode; and a soft decision forward error correction (FEC) decoder decoding the floating point information, and outputting bit data. Technical solutions provided in the present invention are used for reducing a quantity of an occupied logic resource of a deinterleaver, and reduces the implementation cost of the deinterleaver.

Description

Method for deinterlacing and communication system

The present invention relates to the field of communications, and in particular, to a method and a communication system for deinterleaving. Background technique

In the communication system, the burst noise existing in the channel may cause burst error; the FEC (Forward Error Correction) system includes the FEC encoder and the FEC decoder, although the FEC system has certain corrections. Burst error capability, but when there are more burst errors, it will exceed the error correction capability of the FEC system, which will lead to the spread of burst errors, and the FEC system will not work properly.

At present, the interleaver is generally used to solve the problem of bursting errors. Please refer to the working principle diagram of the interleaver shown in FIG. 1. The interleaver "breaks" successive burst errors into different FEC codewords. The burst error amount in each codeword is made smaller than the correction burst error capability of the FEC system.

In the communication system of the current interleaver, the data processed by the interleaver and the deinterleaver are bit data, and the traditional interleaving processing method and deinterleaving processing method are suitable for the hard-decision FEC communication system and the low modulation mode (such as BPSK (Binary Phase Shift Keying), QPSK (Quadature Phase Shift Keying), 16-QAM (Quadature Amplitude Modulation), soft-decision FEC communication system, When applied to a soft decision FEC communication system with high modulation mode (such as 64-QAM, 256-QAM, 512-QAM), such as LDPC (Low-Density Parity-Check Code) communication system with modulation mode of 256-QAM The bit data processed by the decoder is floating point information, and each symbol information is demodulated by the demodulator to obtain M floating point information, such as M of the 256-QAM demodulator is equal to 8, each floating point information To be represented by N bits, then each After the demodulation, the symbol information is changed from the original 2 Ν 比特 bits (including the real part and the imaginary part) to Μ χ Ν bits. The deinterleaver needs to process a large amount of data, which will occupy a large amount of logic resources, so that the deinterleaving The implementation complexity of the device is high, and the cost of deinterleaving is high.

Summary of the invention

In view of this, the embodiment of the present invention provides a de-interleaving method and a communication system, so as to reduce the logic resource occupation of the deinterleaver and reduce the implementation cost of the deinterleaver.

In a first aspect, an embodiment of the present invention provides a method for deinterleaving, including: performing, by an analog-to-digital converter, analog-to-digital conversion on a first symbol information sent by a transmitting end to obtain second symbol information;

Deinterleaver deinterleaving the second symbol information in units of symbols to obtain third symbol information;

Demodulating the third symbol information to obtain floating point information expressed in bits;

Soft Decision Forward Error Correction The FEC decoder decodes the floating point information and outputs bit data.

In a first possible implementation manner of the first aspect, the deinterleaver performs deinterleaving processing on the second symbol information by using a symbol unit:

Receiving the second symbol information from an analog to digital converter;

And storing, in the receiving order, the mth symbol in the second symbol information into the jth row of the i th random memory RAM until all symbols are stored in the RAM; when m is an integer multiple of n, i= n, j=m/n; when m is not an integer multiple of n, i=m%n, j=[m/n+l], where [] denotes rounding; where m, n, i and j are positive Integer, n is the total RAM number;

Extract all the symbols in the RAM in turn, after extracting all the symbols in a RAM, All symbols in the next RAM are extracted again until all the symbols are extracted; the extracted symbols are sent to the demodulator as the third symbol information in the extraction order. In a second possible implementation manner of the first aspect, the demodulator demodulates the third symbol information to obtain floating-point information in a bit manner, specifically:

Receiving the third symbol information sent by the deinterleaver;

Decoding the constellation point into floating point information according to a quantization bit width of the constellation point, using each symbol in the third symbol information as a constellation point in a constellation corresponding to a modulation mode of the demodulator, Floating point information expressed in bits.

In a second aspect, an embodiment of the present invention provides a deinterleaving communication system, including: an analog to digital converter, a deinterleaver, a demodulator, and a soft decision forward error correction FEC decoder:

An analog-to-digital converter, configured to perform analog-to-digital conversion on the first symbol information sent by the transmitting end, to obtain second symbol information;

a deinterleaver, configured to deinterleave the second symbol information in units of symbols to obtain third symbol information;

a demodulator, configured to demodulate the third symbol information to obtain floating point information expressed in bits;

A soft decision FEC decoder is used to decode the floating point information and output bit data. In a first possible implementation manner of the second aspect, the deinterleaver specifically includes: a receiving unit, a storage unit, an extracting unit, and a sending unit:

a receiving unit, configured to receive the second symbol information from an analog to digital converter;

a storage unit, configured to store the mth symbol in the second symbol information into the jth row of the i th random memory RAM according to the receiving order, until all symbols are stored in the RAM; when m is an integer of n When times, i=n, j=m/n; when m is not an integer multiple of n, i=m%n, j=[m/n+l] , where [] denotes rounding; where m, n, i, and j are positive integers, and n is the total RAM number;

The extracting unit is configured to sequentially extract all the symbols in the RAM, extract all the symbols in one RAM, and then extract all the symbols in the next RAM until all the symbols are extracted;

And a sending unit, configured to send the extracted symbol as the third symbol information to the demodulator according to the extraction order.

In a second possible implementation manner of the second aspect, the demodulator specifically includes a receiving unit and a demapping unit:

a receiving unit, configured to receive the third symbol information sent by the deinterleaver;

a demapping unit, configured to use each symbol in the third symbol information as a constellation point in a constellation corresponding to a modulation mode of the demodulator, and demap the constellation point according to a quantization bit width of a constellation point The floating point information is obtained, and the floating point information expressed in bits is obtained.

With the above technical solution, the deinterleaver is placed in front of the demodulator, and the symbol information is deinterleaved in units of symbols instead of deinterleaving the demodulated bit data, so the amount of data input to the deinterleaver is greatly Reduced, thereby reducing the amount of logic resources occupied by the deinterleaver, reducing the implementation complexity of the deinterleaver and the implementation cost of the deinterleaving process.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without paying creative labor.

1 is a schematic diagram of the working principle of an interleaver; schematic diagram;

3 is a schematic diagram of a soft decision communication system in a high modulation mode according to an embodiment of the present invention; and FIG. 4 is a diagram showing an example in which an interleaver performs interleaving processing on bit data obtained after coding in units of symbols;

FIG. 5 is a schematic flowchart diagram of a method for deinterleaving according to an embodiment of the present invention;

6 is a schematic diagram of a transmitting end of a microwave 4 4 MIMO communication system according to an embodiment of the present invention. FIG. 7 is a schematic diagram of a receiving end of a microwave 4 4 MIMO communication system according to an embodiment of the present invention; FIG. 8 is a deinterleaving communication system according to an embodiment of the present invention; FIG. 9 is a schematic structural diagram of a deinterleaving communication system according to an embodiment of the present invention.

detailed description

In order to better understand the technical solutions of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The embodiment of the present invention provides a method for deinterleaving. In the method of deinterleaving, the input bit data needs to be processed at the transmitting end, and then deinterleaved by the receiving end; please refer to the schematic diagram; The method includes the following steps:

Step 201, the soft decision FEC encoder encodes the bit data.

Specifically, please refer to FIG. 3 , which is a schematic diagram of a soft decision high modulation communication system according to an embodiment of the present invention. At the transmitting end, a soft decision FEC encoder receives signal source data, and uses a signal source. The bit data ^, ..., ― ^^ ^ in the data is subjected to encoding processing, and the bit data obtained by the encoding process is transmitted to the interleaver; in this embodiment, the soft decision FEC encoder may be LDPC coded. Or Turbo code encoder, but not limited to these two encoders.

The LDPC encoder is taken as an example to illustrate the method of encoding the bit data by the soft decision FEC encoder: The signal source data is input to the LDPC encoder, and the LDPC encoder is a linear block code, and each bit data in the source data is compared with the generation matrix. Multiply the corresponding check code to obtain the check code and the bit data to form an LDPC code word, and the LDPC code word is the bit data after the encoding process.

Step 202: The interleaver performs interleaving processing on the encoded bit data in units of symbols.

Specifically, referring to FIG. 3, the interleaver receives the encoded bit data ^''''' ^^ ² , ^-1 from the soft decision FEC encoder, and then uses the symbol in the modulation mode of the modulator. The number of bits included is in units of the symbol size corresponding to the modulation method, and the received bit data is stored in a RAM (Random Access Memory) until all the bit data is stored in the RAM.

Then the interleaver needs to extract the bit data from the RAM in units of symbols, starting from the first RAM, extracting the first line symbol of each RAM, extracting the first line symbol of all RAMs, and starting from the first RAM. , extract the 2nd line symbol of each RAM, and so on; the last interleaver sends the extracted symbols to the modulator for modulation processing in the extraction order.

For example, as shown in FIG. 4, the interleaver performs interleaving processing on the encoded bit data in units of symbols, taking the modulator as 1024-QAM as an example, and the interleaving depth is 108 LDPC codewords. The interleaving depth is the number of stored LDPC code frames, and the total amount of stored bit data is LDPC. The frame length is multiplied by the interleaving depth. Each symbol of 1024-QAM contains 10 bits, and the interleaver will store the received bit data in RAM in units of 10 bits, and the interleaver will store the received first 10 bits into the first RAM. One row, the second 10 bits are stored in the second row of the first RAM, and so on, until the n-1th 10 bits are stored in the n-1th row of the first RAM, the first RAM is stored. Full; then store the nth 10 bits in the first row of the second RAM, the n+1th 10 bits in the second row of the second RAM, and so on, until the second RAM is full So far, and so on, until the interleaver stores the received bit data obtained in the RAM into the RAM.

Here, the symbol sent by the interleaver to the modulator is the recombined bit data, 3 · · ' 3 ² , y _n -i , that is, the interleaver breaks up the encoded bit data in units of symbols, and then outputs The recombined bit data ^, , ^'...' ^ ² , ^ ; The interleaving process of the bit data by the interleaver does not change the essence of the bit data, but changes the structural order of the bit data, and breaks up the burst error. , to maximize the dispersion of burst errors during channel transmission.

Step 203: The modulator modulates the bit data obtained after the interleaving process to obtain first symbol information.

Specifically, referring to FIG. 3, the modulator receives bit data obtained by interleaving from the interleaver; y. ,; ν^,···, )^,)^, will be bit data; y. , ν^,···, )^, )^ map to the constellation diagram corresponding to the modulation mode of the modulator, forming corresponding constellation points, one constellation point is a symbol information, and one symbol information includes I and Q The components correspond to the real and imaginary parts of the constellation, respectively, and the modulator transmits the first symbol information generated by the mapping to the digital-to-analog converter; for example, for a 256-QAM modulator, the modulator can have 8 bits The bit data is modulated into one symbol information.

Step 204: The first symbol information is sent to the DAC and then sent to the noise channel. ADC.

Specifically, please refer to FIG. 3, the DAC (Digital to Analog Converter) receives the first symbol information ^^ , ^^ sent by the modulator, and converts the first symbol information in the digital format into analog information; The noise channel is connected, and the DAC sends the analog information obtained by the digital-to-analog conversion to the noise channel, and the ADC (Analog to Digital Converter) at the receiving end receives the analog information through the noise channel.

Referring to FIG. 5, which is a schematic flowchart of a method for deinterleaving according to an embodiment of the present invention, as shown in FIG. 5, the method includes the following steps:

Step 501: The ADC performs analog-to-digital conversion on the first symbol information sent by the sending end to obtain second symbol information.

Specifically, referring to FIG. 3, at the receiving end, the ADC receives the first symbol information sent by the transmitting end through the noise channel, and the ADC performs analog-to-digital conversion on the analog information received from the noise channel, and converts the analog signal into a digital format. Symbol information, obtaining second symbol information

s. , , ₂ , ^ ', and send the second symbol information ^ ' to the deinterleaver.

Step 502: The deinterleaver performs deinterleaving processing on the second symbol information in units of symbols to obtain third symbol information.

Specifically, referring to FIG. 3, the second symbol information W '···' ^{2 is} received by the deinterleaver from the ADC at the receiving end, and is in units of symbols, that is, the symbol size corresponding to the modulation mode, The second symbol information, '...' ² , performs deinterleaving processing, that is, performs an inverse process of the interleaving process, and stores the mth symbol information in the second symbol information into the jth row of the i th RAM until all The symbols are all stored in the RAM; wherein, the amount of all symbols to be stored is determined according to the interleaving depth; wherein i and j are positive integers, and n is the total RAM number; When m is an integer multiple of n, i=n, j=m/n; when m is not an integer multiple of n, i=m%n, j=[m/n+l], where [] represents rounding; Where m, n, i, and j are positive integers, and n is the total RAM number; that is, the symbol information is stored from the first row of the first RAM, and the received first symbol information is stored in the first RAM. In the first row, the received second symbol information is stored in the first row of the second RAM, and after the first row of all RAMs is stored, the received symbol information is stored in the first RAM. In line 2, and so on, until all symbol information is stored in RAM.

Starting from the first RAM, extract all the symbols in each RAM in turn, that is, after extracting all the symbols in one RAM, extract all the symbols in the next RAM until all the symbols are extracted; finally, according to the extraction order The extracted symbol is sent to the demodulator as the third symbol information for demodulation processing, thereby processing the second symbol information into the order of the encoded bit data, '...'; in this embodiment, the deinterleaver receives The second symbol information is subjected to deinterleave processing on the second symbol information, instead of deinterleaving the demodulated bit data in the prior art.

Step 503: The demodulator demodulates the third symbol information to obtain floating point information expressed in bits.

Specifically, referring to FIG. 3, the demodulator receives the third symbol information s ₀ , s;, s ₂ , -, s _n _ ₂ , s _n _; sent by the deinterleaver, and the received third symbol information. Performing demodulation, using each symbol in the third symbol information as a constellation point in the constellation corresponding to the modulation mode of the demodulator, and demaping the constellation point into floating point information according to the quantization bit width of the constellation point, The floating point information represented by the bit mode; wherein the quantization bit width of the constellation point is determined by the characteristics of the ADC device. For example, if the quantization bit width is 8 bits, the demodulator demodulates one symbol information into 8 floating point information, and each floating point information is represented by 8 bits, and each symbol information is demodulated into 64 bits; Will The floating point information c obtained by the mapping. , , , . , ' is sent to the soft decision FEC decoder. After demodulation processing by the demodulator, the third symbol information will become larger data bit data and sent to the soft decision FEC decoder.

In step 504, the soft decision FEC decoder decodes the floating point information and outputs the bit data. Specifically, please refer to FIG. 3, the soft decision FEC decoder receives the floating point information obtained after demodulation, _3⁄4 , ...^- ₂ , _l ', and decodes the floating point information by using a decoding algorithm, The error code in the floating point information is error-corrected, and the bit data obtained after the error correction is output, «,····, ₂ , U where the error code in the floating point information includes the burst error and the random error in the channel code. The decoding algorithm may be an LDPC decoding algorithm, a Turbo code decoding algorithm, etc., wherein the soft decision FEC decoder may be an LDPC decoder or a Turbo code decoder, but is not limited to the two decoders, as long as it is soft The decision FEC decoder corresponds to the soft decision FEC encoder.

Since in the traditional hard-decision FEC encoder and the communication system with low modulation mode, the demodulator processes the symbol information, and each symbol information is demodulated by M (for example, M=8 of the 256-QAM demodulator). ) floating-point information, each floating-point information is represented by N bits, and after each symbol information is demodulated, the original 2 Ν 比特 bits (including the real part and the imaginary part) become Μ χ Ν bits The deinterleaver performs deinterleaving processing on the N bits of bit data. In this embodiment, the deinterleaver processing is located before the demodulator, so the deinterleaver is symbol information for 2 χ Ν bits. The deinterleaving process is performed. The logical resource of the conventional deinterleaver is (MN)/(2 N)= M/2 times of the logical resource of the deinterleaver in this embodiment. Taking a 256-QAM modulator as an example, M =8, the logical resource of the traditional deinterleaver is four times that of the deinterleaver in this embodiment, and the deinterleaver of this embodiment can save 4 times of logic resources.

Specific embodiment

Microwave 4 X 4 MIMO communication system, LDPC encoder with code length of 8640, modulation The mode is 1024-QAM as an example. Since the modulation mode is 1024-QAM, each symbol information is 10 bits, and the quantization bit width of the floating point information is 8 bits.

Please refer to FIG. 6, which is a schematic diagram of a transmitting end of a microwave 4×4 MIMO communication system according to an embodiment of the present invention. At the transmitting end, there are 4 signal source data, and 4 interleavers are used, and each interleaver has a processing unit of 10 Bits, each 10 bits are mapped into one constellation point, and the coordinates of the constellation points include real and imaginary parts. Since the quantization bit width is 8 bits, the mapped floating point information is 16 bits.

On the sending side, there are the following processes:

Fixed frame processing: After the signal source data is subjected to the framing processing of the BB (Base Band) frame, the LDPC is framed and transmitted to the LDPC encoder with 10 bits of parallel bit width.

Encoding process: In order to save logic resources, the LDPC encoder adopts time division multiplexing mode, and uses one LDPC encoder to be compatible with encoding of four channels of source data; the LDPC encoder converts four channels of source data sent by the BB frame by time division. The 1 channel source data is synthesized by the method, and the 1 channel source data is LDPC coded, and the encoded 1 channel source data is further divided into 4 aligned bit data and sent to 4 interleavers respectively. Here, the modulation mode control unit may configure a parameter of the corresponding modulation mode on the LDPC encoder according to the difference of the signal quality, and is used to indicate the modulation mode of the transmitting end, and an LDPC encoder can support multiple modulation modes, such as 16-QAM, 64-QAM, 256-QAM, 512-QAM or 1024-QAM, etc., and each bit data can use the same modulation mode or different modulation modes. For example, when the parameter of the modulation mode is configured as 1 , indicating that the modulation mode is 16-QAM, and the parameter of the modulation mode is set to 2, indicating that the modulation mode is 64-QAM, and the LDPC encoder transmits the parameters of the modulation mode to the downstream processing module through the control signal, and the downstream processing module can Interleave processing: In order for bit data to not affect each other, each bit of data is used separately

1 interleaver, each interleaver has an interleaving depth of 100 LDPC frames, then 4 interleavers need 4 x 8640 X 100= 3456000 bits of RAM resources, and the interleaving unit of the interleaver is one symbol, that is, 10 bits are a symbol.

Modulation processing: the 10-bit wide bit data output by the interleaver is modulated by the modulator, and each symbol information output includes two paths of I and Q, and each symbol information is quantized by 8 bits s to obtain a total of 16 bits. Symbol information.

Please refer to FIG. 7, which is a schematic diagram of a receiving end of a microwave 4 X 4 MIMO communication system according to an embodiment of the present invention. The receiving end has the following processing procedure:

Deinterleaving processing: The symbol information transmitted from the noisy channel enters the deinterleaver, and the deinterleaver deinterleaves the symbol information in the form of a symbol, and each symbol information transmitted is 16 bits. Similarly, the modulation of the transmitting end is similar. Here, the modulation mode control unit may configure a parameter of the corresponding modulation mode on the deinterleaver according to the difference of the signal quality, and is used to indicate the modulation mode of the receiving end, and an LDPC decoder can support multiple types. Modulation mode, such as 16-QAM, 64-QAM, 256-QAM, 512-QAM or 1024-QAM, etc., and each bit data can use the same modulation mode or different modulation modes, for example, When the parameter of the modulation mode is set to 1, the modulation mode is 16-QAM, and when the parameter of the modulation mode is 2, the modulation mode is 64-QAM, and the deinterleaver transmits the parameters of the modulation mode to the downstream processing module through the control signal. The downstream processing module can learn the modulation mode according to the parameters of the modulation mode.

Demodulation processing: The 16-bit data output by the deinterleaver is sent to the demodulator. After demodulation processing by the demodulator, one constellation point is demapped into 10 floating point information, and each floating point information is represented by 8 bits. Then, the demodulator outputs 80 bits of bit data in each channel. Decoding processing: The LDPC decoder uses a time division multiplexing method to decode 4 bits of data by using one LDPC decoder; first, synthesize 4 bits of bit data into 1 bit of bit data, and perform 1 bit of bit data. After LDPC decoding, the decoded 1-bit data is divided into 4 bits of data and sent to 4 BB frames.

In the above communication system, the number of bits of the RAM to be used by the deinterleaver is: (8640/10) X 16 X 100 = 13382400 bits. If the deinterleave processing of the deinterleaver is placed after the demodulation process of the demodulator in the conventional manner, the logical resource of the RAM is required to be (8640/10) X lO x 8 X 100=6912000 bits, so in the conventional manner The multiple of the logical resource of the deinterleaver is five times that of the deinterleaver in the embodiment of the present invention. 8640 is the frame length of an LDPC code, ( 8640/10 ) = 864 is the number of symbols included in each LDPC code, 10 is the number of floating point information after demodulation of each symbol information, and 8 is each floating point information. The 8-bit quantization bit width is used.

Embodiments of the present invention further provide an apparatus embodiment for implementing the steps and methods in the foregoing method embodiments.

Please refer to FIG. 8, which is a functional block diagram of a deinterleaving communication system according to an embodiment of the present invention. As shown, the deinterleaved communication system includes: an analog to digital converter 81, a deinterleaver 82, a demodulator 83, and a soft decision FEC decoder 84;

The analog-to-digital converter 81 is configured to perform analog-to-digital conversion on the first symbol information sent by the transmitting end to obtain second symbol information.

The deinterleaver 82 is configured to perform deinterleaving on the second symbol information in units of symbols to obtain third symbol information.

a demodulator 83, configured to demodulate the third symbol information to obtain floating point information represented by bits; The soft decision FEC decoder 84 is configured to decode the floating point information and output bit data.

The deinterleaver 82 specifically includes a receiving unit 821, a storage unit 822, an extracting unit 823, and a sending unit 824:

The receiving unit 821 is configured to receive second symbol information from the analog to digital converter;

The storage unit 822 is configured to store the mth symbol in the second symbol information into the jth row of the i th random memory RAM according to the receiving order, until all symbols are stored in the RAM; when m is n In integer multiples, i=n, j=m/n; when m is not an integer multiple of n, i=m%n, j=[m/n+l], where [] denotes rounding; where m, n , i and j are positive integers, and n is the total RAM number;

The extracting unit 823 is configured to sequentially extract all the symbols in the RAM, extract all the symbols in one RAM, and then extract all the symbols in the next RAM until all the symbols are extracted;

The transmitting unit 824 is configured to send the extracted symbol as the third symbol information to the demodulator 83 in the extraction order.

The demodulator 83 specifically includes a receiving unit 831 and a demapping unit 832: a receiving unit 831, configured to receive third symbol information sent by the deinterleaver;

a demapping unit 832, configured to use each symbol in the third symbol information as a constellation point in a constellation corresponding to a modulation mode of the demodulator, and to solve the constellation point according to a quantization bit width of a constellation point Map to floating point information to obtain floating point information expressed in bits.

Please refer to FIG. 9, which is a schematic structural diagram of a deinterleaving communication system according to an embodiment of the present invention. As shown, the communication system includes:

The analog-to-digital converter 91 receives the first symbol information sent by the transmitting end, and receives the first symbol The number information is subjected to analog-to-digital conversion to obtain second symbol information;

a memory 92, configured to store information including a program routine;

The processor 93 is coupled to the memory 92 and the analog-to-digital converter 91 for controlling the execution of the program routine, and specifically includes: deinterleaving the second symbol information in units of symbols to obtain third symbol information. Demodulating the third symbol information to obtain floating point information expressed in bits; decoding the floating point information to output bit data.

In the technical solution provided by the present invention, the deinterleaver is placed in front of the demodulator, and the symbol information is deinterleaved in units of symbols instead of deinterleaving the demodulated bit data, so the input deinterleaver The amount of data is greatly reduced, thereby reducing the amount of logic resources occupied by the deinterleaver, reducing the implementation complexity of the deinterleaver and the implementation cost of the deinterleaving process.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalents, improvements, etc., which are made within the spirit and principles of the present invention, should be included in the present invention. Within the scope of protection.

Claims

claims

1. A method of deinterleaving, characterized in that the method includes:

The analog-to-digital converter performs analog-to-digital conversion on the first symbol information sent by the transmitter to obtain the second symbol information;

The deinterleaver deinterleaves the second symbol information in units of symbols to obtain the third symbol information;

The demodulator demodulates the third symbol information to obtain floating point information expressed in bits;

The soft-decision forward error correction FEC decoder decodes the floating point information and outputs bit data.

2. The method according to claim 1, characterized in that the deinterleaver performs deinterleaving processing on the second symbol information in units of symbols, specifically as follows:

receiving the second symbol information from an analog-to-digital converter;

According to the reception order, store the m-th symbol in the second symbol information in the j-th row of the i-th random access memory RAM until all symbols are stored in the RAM; when m is an integer multiple of n, i= n, j=m/n; when m is not an integer multiple of n, i=m%n, j=[m/n+l], where [] represents rounding; where m, n, i and j are positive Integer, n is the total number of RAM;

Extract all symbols in RAM in sequence. After extracting all symbols in one RAM, extract all symbols in the next RAM until all symbols are extracted;

The extracted symbols are sent to the demodulator as third symbol information in the order of extraction.

3. The method according to claim 1, characterized in that the demodulator demodulates the third symbol information to obtain floating point information expressed in bits, specifically:

Receive the third symbol information sent by the deinterleaver; Using each symbol in the third symbol information as a constellation point in the constellation diagram corresponding to the modulation mode of the demodulator, de-mapping the constellation point into floating point information according to the quantized bit width of the constellation point, we obtain Floating point information represented as bits.

4. A deinterleaved communication system, characterized in that the system includes an analog-to-digital converter, a deinterleaver, a demodulator and a soft-decision forward error correction FEC decoder:

An analog-to-digital converter is used to perform analog-to-digital conversion on the first symbol information sent by the transmitting end to obtain the second symbol information;

A deinterleaver, configured to deinterleave the second symbol information in symbol units to obtain third symbol information;

A demodulator, used to demodulate the third symbol information to obtain floating-point information expressed in bits;

Soft decision FEC decoder is used to decode the floating point information and output bit data.

5. The communication system according to claim 4, characterized in that the deinterleaving device specifically includes: a receiving unit, a storage unit, an extraction unit and a sending unit:

A receiving unit, configured to receive the second symbol information from the analog-to-digital converter;

The storage unit is used to store the m-th symbol in the second symbol information in the j-th row of the i-th random access memory RAM according to the reception order until all symbols are stored in the RAM; when m is an integer of n When multiples, i=n, j=m/n; when m is not an integer multiple of n, i=m%n, j=[m/n+l], where [] means rounding; where m, n, i and j are positive integers, n is the total number of RAM;

The extraction unit is used to extract all symbols in RAM in sequence. After extracting all symbols in one RAM, extract all symbols in the next RAM until all symbols are extracted; The sending unit is configured to send the extracted symbols as third symbol information to the demodulator according to the extraction order.

6. The communication system according to claim 4, characterized in that the demodulator specifically includes a receiving unit and a demapping unit:

A demapping unit, configured to use each symbol in the third symbol information as a constellation point in the constellation diagram corresponding to the modulation mode of the demodulator, and demap the constellation point according to the quantized bit width of the constellation point. into floating-point information, and obtain floating-point information expressed in bits.