WO2014149040A1 - Routeurs hybrides dans des architectures multi-cœur - Google Patents

Routeurs hybrides dans des architectures multi-cœur Download PDF

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Publication number
WO2014149040A1
WO2014149040A1 PCT/US2013/033115 US2013033115W WO2014149040A1 WO 2014149040 A1 WO2014149040 A1 WO 2014149040A1 US 2013033115 W US2013033115 W US 2013033115W WO 2014149040 A1 WO2014149040 A1 WO 2014149040A1
Authority
WO
WIPO (PCT)
Prior art keywords
energy
delay
channel
packet
switched
Prior art date
Application number
PCT/US2013/033115
Other languages
English (en)
Inventor
Yan Solihin
Original Assignee
Empire Technology Development, Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Empire Technology Development, Llc filed Critical Empire Technology Development, Llc
Priority to PCT/US2013/033115 priority Critical patent/WO2014149040A1/fr
Priority to US14/005,520 priority patent/US9473426B2/en
Priority to CN201380074889.1A priority patent/CN105164664B/zh
Priority to TW103108408A priority patent/TWI565265B/zh
Publication of WO2014149040A1 publication Critical patent/WO2014149040A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/60—Software-defined switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/60—Router architectures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/251—Cut-through or wormhole routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/252—Store and forward routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix

Abstract

L'invention porte de manière générale sur des technologies pour des procédés et des systèmes efficaces pour mettre en œuvre des routeurs hybrides dans des architectures multi-cœur. Un premier pavé peut comprendre un cœur de processeur, un cache configuré pour être en communication avec le cœur de processeur et un routeur configuré pour être en communication avec le cache. Le routeur peut être efficace pour déplacer des données avec un canal de commutation de paquets ou un canal de commutation de circuits. Le premier pavé peut comprendre une logique de commutation configurée pour être en communication avec le cache et avec le routeur. La logique de commutation peut être efficace pour recevoir un objectif de routage qui peut concerner des coûts en énergie ou en retard dans le routage de données dans le réseau. La logique de commutation peut sélectionner l'un du canal de commutation de paquets ou du canal de commutation de circuits pour déplacer les données dans le réseau sur la base de l'objectif de routage.
PCT/US2013/033115 2013-03-20 2013-03-20 Routeurs hybrides dans des architectures multi-cœur WO2014149040A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/US2013/033115 WO2014149040A1 (fr) 2013-03-20 2013-03-20 Routeurs hybrides dans des architectures multi-cœur
US14/005,520 US9473426B2 (en) 2013-03-20 2013-03-20 Hybrid routers in multicore architectures
CN201380074889.1A CN105164664B (zh) 2013-03-20 2013-03-20 多核架构中的混合路由器
TW103108408A TWI565265B (zh) 2013-03-20 2014-03-11 多核心架構中之混合路由器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2013/033115 WO2014149040A1 (fr) 2013-03-20 2013-03-20 Routeurs hybrides dans des architectures multi-cœur

Publications (1)

Publication Number Publication Date
WO2014149040A1 true WO2014149040A1 (fr) 2014-09-25

Family

ID=51569074

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2013/033115 WO2014149040A1 (fr) 2013-03-20 2013-03-20 Routeurs hybrides dans des architectures multi-cœur

Country Status (4)

Country Link
US (1) US9473426B2 (fr)
CN (1) CN105164664B (fr)
TW (1) TWI565265B (fr)
WO (1) WO2014149040A1 (fr)

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US9553762B1 (en) * 2014-06-26 2017-01-24 Altera Corporation Network-on-chip with fixed and configurable functions
US11321263B2 (en) * 2014-12-17 2022-05-03 Intel Corporation High bandwidth core to network-on-chip interface
US9961019B2 (en) * 2014-12-22 2018-05-01 Intel Corporation Adaptively switched network-on-chip
CN104980358A (zh) * 2015-05-29 2015-10-14 上海斐讯数据通信技术有限公司 一种无线路由器及其无线网络管理方法
CN107094118B (zh) * 2017-06-26 2020-10-23 太仓市同维电子有限公司 利用1200m传输速率模块搭配成无线2400m传输速率的无线路由器

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US8284766B2 (en) * 2007-12-28 2012-10-09 Intel Corporation Multi-core processor and method of communicating across a die

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US5729544A (en) * 1994-05-09 1998-03-17 Motorola, Inc. Method for transmitting data packets based on message type
TW516294B (en) * 2000-05-22 2003-01-01 Ericsson Telefon Ab L M Combining differing transport technologies in a telecommunications system
US6882640B1 (en) * 2000-09-22 2005-04-19 Siemens Communications, Inc. System and method for utilizing circuit switched and packet switched resources
US6512784B2 (en) * 2001-03-01 2003-01-28 Linex Technologies, Inc. Efficient sharing of capacity by remote stations using circuit switching and packet switching
US20040225771A1 (en) * 2000-12-28 2004-11-11 Riesenman Robert J. Data pre-fetch control mechanism and method for retaining pre-fetched data after PCI cycle termination
US20020191588A1 (en) * 2001-06-13 2002-12-19 Drexel University Integrated circuit and packet switching system
JP2005531061A (ja) * 2002-06-24 2005-10-13 ドコモ コミュニケーションズ ラボラトリーズ ユー・エス・エー インコーポレーティッド モバイルアプリケーションのための実行環境
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WO2007139536A2 (fr) * 2006-05-21 2007-12-06 International Business Machines Corporation Procédé et appareil pour transférer des données entre des noyaux dans un circuit intégré

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US8284766B2 (en) * 2007-12-28 2012-10-09 Intel Corporation Multi-core processor and method of communicating across a die

Non-Patent Citations (3)

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Title
JERGER, N. E. ET AL.: "Circuit-Switched Coherence", SECOND ACM/ IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS 2008, 2008, pages 193 - 202 *
MODARRESSI, M. ET AL.: "A Hybrid Packet-Circuit Switched On-Chip Network Based on SDM", PROCEEDINGS OF THE DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, April 2009 (2009-04-01), FRANCE, pages 566 - 569 *
SECCHI, S. ET AL.: "A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching", PROCEEDINGS OF THE 2008 11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, WASHINGTON, DC, USA, pages 141 - 148 *

Also Published As

Publication number Publication date
TWI565265B (zh) 2017-01-01
TW201507408A (zh) 2015-02-16
CN105164664A (zh) 2015-12-16
US9473426B2 (en) 2016-10-18
CN105164664B (zh) 2018-06-15
US20140286179A1 (en) 2014-09-25

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