WO2014133190A1

WO2014133190A1 - Method for forming microstructure, and fin structure

Info

Publication number: WO2014133190A1
Application number: PCT/JP2014/055702
Authority: WO
Inventors: 軍司　勲男; 勇作柏木; 正和杉山
Original assignee: 東京エレクトロン株式会社; 国立大学法人東京大学
Priority date: 2013-02-27
Filing date: 2014-02-27
Publication date: 2014-09-04
Also published as: JP2016094303A; TW201440130A

Abstract

Provided is a method for forming a microstructure capable of yielding a high-quality III-V semiconductor microstructure. A trench (24) is formed in a wet-etch stop layer (22) and a covering layer (23) for covering a wafer (W), the crystal surface (25) of the silicon of the wafer (W) is exposed in the bottom section of the trench (24), the trench (24) is filled with gas-phase indium phosphide, the indium-phosphide-filled trench (24) and the covering layer (23) are covered with an indium layer (27), and the indium phosphide filling the trench (24) is heated to melting, after which the melted indium phosphide is gradually cooled, and crystallized indium phosphide (32) is precipitated using the crystal surface (25) of the silicon as a kernel, and the covering layer (23) is removed.

Description

Fine structure forming method and fin structure

The present invention relates to a fine structure forming method and a fin structure, and more particularly to a fine structure forming method for forming a III-V semiconductor fine structure on a substrate.

III-V group semiconductors composed of compounds of group III elements (aluminum (Al), gallium (Ga), indium (In)) and group V elements (phosphorus (P), arsenic (As), antimony (Sb)) Some semiconductors have higher carrier mobility and smaller band gap than silicon (Si), which is a common semiconductor, so that a semiconductor element exceeding the physical properties of silicon can be produced by using a III-V semiconductor. Can do.

On the other hand, for many years, wafers made of silicon (001) have been used as ULSI manufacturing substrates, and many manufacturing process equipment groups handling large-diameter wafers with a diameter of 300 mm have been introduced into mass production plants around the world.

Therefore, high-quality gallium arsenide (GaAs), gallium antimony (GaSb), indium phosphide (InP), indium arsenide (InAs), indium antimony (No) on a wafer having a crystal plane with a Miller index of (001). If a microstructure of a III-V group semiconductor such as InSb) or indium gallium arsenide (InGaAs) can be formed, a large number of semiconductor manufacturing techniques accumulated so far and a large number of manufacturing process apparatus groups already introduced This makes it possible to manufacture a III-V semiconductor ULSI that surpasses the physical properties of silicon, thereby improving the performance of the ULSI while avoiding a rapid increase in mass production costs.

However, if the above-described group III-V semiconductor is simply deposited on silicon, many crystal defects are generated in the microstructure of the group III-V semiconductor due to the difference in lattice constant between silicon and group III-V semiconductor. It is difficult to exhibit the expected performance of a semiconductor element made of a III-V group semiconductor.

Incidentally, as one method for growing indium phosphide with few crystal defects, there is an LPE (Liquid Phase Epitaxy) method. In the LPE method, liquid indium slightly containing phosphorus filled in a crucible around which a heater is wound is brought into contact with a crystal substrate of indium phosphorus provided on a slider in a crystal growth furnace. To generate a temperature difference between the liquid phase indium and the crystal substrate of indium phosphide and maintain the temperature difference, and using the crystal substrate as a seed, crystals of indium phosphide with few crystal defects are formed from the crystal plane of the crystal substrate. Epitaxial growth is performed (see, for example, Patent Document 1). There have also been reports of attempts to grow indium phosphide crystals on a silicon substrate using the LPE method (see, for example, Non-Patent Documents 1 to 3).

JP 63-144200 A

However, when a ULSI transistor is processed into a three-dimensional shape, the width of the fin structure needs to be suppressed to about 10 nm in order to exhibit the expected performance of the channel of the fin structure transistor made of indium phosphide.

In order to form a fin structure with a narrow width, it is preferable to form a narrow trench in an insulating film on a silicon substrate, flow an indium solution into the trench, and grow an indium phosphorus crystal in the trench. Since the indium solution has low wettability with the insulating film, it is difficult to reach the silicon surface exposed at the bottom of the trench. In particular, since the height of the fin is several tens of nm, the aspect ratio, which is the ratio of the height and width of the fin structure, becomes considerably large, and it becomes more difficult to flow the indium solution to the bottom of the trench.

An object of the present invention is to provide a high-quality method for forming a III-V semiconductor microstructure and a fin structure in order to overcome the above-described difficulties and satisfy the requirements of the most advanced transistors.

In order to solve the above-mentioned problems, according to the present invention, a groove forming step of forming a narrow groove in a coating layer covering a silicon substrate and exposing a silicon crystal plane of the silicon substrate at the bottom of the groove; A filling step of filling the groove with a group III-V semiconductor in a gas phase or a solid phase, and heating and melting the filled group III-V semiconductor, and then slowly cooling the molten group III-V semiconductor Then, there is provided a microstructure forming method including a precipitation step of depositing the III-V group semiconductor crystal using the silicon crystal plane as a seed, and a removal step of removing the coating layer.

According to the present invention, a high-quality III-V semiconductor microstructure can be obtained.

It is sectional drawing which shows roughly the structure of the CVD film-forming apparatus used for the fine structure formation method which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows roughly the structure of the heat processing apparatus used for the microstructure formation method which concerns on this Embodiment. It is process drawing which shows the fine structure formation method which concerns on this Embodiment. It is process drawing which shows the fine structure formation method which concerns on this Embodiment. It is sectional drawing which shows roughly the structure of the PVD film-forming apparatus used for the microstructure formation method which concerns on this Embodiment. FIG. 3 is a cross-sectional view schematically showing the configuration of an indium gallium arsenide / indium aluminum arsenide quantum well type channel to which the fine structure of indium phosphide formed by the fine structure forming method according to the present embodiment is applied; The case of using the fin structure is shown. 1 is a cross-sectional view schematically showing a configuration of an indium gallium arsenide / indium aluminum arsenide quantum well type channel to which an indium phosphide microstructure formed by the microstructure forming method according to the present embodiment is applied; The case where the planar structure of phosphorus is used is shown. It is sectional drawing which shows schematically the structure of the modification of the heat processing apparatus of FIG. It is an expanded sectional view which shows roughly the structure of the periphery of the fine structure in the modification of the fine structure formation method which concerns on this Embodiment, and shows the case where a cap layer is not formed. It is an expanded sectional view showing roughly composition of the circumference of a fine structure in a modification of a fine structure formation method concerning this embodiment, and shows a case where only a trench is covered with an indium layer. It is process drawing which shows the microstructure formation method which concerns on the 2nd Embodiment of this invention. It is an expanded sectional view which shows roughly the structure of the periphery of the fine structure in the modification of the fine structure formation method concerning this Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, the microstructure formation method according to the first embodiment of the present invention will be described.

FIG. 1 is a cross-sectional view schematically showing a configuration of a CVD film forming apparatus used in the fine structure forming method according to the present embodiment, and FIG. 2 is used in the fine structure forming method according to the present embodiment. It is sectional drawing which shows the structure of a heat processing apparatus roughly.

Referring to FIG. 1, a CVD film forming apparatus 10 includes a chamber 11 that accommodates a semiconductor wafer, for example, a silicon substrate (hereinafter simply referred to as “wafer”) W, and a wafer W placed on the bottom of the chamber 11. A stage 12 to be placed, a shower head 13 disposed on the ceiling of the chamber 11 and facing the stage 12, a heater 14 connected to the stage 12, and an exhaust pipe 15 for exhausting the interior of the chamber 11.

A processing gas, for example, a mixed gas of trimethylindium and tertiary butylphosphine vaporized using a vaporizer (not shown) is introduced into the processing space S in the chamber 11 using the shower head 13. The processing gas may contain an inert gas such as hydrogen gas or nitrogen gas as a carrier gas. The processing gas supplied to the processing space S reacts on the surface of the wafer W heated by the heater 14 and is deposited as indium phosphide. The CVD film forming apparatus 10 may perform plasma CVD.

In FIG. 2, the heat treatment apparatus 16 includes a chamber 17 made of quartz (quartz), a table-like susceptor 18 placed on the bottom of the chamber 17 for placing the wafer W thereon, A plurality of lamp heaters 19 arranged to face the wafer W placed on the susceptor 18 outside 17 and hydrogen (H ₂ ) gas as a carrier gas were vaporized into the processing space S ′ in the chamber 17. A gas introduction pipe 20 for introducing phosphorus in the gas phase such as phosphorus or phosphine, a cooling gas supply passage 21 disposed in the susceptor 18 and opened to the upper surface of the susceptor 18, and an excess gas phase in the processing space S ′ And an exhaust pipe 20a for discharging phosphorus or the like.

In the heat treatment apparatus 16, the heat rays irradiated by the lamp heater 19 pass through the wall portion of the chamber 17, the wafer W placed on the susceptor 18 is heated by the heat rays, and the cooling gas supply path 21 is placed on the susceptor 18. The cooling gas is supplied toward the bottom surface of the wafer W to cool the wafer W from the bottom surface side.

3 and 4 are process diagrams showing the fine structure forming method according to the present embodiment. In this fine structure forming method, a fin structure 33 of crystallized indium phosphide 32 is formed on the surface of the wafer W.

First, in a film forming apparatus such as the CVD film forming apparatus 10, silicon nitride (Si ₃ N ₄ ) is deposited on the surface of the wafer W to form the wet etch stop layer 22, and further on the wet etch stop layer 22. A coating layer 23 made of silicon oxide is formed (FIG. 3A).

Next, after forming a mask (not shown) having an opening of a predetermined pattern on the coating layer 23 in a lithography process, the width of the coating layer 23 and the wet etch stop layer 22 is 10 nm ~ in an etching apparatus (not shown). A trench 24 (narrow groove) having a thickness of 50 nm, preferably 10 nm, a depth of 10 to 100 nm, and an aspect (depth / width) ratio of 1 or more, preferably 3 to 10 is formed (see FIG. 3 (B)). Note that the etching apparatus is not limited to a wet etching apparatus, and may be a dry etching apparatus.

Next, when the wet etch stop layer 22 is removed by etching, a natural oxide film (not shown) may be formed on the surface of the wafer W exposed at the bottom of the trench 24. Therefore, the natural oxide film is removed. The crystal face 25 of the silicon Miller index (001) of the wafer W is exposed at the bottom of the trench 24 (FIG. 3C) (groove forming step).

Next, in the CVD film forming apparatus 10, indium phosphide is generated using a mixed gas of trimethylindium and tertiary butylphosphine vaporized using a vaporizer as a processing gas. Since the mixed gas is a gas phase and diffuses in the processing space S and has no relation to the wettability, the mixed gas enters the trench 24 without a gap. The indium and phosphorus that have entered the trench 24 without gaps react with each other to produce solid phase indium phosphorus, and the trench 24 is filled with the indium phosphorus 26 (III-V semiconductor) without gap (MOCVD (Metal)). (Organic Chemical Vapor Deposition))). At this time, indium phosphide is generated preferentially from the crystal face 25 rather than the surface of the cover layer 23 due to the difference in chemical state between the surface of the cover layer 23 and the silicon crystal face 25 at the bottom of the trench 24. The CVD film forming apparatus 10 can selectively fill the trench 24 with indium phosphide 26 ((D) in FIG. 3) (filling step). The filling method of indium phosphide 26 into the trench 24 is not limited to CVD, and any method may be used as long as it fills the trench 24 with indium phosphide other than the liquid phase. For example, PVD (Physical Vapor Deposition) targeting indium or indium phosphide may be used, or a fine powder of indium phosphide may be directly embedded in the trench 24.

Next, in the PVD film forming apparatus 28 shown in FIG. 5, indium (group III metal) is deposited on the surface of the coating layer 23 and the surface of the indium phosphide 26 filled in the trench 24 by PVD targeting the bulk material 29 of indium. Then, an indium layer 27 is formed (FIG. 3E). In PVD, the target may be cooled in consideration of film forming conditions such as a melting point of the target and a film forming rate. The thickness of the indium layer 27 may be 100 nm or more, and more preferably 200 nm to 300 nm. The method of forming the indium layer 27 is not limited to PVD, and it is not always necessary to deposit indium on both the surface of the coating layer 23 and the surface of indium phosphide 26 filled in the trench 24. At least indium filled Indium may be deposited on the surface of the phosphorus 26.

Next, in a film forming apparatus such as the CVD film forming apparatus 10, silicon oxide is deposited on the indium layer 27 to form a cap layer 30 (another coating layer) ((F) in FIG. 3).

Next, the wafer W is heated by the lamp heater 19 in the heat treatment apparatus 16. The melting point of indium phosphide is 1062 ° C., while the melting point of indium is 156.6 ° C. Therefore, in the wafer W, the indium layer 27 is first melted. Here, since the melting point of silicon oxide is 1650 ° C., for example, the cap layer 30 does not melt even when the temperature of the indium phosphide 26 is melted (1062 ° C.) as well as the indium layer 27. Therefore, even if the indium layer 27 is melted, indium can be prevented from flowing out from the wafer W, and indium can be retained on the trench 24.

The molten indium contacts the indium phosphide 26 in the trench 24 as a solvent. When the indium phosphorus 26 comes into contact with indium (hereinafter referred to as “solvent indium”) 27a as a solvent, the phosphorus contained in the indium phosphorus 26 gradually moves to the solvent indium 27a, and at the interface between the solvent indium 27a and the indium phosphorus 26. The indium phosphorus 26 in contact with the solvent indium 27a gradually melts without heating the wafer W to 1062 ° C., which is the melting point of indium phosphorus, by decreasing the phosphorus content and the melting point to about 700 ° C. (A in FIG. 4). Since the melted indium phosphide 26 is dissolved in the solvent indium 27a, the indium phosphide 26 immediately below the melted indium phosphide 26 is brought into contact with the solvent indium 27a, and the indium phosphide 26 immediately below is melted in the same manner. In other words, the indium phosphide 26 in the trench 24 gradually melts from the top to the bottom of the trench 24 (see the arrow in FIG. 4A). If the temperature of the wafer W is maintained at 700 ° C. for about 1 hour, all of the indium phosphorus 26 in the trench 24 is melted, and the trench 24 is filled with the solvent indium 27a in which the indium phosphorus 26 is dissolved as a solute. At this time, phosphorus that has moved to the solvent indium 27a may be released. However, since the solvent indium 27a is covered with the cap layer 30, the phosphorus remains in the solvent indium 27a, and the crystalline indium phosphorus that is deposited later forms phosphorus. It can prevent that content falls.

Next, when the cooling gas is supplied from the cooling gas supply passage 21 of the susceptor 18 and the wafer W is gradually cooled from the bottom surface side, crystallized indium phosphide 32 is deposited using the silicon crystal surface 25 at the bottom of the trench 24 as a seed (see FIG. 4 (B)) (precipitation step). The precipitation of crystallized indium phosphide 32 continues upward from the bottom of the trench 24 (see the arrow in FIG. 4B). During the deposition of crystallized indium phosphide 32, the wafer W is maintained at about 610 ° C. At this time, if the temperature difference between the solvent indium 27a and the wafer W is maintained at about 10 ° C., high-quality single-crystallized indium phosphide 32 is deposited.

Crystallized indium phosphide 32 precipitates using the crystal plane 25 of silicon as a seed, and thus inherits the crystallinity of the Miller index (001). Threading dislocation defects 31 are generated. Here, the threading dislocation defect 31 is not perpendicular to the crystal plane 25 but grows obliquely, for example, along a direction of 45 °. Therefore, if the aspect ratio of the trench 24 is 1 or more, the threading dislocation defect 31 does not reach the top of the trench 24, and if the aspect ratio is 2 or more, the threading dislocation defect 31 in the crystallized indium phosphorus 32. It is possible to secure a sufficient portion where no exists. Further, if the aspect ratio is 3 to 10, a portion where the threading dislocation defect 31 does not exist in the crystallized indium phosphide 32 can be more sufficiently secured.

Next, after the trench 24 is entirely filled with crystallized indium phosphide 32, the cooling is further continued to solidify all of the solvent indium 27a to form the indium layer 27, and then the cap layer 30 and the trench 24 above. The indium layer 27 present in the substrate is removed by wet etching or CMP (Chemical Mechanical Polishing) ((C) in FIG. 4).

Next, the covering layer 23 is removed by wet etching to obtain a fin structure 33 of crystallized indium phosphide 32 (removal step). When only the indium layer 27 existing above the trench 24 can be removed by wet etching or CMP, the shape of the trench 24 is reflected in the fin structure 33, and the width of the fin structure 33 is the same as the width of the trench 24. The height is the same as the depth of the trench 24. On the other hand, when not only the indium layer 27 existing above the trench 24 but also the indium layer 27 existing in the trench 24 is removed to some extent by wet etching or CMP, the aspect ratio of the obtained fin structure 33 is the trench ratio. Similarly to the aspect ratio of 24, it may be 1 or more, preferably 3 to 10. Next, after obtaining the fin structure 33, the present process is terminated.

6A and 6B show the configuration of an indium gallium arsenide / indium aluminum arsenide quantum well (Quantum Well) channel to which the fine structure of indium phosphide formed by the fine structure forming method according to the present embodiment is applied. FIG. 6A shows a case where a fin structure of indium phosphide is used, and FIG. 6B shows a case where a fine planar structure of indium phosphide is used.

In FIG. 6A, an indium aluminum arsenide (InAlAs) layer 34, an indium gallium arsenide (InGaAs) layer 35, and a layer are sequentially formed so as to cover the surface of the fin structure 33 formed by the microstructure forming method according to the present embodiment. An indium phosphide layer 36 is formed, and in FIG. 6B, the crystallized indium phosphide 32 is embedded in the coating layer 23 by removing the step (D) of FIG. 4 from the microstructure forming method according to the present embodiment. In addition, an indium aluminum arsenide layer 34, an indium gallium arsenide layer 35, and an indium phosphide layer 36 are sequentially formed so as to cover the exposed surface of the crystallized indium phosphide 32. The indium aluminum arsenide layer 34 is a lower barrier layer, the indium gallium arsenide layer 35 is a channel layer, and the indium phosphide layer 36 is an upper barrier layer.

Conventionally, when a channel of indium gallium arsenide / indium aluminum arsenide quantum well type is formed on a silicon crystal plane of a wafer W through a gallium arsenide (GaAs) layer, the lattice constant of gallium arsenide and indium aluminum arsenide is In contrast, threading dislocation defects due to lattice mismatching occur, and therefore the film thickness of the indium aluminum arsenide layer, which is a buffer layer for absorbing the threading dislocation defects, needs to be increased, for example, about 700 nm. It was.

However, when forming a channel of indium gallium arsenide / indium aluminum arsenide quantum well type using the indium phosphide microstructure formed by the microstructure forming method according to the present embodiment as a base, indium phosphide is more than gallium arsenide. The lattice constant is close to that of indium aluminum arsenide, and threading dislocation defects due to lattice mismatch are unlikely to occur. As a result, the indium aluminum arsenide layer 34 can be made thinner than the conventional buffer layer. In particular, when the fin structure 33 is used as a base, for example, a portion other than the protruding fin structure 33 is covered with a mask film, and an indium aluminum arsenide layer 34, an indium gallium arsenide layer 35, and an indium phosphide layer 36 are formed on the fin structure 33. Therefore, it is not necessary to remove unnecessary portions by dry etching using plasma after the whole is covered with the indium aluminum arsenide layer 34, the indium gallium arsenide layer 35, and the indium phosphide layer 36. As a result, the channel can be prevented from being damaged by the plasma.

According to the microstructure forming method according to the present embodiment, indium phosphide 26 is filled in the vapor phase in the trench 24, so that the indium phosphide 26 is filled in the trench 24 without any gap and the silicon crystal face 25 at the bottom of the trench 24 is filled. The indium phosphide 26 filled in the trench 24 having an aspect ratio of 1 or more, preferably 3 to 10, is heated and melted, and then the melted indium phosphide 26 is gradually cooled to obtain silicon crystals. Since the crystallized indium phosphide 32 is deposited by using the surface 25 as a seed, the fin structure 33 of the crystallized indium phosphide 32 in which the shape of the trench 24 is reflected and the portion where the threading dislocation defect 31 does not exist can be obtained. As a result, a high-quality indium phosphide fin structure 33 with high electron mobility can be obtained.

In the fine structure forming method according to the present embodiment described above, the trench 24 filled with indium phosphide 26 is covered with the indium layer 27, so that the solvent indium 27 a is deposited in the indium 24 in the crystallized indium phosphide 32. In contact with the phosphorus 26, the phosphorus in the indium phosphorus 26 moves to the solvent indium 27a, and the phosphorus content in the indium phosphorus 26 decreases. As a result, since the melting point of the indium phosphide 26 is lowered, the temperature at which all of the indium phosphide 26 filled in the trench 24 is melted can be lowered, so that the heat is applied to the other layers formed on the wafer W. Damage can be prevented, thermal energy can be reduced, and heating time can be shortened to improve throughput.

Furthermore, the fine structure forming method according to the present embodiment described above can be performed using a conventional semiconductor manufacturing apparatus such as the CVD film forming apparatus 10, the heat treatment apparatus 16, the PVD film forming apparatus 28, and the etching apparatus. This eliminates the need to use a crystal growth furnace dedicated to LPE. In addition, since conventional semiconductor manufacturing equipment processes large-diameter silicon wafers (for example, silicon wafers with a diameter of 300 mm), it can process with higher productivity than a crystal growth furnace dedicated to LPE that processes relatively small-diameter substrates. It can be performed. Therefore, the manufacturing cost of the fin structure 33 can be significantly reduced.

Further, the cap layer 30 may not be formed by removing the step (F) of FIG. 3 from the fine structure forming method according to the present embodiment described above. However, in this case, since the solvent indium 27a may flow out of the wafer W, the wafer W is heated by the heat treatment apparatus 37 shown in FIG.

7 is different from the heat treatment apparatus 16 of FIG. 2 in that it has an outflow prevention wall 38 so as to surround the wafer W on which the susceptor 18 is placed. In the heat treatment apparatus 37, even if the wafer W on which the cap layer 30 is not formed is heated, the outflow prevention wall 38 can prevent the solvent indium 27 a from flowing out from the wafer W. Further, in this case, since the solvent indium 27a is directly exposed to the processing space S ′ in the chamber 17, when further phosphorus is added to the indium phosphorus 26, the vaporized phosphorus is introduced into the processing space S ′ by the gas introduction pipe 20. By increasing the partial pressure of phosphorus in the processing space S ′, phosphorus can be easily added to the indium phosphorus 26 via the solvent indium 27a. Further, an additive (for example, zinc (Zn), When sulfur (S) or iron (Fe)) is added, the additive can be easily added to the indium phosphide 26 through the solvent indium 27a (FIG. 8A). Further, when the cap layer 30 is not formed, the indium layer 27 does not need to be formed so as to cover both the surface of the covering layer 23 and the trench 24, and is formed so as to cover only the trench 24 as shown in FIG. 8B. May be. Thereby, the usage-amount of indium can be reduced.

Further, in the fine structure forming method according to the present embodiment, if it is not necessary to lower the melting point of indium phosphide, it is not necessary to form the indium layer 27, and the wafer W is heated after the trench 24 is filled with the indium phosphide 26. Then, the indium phosphide 26 may be melted, and the wafer W may be gradually cooled to precipitate the crystallized indium phosphide 32 from the silicon crystal face 25.

In the fine structure forming method according to the present embodiment described above, the fin structure 33 is formed of indium phosphorus. However, the fine structure forming method according to the present embodiment is not limited to other III-V semiconductors such as aluminum phosphorus (AlP). ), Aluminum arsenic (AlAs), aluminum antimony (AlSb), gallium phosphide (GaP), gallium arsenide, gallium antimony (GaSb), indium arsenic (InAs), indium antimony (InSb), or a compound containing these to form a fin structure The present invention can also be applied when forming. When using an aluminum-based III-V group semiconductor, after filling the trench 24 with an aluminum-based III-V group semiconductor, the trench 24 is covered with an aluminum layer, and an indium-based III-V group semiconductor is used. After the trench 24 is filled with an indium III-V group semiconductor, the trench 24 is covered with an indium layer. When a gallium III-V semiconductor is used, the trench 24 is gallium III-V group. After filling with a semiconductor, the trench 24 is covered with a gallium layer. Since gallium has a low melting point and may be in a liquid phase at room temperature, when the trench 24 is covered with a gallium layer, an outflow prevention wall surrounding the wafer W is provided to prevent outflow of liquid gallium. Is preferred.

Next, a microstructure forming method according to the second embodiment of the present invention will be described.

In the microstructure forming method according to the present embodiment, the trench 24 is filled with indium instead of indium phosphorus.

FIG. 9 is a process diagram showing the fine structure forming method according to the present embodiment.

3A to 3C are performed to form a trench 24 in the wet etch stop layer 22 and the coating layer 23 on the wafer W, and a silicon mirror index is formed at the bottom of the trench 24. The crystal plane 25 of (001) is exposed ((A) of FIG. 9) (groove forming step).

Next, in the PVD film forming apparatus 28, the surface of the trench 24 and the covering layer 23 is covered with solid-state indium 39 by PVD targeting the bulk material 29 of indium. Further, since the solid phase indium 39 has no relation to the wettability, the indium 39 enters the trench 24 without any gap, and the trench 24 is filled with the indium 39 without any gap ((B) in FIG. 9) (filling step).

The method of filling the trench 24 with indium is not limited to PVD, and any method may be used as long as it is a method of filling the trench 24 with indium other than the liquid phase. For example, CVD that fills the trench 24 with vapor-phase indium may be used. Since CVD has a high step coverage, even if the aspect ratio of the trench 24 is high, the inner surface of the trench 24 can be covered with indium 39 without gaps, and as a result, the indium 39 can be reliably filled in the trenches 24 without gaps. Can do.

Note that indium 39 may be filled into the trench 24 by using reflow after PVD. Alternatively, a small amount of indium phosphorus may be filled in the trench 24 in advance, and then indium may be filled in the trench 24. Note that conventional methods such as thermal CVD, photo CVD, and plasma CVD can be used for CVD. However, in order to relatively reduce impurities in indium to be filled, CVD other than plasma CVD is used. desirable.

Next, in the heat treatment apparatus 37 of FIG. 7, the wafer W is heated by the lamp heater 19 to melt the indium 39, and then gaseous phosphorus is supplied from the gas introduction tube 20 to the processing space S ′ (FIG. 9C )). At this time, since the indium 39 is not covered with other layers, the supplied phosphorus contacts and melts into the molten indium 39, and indium phosphorus is formed in the molten indium 39. In this embodiment, since the wafer W is surrounded by the outflow prevention wall 38, the molten indium 39 does not flow out from the wafer W.

After indium phosphide is also formed in the melted indium 39 in the trench 24, when cooling gas is supplied from the cooling gas supply path 21 of the susceptor 18 and the wafer W is gradually cooled from the bottom surface side, silicon at the bottom of the trench 24 is formed. Single-crystallized indium phosphide 32 is deposited using the crystal plane 25 as a seed (FIG. 9D) (precipitation step). The precipitation of crystallized indium phosphide 32 continues upward from the bottom of the trench 24 (see the arrow in FIG. 9D).

At this time, as in the first embodiment, the threading dislocation defect 31 is generated from the crystal plane 25 due to lattice mismatch. If the aspect ratio of the trench 24 is 1 or more, the threading dislocation defect 31 is a trench. If the aspect ratio is 2 or more, a portion where the threading dislocation defect 31 does not exist in the crystallized indium phosphorus 32 can be sufficiently secured. Further, if the aspect ratio is 3 to 10, a portion where the threading dislocation defect 31 does not exist in the crystallized indium phosphide 32 can be more sufficiently secured.

Next, after the inside of the trench 24 is filled with crystallized indium phosphide 32, cooling is further continued to solidify all the melted indium 39, and then the indium 39 existing above the trench 24 is removed by CMP or the like. Further, the covering layer 23 is removed by dry etching or wet etching to obtain a fin structure 33 of crystallized indium phosphide 32 ((F) in FIG. 9) (removal step). The process ends.

According to the fine structure forming method according to the present embodiment, indium 39 is filled in the trench 24 in a solid phase, so that the indium 39 is filled in the trench 24 without any gap and is in contact with the silicon crystal plane 25 at the bottom of the trench 24. Indium 39 filled in the trench 24 is heated and melted, phosphorus is added to generate indium phosphorus in the melted indium 39, and the melted indium 39 is gradually cooled to form silicon. In order to deposit the crystallized indium phosphide 32 using the crystal plane 25 as a seed, the fin structure 33 of the crystallized indium phosphide 32 in which the shape of the trench 24 is reflected and the part where the threading dislocation defect 31 does not exist is secured. Can do.

In the fine structure forming method according to the present embodiment described above, the indium 39 also covers the surface of the coating layer 23. Therefore, when the indium 39 is heated and melted, the coating layer 23 is also covered with the molten indium 39. This increases the contact area between the vapor phase phosphorus supplied to the processing space S ′ and the molten indium 39, so that phosphorus can be easily added to the molten indium 39.

Further, in the fine structure forming method according to the above-described embodiment, the melted indium 39 is directly exposed to the processing space S ′ in the chamber 17. Thus, an additive can be easily added to indium phosphide. Further, it is not necessary to cover both the surface of the coating layer 23 and the trench 24 with indium 39, and only the trench 24 may be covered as shown in FIG. Thereby, the usage-amount of indium can be reduced.

The microstructure forming method according to this embodiment described above is a group III-V semiconductor other than indium phosphorus, such as aluminum phosphorus, aluminum arsenic, aluminum antimony, gallium phosphorus, gallium arsenide, gallium antimony, indium arsenic, indium antimony, or The present invention can also be applied to the case where a fin structure is formed using a compound containing these. When the fin structure is formed of an aluminum-based III-V group semiconductor, the trench 24 is filled with aluminum, and when the fin structure is formed of an indium-based III-V group semiconductor, the trench 24 is filled with indium. When the fin structure is formed of a gallium-based III-V group semiconductor, the trench 24 is filled with gallium.

As mentioned above, although this invention was demonstrated using said each embodiment, this invention is not limited to said each embodiment.

For example, in each of the above embodiments, the crystal face 25 of the silicon Miller index (001) is exposed at the bottom of the trench 24, but the Miller index of the exposed crystal face 25 is not limited to this, for example, (010), It may be (011), (100), (101), (110) or (111).

In each of the above embodiments, the indium phosphide microstructure is formed using the trench 24. However, the indium phosphide microstructure is formed using the holes provided in the wet etch stop layer 22 and the covering layer 23. May be.

Further, the fin structure 33 obtained by each of the above embodiments can be suitably used for a three-dimensional MOSFET, so-called FinFET. Moreover, you may use for photonic devices other than FET, such as LED, a semiconductor laser, a photodetector, and a solar cell.

In each embodiment of the present invention, the aspect ratio of the trench 24 (fin structure 33) is set to 1 or more from the viewpoint of securing a portion where the threading dislocation defect 31 does not exist in the fin structure 33. Since the effect of facilitating filling of indium phosphide / indium can be achieved, the present invention is also applied to filling of indium phosphide / indium into trenches having a width of 100 nm or less, which makes filling of indium phosphide / indium difficult. be able to. In this case, even if the width of the trench is 100 nm or less, the trench can be surely filled with indium phosphide / indium.

Further, in the case of a laser circuit or a high-frequency circuit other than ULSI, the fine fin structure 33 having a width of 100 nm or less is not necessary. However, even if the width is larger than 100 nm, the laser circuit or the high-frequency circuit has III-V. Since the fin structure of a group semiconductor is useful, the present invention may be applied to filling indium phosphide / indium into trenches having a width greater than 100 nm.

Another object of the present invention is to supply a storage medium storing software program codes for realizing the functions of the above-described embodiments to a computer (not shown) included in the CVD film forming apparatus 10 and the like, and to execute the CPU of the computer. Is also achieved by reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code and the storage medium storing the program code constitute the present invention.

Examples of the storage medium for supplying the program code include RAM, NV-RAM, floppy (registered trademark) disk, hard disk, magneto-optical disk, CD-ROM, CD-R, CD-RW, DVD (DVD). -ROM, DVD-RAM, DVD-RW, DVD + RW) and other optical disks, magnetic tapes, non-volatile memory cards, other ROMs, etc., as long as they can store the program code. Alternatively, the program code may be supplied to the computer by downloading from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.

Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) running on the CPU based on the instruction of the program code. Includes a case where part or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.

Further, after the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. This includes a case where the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

The form of the program code may be in the form of object code, program code executed by an interpreter, script data supplied to the OS, and the like.

This application claims priority based on Japanese Application No. 2013-037136 filed on Feb. 27, 2013, the entire contents of which are incorporated in this application.

W wafer 23 coating layer 24 trench 25 crystal plane 26 indium phosphide 27 indium layer 30 cap layer 31 threading dislocation defect 32 crystallized indium phosphide 39 indium

Claims

Forming a narrow groove in the coating layer covering the silicon substrate, and exposing the silicon crystal plane of the silicon substrate at the bottom of the groove; and
A filling step of filling the groove with a III-V semiconductor in a gas phase or a solid phase;
Precipitation for heating and melting the filled group III-V semiconductor and then gradually cooling the melted group III-V semiconductor to precipitate the group III-V semiconductor crystal using the silicon crystal plane as a seed. Steps,
And a removal step of removing the coating layer.
2. The fine structure forming method according to claim 1, wherein the narrow groove has an aspect ratio of 1 or more.
2. The method for forming a microstructure according to claim 1, wherein the groove filled with the III-V semiconductor is covered with a group III metal layer between the filling step and the deposition step.
The fine structure forming method according to claim 1, wherein, in the precipitation step, a group V element is added to the molten group III-V semiconductor.
2. The microstructure forming method according to claim 1, wherein an additive is added to the molten group III-V semiconductor in the precipitation step.
4. The microstructure forming method according to claim 3, wherein the group III metal layer is further covered with another coating layer between the filling step and the deposition step.
In the filling step, the III-V group semiconductor is filled into the groove by MOCVD.
2. The microstructure forming method according to claim 1, wherein the group III metal layer is formed by PVD.
The Miller index of the silicon crystal plane exposed at the bottom of the groove is (001), (010), (011), (100), (101), (110) or (111). The fine structure forming method according to claim 1.
2. The method for forming a microstructure according to claim 1, wherein the III-V semiconductor is indium phosphide.
Forming a narrow groove in the coating layer covering the silicon substrate, and exposing the silicon crystal plane of the silicon substrate at the bottom of the groove; and
A filling step of filling the groove with a Group III metal in a gas phase or a solid phase;
The filled Group III metal is heated and melted, and then a Group V element is added to the melted Group III metal to generate a Group III-V semiconductor. A precipitation step of precipitating a crystal of the group III-V semiconductor using as a seed;
And a removal step of removing the coating layer.
12. The method for forming a fine structure according to claim 11, wherein the narrow groove has an aspect ratio of 1 or more.
12. The microstructure forming method according to claim 11, wherein in the filling step, the group III metal also covers the surface of the coating layer.
12. The microstructure forming method according to claim 11, wherein in the precipitation step, an additive is added to the molten group III metal.
12. The microstructure forming method according to claim 11, wherein in the filling step, the group III metal is filled into the groove by PVD.
12. The microstructure forming method according to claim 11, wherein in the filling step, the group III metal is filled into the groove by CVD.
The Miller index of the silicon crystal plane exposed at the bottom of the groove is (001), (010), (011), (100), (101), (110) or (111). The fine structure forming method according to claim 11.
12. The method for forming a microstructure according to claim 11, wherein the III-V semiconductor is indium phosphide.
Precipitation in which the III-V semiconductor filled in the groove is heated and melted, and then the molten III-V semiconductor is gradually cooled to precipitate the III-V semiconductor crystal using the crystal plane of the substrate as a seed. A method for forming a microstructure characterized by comprising steps.
20. The fine structure forming method according to claim 19, wherein the fine structure is a Fin-FET.
A fin structure formed on a silicon substrate, made of a single crystal III-V group semiconductor, having a width of 10 nm to 50 nm and an aspect ratio of 1 or more.