WO2014128793A1 - Semiconductor device and method of producing same - Google Patents

Semiconductor device and method of producing same Download PDF

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Publication number
WO2014128793A1
WO2014128793A1 PCT/JP2013/005835 JP2013005835W WO2014128793A1 WO 2014128793 A1 WO2014128793 A1 WO 2014128793A1 JP 2013005835 W JP2013005835 W JP 2013005835W WO 2014128793 A1 WO2014128793 A1 WO 2014128793A1
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Prior art keywords
film
semiconductor device
cap
barrier film
wiring
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PCT/JP2013/005835
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French (fr)
Japanese (ja)
Inventor
浜田　政一
松本　晋
小堀　悦理
平野　博茂
道成 手谷
垂水　喜明
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パナソニック株式会社
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Publication of WO2014128793A1 publication Critical patent/WO2014128793A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1646—Characteristics of the product obtained
    • C23C18/165—Multilayered product
    • C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections

Definitions

  • the present invention relates to a structure of a rewiring formed on a semiconductor device and a manufacturing method thereof.
  • the semiconductor device has a semiconductor element such as a MISFET formed on a semiconductor substrate and a multilayer wiring formed above the semiconductor element.
  • a rewiring is formed on the uppermost wiring.
  • copper is used as a material for multilayer wiring and rewiring of semiconductor devices because of its low electrical resistance.
  • Patent Document 1 describes a method of forming a barrier film that prevents intrusion of moisture and oxygen and prevents diffusion of copper wiring on the surface of the copper wiring whose surface has been activated by electroless electroplating. Yes.
  • a catalyst is always required when the barrier film covering the copper wiring is formed by electroless plating.
  • palladium (Pd) is used as a catalyst in order to form a barrier film.
  • Pd as a catalyst is formed not only on the surface of the copper wiring but also on the surface of the underlying insulating film below the copper wiring. For this reason, the same metal as the barrier film is deposited on the surface of the base insulating film.
  • the adjacent copper wirings are not short-circuited by the metal formed on the base insulating film. Further, if the semiconductor device is driven at a low voltage, a leak current that affects the operation does not occur. However, when the distance between the copper wirings is short or in a high voltage semiconductor device, the metal formed on the base insulating film causes a short circuit or a leak, thereby reducing the reliability of the semiconductor device.
  • the present application is to suppress an increase in wiring resistance due to oxidation of copper wiring and a decrease in reliability due to electromigration, and to realize a semiconductor device in which short-circuiting and leakage between copper wirings are unlikely to occur and a method for manufacturing the same. Objective.
  • One embodiment of a method for manufacturing a semiconductor device includes a step of forming an insulating film on a substrate provided with a semiconductor element, a step of forming a first barrier film on the insulating film, A step of forming a seed film thereon, a step of forming a trench pattern for forming a wiring having an opening that exposes the seed film by using a photosensitive material and covering the insulating film; and copper wiring by electrolytic plating in the opening A step of forming a cap film on the copper wiring, a step of removing the wiring formation groove pattern, and a step of removing the wiring formation groove pattern after the step of forming the cap film.
  • the side surface of the first barrier film, the side surface of the seed film, Side of copper wiring and cap The side and upper surfaces of the film, and a step of forming a second barrier film cap layer as a catalyst.
  • the step of forming the cap film may be a step of forming a crystalline metal film by electrolytic plating.
  • the cap film may be Ni, Fe, Co, Ru, Ir, Pd, or Pt.
  • the cap film may be a laminated film in which a plurality of metal films are laminated.
  • the step of forming the second barrier film may be a step of forming an amorphous metal film by electroless plating.
  • the second barrier film may be Ni, Co, CoWP, Pd, Ru, Ag, Au, or Pt.
  • the barrier film may be a Ni film containing phosphorus.
  • One embodiment of a semiconductor device is formed over an insulating film formed over a substrate provided with a semiconductor element, a first barrier film formed over the insulating film, and the first barrier film.
  • the second barrier film may continuously cover a side surface of the first barrier film, a side surface of the copper wiring, and a side surface and an upper surface of the cap film.
  • the cap film may be a crystalline metal film
  • the barrier film may be an amorphous metal film
  • the crystalline metal film may be formed by an electrolytic plating method, and the amorphous metal film may be formed by an electroless plating method.
  • the cap film may be Ni, Fe, Co, Ru, Ir, Pd, or Pt.
  • the second barrier film may be Ni, Co, CoWP, Pd, Ru, Ag, Au, or Pt.
  • the second barrier film may be a Ni film containing phosphorus.
  • the cap film may be a laminated film in which a plurality of metal films are laminated.
  • the cap film may be a stacked film of an amorphous Ni film and a crystalline Pd film provided on the amorphous Ni.
  • a semiconductor device that suppresses an increase in wiring resistance due to oxidation of copper wiring and a decrease in reliability due to electromigration, and is less prone to short circuit and leakage between copper wirings. And a manufacturing method thereof.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment.
  • FIG. 2A is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps.
  • FIG. 2B is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment in the order of steps.
  • FIG. 2C is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps.
  • FIG. 3A is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps.
  • FIG. 3B is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment in the order of steps.
  • FIG. 3C is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment in the order of steps.
  • FIG. 4A is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps.
  • FIG. 4B is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps.
  • FIG. 4C is a cross-sectional view showing the method of manufacturing the semiconductor device according to one embodiment in the order of steps.
  • FIG. 5 is a cross-sectional view showing a modification of the semiconductor device according to the embodiment.
  • FIG. 6A is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a modification in order of processes.
  • FIG. 6B is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the modification in order of processes.
  • FIG. 6C is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the modification in order of processes.
  • FIG. 7A is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a modification in order of processes.
  • FIG. 7B is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the modification in order of processes.
  • FIG. 8A is a cross-sectional view for explaining a problem that may occur when a copper wiring is formed.
  • FIG. 8B is a cross-sectional view for explaining a problem that may occur when the copper wiring is formed.
  • a catalyst is always required.
  • palladium (Pd) is used as a catalyst to form a barrier film.
  • Pd particles are deposited on the surface of the copper wiring by the reactions shown in the following formulas (1) and (2).
  • Pd 2+ + 2e ⁇ ⁇ Pd (2) Using the Pd particles deposited on the surface of the copper wiring as a catalyst, a barrier film is formed on the surface of the copper wiring.
  • Ni nickel
  • reactions of the following formulas (3) to (6) occur in the plating solution, and a Ni film is formed on the surface of the copper wiring.
  • hypophosphorous acid is oxidized to phosphorous acid by a Pd catalyst.
  • Ni 2+ present in the plating solution is reduced to Ni and adheres to the surface of the copper wiring.
  • Ni acts as a catalyst like Pd, as shown in formula (5), and Ni2 + is reduced to Ni as shown in formula (6).
  • a Ni film is formed on the Cu surface.
  • Patent Document 2 also describes a method of forming a Ni barrier film on the surface of a copper wiring. Specifically, it is described that a surface barrier film that covers each of these surfaces is formed by electroless plating using the surface of the copper wiring and the side surface of the bottom barrier film as seeds. Also in this case, a catalyst such as Pd is required for electroless plating of Ni on the surface of the copper wiring.
  • the Pd particles 205 are deposited on the surface of the copper wiring 204, the Pd particles 205 are also deposited on a region other than the surface of the copper wiring 204, for example, the base insulating film 203.
  • the Ni film is coated not only on the surface of the copper wiring 204 but also on the base insulating film 203 so as to cover the Pd particles 205.
  • 206 is electrolessly plated. The same phenomenon occurs not only when the barrier film is made of Ni but also when the barrier film is formed using other materials.
  • the Ni film 206 formed on the base insulating film 203 causes a short circuit or a leak.
  • the semiconductor device of this embodiment has a multilayer wiring layer 110 and a rewiring 120 provided on a semiconductor substrate 100 on which a semiconductor element (not shown) is formed.
  • the multilayer wiring layer 110 includes a plurality of interlayer insulating films 111 and 112, wirings 113 and 114, and plugs 115 and 116.
  • the wirings 113 and 114 are wirings made of copper (Cu) electrically connected to the semiconductor element, and are electrically connected by the plug 115.
  • the rewiring 120 is provided on the multilayer wiring layer 110 and is electrically connected to the wiring 114 by the plug 116.
  • a protective film 103 is provided so as to cover the rewiring 120 and the multilayer wiring layer 110.
  • the rewiring 120 includes a first barrier film 121, a seed film 122, a copper wiring 125, and a cap film 126 that are sequentially provided on the multilayer wiring layer 110.
  • a side surface of the first barrier film 121, a side surface of the seed film 122, a side surface of the copper wiring 125, and a side surface and an upper surface of the cap film 126 are covered with the second barrier film 127.
  • the first barrier film 121 may be a titanium (Ti) film having a thickness of 100 nm.
  • the seed film 122 may be a Cu layer having a thickness of 100 nm, for example.
  • the copper wiring 125 can have a thickness of 5 ⁇ m, for example.
  • the cap film 126 can be a crystalline Ni film having a thickness of 1 ⁇ m, for example.
  • the second barrier film 127 can be an amorphous Ni film having a thickness of 1 ⁇ m, for example.
  • the cap film 126 is formed of a material that functions as a catalyst in the electroless plating for forming the second barrier film 127.
  • the cap film 126 is formed in contact with the upper surface of the copper wiring 125 and is not formed on the side surface of the copper wiring 125. Therefore, the cap film 126 is not in contact with any of the upper surface of the interlayer insulating film 112, the side surface of the first barrier film 121, and the side surface of the seed film 122. Since the cap film 126 serving as the catalyst is formed only on the upper surface of the copper wiring 125, the cap film 126 serving as the catalyst can be formed in a state where the portion other than the upper surface of the copper wiring 125 is covered.
  • the catalyst for forming the second barrier film 127 does not adhere to the upper surface of the multilayer wiring layer 110. Therefore, short circuit between the rewirings 120 and the occurrence of leakage current between the rewiring 120 and the multilayer wiring layer 110 can be prevented, and the reliability of the semiconductor device can be improved.
  • a multilayer wiring layer 110 is formed on a semiconductor substrate 100 such as a silicon substrate on which a semiconductor element (not shown) is formed.
  • the multilayer wiring layer 110 may be formed as follows, for example. First, the interlayer insulating film 111 is formed, and the wiring 113 made of Cu is formed in the interlayer insulating film 111. An interlayer insulating film 112 is further formed on the interlayer insulating film 111 on which the wiring 113 is formed, and a wiring 114 is formed in the interlayer insulating film 112.
  • the multilayer wiring layer 110 has a two-layer structure, but the multilayer wiring layer 110 having a desired number of layers can be formed by repeating the wiring formation process.
  • a first barrier film 121 made of Ti having a thickness of 100 nm and a seed film 122 having a thickness of 100 nm are formed on the entire surface of the semiconductor substrate 100 on which the multilayer wiring layer 110 is formed. Films are formed in order by sputtering.
  • the first barrier film 121 is not limited to Ti, and may be tantalum (Ta) or the like, or may be a metal compound containing nitrogen (N) or the like, or a laminated film thereof.
  • a photosensitive material having a thickness of 10 ⁇ m is applied on the seed film 122. Thereafter, the photosensitive material is exposed and developed by a normal lithography process to form a wiring forming groove pattern 131 having an opening 131a that covers the multilayer wiring layer 110 and exposes the seed film 122.
  • the width of the opening 131a (corresponding to the wiring width) of the groove pattern 131 for wiring formation is 20 ⁇ m, and the interval between the adjacent openings 131a (corresponding to the wiring interval) is 20 ⁇ m.
  • the wiring width and the wiring interval are examples, and wiring of any size may be formed.
  • the wiring forming groove pattern 131 may have a forward tapered shape.
  • the opening 131a may have an upper opening width larger than a bottom opening width.
  • a copper wiring 125 having a thickness of 5 ⁇ m is formed in the opening 131a by Cu electrolytic plating.
  • the film thickness of the copper wiring 125 can be appropriately changed according to the performance of the semiconductor device.
  • a cap film 126 made of Ni having a thickness of 1 ⁇ m is formed on the upper surface of the copper wiring 125 by electrolytic plating in the state where the wiring forming groove pattern 131 exists.
  • the crystalline cap film 106 can be formed only on the upper surface of the copper wiring 125 by forming the cap film 126 by electrolytic plating.
  • the cap film 126 can be formed without contacting any of the upper surface of the interlayer insulating film 112, the side surface of the first barrier film 121, and the side surface of the seed film 122.
  • the film thickness of the cap film 126 can be changed as appropriate according to the performance of the semiconductor device.
  • the cap film 126 is formed by the electrolytic plating method.
  • the cap film 126 is formed by using an electroless plating method, a vapor deposition method, or the like as long as it is performed in a state where the wiring forming groove pattern 131 exists. Also good.
  • By forming the cap film 126 before removing the wiring forming groove pattern 131 it is possible to prevent metal from adhering to the upper surface of the multilayer wiring layer 110.
  • the cap film 126 has a catalytic action and can be formed of a metal that can be formed by electrolytic plating, electroless plating, or vapor deposition.
  • a metal that can be formed by electrolytic plating, electroless plating, or vapor deposition.
  • it can be formed of iron (Fe), Co, Ru, iridium (Ir), Pd, Pt or the like instead of Ni.
  • the wiring formation groove pattern 131 is removed.
  • the seed film 122 and the first barrier film 121 exposed from between the copper wirings 125 are removed by a wet etching method.
  • the seed film 122 and the first barrier film 121 are in a state that exists only below the copper wiring 125.
  • the side surfaces of the seed film 122 and the first barrier film 121 may not be aligned with the side surfaces of the copper wiring 125.
  • the side surfaces of the seed film 122 and the first barrier film 121 may have a shape that enters the inside from the position of the side surface of the copper wiring 125 or a shape that protrudes to the outside.
  • the semiconductor substrate 100 on which the copper wiring 125 and the cap film 126 are formed is immersed in a Ni electroless plating solution, and the side surfaces of the first barrier film 121, the seed film 122, A second barrier film 127 made of Ni is formed on the side surfaces of the copper wiring 125 and the side surfaces and upper surface of the cap film 126.
  • a Ni electroless plating solution an acidic (pH 4 to 6) solution containing nickel sulfate and sodium hypophosphite as main components was used.
  • the thickness of the formed second barrier film 127 is as follows: the side surface of the first barrier film 121, the side surface of the seed film 122, the copper wiring The film thickness is substantially uniform at any of the side surfaces of 125 and the side surfaces and upper surface of the cap film 126.
  • the rewiring 120 has a reverse taper shape in which the bottom width is narrower than the top width.
  • a protective film 103 that covers the rewiring 120 is formed.
  • a cap film 126 made of Ni is formed on the copper wiring 125.
  • the cap film 126 acts as a catalyst represented by the formula (7) in the Ni electroless plating solution.
  • hypophosphorous acid in the electroless plating solution is oxidized to phosphorous acid to release electrons, and Ni ions in the electroless plating solution are reduced as shown in Formula (8).
  • the second barrier film 127 made of Ni having a thickness of 1 ⁇ m is formed on the side surface of the first barrier film 121, the side surface of the seed film 122, the side surface of the copper wiring 125, and the side surface and the upper surface of the cap film 126. Is done.
  • the second barrier film 127 formed in this way is an amorphous Ni film containing 4 wt% or more of phosphorus (P).
  • the second barrier film 127 continuously covers the side surface of the first barrier film 121, the side surface of the copper wiring 125, and the side surface and upper surface of the cap film 126.
  • the amorphous Ni film formed by the electroless plating method has fewer grain boundaries in the film than the crystalline Ni film formed by the electroplating method. For this reason, it is more excellent as a barrier film that suppresses the diffusion of Cu forming the copper wiring 125 into the protective film 103. Further, when the phosphorus concentration in the film is increased, there is an advantage that the Ni film tends to be in an amorphous state and the film stress can be reduced.
  • hypophosphorous acid is used as the electroless plating solution
  • dimethylamine borane or the like having an action of promoting the catalytic action of the cap film 126 may be used.
  • the Ni film is formed as the second barrier film 127
  • any metal that can be electrolessly plated using the cap film 126 as a catalyst can be formed in the same manner.
  • a second barrier film made of cobalt (Co), cobalt compound CoWP, Pd, ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), or the like can be formed. .
  • the cap film may be a laminated film in which a plurality of metal films are laminated.
  • a cap film 136 which is a laminated film in which a first cap film 136A made of Ni and a second cap film 136B made of Pd are sequentially laminated may be provided.
  • a cap film combining the characteristics (for example, magnetism and barrier properties) of each metal or a cap film showing various resistance values is created.
  • the rewiring can have functionality.
  • the copper wiring 125 is formed in the same manner as in the steps up to FIG. 3A. Thereafter, as shown in FIG. 6A, the first cap made of Ni having a thickness of 0.2 ⁇ m is formed on the upper surface of the copper wiring 125 by the electroless plating method in the state where the groove pattern 131 for wiring formation exists.
  • the film 136A may be formed.
  • a second cap film 136B made of Pd having a thickness of 0.3 ⁇ m may be formed by electrolytic plating.
  • the barrier property of the copper wiring 125 is increased.
  • the first cap film 136A may be a crystalline film formed by an electrolytic plating method or the like.
  • the first cap film 136A may be formed by a vapor deposition method or the like.
  • the first cap film 136A and the second cap film 136B may be different metal films having a catalytic action. Specifically, the first cap film 136A and the second cap film 136B may be a combination of two kinds of metals selected from Ni, Fe, Co, Ru, Ir, Pd, and Pt.
  • the second cap film 136B may be formed by an electroless plating method, a vapor deposition method, or the like.
  • the first cap film 136A and the second cap film 136B may be formed by the same method.
  • the film thicknesses of the first cap film 136A and the second cap film 136B can be changed as appropriate according to the performance of the semiconductor device.
  • the wiring formation groove pattern 131 is removed.
  • the seed film 122 and the first barrier film 121 exposed from between the copper wirings 125 are removed by a wet etching method.
  • the semiconductor substrate 100 on which the copper wiring 125 and the cap film 136 are formed is immersed in an Ni electroless plating solution, and the side surfaces of the first barrier film 121, the seed film 122, A second barrier film 127 made of Ni is formed on the side surfaces of the copper wiring 125 and the side surfaces and upper surface of the cap film 136.
  • a protective film 103 covering the rewiring 120 is formed.
  • the structure and the manufacturing method of this embodiment are useful in a semiconductor device that requires a high breakdown voltage of 600 V or higher.
  • the semiconductor device and the manufacturing method thereof according to the present disclosure can suppress an increase in wiring resistance due to oxidation of copper wiring and a decrease in reliability due to electromigration, and can make shorting and leakage between copper wirings less likely to occur. It is useful as a highly integrated and high power semiconductor device.

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Abstract

The purpose of the present invention is to achieve a semiconductor device which suppresses increase in wiring resistance caused by oxidation of copper wiring and decrease in reliability caused by electromigration, and which is resistant to short circuits between copper wiring, leakage, and the like. The semiconductor device is provided with: an insulating film which is formed upon a substrate which is provided with a semiconductor element; a first barrier film formed upon the insulating film; copper wiring formed upon the first barrier film; a cap film formed upon and in contact with the copper wiring; and a second barrier film which covers sides of the first barrier film, sides of the copper wiring, and sides and the top of the cap film.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置の上に形成される再配線の構造及び製造方法に関する。 The present invention relates to a structure of a rewiring formed on a semiconductor device and a manufacturing method thereof.
　半導体装置の高集積化と高機能化を達成するために、動作速度の向上やメモリの大容量化が要求されている。それに合わせて半導体基板上に設ける再配線の形成プロセスにおいても、微細化及び低抵抗化が要求されている。 In order to achieve high integration and high functionality of semiconductor devices, it is required to improve operation speed and increase memory capacity. Accordingly, miniaturization and low resistance are also required in the rewiring forming process provided on the semiconductor substrate.
　半導体装置は、半導体基板上に形成されたＭＩＳＦＥＴ等の半導体素子と、この半導体素子の上方に形成された多層の配線を有する。最上層配線の上には、再配線が形成される。一般的に、半導体装置の多層配線や再配線の材料には、電気抵抗が低いことから、銅が使用されている。 The semiconductor device has a semiconductor element such as a MISFET formed on a semiconductor substrate and a multilayer wiring formed above the semiconductor element. A rewiring is formed on the uppermost wiring. Generally, copper is used as a material for multilayer wiring and rewiring of semiconductor devices because of its low electrical resistance.
　しかし、配線材料として銅を使用した場合、配線の微細化に伴って発生する配線間のリーク、絶縁膜中の水分や酸素により銅配線の表面が酸化することによる配線抵抗の増加、及びエレクトロマイグレーションによる信頼性低下等の問題が生じる。これらの問題を解決することを目的とした検討がなされている（例えば、特許文献１、非特許文献１を参照）。例えば、特許文献１には、水分や酸素の侵入を防ぐと共に、銅配線の拡散を防止するバリア膜を、表面を活性化した銅配線の表面に無電解電気めっきにより形成する方法が記載されている。 However, when copper is used as the wiring material, leakage between wirings due to miniaturization of wiring, increase in wiring resistance due to oxidation of the surface of the copper wiring by moisture or oxygen in the insulating film, and electromigration This causes problems such as reliability degradation. Studies aimed at solving these problems have been made (see, for example, Patent Document 1 and Non-Patent Document 1). For example, Patent Document 1 describes a method of forming a barrier film that prevents intrusion of moisture and oxygen and prevents diffusion of copper wiring on the surface of the copper wiring whose surface has been activated by electroless electroplating. Yes.
国際公開２０１１／０８０８２７号公報International Publication No. 2011/080827 特開２００８－１５９７９６号公報JP 2008-159796 A
　しかしながら、銅配線を被覆するバリア膜を無電解めっきにより形成する場合には、必ず触媒が必要となる。特許文献１に記載の配線構造の形成方法においては、バリア膜を形成するためにパラジウム（Ｐｄ）を触媒として用いる。触媒であるＰｄは、銅配線の表面だけでなく銅配線の下方の下地絶縁膜の表面にも形成される。このため、下地絶縁膜の表面にもバリア膜と同じ金属が堆積される。 However, a catalyst is always required when the barrier film covering the copper wiring is formed by electroless plating. In the method for forming a wiring structure described in Patent Document 1, palladium (Pd) is used as a catalyst in order to form a barrier film. Pd as a catalyst is formed not only on the surface of the copper wiring but also on the surface of the underlying insulating film below the copper wiring. For this reason, the same metal as the barrier film is deposited on the surface of the base insulating film.
　隣接する銅配線同士の間隔が十分に広い場合には、下地絶縁膜上に形成された金属により隣接する銅配線同士がショートすることはない。また、低電圧で駆動する半導体装置であれば、動作に影響するようなリーク電流も発生しない。しかし、銅配線間の距離が狭い場合や、高電圧の半導体装置においては、下地絶縁膜上に形成された金属は、ショートやリークの原因となり、半導体装置の信頼性を低下させる。 When the interval between adjacent copper wirings is sufficiently wide, the adjacent copper wirings are not short-circuited by the metal formed on the base insulating film. Further, if the semiconductor device is driven at a low voltage, a leak current that affects the operation does not occur. However, when the distance between the copper wirings is short or in a high voltage semiconductor device, the metal formed on the base insulating film causes a short circuit or a leak, thereby reducing the reliability of the semiconductor device.
　下地絶縁膜の上に形成された金属触媒を洗浄により除去する方法も考えられるが、金属触媒を除去するために薬液を使用すると、配線自体が溶解して金属粒子（パーティクル）が生成する。配線間に金属粒子（パーティクル）が付着すると、金属触媒が付着している場合と同じ結果になる。 Although a method of removing the metal catalyst formed on the base insulating film by washing is also conceivable, when a chemical solution is used to remove the metal catalyst, the wiring itself is dissolved to generate metal particles (particles). When metal particles (particles) are attached between the wirings, the same result as when the metal catalyst is attached is obtained.
　本願は、銅配線の酸化による配線抵抗の増加及びエレクトロマイグレーションによる信頼性の低下等を抑えると共に、銅配線同士のショート及びリーク等が生じにくい半導体装置及びその製造方法を実現できるようにすることを目的とする。 The present application is to suppress an increase in wiring resistance due to oxidation of copper wiring and a decrease in reliability due to electromigration, and to realize a semiconductor device in which short-circuiting and leakage between copper wirings are unlikely to occur and a method for manufacturing the same. Objective.
　半導体装置の製造方法の一態様は、半導体素子が設けられた基板の上に絶縁膜を形成する工程と、絶縁膜の上に第１のバリア膜を形成する工程と、第１のバリア膜の上にシード膜を形成する工程と、感光性材料を用いて、絶縁膜を覆い、シード膜を露出する開口部を有する配線形成用溝パターンを形成する工程と、開口部に電解めっきにより銅配線を形成する工程と、銅配線の上にキャップ膜を形成する工程と、キャップ膜を形成する工程よりも後に、配線形成用溝パターンを除去する工程と、配線形成用溝パターンを除去する工程よりも後に、第１のバリア膜及びシード膜の露出した部分を除去する工程と、第１のバリア膜及びシード膜を除去する工程よりも後に、第１のバリア膜の側面、シード膜の側面、銅配線の側面、並びにキャップ膜の側面及び上面に、キャップ膜を触媒として第２のバリア膜を形成する工程とを備えている。 One embodiment of a method for manufacturing a semiconductor device includes a step of forming an insulating film on a substrate provided with a semiconductor element, a step of forming a first barrier film on the insulating film, A step of forming a seed film thereon, a step of forming a trench pattern for forming a wiring having an opening that exposes the seed film by using a photosensitive material and covering the insulating film; and copper wiring by electrolytic plating in the opening A step of forming a cap film on the copper wiring, a step of removing the wiring formation groove pattern, and a step of removing the wiring formation groove pattern after the step of forming the cap film. After the step of removing the exposed portions of the first barrier film and the seed film and the step of removing the first barrier film and the seed film, the side surface of the first barrier film, the side surface of the seed film, Side of copper wiring and cap The side and upper surfaces of the film, and a step of forming a second barrier film cap layer as a catalyst.
　製造方法の一態様において、キャップ膜を形成する工程は、電解めっきにより結晶性の金属膜を形成する工程であってもよい。 In one embodiment of the manufacturing method, the step of forming the cap film may be a step of forming a crystalline metal film by electrolytic plating.
　製造方法の一態様において、キャップ膜は、Ｎｉ、Ｆｅ、Ｃｏ、Ｒｕ、Ｉｒ、Ｐｄ、又はＰｔであってもよい。 In one aspect of the manufacturing method, the cap film may be Ni, Fe, Co, Ru, Ir, Pd, or Pt.
　製造方法の一態様において、キャップ膜は、複数の金属膜が積層された積層膜であってもよい。 In one aspect of the manufacturing method, the cap film may be a laminated film in which a plurality of metal films are laminated.
　製造方法の一態様において、第２のバリア膜を形成する工程は、無電解めっきによりアモルファス性の金属膜を形成する工程であってもよい。 In one embodiment of the manufacturing method, the step of forming the second barrier film may be a step of forming an amorphous metal film by electroless plating.
　製造方法の一態様において、第２のバリア膜は、Ｎｉ、Ｃｏ、ＣｏＷＰ、Ｐｄ、Ｒｕ、Ａｇ、Ａｕ、又はＰｔであってもよい。 In one aspect of the manufacturing method, the second barrier film may be Ni, Co, CoWP, Pd, Ru, Ag, Au, or Pt.
　製造方法の一態様において、バリア膜は、リンを含むＮｉ膜であってもよい。 In one embodiment of the manufacturing method, the barrier film may be a Ni film containing phosphorus.
　半導体装置の一態様は、半導体素子が設けられた基板の上に形成された絶縁膜と、絶縁膜の上に形成された第１のバリア膜と、第１のバリア膜の上に形成された銅配線と、銅配線の上に接して形成されたキャップ膜と、第１のバリア膜の側面、銅配線の側面並びにキャップ膜の側面及び上面を覆う第２のバリア膜とを備えている。 One embodiment of a semiconductor device is formed over an insulating film formed over a substrate provided with a semiconductor element, a first barrier film formed over the insulating film, and the first barrier film. A copper wiring; a cap film formed on and in contact with the copper wiring; and a second barrier film that covers a side surface of the first barrier film, a side surface of the copper wiring, and a side surface and an upper surface of the cap film.
　半導体装置の一態様において、第２のバリア膜は、第１のバリア膜の側面、銅配線の側面及びキャップ膜の側面及び上面を連続して覆っていてもよい。 In one embodiment of the semiconductor device, the second barrier film may continuously cover a side surface of the first barrier film, a side surface of the copper wiring, and a side surface and an upper surface of the cap film.
　半導体装置の一態様において、キャップ膜は結晶性の金属膜であり、バリア膜はアモルファス性の金属膜であってもよい。 In one embodiment of the semiconductor device, the cap film may be a crystalline metal film, and the barrier film may be an amorphous metal film.
　半導体装置の一態様において、結晶性の金属膜は電解めっき法により形成され、アモルファス性の金属膜は無電解めっき法により形成されていていてもよい。 In one embodiment of the semiconductor device, the crystalline metal film may be formed by an electrolytic plating method, and the amorphous metal film may be formed by an electroless plating method.
　半導体装置の一態様において、キャップ膜は、Ｎｉ、Ｆｅ、Ｃｏ、Ｒｕ、Ｉｒ、Ｐｄ、又はＰｔであってもよい。 In one embodiment of the semiconductor device, the cap film may be Ni, Fe, Co, Ru, Ir, Pd, or Pt.
　半導体装置の一態様において、第２のバリア膜は、Ｎｉ、Ｃｏ、ＣｏＷＰ、Ｐｄ、Ｒｕ、Ａｇ、Ａｕ、又はＰｔであってもよい。 In one embodiment of the semiconductor device, the second barrier film may be Ni, Co, CoWP, Pd, Ru, Ag, Au, or Pt.
　半導体装置の一態様において、第２のバリア膜は、リンを含むＮｉ膜であってもよい。 In one embodiment of the semiconductor device, the second barrier film may be a Ni film containing phosphorus.
　半導体装置の一態様において、キャップ膜は、複数の金属膜が積層された積層膜であってもよい。 In one embodiment of the semiconductor device, the cap film may be a laminated film in which a plurality of metal films are laminated.
　半導体装置の一態様において、キャップ膜は、アモルファス性のＮｉ膜と、アモルファス性のＮｉの上に設けられた結晶性のＰｄ膜との積層膜であってもよい。 In one embodiment of the semiconductor device, the cap film may be a stacked film of an amorphous Ni film and a crystalline Pd film provided on the amorphous Ni.
　本発明に係る半導体装置の構造及び製造方法によれば、銅配線の酸化による配線抵抗の増加及びエレクトロマイグレーションによる信頼性の低下等を抑えると共に、銅配線同士のショート及びリーク等が生じにくい半導体装置及びその製造方法を実現できる。 According to the structure and the manufacturing method of the semiconductor device according to the present invention, a semiconductor device that suppresses an increase in wiring resistance due to oxidation of copper wiring and a decrease in reliability due to electromigration, and is less prone to short circuit and leakage between copper wirings. And a manufacturing method thereof.
図１は、一実施形態に係る半導体装置を示す断面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment. 図２Ａは、一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 2A is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps. 図２Ｂは、一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 2B is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment in the order of steps. 図２Ｃは、一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 2C is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps. 図３Ａは、一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 3A is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps. 図３Ｂは、一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 3B is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment in the order of steps. 図３Ｃは、一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 3C is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment in the order of steps. 図４Ａは、一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 4A is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps. 図４Ｂは、一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 4B is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment in the order of steps. 図４Ｃは、一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 4C is a cross-sectional view showing the method of manufacturing the semiconductor device according to one embodiment in the order of steps. 図５は、一実施形態に係る半導体装置の変形例を示す断面図である。FIG. 5 is a cross-sectional view showing a modification of the semiconductor device according to the embodiment. 図６Ａは、変形例に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 6A is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a modification in order of processes. 図６Ｂは、変形例に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 6B is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the modification in order of processes. 図６Ｃは、変形例に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 6C is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the modification in order of processes. 図７Ａは、変形例に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 7A is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a modification in order of processes. 図７Ｂは、変形例に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 7B is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the modification in order of processes. 図８Ａは、銅配線を形成する際に生じうる問題を説明するための断面図である。FIG. 8A is a cross-sectional view for explaining a problem that may occur when a copper wiring is formed. 図８Ｂは、銅配線を形成する際に生じうる問題を説明するための断面図である。FIG. 8B is a cross-sectional view for explaining a problem that may occur when the copper wiring is formed.
　まず、従来の半導体装置において、銅配線同士のショート及びリーク等が発生する理由を説明する。 First, the reason why a short circuit and leakage between copper wirings occur in a conventional semiconductor device will be described.
　銅配線を被覆する金属のバリア膜を無電解めっき法により形成する場合、必ず触媒が必要となる。特許文献１に記載の配線構造の形成方法では、バリア膜を形成するためにパラジウム（Ｐｄ）を触媒として用いている。銅配線表面の活性化処理においては、以下の式（１）及び式（２）に示す反応により、銅配線の表面にＰｄ粒子が析出される。
Ｃｕ　→　Ｃｕ２＋　＋　２ｅ－・・・・・（１）
Ｐｄ２＋　＋　２ｅ－　→　Ｐｄ・・・・・（２）
　銅配線の表面に析出したＰｄ粒子を触媒として、銅配線の表面にバリア膜を成膜する。例えば、ニッケル（Ｎｉ）をバリア膜として成膜する場合、めっき液中では、以下の式（３）～（６）の反応が起こり、Ｎｉ膜が銅配線表面に形成される。 When the metal barrier film covering the copper wiring is formed by the electroless plating method, a catalyst is always required. In the method for forming a wiring structure described in Patent Document 1, palladium (Pd) is used as a catalyst to form a barrier film. In the activation process of the copper wiring surface, Pd particles are deposited on the surface of the copper wiring by the reactions shown in the following formulas (1) and (2).
Cu → Cu 2+ + 2e − (1)
Pd 2+ + 2e − → Pd (2)
Using the Pd particles deposited on the surface of the copper wiring as a catalyst, a barrier film is formed on the surface of the copper wiring. For example, when nickel (Ni) is formed as a barrier film, reactions of the following formulas (3) to (6) occur in the plating solution, and a Ni film is formed on the surface of the copper wiring.
　まず、式（３）に示すように、Ｐｄ触媒により、次亜リン酸を亜リン酸に酸化する。これと同時に、式（４）に示すように、めっき液中に存在するＮｉ２＋が還元されてＮｉとなり銅配線の表面に付着する。一度、銅配線の表面にＮｉが付着すると、式（５）に示すように、ＮｉはＰｄと同様、触媒として作用し、式（６）に示すように、Ｎｉ２＋を還元し、Ｎｉとなるため、Ｃｕ表面にはＮｉ膜が成膜される。
Ｈ２ＰＯ２ －　→　Ｈ２ＰＯ３ －＋　２ｅ－（Ｐｄ触媒）・・・・・（３）
Ｎｉ２＋　＋　２ｅ－　→　Ｎｉ・・・・・（４）
Ｈ２ＰＯ２ －　→　Ｈ２ＰＯ３ －　＋　２ｅ－（Ｎｉ触媒）・・・・・（５）
Ｎｉ２＋　＋　２ｅ－　→　Ｎｉ・・・・・（６）
　ところで、特許文献２にも銅配線の表面にＮｉのバリア膜を形成する方法が記載されている。具体的には、無電解めっき法により、銅配線の表面及び底面バリア膜の側面をシードとして、これらの各面を被覆する表面バリア膜を形成すると記載されている。この場合にも、Ｎｉを銅配線の表面に無電解めっきをするには、Ｐｄ等の触媒が必要である。 First, as shown in Formula (3), hypophosphorous acid is oxidized to phosphorous acid by a Pd catalyst. At the same time, as shown in the equation (4), Ni 2+ present in the plating solution is reduced to Ni and adheres to the surface of the copper wiring. Once Ni adheres to the surface of the copper wiring, Ni acts as a catalyst like Pd, as shown in formula (5), and Ni2 + is reduced to Ni as shown in formula (6). A Ni film is formed on the Cu surface.
H 2 PO 2 − → H 2 PO 3 − + 2e − (Pd catalyst) (3)
Ni 2+ + 2e − → Ni (4)
H 2 PO 2 − → H 2 PO 3 − + 2e − (Ni catalyst) (5)
Ni 2+ + 2e − → Ni (6)
Incidentally, Patent Document 2 also describes a method of forming a Ni barrier film on the surface of a copper wiring. Specifically, it is described that a surface barrier film that covers each of these surfaces is formed by electroless plating using the surface of the copper wiring and the side surface of the bottom barrier film as seeds. Also in this case, a catalyst such as Pd is required for electroless plating of Ni on the surface of the copper wiring.
　図８Ａに示すようにして、Ｐｄ粒子２０５を銅配線２０４の表面に析出させると、Ｐｄ粒子２０５は銅配線２０４の表面以外の領域、例えば下地絶縁膜２０３の上にも析出する。この状態においてバリア膜を形成するための無電解めっきを行うと、図８Ｂに示すように、銅配線２０４の表面だけでなく下地絶縁膜２０３の上にもＰｄ粒子２０５を被覆するようにＮｉ膜２０６が無電解めっきされる。バリア膜をＮｉとする場合だけでなく、他の材料を用いてバリア膜を形成する場合も同様の現象が起こる。 As shown in FIG. 8A, when the Pd particles 205 are deposited on the surface of the copper wiring 204, the Pd particles 205 are also deposited on a region other than the surface of the copper wiring 204, for example, the base insulating film 203. When electroless plating for forming a barrier film is performed in this state, as shown in FIG. 8B, the Ni film is coated not only on the surface of the copper wiring 204 but also on the base insulating film 203 so as to cover the Pd particles 205. 206 is electrolessly plated. The same phenomenon occurs not only when the barrier film is made of Ni but also when the barrier film is formed using other materials.
　銅配線２０４同士の距離が狭い場合や、高電圧の半導体装置においては、下地絶縁膜２０３の上に形成されたＮｉ膜２０６は、ショートやリークの原因となる。このため、半導体装置のショートやリークを抑えるためには、下地絶縁膜の上に触媒粒子が付着しないようにして、バリア膜を形成することが好ましい。以下においては、銅配線の間等にバリア膜と同じ金属膜が残存していない半導体装置及びその製造方法について説明する。 In a case where the distance between the copper wirings 204 is narrow or in a high voltage semiconductor device, the Ni film 206 formed on the base insulating film 203 causes a short circuit or a leak. For this reason, in order to suppress a short circuit or leakage of the semiconductor device, it is preferable to form a barrier film so that catalyst particles do not adhere to the base insulating film. In the following, a semiconductor device in which the same metal film as the barrier film does not remain between copper wirings and the manufacturing method thereof will be described.
　（一実施形態）
　まず、一実施形態に係る半導体装置の構成について図１を参照して説明する。本実施形態の半導体装置は、半導体素子（図示せず）が形成された半導体基板１００の上に設けられた、多層配線層１１０及び再配線１２０を有している。多層配線層１１０は、複数の層間絶縁膜１１１、１１２と、配線１１３、１１４と、プラグ１１５、１１６とを有している。配線１１３、１１４は、半導体素子と電気的に接続された銅（Ｃｕ）からなる配線であり、プラグ１１５により電気的に接続されている。再配線１２０は、多層配線層１１０の上に設けられ、プラグ１１６により配線１１４と電気的に接続されている。再配線１２０及び多層配線層１１０を覆うように保護膜１０３が設けられている。 (One embodiment)
First, a configuration of a semiconductor device according to an embodiment will be described with reference to FIG. The semiconductor device of this embodiment has a multilayer wiring layer 110 and a rewiring 120 provided on a semiconductor substrate 100 on which a semiconductor element (not shown) is formed. The multilayer wiring layer 110 includes a plurality of interlayer insulating films 111 and 112, wirings 113 and 114, and plugs 115 and 116. The wirings 113 and 114 are wirings made of copper (Cu) electrically connected to the semiconductor element, and are electrically connected by the plug 115. The rewiring 120 is provided on the multilayer wiring layer 110 and is electrically connected to the wiring 114 by the plug 116. A protective film 103 is provided so as to cover the rewiring 120 and the multilayer wiring layer 110.
　再配線１２０は、多層配線層１１０の上に順次設けられた第１のバリア膜１２１、シード膜１２２、銅配線１２５、及びキャップ膜１２６を有している。第１のバリア膜１２１の側面、シード膜１２２の側面、銅配線１２５の側面、並びにキャップ膜１２６の側面及び上面は、第２のバリア膜１２７に覆われている。第１のバリア膜１２１は、例えば厚さが１００ｎｍのチタン（Ｔｉ）膜とすることができる。シード膜１２２は、例えば厚さが１００ｎｍのＣｕ層とすることができる。銅配線１２５は、例えば厚さが５μｍとすることができる。キャップ膜１２６は、例えば厚さが１μｍの結晶性のＮｉ膜とすることができる。第２のバリア膜１２７は、例えば厚さが１μｍのアモルファスＮｉ膜とすることができる。 The rewiring 120 includes a first barrier film 121, a seed film 122, a copper wiring 125, and a cap film 126 that are sequentially provided on the multilayer wiring layer 110. A side surface of the first barrier film 121, a side surface of the seed film 122, a side surface of the copper wiring 125, and a side surface and an upper surface of the cap film 126 are covered with the second barrier film 127. For example, the first barrier film 121 may be a titanium (Ti) film having a thickness of 100 nm. The seed film 122 may be a Cu layer having a thickness of 100 nm, for example. The copper wiring 125 can have a thickness of 5 μm, for example. The cap film 126 can be a crystalline Ni film having a thickness of 1 μm, for example. The second barrier film 127 can be an amorphous Ni film having a thickness of 1 μm, for example.
　キャップ膜１２６は、第２のバリア膜１２７を形成する無電解めっきの際に、触媒として機能する材料により形成されている。また、キャップ膜１２６は銅配線１２５の上面に接して形成されており、銅配線１２５の側面には形成されていない。従って、キャップ膜１２６は、層間絶縁膜１１２の上面、第１のバリア膜１２１の側面、シード膜１２２の側面のいずれにも接触していない。触媒となるキャップ膜１２６を銅配線１２５の上面にのみ形成しているため、銅配線１２５の上面以外の部分が被覆された状態で触媒となるキャップ膜１２６を形成することができる。このため、第２のバリア膜１２７を形成するための触媒が多層配線層１１０の上面に付着することがなくなる。従って、再配線１２０同士のショートや、再配線１２０と多層配線層１１０との間のリーク電流の発生を防ぐことができ、半導体装置の信頼性を向上させることができる。 The cap film 126 is formed of a material that functions as a catalyst in the electroless plating for forming the second barrier film 127. The cap film 126 is formed in contact with the upper surface of the copper wiring 125 and is not formed on the side surface of the copper wiring 125. Therefore, the cap film 126 is not in contact with any of the upper surface of the interlayer insulating film 112, the side surface of the first barrier film 121, and the side surface of the seed film 122. Since the cap film 126 serving as the catalyst is formed only on the upper surface of the copper wiring 125, the cap film 126 serving as the catalyst can be formed in a state where the portion other than the upper surface of the copper wiring 125 is covered. Therefore, the catalyst for forming the second barrier film 127 does not adhere to the upper surface of the multilayer wiring layer 110. Therefore, short circuit between the rewirings 120 and the occurrence of leakage current between the rewiring 120 and the multilayer wiring layer 110 can be prevented, and the reliability of the semiconductor device can be improved.
　次に、本実施形態の半導体装置の製造方法を説明する。まず、図２Ａに示すように、半導体素子（図示せず）が形成されたシリコン基板等の半導体基板１００の上に多層配線層１１０を形成する。多層配線層１１０は例えば、以下のようにして形成すればよい。まず、層間絶縁膜１１１を形成し、層間絶縁膜１１１中にＣｕからなる配線１１３を形成する。配線１１３が形成された層間絶縁膜１１１の上にさらに層間絶縁膜１１２を形成し、層間絶縁膜１１２中に配線１１４を形成する。図面においては、多層配線層１１０は２層構造であるが、配線形成工程を繰り返し行い所望層数の多層配線層１１０を形成することができる。 Next, a method for manufacturing the semiconductor device of this embodiment will be described. First, as shown in FIG. 2A, a multilayer wiring layer 110 is formed on a semiconductor substrate 100 such as a silicon substrate on which a semiconductor element (not shown) is formed. The multilayer wiring layer 110 may be formed as follows, for example. First, the interlayer insulating film 111 is formed, and the wiring 113 made of Cu is formed in the interlayer insulating film 111. An interlayer insulating film 112 is further formed on the interlayer insulating film 111 on which the wiring 113 is formed, and a wiring 114 is formed in the interlayer insulating film 112. In the drawing, the multilayer wiring layer 110 has a two-layer structure, but the multilayer wiring layer 110 having a desired number of layers can be formed by repeating the wiring formation process.
　次に、図２Ｂに示すように、多層配線層１１０が形成された半導体基板１００上の全面に厚さが１００ｎｍのＴｉからなる第１のバリア膜１２１と、厚さが１００ｎｍのシード膜１２２をスパッタ法により順に成膜する。第１のバリア膜１２１は、Ｔｉに限らず、タンタル（Ｔａ）等でもよく、窒素（Ｎ）等を含む金属化合物又はこれらの積層膜としてもよい。 Next, as shown in FIG. 2B, a first barrier film 121 made of Ti having a thickness of 100 nm and a seed film 122 having a thickness of 100 nm are formed on the entire surface of the semiconductor substrate 100 on which the multilayer wiring layer 110 is formed. Films are formed in order by sputtering. The first barrier film 121 is not limited to Ti, and may be tantalum (Ta) or the like, or may be a metal compound containing nitrogen (N) or the like, or a laminated film thereof.
　次に、図２Ｃに示すように、シード膜１２２の上に厚さが１０μｍの感光性材料を塗布する。この後、通常のリソグラフィ工程により感光性材料を露光・現像することにより、多層配線層１１０を覆い、シード膜１２２を露出する開口部１３１ａを有する配線形成用溝パターン１３１を形成する。本実施形態においては、配線形成用溝パターン１３１の開口部１３１ａの幅（配線幅に対応する。）を２０μｍとし、隣接する開口部１３１ａ同士の間隔（配線間隔に対応する）を２０μｍとする。なお、配線幅及び配線間隔は一例であり、どのような寸法の配線を形成してもよい。また、感光性材料の特性により、配線形成用溝パターン１３１は順テーパー形状となってもよい。例えば、開口部１３１ａは、上部開口幅が底部開口幅よりも大きくなっていても構わない。 Next, as shown in FIG. 2C, a photosensitive material having a thickness of 10 μm is applied on the seed film 122. Thereafter, the photosensitive material is exposed and developed by a normal lithography process to form a wiring forming groove pattern 131 having an opening 131a that covers the multilayer wiring layer 110 and exposes the seed film 122. In the present embodiment, the width of the opening 131a (corresponding to the wiring width) of the groove pattern 131 for wiring formation is 20 μm, and the interval between the adjacent openings 131a (corresponding to the wiring interval) is 20 μm. Note that the wiring width and the wiring interval are examples, and wiring of any size may be formed. Further, depending on the characteristics of the photosensitive material, the wiring forming groove pattern 131 may have a forward tapered shape. For example, the opening 131a may have an upper opening width larger than a bottom opening width.
　次に、図３Ａに示すように、Ｃｕ電解めっき法により開口部１３１ａ内に厚さが５μｍの銅配線１２５を成膜する。銅配線１２５の膜厚は、半導体装置の性能に応じて適宜変更することができる。 Next, as shown in FIG. 3A, a copper wiring 125 having a thickness of 5 μm is formed in the opening 131a by Cu electrolytic plating. The film thickness of the copper wiring 125 can be appropriately changed according to the performance of the semiconductor device.
　次に、図３Ｂに示すように、配線形成用溝パターン１３１が存在している状態において、電解めっき法により、銅配線１２５の上面に厚さが１μｍのＮｉからなるキャップ膜１２６を成膜する。配線形成用溝パターン１３１が存在している状態において、キャップ膜１２６を電解めっき法により成膜することにより、銅配線１２５の上面にのみ、結晶性のキャップ膜１０６を形成できる。具体的には、キャップ膜１２６は、層間絶縁膜１１２の上面、第１のバリア膜１２１の側面、シード膜１２２の側面のいずれにも接触することなく形成することができる。キャップ膜１２６の膜厚は、半導体装置の性能に応じて適宜変更することができる。 Next, as shown in FIG. 3B, a cap film 126 made of Ni having a thickness of 1 μm is formed on the upper surface of the copper wiring 125 by electrolytic plating in the state where the wiring forming groove pattern 131 exists. . In the state where the wiring forming groove pattern 131 exists, the crystalline cap film 106 can be formed only on the upper surface of the copper wiring 125 by forming the cap film 126 by electrolytic plating. Specifically, the cap film 126 can be formed without contacting any of the upper surface of the interlayer insulating film 112, the side surface of the first barrier film 121, and the side surface of the seed film 122. The film thickness of the cap film 126 can be changed as appropriate according to the performance of the semiconductor device.
　キャップ膜１２６を電解めっき法により形成する例を示したが、配線形成用溝パターン１３１が存在している状態で行う限り、無電解めっき法、蒸着法等を用いてキャップ膜１２６を形成してもよい。配線形成用溝パターン１３１を除去する前にキャップ膜１２６を成膜することにより、多層配線層１１０の上面に金属が付着することを防ぐことができる。 Although the example in which the cap film 126 is formed by the electrolytic plating method has been shown, the cap film 126 is formed by using an electroless plating method, a vapor deposition method, or the like as long as it is performed in a state where the wiring forming groove pattern 131 exists. Also good. By forming the cap film 126 before removing the wiring forming groove pattern 131, it is possible to prevent metal from adhering to the upper surface of the multilayer wiring layer 110.
　キャップ膜１２６は、触媒作用を有し、電解めっき法、無電解めっき法又は蒸着法により成膜が可能な金属により形成することができる。例えば、Ｎｉに代えて、鉄（Ｆｅ）、Ｃｏ、Ｒｕ、イリジウム（Ｉｒ）、Ｐｄ、又はＰｔ等により形成することができる。 The cap film 126 has a catalytic action and can be formed of a metal that can be formed by electrolytic plating, electroless plating, or vapor deposition. For example, it can be formed of iron (Fe), Co, Ru, iridium (Ir), Pd, Pt or the like instead of Ni.
　次に、図３Ｃに示すように、配線形成用溝パターン１３１を除去する。次に、図４Ａに示すように、銅配線１２５の間から露出するシード膜１２２及び第１のバリア膜１２１をウエットエッチング法により除去する。これにより、シード膜１２２及び第１のバリア膜１２１は、銅配線１２５の下方にのみ存在する状態となる。ウエットエッチングの条件によっては、シード膜１２２及び第１のバリア膜１２１の側面は、銅配線１２５の側面と揃わない場合もある。具体的には、シード膜１２２及び第１のバリア膜１２１の側面が、銅配線１２５の側面の位置から内側に入り込んだ形状となったり、外側に突出した形状となったりする場合がある。 Next, as shown in FIG. 3C, the wiring formation groove pattern 131 is removed. Next, as shown in FIG. 4A, the seed film 122 and the first barrier film 121 exposed from between the copper wirings 125 are removed by a wet etching method. As a result, the seed film 122 and the first barrier film 121 are in a state that exists only below the copper wiring 125. Depending on the wet etching conditions, the side surfaces of the seed film 122 and the first barrier film 121 may not be aligned with the side surfaces of the copper wiring 125. Specifically, the side surfaces of the seed film 122 and the first barrier film 121 may have a shape that enters the inside from the position of the side surface of the copper wiring 125 or a shape that protrudes to the outside.
　次に、図４Ｂに示すように、銅配線１２５、キャップ膜１２６の形成された半導体基板１００をＮｉ無電解めっき液中に浸漬し、第１のバリア膜１２１の側面、シード膜１２２の側面、銅配線１２５の側面、並びにキャップ膜１２６の側面及び上面にＮｉからなる第２のバリア膜１２７を成膜する。Ｎｉ無電解めっき液には、硫酸ニッケル、及び次亜リン酸ナトリウムを主成分とする、酸性（ｐＨ４～６）溶液を用いた。ここで、第２のバリア膜１２７は無電解めっき法により形成するため、形成される第２のバリア膜１２７の膜厚は、第１のバリア膜１２１の側面、シード膜１２２の側面、銅配線１２５の側面、並びにキャップ膜１２６の側面及び上面のいずれの場所においても、ほぼ均一な膜厚となる。図２Ｃにおいて順テーパー形状の配線形成用溝パターン１３１が形成された場合、再配線１２０は、底部の幅が上部の幅よりも狭い逆テーパー形状となる。 Next, as shown in FIG. 4B, the semiconductor substrate 100 on which the copper wiring 125 and the cap film 126 are formed is immersed in a Ni electroless plating solution, and the side surfaces of the first barrier film 121, the seed film 122, A second barrier film 127 made of Ni is formed on the side surfaces of the copper wiring 125 and the side surfaces and upper surface of the cap film 126. As the Ni electroless plating solution, an acidic (pH 4 to 6) solution containing nickel sulfate and sodium hypophosphite as main components was used. Here, since the second barrier film 127 is formed by an electroless plating method, the thickness of the formed second barrier film 127 is as follows: the side surface of the first barrier film 121, the side surface of the seed film 122, the copper wiring The film thickness is substantially uniform at any of the side surfaces of 125 and the side surfaces and upper surface of the cap film 126. In the case where the forward taper-shaped wiring forming groove pattern 131 is formed in FIG. 2C, the rewiring 120 has a reverse taper shape in which the bottom width is narrower than the top width.
　次に、図４Ｃに示すように、再配線１２０を覆う保護膜１０３を形成する。 Next, as shown in FIG. 4C, a protective film 103 that covers the rewiring 120 is formed.
　本実施形態においては、銅配線１２５の上にＮｉからなるキャップ膜１２６を形成している。キャップ膜１２６は、Ｎｉ無電解めっき液中において、式（７）に示す触媒として作用する。これにより、無電解めっき液中の次亜リン酸が亜リン酸に酸化されて電子が放出され、式（８）に示すように無電解めっき液中のＮｉイオンが還元される。
Ｈ２ＰＯ２ －　→　Ｈ２ＰＯ３ －　＋　２ｅ－（Ｎｉ触媒）・・・・・（７）
Ｎｉ２＋　＋　２ｅ－　→　Ｎｉ・・・・・・（８）
　これにより、第１のバリア膜１２１の側面、シード膜１２２の側面、銅配線１２５の側面、並びにキャップ膜１２６の側面及び上面に、厚さが１μｍのＮｉからなる第２のバリア膜１２７が形成される。このようにして形成した第２のバリア膜１２７は、リン（Ｐ）を４ｗｔ％以上含むアモルファス性のＮｉ膜である。第２のバリア膜１２７は、第１のバリア膜１２１の側面、銅配線１２５の側面及びキャップ膜１２６の側面及び上面を連続して被覆する。 In the present embodiment, a cap film 126 made of Ni is formed on the copper wiring 125. The cap film 126 acts as a catalyst represented by the formula (7) in the Ni electroless plating solution. As a result, hypophosphorous acid in the electroless plating solution is oxidized to phosphorous acid to release electrons, and Ni ions in the electroless plating solution are reduced as shown in Formula (8).
H 2 PO 2 − → H 2 PO 3 − + 2e − (Ni catalyst) (7)
Ni 2+ + 2e − → Ni (8)
Thus, the second barrier film 127 made of Ni having a thickness of 1 μm is formed on the side surface of the first barrier film 121, the side surface of the seed film 122, the side surface of the copper wiring 125, and the side surface and the upper surface of the cap film 126. Is done. The second barrier film 127 formed in this way is an amorphous Ni film containing 4 wt% or more of phosphorus (P). The second barrier film 127 continuously covers the side surface of the first barrier film 121, the side surface of the copper wiring 125, and the side surface and upper surface of the cap film 126.
　無電解めっき法により形成されるアモルファス性のＮｉ膜は、電解めっき法で形成される結晶性のＮｉ膜と比較して、膜中の粒界が少ない。このため、銅配線１２５を形成するＣｕが保護膜１０３中へ拡散することを抑制するバリア膜として、より優れている。また、膜中のリン濃度を高くするとＮｉ膜はアモルファス状態になりやすく、膜ストレスも軽減できるという利点がある。 The amorphous Ni film formed by the electroless plating method has fewer grain boundaries in the film than the crystalline Ni film formed by the electroplating method. For this reason, it is more excellent as a barrier film that suppresses the diffusion of Cu forming the copper wiring 125 into the protective film 103. Further, when the phosphorus concentration in the film is increased, there is an advantage that the Ni film tends to be in an amorphous state and the film stress can be reduced.
　無電解めっき液として次亜リン酸を用いている例を示したが、キャップ膜１２６の触媒作用を促進する作用を有するジメチルアミンボラン等を用いてもよい。また、第２のバリア膜１２７としてＮｉ膜を形成する例を示したが、キャップ膜１２６を触媒として無電解めっきが可能な金属であれば同様にして成膜できる。例えば、コバルト（Ｃｏ）、コバルトの化合物であるＣｏＷＰ、Ｐｄ、ルテニウム（Ｒｕ）、銀（Ａｇ）、金（Ａｕ）、及び白金（Ｐｔ）等からなる第２のバリア膜を形成することができる。 Although an example in which hypophosphorous acid is used as the electroless plating solution has been shown, dimethylamine borane or the like having an action of promoting the catalytic action of the cap film 126 may be used. Further, although an example in which the Ni film is formed as the second barrier film 127 is shown, any metal that can be electrolessly plated using the cap film 126 as a catalyst can be formed in the same manner. For example, a second barrier film made of cobalt (Co), cobalt compound CoWP, Pd, ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), or the like can be formed. .
　以下の変形例に示すように、キャップ膜は複数の金属膜が積層された積層膜としてもよい。例えば、図５に示すように、Ｎｉからなる第１のキャップ膜１３６Ａと、Ｐｄからなる第２のキャップ膜１３６Ｂとが順次積層された積層膜であるキャップ膜１３６を設けてもよい。キャップ膜を、例えば異種金属の積層膜とすることにより、それぞれの金属が有する特徴（例えば、磁性やバリア性）を組み合わせたキャップ膜を作成したり、種々の抵抗値を示すキャップ膜を作成したりすることができ、再配線に機能性を持たせることができるという利点が得られる。 As shown in the following modifications, the cap film may be a laminated film in which a plurality of metal films are laminated. For example, as shown in FIG. 5, a cap film 136 which is a laminated film in which a first cap film 136A made of Ni and a second cap film 136B made of Pd are sequentially laminated may be provided. For example, by forming the cap film as a laminated film of dissimilar metals, a cap film combining the characteristics (for example, magnetism and barrier properties) of each metal or a cap film showing various resistance values is created. There is an advantage that the rewiring can have functionality.
　この場合、図３Ａまでの工程と同様にして、銅配線１２５を形成する。この後、図６Ａに示すように、配線形成用溝パターン１３１が存在している状態において、無電解めっき法により、銅配線１２５の上面に厚さが０．２μｍのＮｉからなる第１のキャップ膜１３６Ａを成膜すればよい。この後、電解めっき法により厚さが０．３μｍのＰｄからなる第２のキャップ膜１３６Ｂを成膜すればよい。 In this case, the copper wiring 125 is formed in the same manner as in the steps up to FIG. 3A. Thereafter, as shown in FIG. 6A, the first cap made of Ni having a thickness of 0.2 μm is formed on the upper surface of the copper wiring 125 by the electroless plating method in the state where the groove pattern 131 for wiring formation exists. The film 136A may be formed. Thereafter, a second cap film 136B made of Pd having a thickness of 0.3 μm may be formed by electrolytic plating.
　第１のキャップ膜１３６Ａを無電解めっき法により形成したアモルファス性の膜とすることにより、銅配線１２５のバリア性が増加する。しかし、第１のキャップ膜１３６Ａを電解めっき法等により形成した結晶性の膜としてもよい。また、第１のキャップ膜１３６Ａを蒸着法等により形成してもよい。 By making the first cap film 136A an amorphous film formed by electroless plating, the barrier property of the copper wiring 125 is increased. However, the first cap film 136A may be a crystalline film formed by an electrolytic plating method or the like. Alternatively, the first cap film 136A may be formed by a vapor deposition method or the like.
　第１のキャップ膜１３６Ａと第２のキャップ膜１３６Ｂとは、触媒作用を有する互いに異なる金属膜であればよい。具体的には第１のキャップ膜１３６Ａ及び第２のキャップ膜１３６Ｂは、Ｎｉ、Ｆｅ、Ｃｏ、Ｒｕ、Ｉｒ、Ｐｄ、及びＰｔから選択した２種類の金属の組み合わせとすればよい。 The first cap film 136A and the second cap film 136B may be different metal films having a catalytic action. Specifically, the first cap film 136A and the second cap film 136B may be a combination of two kinds of metals selected from Ni, Fe, Co, Ru, Ir, Pd, and Pt.
　第２のキャップ膜１３６Ｂは、無電解めっき法、又は蒸着法等により形成してもよい。第１のキャップ膜１３６Ａと第２のキャップ膜１３６Ｂとは同じ方法により形成してもよい。第１のキャップ膜１３６Ａ及び第２のキャップ膜１３６Ｂの膜厚は、半導体装置の性能に応じて適宜変更することができる。 The second cap film 136B may be formed by an electroless plating method, a vapor deposition method, or the like. The first cap film 136A and the second cap film 136B may be formed by the same method. The film thicknesses of the first cap film 136A and the second cap film 136B can be changed as appropriate according to the performance of the semiconductor device.
　次に、図６Ｂに示すように、配線形成用溝パターン１３１を除去する。次に、図６Ｃに示すように、銅配線１２５の間から露出するシード膜１２２及び第１のバリア膜１２１をウエットエッチング法により除去する。 Next, as shown in FIG. 6B, the wiring formation groove pattern 131 is removed. Next, as shown in FIG. 6C, the seed film 122 and the first barrier film 121 exposed from between the copper wirings 125 are removed by a wet etching method.
　次に、図７Ａに示すように、銅配線１２５、キャップ膜１３６の形成された半導体基板１００をＮｉ無電解めっき液中に浸漬し、第１のバリア膜１２１の側面、シード膜１２２の側面、銅配線１２５の側面、並びにキャップ膜１３６の側面及び上面にＮｉからなる第２のバリア膜１２７を成膜する。 Next, as shown in FIG. 7A, the semiconductor substrate 100 on which the copper wiring 125 and the cap film 136 are formed is immersed in an Ni electroless plating solution, and the side surfaces of the first barrier film 121, the seed film 122, A second barrier film 127 made of Ni is formed on the side surfaces of the copper wiring 125 and the side surfaces and upper surface of the cap film 136.
　次に、図７Ｂに示すように、再配線１２０を覆う保護膜１０３を形成する。 Next, as shown in FIG. 7B, a protective film 103 covering the rewiring 120 is formed.
　本実施形態においては、多層配線層の上面を配線形成用溝パターンにより被覆した状態で、再配線を構成する銅配線上のみに、第２のバリア膜を成膜するための触媒作用を有するキャップ膜を形成する。このため、再配線の近傍に配線間をショートさせたり、リーク電流の原因となったりする金属膜が成長することを防止でき、信頼性の高い半導体装置を実現することできる。特に６００Ｖ以上の高耐圧が必要な半導体装置において、本実施形態の構造及び製造方法は有用である。 In the present embodiment, a cap having a catalytic action for forming the second barrier film only on the copper wiring constituting the rewiring with the upper surface of the multilayer wiring layer covered with the wiring forming groove pattern. A film is formed. For this reason, it is possible to prevent the growth of a metal film that causes a short circuit between wirings or causes a leakage current in the vicinity of the rewiring, and a highly reliable semiconductor device can be realized. In particular, the structure and the manufacturing method of this embodiment are useful in a semiconductor device that requires a high breakdown voltage of 600 V or higher.
　本開示の半導体装置及びその製造方法は、銅配線の酸化による配線抵抗の増加及びエレクトロマイグレーションによる信頼性の低下等を抑えると共に、銅配線同士のショート及びリーク等が生じにくくすることができ、特に、高集積及び高パワーの半導体装置等として有用である。 The semiconductor device and the manufacturing method thereof according to the present disclosure can suppress an increase in wiring resistance due to oxidation of copper wiring and a decrease in reliability due to electromigration, and can make shorting and leakage between copper wirings less likely to occur. It is useful as a highly integrated and high power semiconductor device.
１００　　　半導体基板
１０３　　　保護膜
１０６　　　キャップ膜
１１０　　　多層配線層
１１１　　　層間絶縁膜
１１２　　　層間絶縁膜
１１３　　　配線
１１４　　　配線
１２０　　　再配線
１２１　　　第１のバリア膜
１２２　　　シード膜
１２５　　　銅配線
１２６　　　キャップ膜
１２７　　　第２のバリア膜
１３１　　　配線形成用溝パターン
１３１ａ　　開口部
１３６　　　キャップ膜
１３６Ａ　　第１のキャップ膜
１３６Ｂ　　第２のキャップ膜 100 Semiconductor substrate 103 Protective film 106 Cap film 110 Multilayer wiring layer 111 Interlayer insulating film 112 Interlayer insulating film 113 Wiring 114 Wiring 120 Rewiring 121 First barrier film 122 Seed film 125 Copper wiring 126 Cap film 127 Second barrier film 131 Wiring forming groove pattern 131a Opening 136 Cap film 136A First cap film 136B Second cap film

Claims (16)

  1. 　半導体素子が設けられた基板の上に絶縁膜を形成する工程と、
    　前記絶縁膜の上に第１のバリア膜を形成する工程と、
    　前記第１のバリア膜の上にシード膜を形成する工程と、
    　感光性材料を用いて、前記絶縁膜を覆い、前記シード膜を露出する開口部を有する配線形成用溝パターンを形成する工程と、
    　前記開口部に銅配線を形成する工程と、
    　前記銅配線の上にキャップ膜を形成する工程と、
    　前記キャップ膜を形成する工程よりも後に、前記配線形成用溝パターンを除去する工程と、
    　前記配線形成用溝パターンを除去する工程よりも後に、前記第１のバリア膜及び前記シード膜の露出した部分を除去する工程と、
    　前記第１のバリア膜及び前記シード膜を除去する工程よりも後に、前記第１のバリア膜の側面、前記シード膜の側面、前記銅配線の側面、並びに前記キャップ膜の側面及び上面に、前記キャップ膜を触媒として第２のバリア膜を形成する工程とを備えている、半導体装置の製造方法。     Forming an insulating film on a substrate provided with a semiconductor element;
    Forming a first barrier film on the insulating film;
    Forming a seed film on the first barrier film;
    Using a photosensitive material to form a wiring forming groove pattern having an opening that covers the insulating film and exposes the seed film;
    Forming a copper wiring in the opening;
    Forming a cap film on the copper wiring;
    Removing the wiring forming groove pattern after the step of forming the cap film;
    A step of removing the exposed portion of the first barrier film and the seed film after the step of removing the wiring forming groove pattern;
    After the step of removing the first barrier film and the seed film, the side surface of the first barrier film, the side surface of the seed film, the side surface of the copper wiring, and the side surface and the upper surface of the cap film, And a step of forming a second barrier film using the cap film as a catalyst.
  2. 　前記キャップ膜を形成する工程は、電解めっきにより結晶性の金属膜を形成する工程である、請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the cap film is a step of forming a crystalline metal film by electrolytic plating.
  3. 　前記キャップ膜は、Ｎｉ、Ｆｅ、Ｃｏ、Ｒｕ、Ｉｒ、Ｐｄ、又はＰｔからなる、請求項１又は２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the cap film is made of Ni, Fe, Co, Ru, Ir, Pd, or Pt.
  4. 　前記キャップ膜を形成する工程において、複数の金属膜が積層された積層膜を形成する、請求項１～３のいずれか１項に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the cap film, a laminated film in which a plurality of metal films are laminated is formed.
  5. 　前記第２のバリア膜を形成する工程は、無電解めっきによりアモルファス性の金属膜を形成する工程を含む、請求項１～４のいずれか１項に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the second barrier film includes a step of forming an amorphous metal film by electroless plating.
  6. 　前記第２のバリア膜は、Ｎｉ、Ｃｏ、ＣｏＷＰ、Ｐｄ、Ｒｕ、Ａｇ、Ａｕ、又はＰｔからなる、請求項１～５のいずれか１項に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 1, wherein the second barrier film is made of Ni, Co, CoWP, Pd, Ru, Ag, Au, or Pt.
  7. 　前記第２のバリア膜は、リンを含むＮｉ膜からなる、請求項１～５のいずれか１項に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 1, wherein the second barrier film is made of a Ni film containing phosphorus.
  8. 　半導体素子を有する基板の上に設けられた絶縁膜と、
    　前記絶縁膜の上に設けられた第１のバリア膜と、
    　前記第１のバリア膜の上に設けられた銅配線と、
    　前記銅配線の上に設けられたキャップ膜と、
    　前記第１のバリア膜の側面、前記銅配線の側面並びに前記キャップ膜の側面及び上面を覆う第２のバリア膜とを備えている、半導体装置。     An insulating film provided on a substrate having a semiconductor element;
    A first barrier film provided on the insulating film;
    A copper wiring provided on the first barrier film;
    A cap film provided on the copper wiring;
    A semiconductor device comprising: a second barrier film that covers a side surface of the first barrier film, a side surface of the copper wiring, and a side surface and an upper surface of the cap film.
  9. 　前記第２のバリア膜は、前記第１のバリア膜の側面、前記銅配線の側面及び前記キャップ膜の側面及び上面を連続して覆う、請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein the second barrier film continuously covers a side surface of the first barrier film, a side surface of the copper wiring, and a side surface and an upper surface of the cap film.
  10. 　前記キャップ膜は結晶性の金属膜であり、前記第２のバリア膜はアモルファス性の金属膜である、請求項８又は９に記載の半導体装置。 10. The semiconductor device according to claim 8, wherein the cap film is a crystalline metal film, and the second barrier film is an amorphous metal film.
  11. 　前記結晶性の金属膜は電解めっき法により形成され、
    　前記アモルファス性の金属膜は無電解めっき法により形成されている、請求項１０に記載の半導体装置。     The crystalline metal film is formed by an electrolytic plating method,
    The semiconductor device according to claim 10, wherein the amorphous metal film is formed by an electroless plating method.
  12. 　前記キャップ膜は、Ｎｉ、Ｆｅ、Ｃｏ、Ｒｕ、Ｉｒ、Ｐｄ、又はＰｔからなる、請求項８～１１のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 8 to 11, wherein the cap film is made of Ni, Fe, Co, Ru, Ir, Pd, or Pt.
  13. 　前記第２のバリア膜は、Ｎｉ、Ｃｏ、ＣｏＷＰ、Ｐｄ、Ｒｕ、Ａｇ、Ａｕ、又はＰｔからなる、請求項８～１２のいずれか１項に記載の半導体装置。 13. The semiconductor device according to claim 8, wherein the second barrier film is made of Ni, Co, CoWP, Pd, Ru, Ag, Au, or Pt.
  14. 　前記第２のバリア膜は、Ｐを含むＮｉ膜である、請求項８～１３のいずれか１項に記載の半導体装置。 14. The semiconductor device according to claim 8, wherein the second barrier film is a Ni film containing P.
  15. 　前記キャップ膜は、複数の金属膜が積層された積層膜である、請求項８～１４のいずれか１項に記載の半導体装置。 15. The semiconductor device according to claim 8, wherein the cap film is a laminated film in which a plurality of metal films are laminated.
  16. 　前記キャップ膜は、アモルファス性のＮｉ膜と、前記アモルファス性のＮｉの上に設けられた結晶性のＰｄ膜との積層膜である、請求項１５に記載の半導体装置。 16. The semiconductor device according to claim 15, wherein the cap film is a laminated film of an amorphous Ni film and a crystalline Pd film provided on the amorphous Ni.
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