WO2014126872A1 - Non-conventional method of silicon wafer sawing using a plurality of wafer saw rotational angles - Google Patents

Non-conventional method of silicon wafer sawing using a plurality of wafer saw rotational angles Download PDF

Info

Publication number
WO2014126872A1
WO2014126872A1 PCT/US2014/015661 US2014015661W WO2014126872A1 WO 2014126872 A1 WO2014126872 A1 WO 2014126872A1 US 2014015661 W US2014015661 W US 2014015661W WO 2014126872 A1 WO2014126872 A1 WO 2014126872A1
Authority
WO
WIPO (PCT)
Prior art keywords
cutting
wafer
integrated circuit
silicon wafer
cutting angle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2014/015661
Other languages
French (fr)
Inventor
Mathew BUNKER
Ekgachai Kenganantanon
Surapol Sawatjeen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Priority to CN201480002572.1A priority Critical patent/CN104685618A/en
Priority to KR1020157008142A priority patent/KR20150120329A/en
Publication of WO2014126872A1 publication Critical patent/WO2014126872A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices

Definitions

  • the present disclosure relates to methods of sawing a silicon wafer for separating a plurality of dice therein, and in particular, to sawing the silicon wafer so that each die corner has an angle that is greater than 90 degrees.
  • Silicon wafer sawing is the process of cutting the wafer so that a plurality of integrated circuit dice are separated therefrom. Scribe lines or saw streets are areas between the dice where the saw passes through to separate the plurality of dice. Currently, sawing of the wafer is performed at zero (0) degrees and 90 degrees, resulting in either square or rectangular dice having four sides and 90 degree corners. However some applications require dice having corners with angles greater than 90 degrees.
  • a method for separating a plurality of integrated circuit dice from a silicon wafer may comprise the steps of: setting a wafer cutting tool to a first cutting angle, wherein the first cutting angle may be at substantially 90 degrees from a zero degree reference; cutting the silicon wafer with the wafer cutting tool at the first cutting angle; setting the wafer cutting tool to a second cutting angle, wherein the second cutting angle may be less than 90 degrees from the zero degree reference; cutting the silicon wafer with the wafer cutting tool at the second cutting angle; setting the wafer cutting tool to a third cutting angle, wherein the third cutting angle may be greater than 90 degrees from the zero degree reference; and cutting the silicon wafer with the wafer cutting tool at the third cutting angle; wherein a plurality of integrated circuit dice may be separated from the silicon wafer and each one of the plurality of integrated circuit dice have six sides with corners greater than 90 degrees.
  • the silicon wafer may be mounted to a wafer mount with mounting tape for holding the silicon wafer during cutting thereof with the wafer cutting tool.
  • passivation of each of the plurality of integrated circuit dice remains sealed after the steps of cutting the silicon wafer.
  • the step of cutting the silicon wafer at the first cutting angle comprises the steps of: cutting a first side of each of the plurality of integrated circuit dice at the first cutting angle; and cutting a second side of each of the plurality of integrated circuit dice at the first cutting angle.
  • the step of cutting the silicon wafer at the second cutting angle comprises the steps of: cutting a third side of each of the plurality of integrated circuit dice at the second cutting angle; and cutting a fourth side of each of the plurality of integrated circuit dice at the second cutting angle.
  • the step of cutting the silicon wafer at the third cutting angle comprises the steps of: cutting a fifth side of each of the plurality of integrated circuit dice at the third cutting angle; and cutting a sixth side of each of the plurality of integrated circuit dice at the third cutting angle.
  • a method for separating a plurality of integrated circuit dice from a silicon wafer may comprise the steps of: setting a wafer cutting tool to a first cutting angle, wherein the first cutting angle may be at substantially 90 degrees from a zero degree reference; cutting the silicon wafer with the wafer cutting tool at the first cutting angle; setting the wafer cutting tool to a second cutting angle, wherein the second cutting angle may be less than 90 degrees from the zero degree reference; cutting the silicon wafer with the wafer cutting tool at the second cutting angle; setting the wafer cutting tool to a third cutting angle, wherein the third cutting angle may be greater than 90 degrees from the zero degree reference; cutting the silicon wafer with the wafer cutting tool at the third cutting angle; setting the wafer cutting tool to a fourth cutting angle, wherein the fourth cutting angle may be at substantially the zero degree reference; and cutting the silicon wafer with the wafer cutting tool at the fourth cutting angle; wherein a plurality of integrated circuit dice may be separated from the silicon wafer and each one of the plurality of integrated circuit dice have eight sides
  • the silicon wafer may be mounted to a wafer mount with mounting tape for holding the silicon wafer during cutting thereof with the wafer cutting tool.
  • passivation of each of the plurality of integrated circuit dice remains sealed after the steps of cutting the silicon wafer.
  • the step of cutting the silicon wafer at the first cutting angle comprises the steps of: cutting a first side of each of the plurality of integrated circuit dice at the first cutting angle; and cutting a second side of each of the plurality of integrated circuit dice at the first cutting angle.
  • the step of cutting the silicon wafer at the second cutting angle comprises the steps of: cutting a third side of each of the plurality of integrated circuit dice at the second cutting angle; and cutting a fourth side of each of the plurality of integrated circuit dice at the second cutting angle.
  • the step of cutting the silicon wafer at the third cutting angle comprises the steps of: cutting a fifth side of each of the plurality of integrated circuit dice at the third cutting angle; and cutting a sixth side of each of the plurality of integrated circuit dice at the third cutting angle.
  • the step of cutting the silicon wafer at the fourth cutting angle comprises the steps of: cutting a seventh side of each of the plurality of integrated circuit dice at the fourth cutting angle; and cutting an eighth side of each of the plurality of integrated circuit dice at the fourth cutting angle.
  • Figure 1 illustrates a schematic process flow diagram of a silicon wafer being separated into a plurality of integrated circuit dice
  • Figure 2 illustrates a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having four sides with 90 degree corners
  • Figure 3 illustrates a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having six sides with corners of greater than 90 degrees, according to a specific example embodiment of this disclosure
  • Figure 4 illustrates a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having eight sides with corners of greater than 90 degrees, according to another specific example embodiment of this disclosure. While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
  • FIG. 1 depicted is a schematic process flow diagram of a silicon wafer being separated into a plurality of integrated circuit dice.
  • a silicon wafer 100 is mounted (122) on a mounting tape 120 that adheres to the back of the wafer 100.
  • the mounting tape 120 provides support for wafer handling during the wafer sawing process 124.
  • the wafer sawing process 124 is used to cut the wafer so that individual integrated circuit dice are separated therefrom.
  • FIG. 2 depicted is a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having 90 degree corners.
  • "Scribe lines” or “saw streets” 106 and 108 are areas between the integrated circuit dice 102 where a dicing saw (not shown) may pass (cut) through the wafer 100, thereby separating the plurality of dice 102 from the wafer 100.
  • Scribe line 108 is oriented at 0 degrees and scribe line 106 is oriented at 90 degrees.
  • Each of the plurality of dice 120 will be square or rectangular and have four sides with 90 degree corners.
  • FIG. 3 depicted is a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having six sides with corners greater than 90 degrees, according to a specific example embodiment of this disclosure.
  • a plurality of integrated circuit dice 202 are separated (cut) from the silicon wafer 100.
  • Each of the dice 202 are six sided and have corners with angles of greater than 90 degrees.
  • the scribe lines 206 are at approximately 90 degrees to a zero degree reference. Scribe lines 210 are less than 90 degrees to the zero degree reference.
  • scribe lines 212 are greater than 90 degrees to the zero degree reference. Therefore the wafer cutting saw (not shown) need be set to only three different cutting angles.
  • Die areas 204 are sacrificial areas for the wafer cutting saw (not shown) to pass through.
  • FIG. 4 depicted is a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having eight sides with corners greater than 90 degrees, according to another specific example embodiment of this disclosure.
  • a plurality of integrated circuit dice 302 are separated (cut) from the silicon wafer 100.
  • Each of the dice 302 are eight sided and have corners with angles of greater than 90 degrees.
  • the scribe lines 306 are at approximately 90 degrees to a zero degree reference.
  • the scribe lines 308 are at approximately 0 degrees to the zero degree reference.
  • Scribe lines 310 are less than 90 degrees to the zero degree reference.
  • scribe lines 312 are greater than 90 degrees to the zero degree reference. Therefore the wafer cutting saw (not shown) need be set to only four different cutting angles.
  • Die areas 304 are sacrificial areas for the wafer cutting saw (not shown) to pass through.

Landscapes

  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A silicon wafer saw can be set to either three or four different cutting angle orientations from a zero degree reference to produce integrated circuit dice having corners greater than 90 degrees. Three different saw angle orientations will produce six sided dice, and four different saw cutting angle orientations will produce eight sided dice.

Description

NON-CONVENTIONAL METHOD OF SILICON WAFER SAWING
USING A PLURALITY OF WAFER SAW ROTATIONAL ANGLES
TECHNICAL FIELD
The present disclosure relates to methods of sawing a silicon wafer for separating a plurality of dice therein, and in particular, to sawing the silicon wafer so that each die corner has an angle that is greater than 90 degrees.
BACKGROUND
Silicon wafer sawing is the process of cutting the wafer so that a plurality of integrated circuit dice are separated therefrom. Scribe lines or saw streets are areas between the dice where the saw passes through to separate the plurality of dice. Currently, sawing of the wafer is performed at zero (0) degrees and 90 degrees, resulting in either square or rectangular dice having four sides and 90 degree corners. However some applications require dice having corners with angles greater than 90 degrees.
SUMMARY
Therefore there is need for a way to separate a plurality of dice from a silicon wafer so that the separated dice have comers with angles greater than 90 degrees.
According to an embodiment, a method for separating a plurality of integrated circuit dice from a silicon wafer may comprise the steps of: setting a wafer cutting tool to a first cutting angle, wherein the first cutting angle may be at substantially 90 degrees from a zero degree reference; cutting the silicon wafer with the wafer cutting tool at the first cutting angle; setting the wafer cutting tool to a second cutting angle, wherein the second cutting angle may be less than 90 degrees from the zero degree reference; cutting the silicon wafer with the wafer cutting tool at the second cutting angle; setting the wafer cutting tool to a third cutting angle, wherein the third cutting angle may be greater than 90 degrees from the zero degree reference; and cutting the silicon wafer with the wafer cutting tool at the third cutting angle; wherein a plurality of integrated circuit dice may be separated from the silicon wafer and each one of the plurality of integrated circuit dice have six sides with corners greater than 90 degrees.
According to a further embodiment of the method, the silicon wafer may be mounted to a wafer mount with mounting tape for holding the silicon wafer during cutting thereof with the wafer cutting tool. According to a further embodiment of the method, passivation of each of the plurality of integrated circuit dice remains sealed after the steps of cutting the silicon wafer.
According to a further embodiment of the method, the step of cutting the silicon wafer at the first cutting angle comprises the steps of: cutting a first side of each of the plurality of integrated circuit dice at the first cutting angle; and cutting a second side of each of the plurality of integrated circuit dice at the first cutting angle. According to a further embodiment of the method, the step of cutting the silicon wafer at the second cutting angle comprises the steps of: cutting a third side of each of the plurality of integrated circuit dice at the second cutting angle; and cutting a fourth side of each of the plurality of integrated circuit dice at the second cutting angle. According to a further embodiment of the method, the step of cutting the silicon wafer at the third cutting angle comprises the steps of: cutting a fifth side of each of the plurality of integrated circuit dice at the third cutting angle; and cutting a sixth side of each of the plurality of integrated circuit dice at the third cutting angle.
According to another embodiment, a method for separating a plurality of integrated circuit dice from a silicon wafer may comprise the steps of: setting a wafer cutting tool to a first cutting angle, wherein the first cutting angle may be at substantially 90 degrees from a zero degree reference; cutting the silicon wafer with the wafer cutting tool at the first cutting angle; setting the wafer cutting tool to a second cutting angle, wherein the second cutting angle may be less than 90 degrees from the zero degree reference; cutting the silicon wafer with the wafer cutting tool at the second cutting angle; setting the wafer cutting tool to a third cutting angle, wherein the third cutting angle may be greater than 90 degrees from the zero degree reference; cutting the silicon wafer with the wafer cutting tool at the third cutting angle; setting the wafer cutting tool to a fourth cutting angle, wherein the fourth cutting angle may be at substantially the zero degree reference; and cutting the silicon wafer with the wafer cutting tool at the fourth cutting angle; wherein a plurality of integrated circuit dice may be separated from the silicon wafer and each one of the plurality of integrated circuit dice have eight sides with corners greater than 90 degrees.
According to a further embodiment of the method, the silicon wafer may be mounted to a wafer mount with mounting tape for holding the silicon wafer during cutting thereof with the wafer cutting tool. According to a further embodiment of the method, passivation of each of the plurality of integrated circuit dice remains sealed after the steps of cutting the silicon wafer. According to a further embodiment of the method, the step of cutting the silicon wafer at the first cutting angle comprises the steps of: cutting a first side of each of the plurality of integrated circuit dice at the first cutting angle; and cutting a second side of each of the plurality of integrated circuit dice at the first cutting angle. According to a further embodiment of the method, the step of cutting the silicon wafer at the second cutting angle comprises the steps of: cutting a third side of each of the plurality of integrated circuit dice at the second cutting angle; and cutting a fourth side of each of the plurality of integrated circuit dice at the second cutting angle.
According to a further embodiment of the method, the step of cutting the silicon wafer at the third cutting angle comprises the steps of: cutting a fifth side of each of the plurality of integrated circuit dice at the third cutting angle; and cutting a sixth side of each of the plurality of integrated circuit dice at the third cutting angle. According to a further embodiment of the method, the step of cutting the silicon wafer at the fourth cutting angle comprises the steps of: cutting a seventh side of each of the plurality of integrated circuit dice at the fourth cutting angle; and cutting an eighth side of each of the plurality of integrated circuit dice at the fourth cutting angle.
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:
Figure 1 illustrates a schematic process flow diagram of a silicon wafer being separated into a plurality of integrated circuit dice;
Figure 2 illustrates a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having four sides with 90 degree corners; Figure 3 illustrates a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having six sides with corners of greater than 90 degrees, according to a specific example embodiment of this disclosure; and
Figure 4 illustrates a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having eight sides with corners of greater than 90 degrees, according to another specific example embodiment of this disclosure. While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
DETAILED DESCRIPTION
Cutting dice from a silicon wafer in way that eliminates sharp 90 degree corners on the dice is desired in certain integrated circuit fabrication and packaging applications. However, when deviating from the traditional square and rectangular dice having 90 degree corners, care must be taken not to break the passivation seal of the desired die. Also it is desirable to maximize the yield of dice having greater than 90 degree corners using existing die/wafer topologies.
Referring now to the drawing, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.
Referring to Figure 1 , depicted is a schematic process flow diagram of a silicon wafer being separated into a plurality of integrated circuit dice. A silicon wafer 100 is mounted (122) on a mounting tape 120 that adheres to the back of the wafer 100. The mounting tape 120 provides support for wafer handling during the wafer sawing process 124. The wafer sawing process 124 is used to cut the wafer so that individual integrated circuit dice are separated therefrom.
Referring to Figure 2, depicted is a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having 90 degree corners. "Scribe lines" or "saw streets" 106 and 108 are areas between the integrated circuit dice 102 where a dicing saw (not shown) may pass (cut) through the wafer 100, thereby separating the plurality of dice 102 from the wafer 100. Scribe line 108 is oriented at 0 degrees and scribe line 106 is oriented at 90 degrees. Each of the plurality of dice 120 will be square or rectangular and have four sides with 90 degree corners. Referring to Figure 3, depicted is a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having six sides with corners greater than 90 degrees, according to a specific example embodiment of this disclosure. A plurality of integrated circuit dice 202 are separated (cut) from the silicon wafer 100. Each of the dice 202 are six sided and have corners with angles of greater than 90 degrees. There are three different angle scribe lines 206, 210 and 212. The scribe lines 206 are at approximately 90 degrees to a zero degree reference. Scribe lines 210 are less than 90 degrees to the zero degree reference. And scribe lines 212 are greater than 90 degrees to the zero degree reference. Therefore the wafer cutting saw (not shown) need be set to only three different cutting angles. Die areas 204 are sacrificial areas for the wafer cutting saw (not shown) to pass through.
Referring to Figure 4, depicted is a schematic plan view of a wafer cutting operation producing a plurality of integrated circuit dice having eight sides with corners greater than 90 degrees, according to another specific example embodiment of this disclosure. A plurality of integrated circuit dice 302 are separated (cut) from the silicon wafer 100. Each of the dice 302 are eight sided and have corners with angles of greater than 90 degrees. There are four different angle scribe lines 306, 308, 310 and 312. The scribe lines 306 are at approximately 90 degrees to a zero degree reference. The scribe lines 308 are at approximately 0 degrees to the zero degree reference. Scribe lines 310 are less than 90 degrees to the zero degree reference. And scribe lines 312 are greater than 90 degrees to the zero degree reference. Therefore the wafer cutting saw (not shown) need be set to only four different cutting angles. Die areas 304 are sacrificial areas for the wafer cutting saw (not shown) to pass through.
While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.

Claims

CLAIMS What is claimed is:
1. A method for separating a plurality of integrated circuit dice from a silicon wafer, said method comprising the steps of:
setting a wafer cutting tool to a first cutting angle, wherein the first cutting angle is at substantially 90 degrees from a zero degree reference;
cutting the silicon wafer with the wafer cutting tool at the first cutting angle; setting the wafer cutting tool to a second cutting angle, wherein the second cutting angle is less than 90 degrees from the zero degree reference;
cutting the silicon wafer with the wafer cutting tool at the second cutting angle;
setting the wafer cutting tool to a third cutting angle, wherein the third cutting angle is greater than 90 degrees from the zero degree reference; and
cutting the silicon wafer with the wafer cutting tool at the third cutting angle; wherein a plurality of integrated circuit dice are separated from the silicon wafer and each one of the plurality of integrated circuit dice have six sides with corners greater than 90 degrees.
2. The method according to claim 1 , wherein the silicon wafer is mounted to a wafer mount with mounting tape for holding the silicon wafer during cutting thereof with the wafer cutting tool.
3. The method according to claim 1 , wherein passivation of each of the plurality of integrated circuit dice remains sealed after the steps of cutting the silicon wafer.
4. The method according to claim 1, wherein the step of cutting the silicon wafer at the first cutting angle comprises the steps of:
cutting a first side of each of the plurality of integrated circuit dice at the first cutting angle; and
cutting a second side of each of the plurality of integrated circuit dice at the first cutting angle.
5. The method according to claim 1, wherein the step of cutting the silicon wafer at the second cutting angle comprises the steps of:
cutting a third side of each of the plurality of integrated circuit dice at the second cutting angle; and
cutting a fourth side of each of the plurality of integrated circuit dice at the second cutting angle.
6. The method according to claim 1, wherein the step of cutting the silicon wafer at the third cutting angle comprises the steps of:
cutting a fifth side of each of the plurality of integrated circuit dice at the third cutting angle; and
cutting a sixth side of each of the plurality of integrated circuit dice at the third cutting angle.
7. A method for separating a plurality of integrated circuit dice from a silicon wafer, said method comprising the steps of:
setting a wafer cutting tool to a first cutting angle, wherein the first cutting angle is at substantially 90 degrees from a zero degree reference;
cutting the silicon wafer with the wafer cutting tool at the first cutting angle; setting the wafer cutting tool to a second cutting angle, wherein the second cutting angle is less than 90 degrees from the zero degree reference;
cutting the silicon wafer with the wafer cutting tool at the second cutting angle;
setting the wafer cutting tool to a third cutting angle, wherein the third cutting angle is greater than 90 degrees from the zero degree reference;
cutting the silicon wafer with the wafer cutting tool at the third cutting angle; setting the wafer cutting tool to a fourth cutting angle, wherein the fourth cutting angle is at substantially the zero degree reference; and
cutting the silicon wafer with the wafer cutting tool at the fourth cutting angle; wherein a plurality of integrated circuit dice are separated from the silicon wafer and each one of the plurality of integrated circuit dice have eight sides with corners greater than 90 degrees.
8. The method according to claim 7, wherein the silicon wafer is mounted to a wafer mount with mounting tape for holding the silicon wafer during cutting thereof with the wafer cutting tool.
9. The method according to claim 7, wherein passivation of each of the plurality of integrated circuit dice remains sealed after the steps of cutting the silicon wafer.
10. The method according to claim 7, wherein the step of cutting the silicon wafer at the first cutting angle comprises the steps of:
cutting a first side of each of the plurality of integrated circuit dice at the first cutting angle; and
cutting a second side of each of the plurality of integrated circuit dice at the first cutting angle.
1 1. The method according to claim 7, wherein the step of cutting the silicon wafer at the second cutting angle comprises the steps of:
cutting a third side of each of the plurality of integrated circuit dice at the second cutting angle; and
cutting a fourth side of each of the plurality of integrated circuit dice at the second cutting angle.
12. The method according to claim 7, wherein the step of cutting the silicon wafer at the third cutting angle comprises the steps of:
cutting a fifth side of each of the plurality of integrated circuit dice at the third cutting angle; and
cutting a sixth side of each of the plurality of integrated circuit dice at the third cutting angle.
13. The method according to claim 7, wherein the step of cutting the silicon wafer at the fourth cutting angle comprises the steps of:
cutting a seventh side of each of the plurality of integrated circuit dice at the fourth cutting angle; and
cutting an eighth side of each of the plurality of integrated circuit dice at the fourth cutting angle.
PCT/US2014/015661 2013-02-18 2014-02-11 Non-conventional method of silicon wafer sawing using a plurality of wafer saw rotational angles Ceased WO2014126872A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201480002572.1A CN104685618A (en) 2013-02-18 2014-02-11 An unconventional method for sawing silicon wafers using multiple wafer saw rotation angles
KR1020157008142A KR20150120329A (en) 2013-02-18 2014-02-11 Non-conventional method of silicon wafer sawing using a plurality of wafer saw rotational angles

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/769,651 US20140235033A1 (en) 2013-02-18 2013-02-18 Non-conventional method of silicon wafer sawing using a plurality of wafer saw rotational angles
US13/769,651 2013-02-18

Publications (1)

Publication Number Publication Date
WO2014126872A1 true WO2014126872A1 (en) 2014-08-21

Family

ID=50159584

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2014/015661 Ceased WO2014126872A1 (en) 2013-02-18 2014-02-11 Non-conventional method of silicon wafer sawing using a plurality of wafer saw rotational angles

Country Status (5)

Country Link
US (1) US20140235033A1 (en)
KR (1) KR20150120329A (en)
CN (1) CN104685618A (en)
TW (1) TW201442091A (en)
WO (1) WO2014126872A1 (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5698840A (en) * 1980-01-08 1981-08-08 Mitsubishi Electric Corp Preparation of semiconductor device
JPS62209816A (en) * 1986-03-10 1987-09-16 Toshiba Corp Semiconductor device
US5393711A (en) * 1991-10-12 1995-02-28 Robert Bosch Gmbh Process for manufacturing semiconductor components
US20050158967A1 (en) * 2004-01-20 2005-07-21 Taiwan Semiconductor Manufacturing Co. Semiconductor chip singulation method
US6924210B1 (en) * 2004-03-06 2005-08-02 International Business Machines Corporation Chip dicing
US7608919B1 (en) * 2003-09-04 2009-10-27 University Of Notre Dame Du Lac Interconnect packaging systems
JP2010040648A (en) * 2008-08-01 2010-02-18 Toshiba Corp Method of manufacturing semiconductor device
US20100078811A1 (en) * 2008-09-30 2010-04-01 Infineon Technologies Ag Method of producing semiconductor devices
US20110095399A1 (en) * 2004-12-29 2011-04-28 Richard Spitz Method For Manufacturing Semiconductor Chips From A Wafer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3169837A (en) * 1963-07-31 1965-02-16 Int Rectifier Corp Method of dicing semiconductor wafers
US6562698B2 (en) * 1999-06-08 2003-05-13 Kulicke & Soffa Investments, Inc. Dual laser cutting of wafers

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5698840A (en) * 1980-01-08 1981-08-08 Mitsubishi Electric Corp Preparation of semiconductor device
JPS62209816A (en) * 1986-03-10 1987-09-16 Toshiba Corp Semiconductor device
US5393711A (en) * 1991-10-12 1995-02-28 Robert Bosch Gmbh Process for manufacturing semiconductor components
US7608919B1 (en) * 2003-09-04 2009-10-27 University Of Notre Dame Du Lac Interconnect packaging systems
US20050158967A1 (en) * 2004-01-20 2005-07-21 Taiwan Semiconductor Manufacturing Co. Semiconductor chip singulation method
US6924210B1 (en) * 2004-03-06 2005-08-02 International Business Machines Corporation Chip dicing
US20110095399A1 (en) * 2004-12-29 2011-04-28 Richard Spitz Method For Manufacturing Semiconductor Chips From A Wafer
JP2010040648A (en) * 2008-08-01 2010-02-18 Toshiba Corp Method of manufacturing semiconductor device
US20100078811A1 (en) * 2008-09-30 2010-04-01 Infineon Technologies Ag Method of producing semiconductor devices

Also Published As

Publication number Publication date
US20140235033A1 (en) 2014-08-21
KR20150120329A (en) 2015-10-27
TW201442091A (en) 2014-11-01
CN104685618A (en) 2015-06-03

Similar Documents

Publication Publication Date Title
US20130130424A1 (en) Process for minimizing chipping when separating mems dies on a wafer
CN105810557A (en) Semiconductor wafer, flattening method therefor, and packaging method
US9543206B2 (en) Wafer die separation
CN105405806A (en) Plasma Etching And Stealth Dicing Laser Process
JP6298723B2 (en) Bonded wafer forming method
KR101990650B1 (en) Machining method
CN106816412A (en) The cutting technique of wafer and the production method of wafer
US8895363B2 (en) Die preparation for wafer-level chip scale package (WLCSP)
CN101607377A (en) The asymmetric chamfer processing method of single chip edge
WO2014126872A1 (en) Non-conventional method of silicon wafer sawing using a plurality of wafer saw rotational angles
US20130264686A1 (en) Semiconductor wafer processing
JP2013058653A (en) Method for dividing plate-like object
WO2018210065A1 (en) Packaging panel, device packaging structure and preparation method therefor
CN105789063A (en) Semiconductor device and fabrication method thereof
CN204136258U (en) A kind of cutting machine jig
JP2016219757A (en) Workpiece division method
TWI644774B (en) a method for separating a brittle material substrate, a substrate holding member for breaking a brittle material substrate, and a frame for adhering the adhesive film used for breaking the brittle material substrate
CN104637875A (en) Method for scribing silicon wafers of integrated circuits
US7294559B2 (en) Wafer dicing process for optical electronic packing
JP4818076B2 (en) Polygonal semiconductor chip manufacturing method and manufacturing apparatus
CN107275284B (en) A kind of preparation method of DAF chip
CN119610433B (en) A method to reduce crystal orientation deviation of wafers after dicing
US10622218B2 (en) Segmented edge protection shield
CN104716056B (en) A kind of wafer bonding method
CN216928546U (en) Packaging substrate adopting wafer-level shape

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14706446

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20157008142

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14706446

Country of ref document: EP

Kind code of ref document: A1