WO2014126237A1 - Circuit d'interface série synchrone - Google Patents

Circuit d'interface série synchrone Download PDF

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Publication number
WO2014126237A1
WO2014126237A1 PCT/JP2014/053630 JP2014053630W WO2014126237A1 WO 2014126237 A1 WO2014126237 A1 WO 2014126237A1 JP 2014053630 W JP2014053630 W JP 2014053630W WO 2014126237 A1 WO2014126237 A1 WO 2014126237A1
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WO
WIPO (PCT)
Prior art keywords
data
ssi
synchronous
clock
unit
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Application number
PCT/JP2014/053630
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English (en)
Japanese (ja)
Inventor
祥実 丹羽
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オムロン株式会社
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Publication date
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Publication of WO2014126237A1 publication Critical patent/WO2014126237A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Definitions

  • the present invention relates to a synchronous serial interface circuit, and more particularly to a synchronous serial interface circuit having a plurality of channels.
  • Synchronous serial communication is serial communication that transmits or receives data in synchronization with a clock.
  • a synchronous serial interface (hereinafter abbreviated as “SSI”) is widely used as a standard interface between a master and a slave used for industrial purposes.
  • Patent Document 1 discloses a signal transmission device that serially transmits an NRZ (Non Return to Zero) signal sequence from a transmission circuit to a reception circuit in synchronization with a clock signal sequence. This signal transmission device performs horizontal and vertical parity checks. The signal transmission device further generates a signal indicating detection of the header and a reception error signal or a reception end signal.
  • NRZ Non Return to Zero
  • an SSI interface circuit serving as an interface with a host device outputs a clock to an SSI compatible device (slave).
  • the SSI-compatible device is, for example, an absolute encoder or a distance measuring sensor.
  • the slave transmits data to the master in synchronization with the clock. Therefore, in the case of data acquisition using SSI, the time required for one data acquisition is determined by the clock cycle and the size (number of bits) of the data. For this reason, the update of data is also repeated at intervals equal to or longer than the time required for data acquisition.
  • SSI serial communication module
  • SSI is a simple data exchange means. Therefore, in order to reduce the cost of equipment, it is conceivable to realize SSI using a general-purpose input / output port.
  • An object of the present invention is to provide a synchronous serial interface circuit capable of realizing SSI communication of a plurality of channels without increasing the data update interval per channel with a small number of communication modules.
  • the present invention is a synchronous serial interface circuit and includes a plurality of channels. Each channel outputs a synchronization clock and receives data sent to each channel in synchronization with the output synchronization clock. At the start of data reception, the plurality of channels simultaneously lower the synchronous clock.
  • each of the plurality of channels sets the frequency of the synchronous clock during a period from when the synchronous clock is lowered to when the synchronous clock is raised at the start of data reception.
  • the plurality of channels can set the frequency of the synchronous clock independently of each other.
  • the synchronous serial interface circuit further includes a storage unit for storing the received data.
  • Each channel has a synchronous clock generator for generating a synchronous clock, a clock controller for operating the synchronous clock generator for a period according to the length of data to be received by the channel, And a DMA control unit for transferring the received data.
  • a plurality of channels of SSI communication can be realized without increasing the data update interval per channel with a small number of communication function modules.
  • FIG. 1 is a block diagram showing a schematic configuration of a motion control system including an interface circuit according to an embodiment of the present invention.
  • motion control system 1 includes a control unit 2, a communication unit 3, a position interface unit 4, a motor driver 5, a motor 6, an encoder 7A, and an SSI encoder 7B.
  • the communication unit 3 is connected to the control unit 2 via a network such as a LAN (Local Area Network).
  • a network such as a LAN (Local Area Network).
  • the communication unit 3 is configured to communicate with the control unit 2 using EtherCAT (registered trademark) or the like.
  • the control unit 2 executes positioning control or motion control of the motor driver 5 in cooperation with the position interface unit 4.
  • the control unit 2 is composed of, for example, a PLC (Programmable Logic Controller).
  • the position interface unit 4 has a position data input / output processing function for positioning control or motion control.
  • the position interface unit 4 is connected to the communication unit 3 and periodically communicates with the control unit 2 via the communication unit 3 and the network. From the position interface unit 4 to the control unit 2, the count values of the encoders 7A and 7B are sent. Conversely, a position command or a speed command is sent from the control unit 2 to the position interface unit 4.
  • the position interface unit 4 includes a pulse output unit 4A, a pulse input unit 4B, and an SSI input unit 4C.
  • the control unit 2 performs a motion calculation at regular intervals, and generates a command value for the pulse output unit 4A.
  • the command value is sent to the pulse output unit 4A every predetermined communication cycle.
  • the pulse output unit 4 ⁇ / b> A generates a pulse having a pulse number and a frequency according to the command value and outputs the pulse to the motor driver 5.
  • the motor driver 5 drives the motor 6 according to the pulse from the pulse output unit 4A.
  • Encoder 7A and SSI encoder 7B detect the rotation of the motor 6.
  • the pulse input unit 4B receives the pulses output from the encoder 7A and counts the pulses.
  • the SSI encoder 7B is an absolute encoder that supports the SSI interface.
  • the SSI input unit 4C implements a “synchronous serial interface circuit” according to the present invention. Specifically, the SSI input unit 4C outputs a synchronous clock to the SSI encoder 7B.
  • the SSI encoder 7B outputs a pulse in synchronization with the clock.
  • the SSI input unit 4C receives data from the SSI encoder 7B.
  • the count value of the pulse input unit 4B and the data received by the SSI input unit 4C are transmitted to the control unit 2 at a predetermined communication cycle.
  • an SSI encoder 7B absolute encoder
  • a sensor corresponding to the SSI interface can be connected to the SSI input unit 4C.
  • a distance measuring sensor corresponding to an SSI interface can be cited.
  • the SSI input unit 4C has a function as a master unit.
  • the SSI encoder 7B has a function as a slave unit.
  • the SSI input unit 4C according to the embodiment of the present invention has a plurality of (for example, two) channels.
  • the number of channels of the SSI input unit 4C is assumed to be two.
  • FIG. 2 is a diagram showing an example of connection between an SSI input unit 4C having two channels and an SSI encoder.
  • SSI input unit 4C has two channels (indicated as “1CH” and “2CH” in FIG. 2).
  • the synchronous clock CLK1 is transmitted from one channel (1CH) to the SSI encoder 7B1.
  • the SSI encoder 7B1 transmits data D1 to the SSI input unit 4C in synchronization with the synchronous clock CLK1.
  • the synchronous clock CLK2 is transmitted from the other channel (2CH) to the SSI encoder 7B2.
  • the SSI encoder 7B2 transmits data D2 to the SSI input unit 4C in synchronization with the synchronous clock CLK2.
  • a twisted pair line is used for clock transmission and data transmission.
  • all two channels of the SSI input unit 4C are used. However, it is not limited in this way. Only one channel may be used.
  • FIG. 3 is a diagram schematically illustrating data transmission according to the embodiment of the present invention. Referring to FIG. 3, before the time t1, both the synchronous clock and the data are at the H (logic high) level.
  • the SSI input unit 4C lowers the synchronous clock from H level to L (logic low) level.
  • data transfer from the SSI encoder 7B (see FIG. 1) is started.
  • data is output bit by bit from the SSI encoder 7B in synchronization with the rising or falling edge of the synchronous clock (whichever is acceptable).
  • the SSI input unit 4C receives data bit by bit. That is, serial communication is performed between the SSI input unit 4C and the SSI encoder 7B.
  • both the synchronous clock and the data become H (logic high) level.
  • the SSI input unit 4C receives data from the two SSI encoders 7B1 and 7B2. For example, as shown in FIG. 4, the SSI input unit 4C acquires the data D1 from the SSI encoder 7B1 on the first channel (1CH), and then from the SSI encoder 7B2 on the second channel (2CH). A method for obtaining the data D2 is conceivable. However, since data acquisition is performed in series, the update interval of each channel increases.
  • the time at which data is generated at the SSI encoder 7B1 is different from the time at which data is generated at the SSI encoder 7B2.
  • the detection time differs between the data from the SSI encoder 7B1 and the data from the SSI encoder 7B2.
  • the SSI input unit 4C can achieve different data transfer rates for each channel. Furthermore, the SSI input unit 4C can synchronize the start of data transfer between the two channels. That is, the detection result at the same time can be received from the SSI encoder 7B1 and the SSI encoder 7B2. Such processing will be described below.
  • FIG. 5 is a block diagram schematically showing functions of the SSI input unit 4C according to the embodiment of the present invention.
  • SSI input unit 4 ⁇ / b> C includes a trigger generation unit 11, data reception units 12 and 13, a storage unit 14, and an I / O unit 15.
  • the trigger generator 11 generates the trigger signal Str at a predetermined cycle, for example. This cycle is determined, for example, according to the communication cycle between the control unit 2 (see FIG. 1) and the position interface unit 4 (see FIG. 1).
  • the trigger signal Str is sent to the data receiving units 12 and 13.
  • the data receiving unit 12 outputs the synchronous clock CLK1 and receives the data D1 from the SSI encoder 7B1 (see FIG. 2).
  • the data receiver 12 includes a synchronous clock generator 21A, a clock controller 22A, and a DMA (Dynamic Access Memory) controller (DMAC) 24A.
  • DMA Dynamic Access Memory
  • the synchronous clock generator 21A generates a pulse train. This pulse train is output from the synchronous clock generator 21A as the synchronous clock CLK1.
  • the synchronous clock generation unit 21A can be realized by a timer or a counter.
  • the clock control unit 22A controls the generation and stop of the synchronous clock CLK1 by controlling the synchronous clock generation unit 21A in response to the trigger signal Str. Note that the clock control unit 22A may read the set value of the period of the synchronous clock CLK1 stored in the storage unit 14 and load the set value into the synchronous clock generation unit 21A.
  • the DMAC 23A acquires the data D1 bit by bit in synchronization with the clock generated by the synchronous clock generation unit 21A, and transmits the bit to the storage unit 14.
  • the DMAC it is possible to cope with high-speed (for example, MHz order) data transmission.
  • the data receiving unit 13 is different from the data receiving unit 12 in that it transmits a synchronous clock CLK2 instead of the synchronous clock CLK1 and receives data D2 instead of the data D1.
  • the data receiver 13 includes a synchronous clock generator 21B, a clock controller 22B, and a DMAC 24B. Since the function of each part of data receiving unit 13 is the same as the function of the corresponding part of data receiving unit 12, the following detailed description will not be repeated.
  • the storage unit 14 stores setting values related to the frequency of the synchronous clocks CLK1 and CLK2, and setting values related to the number of pulses of the synchronous clock.
  • the storage unit 14 may be either a volatile memory or a nonvolatile memory. For example, if the storage unit 14 is a volatile memory, when the SSI input unit 4C is activated, it is transferred from the control unit 2 to the storage unit 14 of the SSI input unit 4C via the network and the communication unit 3 (both see FIG. 1). The set value is input.
  • the I / O unit 15 receives a command from the control unit 2 shown in FIG. 1 and transmits the acquired data D1 and D2 to the control unit 2, for example.
  • the SSI input unit 4C may perform appropriate processing on the data D1 and D2 and transmit the processed data to the control unit 2.
  • FIG. 5 shows a configuration according to one embodiment, and does not limit the configuration of the SSI input interface.
  • a plurality of functional blocks may be integrated into one.
  • one functional block can be divided into a plurality of functional blocks.
  • FIG. 6 is a timing chart showing an example of the operation of the SSI input unit 4C according to the embodiment of the present invention.
  • trigger generation unit 11 generates trigger signal Str at time t10.
  • the synchronous clock generators 21A and 21B and the clock controllers 22A and 22B are started in response to the trigger signal Str and change the synchronous clocks CLK1 and CLK2 from H level to L level, respectively.
  • the synchronous clocks CLK1 and CLK2 fall simultaneously at time t11.
  • the frequencies of the synchronization clocks CLK1 and CLK2 are set.
  • the frequencies of the synchronous clocks CLK1 and CLK2 are the same. Therefore, after time t12, the synchronous clocks CLK1 and CLK2 change in the same cycle.
  • 1-bit data is acquired for each period of the synchronous clock.
  • the lengths of the data D1 and D2 are different in this example. That is, the number of bits of the data D1 is 5, and the number of bits of the data D2 is 8.
  • the clock control unit 22A turns off the synchronous clock generation unit 21A. Therefore, after time t12, the synchronous clock CLK1 becomes H level. Thereafter, at time t14, the transfer of the data D2 is completed.
  • the clock control unit 22B turns off the synchronous clock generation unit 21B. After time t14, the synchronous clock CLK2 becomes H level.
  • the trigger generating unit 11 generates the trigger signal Str again.
  • the synchronous clock generators 21A and 21B and the clock controllers 22A and 22B are started in response to the trigger signal Str and change the synchronous clocks CLK1 and CLK2 from H level to L level, respectively. Therefore, synchronous clocks CLK1 and CLK2 fall at the same time at time t16. Since the transfer of data D1 and D2 after time t21 is the same as the above processing, the following description will not be repeated.
  • FIG. 7 is a timing chart showing another example of the operation of the SSI input unit according to the embodiment of the present invention.
  • the operation of SSI input unit 4C at each of times t20 to t24 corresponds to the operation of SSI input unit 4C at each of times t10 to t14. That is, at time t20, the trigger generator 11 generates the trigger signal Str. Accordingly, synchronous clocks CLK1 and CLK2 fall simultaneously at time t21.
  • the synchronous clock generators 21A and 21B are activated and measure a certain time. The time when the time measurement ends is time t21.
  • the frequencies of the synchronous clocks CLK1 and CLK2 are set between time t21 and time t22.
  • the frequencies of the synchronous clocks CLK1 and CLK2 are different.
  • the frequency of the synchronous clock CLK2 is lower than the frequency of the synchronous clock CLK1.
  • the SSI encoder 7B requires a certain amount of time to determine data. Therefore, as shown in FIG. 7, synchronous clocks CLK1 and CLK2 are once lowered at time t21. Thereafter, the frequencies of the synchronous clocks CLK1 and CLK2 are set.
  • the synchronous clock generators 21A and 21B output a clock having the set frequency.
  • the means for generating the clock is not particularly limited, and the clock may be generated by a timer, for example.
  • the data D2 is expressed as 4-bit data for convenience of illustration. However, the number of bits of the data D2 is not limited in this way.
  • the synchronous clock is simultaneously lowered when data is received on a plurality of channels.
  • the start of data transfer can be synchronized between the two channels. That is, the detection result at the same time can be received from the SSI encoder 7B1 and the SSI encoder 7B2.
  • the functional blocks that generate the synchronous clock are independent of each other.
  • data reception on a plurality of channels can be executed in parallel. Therefore, the data update interval can be shortened in each channel.
  • the frequency of the synchronous clock can be made different among a plurality of channels.
  • the frequency of the synchronous clock can be made different among a plurality of channels.
  • data can be received by one unit. Accordingly, it is possible to suppress an increase in cost due to the use of a method of using a high-function (and therefore expensive) microcomputer or providing a plurality of input units.
  • 1 motion control system 2 control unit, 3 communication unit, 4 position interface unit, 4A pulse output unit, 4B pulse input unit, 4C SSI input unit, 5 motor driver, 6 motor, 7A encoder, 7B, 7B1, 7B2 SSI encoder 11 trigger generation unit 12, 13 data reception unit, 14 storage unit, 15 I / O unit, 21A, 21B synchronous clock generation unit, 22A, 22B clock control unit.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)

Abstract

L'invention porte sur un circuit d'interface série synchrone qui peut réaliser des communications d'interface série synchrone (SSI) sur de multiples canaux sans augmenter un intervalle de mise à jour de données par canal tout en utilisant un petit nombre de modules de communication. Une unité d'entrée d'interface série synchrone (SSI) (4C) est équipée de multiples canaux (1CH, 2CH). Les canaux respectifs délivrent des horloges synchrones (CLK1, CLK2) et reçoivent des données (D1, D2) qui sont transmises aux canaux respectifs en synchronisme avec les horloges synchrones de sortie. Lorsqu'ils commencent à recevoir les données, les multiples canaux amènent simultanément les horloges synchrones (CLK1, CLK2) à descendre.
PCT/JP2014/053630 2013-02-15 2014-02-17 Circuit d'interface série synchrone WO2014126237A1 (fr)

Applications Claiming Priority (2)

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JP2013-027646 2013-02-15
JP2013027646A JP6201331B2 (ja) 2013-02-15 2013-02-15 同期シリアルインタフェース回路

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112600807A (zh) * 2020-12-03 2021-04-02 航宇救生装备有限公司 一种同步串行接口编码器的无线采集方法

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPH01146442A (ja) * 1987-12-02 1989-06-08 Fuji Xerox Co Ltd ビデオデータ伝送方式
JP2010504698A (ja) * 2006-09-21 2010-02-12 アナログ・デバイシズ・インコーポレーテッド シリアルディジタルデータ通信インターフェイス
JP2010213272A (ja) * 2009-03-06 2010-09-24 Robert Bosch Gmbh 電流信号を受け取る受信装置、受信装置を備えた回路装置、及びバスシステムを介して電流信号を伝送する方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL114924A (en) * 1994-08-18 2000-02-17 Omnipoint Corp Multi-land multi-mode communication system
US6031847A (en) * 1997-07-01 2000-02-29 Silicon Graphics, Inc Method and system for deskewing parallel bus channels

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01146442A (ja) * 1987-12-02 1989-06-08 Fuji Xerox Co Ltd ビデオデータ伝送方式
JP2010504698A (ja) * 2006-09-21 2010-02-12 アナログ・デバイシズ・インコーポレーテッド シリアルディジタルデータ通信インターフェイス
JP2010213272A (ja) * 2009-03-06 2010-09-24 Robert Bosch Gmbh 電流信号を受け取る受信装置、受信装置を備えた回路装置、及びバスシステムを介して電流信号を伝送する方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112600807A (zh) * 2020-12-03 2021-04-02 航宇救生装备有限公司 一种同步串行接口编码器的无线采集方法

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JP2014158150A (ja) 2014-08-28

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