WO2014110846A1 - 一种短时与长时存储器件及存储方法 - Google Patents

一种短时与长时存储器件及存储方法 Download PDF

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Publication number
WO2014110846A1
WO2014110846A1 PCT/CN2013/071157 CN2013071157W WO2014110846A1 WO 2014110846 A1 WO2014110846 A1 WO 2014110846A1 CN 2013071157 W CN2013071157 W CN 2013071157W WO 2014110846 A1 WO2014110846 A1 WO 2014110846A1
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electrode layer
resistance state
memory device
volatile low
time
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English (en)
French (fr)
Inventor
缪向水
李祎
钟应鹏
许磊
孙华军
徐小华
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0035—Evaluating degradation, retention or wearout, e.g. by counting writing cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8822—Sulfides, e.g. CuS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse

Definitions

  • the present invention is in the field of information storage devices, and more particularly, relates to a short-term and long-term storage device and a storage method.
  • DRAM Dynamic Random-Access Memory
  • the information storage of the human brain has the functions of short-term memory and long-term memory, which can forget most of the irrelevant information, thereby improving information storage and processing efficiency.
  • the open number is CN 101419836A, and the patent application file entitled "A Phase Change Random Access Memory” contains only a long-term memory module and cannot implement a short-term memory function.
  • the present invention provides a short-term and long-term memory device comprising a first electrode layer, a functional material layer connected to the first electrode layer, and a second electrode layer connected to the functional material layer;
  • the material of the electrode layer is an inert conductive metal
  • the material of the second electrode layer is a reactive conductive metal
  • the material of the functional material layer is a sulfur-based compound.
  • the first electrode layer is configured to receive an external pulse signal
  • the second The pole layer is configured to receive an external pulse signal
  • the memory device changes from a high resistance state to a volatile a low resistance state, after the forgetting time, the memory device recovers from the volatile low resistance state to the high resistance state, realizing a short time storage function
  • the voltage between the layers is a second write pulse, and the memory device transitions from a high resistance state to a nonvolatile low resistance state to realize a long-term storage function.
  • the first electrode layer is configured to receive an external pulse signal
  • the second electrode layer is configured to receive an external pulse signal
  • the voltage is a plurality of first write pulses separated by a first interval
  • the memory device transitions from a high resistance state to a volatile low resistance state, and the memory device is removed from the volatile low resistance state after a forgotten time Recovering to the high resistance state, realizing a short-time storage function
  • the voltage applied between the first electrode layer and the second electrode layer is a plurality of first write pulses separated by a second interval
  • the storage device transitions from a high resistance state to a non-volatile low resistance state to implement a long-term storage function; the second interval time is less than the first interval time.
  • the first electrode layer is configured to receive an external pulse signal
  • the second electrode layer is configured to receive an external pulse signal; when applied between the first electrode layer and the second electrode layer
  • the voltage is a reset pulse
  • the memory device recovers from a volatile low-resistance state or a non-volatile low-resistance state to a high-impedance state to implement a reset function.
  • the voltage amplitude of the first write pulse is greater than the first voltage threshold and less than the second voltage threshold; the voltage amplitude of the second write pulse is greater than the second voltage threshold; Greater than a time threshold; the second interval time is less than a time threshold.
  • the first voltage threshold ranges from 0.5 to 1.5 V
  • the second voltage threshold ranges from 1.6 to 3 V
  • the time threshold ranges from lms to 168 h.
  • first electrode layer, the functional material layer and the second electrode layer constitute a sandwich laminate structure, a T-type structure, an I-type structure or a pyramid-type structure.
  • the material of the first electrode layer is platinum, titanium tungsten or tantalum.
  • the material of the functional material layer is an alloy composed of any two or more of yttrium, lanthanum, cerium, tin, selenium and tellurium.
  • the material of the second electrode layer is silver or copper.
  • the invention also provides a short-term and long-term storage method, comprising the following steps:
  • the long-term storage function is realized by controlling the voltage between the first electrode layer and the second electrode layer to be a second write pulse to cause the memory device to transition from a high resistance state to a non-volatile low resistance state.
  • the method further includes the following steps:
  • Controlling the memory device from a high resistance state to a volatile low resistance state by controlling a voltage between the first electrode layer and the second electrode layer to be a plurality of first write pulses separated by a first interval time And after the forgetting time, the storage device recovers from the volatile low resistance state to the high resistance state, and realizes a short-time storage function;
  • Controlling the memory device from a high resistance state to a nonvolatile low resistance by controlling a voltage between the first electrode layer and the second electrode layer to be a plurality of first write pulses separated by a second interval time State, realizes long-term storage function;
  • the second interval time is less than the first interval time.
  • the method further includes the steps of: controlling the memory device from a volatile low-resistance state by controlling a voltage between the first electrode layer and the second electrode layer as a reset pulse
  • the volatile low-resistance state returns to a high-impedance state, realizing the reset function.
  • the memory device under the action of a single first write signal or a plurality of first write pulses having a first interval time, the memory device is switched from a high resistance state to a volatile low resistance state, and the stored information can be maintained for a short period of time;
  • the memory device switches from a high resistance state or a volatile low resistance state to a nonvolatile low resistance state under a single second write pulse or a plurality of first write pulses having a second interval time, and the information information can be stored.
  • FIG. 1 is a schematic structural diagram of a short-term and long-term memory device according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a test for simulating human brain short-term memory and long-term memory according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a short-term and long-term storage device simulating human brain short-term memory test according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a short-term and long-term storage device for simulating a human brain long-term memory test according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a simulated human brain memory elimination test for a short-term and long-term storage device according to an embodiment of the present invention
  • FIG. 6 is a flowchart of a method for operating a short-term and long-term storage device according to an embodiment of the present invention. [specifically fresh]
  • the present invention proposes a new memory device and a storage method thereof, which are capable of short-term storage and long-term storage of information. It can be used to simulate the information storage mode of the human brain. Combining short-term memory and long-term memory is a possible method and direction to improve the efficiency of existing storage devices.
  • the short-term and long-term storage device includes a first electrode layer, a functional material layer connected to the first electrode layer, and a second electrode layer connected to the functional material layer; the material of the first electrode layer is inert conductive
  • the metal, the material of the second electrode layer is a living conductive metal, and the material of the functional material layer is a sulfur-based compound.
  • the memory device can simulate short-term memory and long-term memory of the human brain, and realizes short-term and long-term information storage functions. It is a two-terminal device, has a simple structure, and the functional material used is a sulfur-based compound material, which has been maturely applied in the information storage technology industry and is easy to prepare. Low cost; device size up to the nanometer level, low power consumption, and greater possibilities for large-scale storage arrays or neural network arrays.
  • the first electrode layer is configured to receive an external pulse signal
  • the second electrode layer is configured to receive an external pulse signal
  • the first electrode layer is configured to receive an external pulse signal
  • the second electrode layer is configured to receive an external pulse signal
  • the memory device when applied to the first electrode layer and the second electrode layer
  • the voltage between the plurality of first write pulses separated by the first interval time the memory device transitions from a high resistance state to a volatile low resistance state, and the memory device is from the volatile low resistance after the forgetting time Returning to the high resistance state, realizing a short-time storage function; when the voltage applied between the first electrode layer and the second electrode layer is a plurality of first write pulses separated by a second interval time,
  • the storage device transitions from a high resistance state to a non-volatile low resistance state to implement a long-term storage function; wherein the second interval time is less than the first interval time.
  • the time of forgetting varies according to the material, and the forgetting time ranges from 5ms to 168h.
  • the first electrode layer is configured to receive an external pulse signal
  • the second electrode layer is configured to receive an external pulse signal; when applied to the first electrode layer and the second electrode layer The voltage between them is a reset pulse, and the memory device recovers from a volatile low resistance state or a nonvolatile low resistance state to a high resistance state, thereby realizing a reset function.
  • the storage device can simulate the functions of human brain short-term memory and long-term memory, and specifically includes: (1) The storage device has at least three resistance states, a high resistance state (OFF state), and a short retention time. Low-impedance state (volatile low-resistance, short-term storage) and stable low-resistance state (nonvolatile low-resistance, long-term storage); (2) Applying a first write pulse enables the memory device From the OFF state to the volatile low-resistance state, but then the device will automatically decay from the volatile low-resistance state to the OFF state for a short period of time to achieve short-term memory function; (3) Apply a plurality of time intervals large enough The first write pulse causes the memory to transition from the OFF state to the volatile low-resistance state, but then the device will decay from the volatile low-resistance state to the OFF state for a period of time to achieve short-term memory function; (4) Apply multiple A first write pulse with
  • the short-length storage device provided by the embodiment of the invention can simulate the functions of real-time short-term memory and long-term memory, and store important data stably for a long time, actively delete and forget the unimportant data, and improve storage efficiency from the function.
  • the short-time and long-term memory devices employ an active electrode/amorphous sulfur-based compound material/inert electrode structure.
  • the functional material layer is a sulfur-based compound, and one end of the device is made of an active metal such as Ag or Cu, and the other end is made of an inert metal such as Pt, Au, Ti, TiN, TiW or Ta.
  • the resistance change of the device is based on two different mechanisms. The first type is based on the oxidation reaction at the interface between the metal electrode and the sulfur-based compound, and the generated active metal ions migrate into the functional material under the action of the electric field to form a metal conductive wire, which lowers the electrical resistance, but the metal conductive wire diffuses with time.
  • the second is based on the phase change of the sulfur-based compound under the action of Joule heat generated by the current, from a high-resistance amorphous state to a low-resistance crystalline state, achieving long-term memory function.
  • the device is initially in a high resistance OFF state.
  • a write pulse When a write pulse is applied, an oxidation reaction occurs between the functional material and the contact surface of the second electrode to form a metal ion of the second electrode material.
  • the metal ion migrates toward the first electrode under the electric field, and will In the functional material, a metal conductive wire is formed between the first electrode and the second electrode, but the functional material is not phase-transformed, so that the device becomes a volatile low-resistance state based on the conductive wire of the metal conductive wire, realizing short-term storage. .
  • the write pulse continues to be applied, the functional material undergoes a phase change due to the energy accumulation effect of the sulfur-based compound material, and becomes stable with low resistance.
  • the device In the crystalline state, the device is a non-volatile low-impedance state, enabling long-term storage.
  • the device is initially in a high-resistance OFF state.
  • a large amplitude write pulse When a large amplitude write pulse is applied, the functional material undergoes a phase change, and the device is in a non-volatile low-impedance state, enabling long-term storage.
  • the device is in the low resistance ON state, if a negative reset pulse is applied, the metal ions in the functional material will migrate to the second electrode, the wires connecting the first electrode and the second electrode are disconnected, and the functional material undergoes a phase change again.
  • the metal conductive wire diffuses in the functional material under the influence of the external environment, and is disconnected after a period of time to return to the high resistance OFF state.
  • the first electrode material is an inert conductive metal such as platinum (Pt), titanium tungsten (TiW), or tantalum (Ta), wherein the second electrode material is active conductive such as silver (Ag) or copper (Cu).
  • Metal; functional material is a sulfur-based compound, including two or more alloys such as germanium (Ge), antimony (Sb), tellurium (Te), and antimony (Bi), such as GeTe, Ge 2 Sb 2 Te 5 , Sb 2 Te 3 , BiTe and AglnSbTe, etc.
  • the voltage amplitude of the first write pulse is greater than the first voltage threshold and less than the second voltage threshold; the voltage amplitude of the second write pulse is greater than the second voltage threshold; the first interval time is greater than the time threshold; The second interval is less than the time threshold.
  • the first electrode layer, the functional material layer and the second electrode layer constitute a sandwich laminate structure, a T-type structure, an I-type structure or a pyramid-type structure.
  • BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a specific structure of the short-term and long-term memory device of the present invention as a sandwich laminate structure; for convenience of explanation, only parts related to the embodiment of the present invention are shown, which are described in detail as follows:
  • the short-term and long-term memory device includes a first electrode 101, a second electrode 103, and a functional material 102 between the first electrode 101 and the second electrode 103.
  • the functional material 102 is in electrical contact with the first electrode 101 and the second electrode 103.
  • the first electrode material is platinum (Pt)
  • the second electrode material is silver (Ag)
  • the functional material is GeTe.
  • a voltage pulse signal is applied to the second electrode 103, and the first electrode 101 is grounded, and the resistance is the resistance between the first electrode 101 and the second electrode 103.
  • the voltage amplitude of the write pulse signal is greater than the first voltage threshold (0.5 ⁇ 1.5V) and less than the second voltage threshold (1.6 ⁇ 3V)
  • the first write pulse when the voltage amplitude of the write pulse signal is greater than the second voltage threshold, it is defined as the second write pulse.
  • the interval of the write pulse signal is greater than the time threshold (lms ⁇ 168h), it is defined as the first interval time, and when the interval time of the write pulse signal is less than the time threshold, it is defined as the second interval time.
  • the device resistance When the device resistance is greater than the first resistance threshold (5 (3 ⁇ 4 ⁇ 10 ⁇ ), it is defined as the high resistance state or OFF state; when the device resistance is less than the second resistance threshold value (lkQ ⁇ 50kQ), it is defined as the low resistance state, that is, the ON state.
  • FIG. 2 is a diagram showing simulation of a human brain short-term memory function and a long-term memory function in a short-term and long-term storage device according to an embodiment of the present invention.
  • the memory device is initially in the OFF state.
  • the device resistance decreases and becomes a volatile low resistance state.
  • the resistance of the device gradually increases. After a period of time, it returns to the OFF state, realizing short-term memory.
  • the memory device is initially in the OFF state.
  • the device resistance decreases and turns into a non-volatile low-impedance state.
  • the device resistance is basically unchanged, and it remains in the low-resistance ON state, achieving long-term memory.
  • FIG. 3 is a diagram showing the simulation of a human brain short-term memory function in a short-term and long-term storage device in accordance with an embodiment of the present invention.
  • the memory device is initially in the OFF state.
  • a first write pulse signal When a first write pulse signal is input, the device resistance decreases and becomes a volatile low resistance state.
  • the input signal is zero, the device resistance gradually increases, and after a period of time, it returns to the OFF state.
  • the first write pulse signal is input after the first time interval, the device resistance decreases again, and becomes a volatile low resistance state, and when the input signal is zero, the device resistance gradually increases, after a period of time. , returns to the OFF state.
  • the device After inputting a number of first write pulse signals separated by a first time interval, the device can still return to the OFF state after transitioning to a volatile low resistance state.
  • FIG. 4 is a diagram showing the simulation of a human brain long-term memory function in a short-term and long-term memory device, in accordance with an embodiment of the present invention.
  • the short- and long-term memory devices are initially in the OFF state.
  • a first write pulse signal When a first write pulse signal is input, The device's resistance is reduced and it becomes a volatile low-impedance state.
  • the input signal When the input signal is zero, the device resistance gradually increases, and after a period of time, it returns to the OFF state.
  • the first write pulse signal is input after the second time interval, the device resistance decreases again, and becomes a volatile low resistance state, and when the input signal is zero, the device resistance gradually increases, after a period of time. , returns to the OFF state.
  • the device After inputting a number of first write pulse signals separated by a second time interval, the device transitions to a non-volatile low resistance state.
  • Figure 5 is a diagram showing the implementation of a human brain memory cancellation function, i.e., a store information erase operation, in a short-term and long-term storage device in accordance with another embodiment of the present invention.
  • a human brain memory cancellation function i.e., a store information erase operation
  • the short-term and long-term memory devices are initially in the ON state.
  • a negative reset pulse signal is input, the device resistance increases and turns to the OFF state, and when the input signal is zero, the device conductance remains unchanged and remains in the OFF state.
  • the long-term storage function is realized by controlling the voltage between the first electrode layer and the second electrode layer to be a second write pulse to cause the memory device to transition from a high resistance state to a non-volatile low resistance state.
  • the foregoing method further includes:
  • Controlling the memory device from a high resistance state to a volatile low resistance state by controlling a voltage between the first electrode layer and the second electrode layer to be a plurality of first write pulses separated by a first interval time And after the forgetting time, the storage device recovers from the volatile low resistance state to the high resistance state, and realizes a short-time storage function;
  • Controlling the memory device from a high resistance state to a low nonvolatile state by controlling a voltage between the first electrode layer and the second electrode layer to be a plurality of first write pulses separated by a second interval time
  • the resistance state realizes a long-term storage function; wherein, the second interval time is less than the first interval time.
  • the memory device By controlling the voltage between the first electrode layer and the second electrode layer as a reset pulse, the memory device is restored from a volatile low resistance state or a nonvolatile low resistance state to a high resistance state, thereby realizing The reset function.
  • Figure 6 is a flow chart showing the implementation of short-term memory, long-term memory and stored information erasing functions in short-term and long-term memory devices in accordance with the present invention.
  • the memory device When the short-term and long-term memory devices are initially in the OFF state, after inputting a first write pulse, or a plurality of first write pulses separated by the first interval, the memory device is converted into a volatile low-resistance state; After writing a pulse, or a plurality of first write pulses separated by a second interval, the memory device transitions to a non-volatile low resistance state.
  • the short-term and long-term memory devices When the short-term and long-term memory devices are initially in a volatile low-impedance state, no signal is input, after a period of time, the device is turned into an OFF state, or a reset pulse is input, and turned into an OFF state; After the first write pulse, or a second write pulse, the memory device transitions to a non-volatile low-impedance state.
  • the reset pulse signal is input and the device transitions to the OFF state.
  • the device of other structure such as T-type structure, I-type structure or pyramid-type structure
  • the first electrode of other materials including inert conductive metals such as titanium tungsten (TiW) and tantalum (Ta), other
  • the second electrode of the material including active conductive metals such as copper (Cu), and other functional materials of sulfur-based compounds, including germanium (Ge), antimony (Sb), antimony (Te) tin, selenium and tellurium (Bi), etc.
  • Two or more alloys such as GeTe, Ge 2 Sb 2 Te 5 , Sb 2 Te 3 , BiTe and AglnSbTe, can also realize the functions of short-term and long-term storage as described above. Said.
  • the short-term and long-term storage device and the storage method provided by the invention can simultaneously simulate the short-term memory function, the long-term memory function and the memory elimination function of the human brain.

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Abstract

本发明属于信息存储器件领域，提供了一种短时与长时存储器件及存储方法；该存储器件包括第一电极层、功能材料层和第二电极层；第一电极层的材料为惰性导电金属，第二电极层的材料为活泼导电金属，功能材料层的材料为硫系化合物；在单个第一写信号或多个具有第一间隔时间的第一写脉冲作用下，存储器件从高阻态转换到易失性低阻态，存储信息能维持一段较短时间；在单个第二写脉冲或多个具有第二间隔时间的第一写脉冲作用下，存储器件从高阻态或易失性低阻态切换到非易失性低阻态，存储信息能维持很长一段时间。可以实现生物短时记忆和长时记忆的功能模拟，将重要数据长期稳定存储，将不重要数据主动遗忘删除，从功能上提高存储效率。

Description

一种耐与长时存储器件及存储
【技术领域】
本发明属于信息存储器件领域， 更具体地， 涉及一种短时与长时存储 器件及存储方法。
【背景技术】
传统存储器分成两种， 一种是非易失性存储器， 譬如磁盘存储和闪存， 另一种是易失性存储器， 譬如动态随机存储器 （Dynamic Random-Access Memory, DRAM)。 传统存储器的发展在于靠减少单元面积来提高存储密 度， 当越来越接近物理极限时， 难以再进一步提升， 难以适应信息呈爆炸 式增长的信息技术飞速发展的当今时代。 除了追求存储器更高密度、 更快 速度、 更高可靠性之外， 也应该从功能的维度驱动存储器发展， 开发出具 有新型功能的存储器， 以提高存储效率。
相比于传统的存储器件， 人脑的信息存储具有短时记忆和长时记忆的 功能， 能够将大部分无关信息遗忘掉， 从而提高信息存储和处理效率。 公 开号为 CN 101419836A, 发明名称为"一种相变随机存储器"的专利申请文 件中存储器仅包含了长时存储模块， 不能实现短时存储功能。
【发明内容】
针对现有技术的缺陷， 本发明的目的在于提供一种能同时实现长时存 储和短时存储的短时与长时存储器件。
本发明提供了一种短时与长时存储器件， 包括第一电极层、 与所述第 一电极层连接的功能材料层， 与所述功能材料层连接的第二电极层； 所述 第一电极层的材料为惰性导电金属， 所述第二电极层的材料为活泼导电金 属， 所述功能材料层的材料为硫系化合物。
更进一步地， 所述第一电极层用于接收外部的脉冲信号， 所述第二电 极层用于接收外部的脉冲信号； 当施加在所述第一电极层与所述第二电极 层之间的电压为第一写脉冲时， 所述存储器件从高阻态转变为易失性低阻 态， 经过遗忘时间后所述存储器件从所述易失性低阻态恢复到所述高阻态， 实现短时存储功能； 当施加在所述第一电极层与所述第二电极层之间的电 压为第二写脉冲， 所述存储器件从高阻态转变为非易失性低阻态， 实现长 时存储功能。
更进一步地， 所述第一电极层用于接收外部的脉冲信号， 所述第二电 极层用于接收外部的脉冲信号； 当施加在所述第一电极层与所述第二电极 层之间的电压为多个相隔第一间隔时间的第一写脉冲， 所述存储器件从高 阻态转变为易失性低阻态， 经过遗忘时间后所述存储器件从所述易失性低 阻态恢复到所述高阻态， 实现短时存储功能； 当施加在所述第一电极层与 所述第二电极层之间的电压为多个相隔第二间隔时间的第一写脉冲， 所述 存储器件从高阻态转变为非易失性低阻态， 实现长时存储功能； 所述第二 间隔时间小于所述第一间隔时间。
更进一步地， 所述第一电极层用于接收外部的脉冲信号， 所述第二电 极层用于接收外部的脉冲信号； 当施加在所述第一电极层与所述第二电极 层之间的电压为复位脉冲， 所述存储器件从易失性低阻态或非易失性低阻 态恢复到高阻态， 实现复位功能。
更进一步地， 所述第一写脉冲的电压幅值大于第一电压阈值且小于第 二电压阈值； 所述第二写脉冲的电压幅值大于所述第二电压阈值； 所述第 一间隔时间大于时间阈值； 所述第二间隔时间小于时间阈值。
更进一步地， 所述第一电压阈值的取值范围为 0.5~1.5V， 所述第二电 压阈值的取值范围为 1.6~3V， 所述时间阈值的取值范围为 lms~168h。
更进一步地， 所述第一电极层、 所述功能材料层和所述第二电极层构 成三明治叠层结构、 T型结构、 I型结构或金字塔型结构。
更进一步地， 所述第一电极层的材料为铂、 钛钨或钽。 更进一步地， 所述功能材料层的材料为由锗、 锑、 碲、 锡、 硒和铋中 任意两种或两种以上的元素构成的合金。
更进一步地， 所述第二电极层的材料为银或铜。
本发明还提供了一种短时与长时存储方法， 包括下述步骤：
在第一电极层和第二电极层上施加脉冲信号；
通过控制所述第一电极层与所述第二电极层之间的电压为第一写脉冲 使得存储器件从高阻态转变为易失性低阻态， 并经过遗忘时间后所述存储 器件从所述易失性低阻态恢复到所述高阻态， 实现了短时存储功能；
通过控制所述第一电极层与所述第二电极层之间的电压为第二写脉冲 使得所述存储器件从高阻态转变为非易失性低阻态， 实现了长时存储功能。
更进一步地， 所述方法还包括下述步骤：
通过控制所述第一电极层与所述第二电极层之间的电压为多个相隔第 一间隔时间的第一写脉冲， 使得所述存储器件从高阻态转变为易失性低阻 态， 并经过遗忘时间后所述存储器件从所述易失性低阻态恢复到所述高阻 态， 实现了短时存储功能；
通过控制所述第一电极层与所述第二电极层之间的电压为多个相隔第 二间隔时间的第一写脉冲， 使得所述存储器件从高阻态转变为非易失性低 阻态， 实现了长时存储功能；
所述第二间隔时间小于所述第一间隔时间。
更进一步地， 所述方法还包括下述步骤： 通过控制所述第一电极层与 所述第二电极层之间的电压为复位脉冲， 使得所述存储器件从易失性低阻 态或非易失性低阻态恢复到高阻态， 实现了复位功能。
本发明中， 在单个第一写信号或多个具有第一间隔时间的第一写脉冲 作用下， 存储器件从高阻态转换到易失性低阻态， 存储信息能维持一段较 短时间； 在单个第二写脉冲或多个具有第二间隔时间的第一写脉冲作用下， 存储器件从高阻态或易失性低阻态切换到非易失性低阻态， 存储信息能维 持很长一段时间； 实现了生物短时记忆和长时记忆的功能模拟， 将重要数 据长期稳定存储， 将不重要数据主动遗忘删除， 从功能上提高存储效率。
【附图说明】
图 1是本发明实施例提供的短时与长时存储器件的结构示意图； 图 2是本发明实施例提供的模拟人脑短时记忆和长时记忆的测试示意 图；
图 3 是本发明实施例提供的短时与长时存储器件模拟人脑短时记忆测 试示意图；
图 4是本发明实施例提供的短时与长时存储器件模拟人脑长时记忆测 试示意图；
图 5 是本发明实施例提供的短时与长时存储器件模拟人脑记忆消除测 试示意图；
图 6是本发明实施例提供的短时与长时存储器件操作方法流程图。 【具体实鮮式】
为了使本发明的目的、 技术方案及优点更加清楚明白， 以下结合附图 及实施例， 对本发明进行进一步详细说明。 应当理解， 此处所描述的具体 实施例仅仅用以解释本发明， 并不用于限定本发明。
本发明提出了一种新的存储器件及其存储方法， 该器件能够对信息进 行短时存储和长时存储。 可以用于模拟人脑的信息存储模式， 将短时记忆 和长时记忆结合在一起， 是提高现有存储器件效率的一个可能方法和方向。
本发明实施例提供的短时与长时存储器件包括第一电极层、 与第一电 极层连接的功能材料层， 与功能材料层连接的第二电极层； 第一电极层的 材料为惰性导电金属， 第二电极层的材料为活泼导电金属， 功能材料层的 材料为硫系化合物。 该存储器件能模拟人脑的短时记忆和长时记忆， 实现 短时和长时的信息存储功能。 其为二端器件， 结构简单， 且所采用的功能 材料为硫系化合物材料， 已在信息存储技术工业界成熟应用， 易于制备， 成本低廉； 装置尺寸可至纳米级， 功耗低， 有较大的可能性应用于大规模 存储阵列或神经网络阵列。
在本发明实施例中， 第一电极层用于接收外部的脉冲信号， 所述第二 电极层用于接收外部的脉冲信号； 当施加在所述第一电极层与所述第二电 极层之间的电压为第一写脉冲时， 所述存储器件从高阻态转变为易失性低 阻态， 经过遗忘时间后所述存储器件从所述易失性低阻态恢复到所述高阻 态， 实现短时存储功能； 当施加在所述第一电极层与所述第二电极层之间 的电压为第二写脉冲， 所述存储器件从高阻态转变为非易失性低阻态， 实 现长时存储功能。
在本发明实施例中， 第一电极层用于接收外部的脉冲信号， 所述第二 电极层用于接收外部的脉冲信号； 当施加在所述第一电极层与所述第二电 极层之间的电压为多个相隔第一间隔时间的第一写脉冲， 所述存储器件从 高阻态转变为易失性低阻态， 经过遗忘时间后所述存储器件从所述易失性 低阻态恢复到所述高阻态， 实现短时存储功能； 当施加在所述第一电极层 与所述第二电极层之间的电压为多个相隔第二间隔时间的第一写脉冲， 所 述存储器件从高阻态转变为非易失性低阻态， 实现长时存储功能； 其中， 第二间隔时间小于所述第一间隔时间。 遗忘时间根据材料不同而不同， 遗 忘时间的范围为 5ms~168h。
在本发明实施例中， 第一电极层用于接收外部的脉冲信号， 所述第二 电极层用于接收外部的脉冲信号； 当施加在所述第一电极层与所述第二电 极层之间的电压为复位脉冲， 所述存储器件从易失性低阻态或非易失性低 阻态恢复到高阻态， 实现复位功能。
本发明实施例提供的存储装置能模拟人脑短时记忆和长时记忆的功 能， 具体包括： （1 ) 存储装置至少存在三个电阻状态， 高阻态 （OFF态）， 保持时间较短的低阻态 （易失性低阻态、 短时存储） 以及稳定保持的低阻 态 （非易失性低阻态、 长时存储）； (2) 施加一个第一写脉冲能使存储器件 从 OFF态转变为易失性低阻态， 但随后在一段时间内器件会从易失性低阻 态自动衰退回 OFF态， 实现短时记忆功能； （3 ) 施加多个相隔时间足够大 的第一写脉冲使存储器从 OFF态转变成易失性低阻态， 但随后在一段时间 内器件会从易失性低阻态衰退回 OFF态， 实现短时记忆功能； （4) 施加多 个相隔时间足够小的第一写脉冲使存储器件从 OFF态转变成非易失性低阻 态， 实现长时记忆功能； （5 ) 施加一个第二写脉冲能使存储器件从 OFF态 转变为非易失性低阻态， 实现长时记忆功能； （6) 对于处于短时记忆的易 失性低阻态或者长时记忆的非易失性低阻态， 施加复位脉冲都能使器件恢 复到 OFF态。 具体实现通过实施例说明。 本发明实施例提供的短长时存储 装置能模拟实现生物短时记忆和长时记忆的功能， 将重要数据长期稳定存 储， 将不重要数据主动遗忘删除， 从功能上提高存储效率。
在本发明实施例中， 短时与长时存储器件采用活性电极 /非晶硫系化合 物材料 /惰性电极结构。 功能材料层是硫系化合物， 器件一端电极采用 Ag、 Cu等活性金属， 另一端采用 Pt、 Au、 Ti、 TiN、 TiW、 Ta等惰性金属。 器 件的电阻变化基于两种不同机制。 第一种是基于金属电极与硫系化合物界 面处发生氧化反应， 生成的活性金属离子在电场作用下进入功能材料内迁 移， 形成金属导电丝， 使电阻下降， 但金属导电丝会随时间扩散而断裂， 使电阻上升， 实现短时记忆功能； 第二种是基于硫系化合物在电流产生的 焦耳热作用下产生相变， 从高电阻的非晶态转变成低电阻的晶态， 实现长 时记忆功能。
器件初始为高电阻 OFF态， 在施加写脉冲时， 功能材料与第二电极接 触面处发生氧化反应形成第二电极材料的金属离子， 金属离子在电场驱动 下往第一电极方向迁移， 将在功能材料中、 第一电极和第二电极之间形成 金属导电丝， 但又不至于使功能材料发生相变， 使器件变为基于金属导电 丝导电的易失性低阻态， 实现短时存储。 如果继续施加写脉冲， 由于硫系 化合物材料的能量累积效应， 功能材料发生相变， 转变成低电阻的稳定的 晶态，此时器件为非易失性低阻态，实现长时存储。器件初始为高电阻 OFF 态， 在施加幅值较大写脉冲时， 功能材料发生相变， 器件为非易失性低阻 态， 实现长时存储。 当器件处于低电阻 ON态， 如果施加负向复位脉冲， 功能材料中的金属离子会往第二电极迁移， 连接第一电极和第二电极的金 属丝断开， 而且使功能材料再次发生相变， 转变成高电阻的稳定的非晶态， 使器件复位到高电阻 OFF态。 此外， 金属导电丝在外界环境影响下， 在功 能材料中扩散， 经过一段时间也会断开， 恢复到高电阻 OFF态。
在本发明实施例中， 第一电极材料为铂 （Pt)、 钛钨 （TiW)、 钽 （Ta) 等惰性导电金属， 其中第二电极材料为银（Ag)、铜（Cu)等活泼导电金属； 功能材料为硫系化合物， 包括锗 （Ge)、 锑 （Sb)、 碲 （Te) 和铋 （Bi) 等 其中两种或两种以上的合金，如 GeTe、 Ge2Sb2Te5、 Sb2Te3、 BiTe和 AglnSbTe 等。
在本发明实施例中， 第一写脉冲的电压幅值大于第一电压阈值且小于 第二电压阈值； 第二写脉冲的电压幅值大于第二电压阈值； 第一间隔时间 大于时间阈值； 第二间隔时间小于时间阈值。
在本发明实施例中， 第一电极层、 所述功能材料层和所述第二电极层 构成三明治叠层结构、 T型结构、 I型结构或金字塔型结构。 图 1示出了本 发明的短时与长时存储器件为三明治叠层结构时的具体结构； 为了便于说 明， 仅示出了与本发明实施例相关的部分， 详述如下：
短时与长时存储器件包括第一电极 101、 第二电极 103和第一电极 101 和第二电极 103之间功能材料 102。 功能材料 102与第一电极 101、 第二电 极 103形成电接触。 在本实施例中， 第一电极材料为铂 （Pt)， 第二电极材 料为银 （Ag)， 功能材料为 GeTe。
在下列测试实例中， 电压脉冲信号施加在第二电极 103上， 第一电极 101接地， 电阻为第一电极 101与第二电极 103之间的电阻。当写脉冲信号 的电压幅值大于第一电压阈值（0.5~1.5V)而小于第二电压阈值（1.6~3V)， 定义为第一写脉冲， 当写脉冲信号的电压幅值大于第二电压阈值， 定义为 第二写脉冲。 当写脉冲信号的间隔时间大于时间阈值（lms~168h)， 定义为 第一间隔时间， 当写脉冲信号的间隔时间小于时间阈值， 定义为第二间隔 时间。 当器件电阻大于第一电阻阈值 （5(¾Ω~10ΜΩ) 时， 定义为高电阻态 即 OFF态； 当器件电阻小于第二电阻阈值（lkQ~50kQ)时， 定义为低电阻 态即 ON态。
图 2是示出根据本发明的实施例， 在短时与长时存储器件中模拟实现 人脑短时记忆功能和长时记忆功能。
存储器件初始处于 OFF态。 当输入一个第一写脉冲信号后， 器件电阻 减小， 转变成易失性低阻态。 之后输入信号为零， 器件电阻逐渐增大， 经 过一段时间后， 恢复到 OFF态， 实现短时记忆。
存储器件初始处于 OFF态。当输入一个第二写脉冲后，器件电阻减小， 转变成非易失性低阻态。 之后输入信号为零， 器件电阻基本不变， 保持在 低电阻 ON态， 实现长时记忆。
图 3 是示出根据本发明的实施例， 在短时与长时存储器件中模拟实现 人脑短时记忆功能。
存储器件初始处于 OFF态。 当输入一个第一写脉冲信号时， 器件电阻 减小， 转变成易失性低阻态。 在输入信号为零时， 器件电阻逐渐增大， 经 过一段时间后， 恢复到 OFF态。 当经过第一时间间隔， 再输入第一写脉冲 信号时， 器件电阻再次减小， 转变成易失性低阻态， 并在输入信号为零时， 器件电阻再逐渐增大， 经过一段时间后， 恢复到 OFF态。 当输入若干个相 隔第一时间间隔的第一写脉冲信号后， 器件转变成易失性低阻态后仍可以 恢复到 OFF态。
图 4是示出根据本发明的实施例， 在短时与长时存储器件中模拟实现 人脑长时记忆功能。
短时与长时存储器件初始处于 OFF态。当输入一个第一写脉冲信号时， 器件电阻减小， 转变成易失性低阻态。 在输入信号为零时， 器件电阻逐渐 增大， 经过一段时间后， 恢复到 OFF态。 当经过第二时间间隔， 再输入第 一写脉冲信号时， 器件电阻再次减小， 转变成易失性低阻态， 并在输入信 号为零时， 器件电阻再逐渐增大， 经过一段时间后， 恢复到 OFF态。 当输 入若干个相隔第二时间间隔的第一写脉冲信号后， 器件转变成非易失性低 阻态。
图 5 是示出根据本发明的另一实施例， 在短时与长时存储器件中模拟 实现人脑记忆消除功能， 即存储信息擦除操作。
短时与长时存储器件初始处于 ON态。 当输入一个负向复位脉冲信号 时， 器件电阻增大， 转变成 OFF态， 并能在输入信号为零时， 器件电导基 本不变， 保持在 OFF态。
采用本发明实施例提供的短时与长时存储器件实现的存储方法具体包 括：
在第一电极层和第二电极层上施加脉冲信号；
通过控制所述第一电极层与所述第二电极层之间的电压为第一写脉冲 使得存储器件从高阻态转变为易失性低阻态， 并经过遗忘时间后所述存储 器件从所述易失性低阻态恢复到所述高阻态， 实现了短时存储功能；
通过控制所述第一电极层与所述第二电极层之间的电压为第二写脉冲 使得所述存储器件从高阻态转变为非易失性低阻态， 实现了长时存储功能。
作为本发明的一个实施例， 上述方法还包括：
通过控制所述第一电极层与所述第二电极层之间的电压为多个相隔第 一间隔时间的第一写脉冲， 使得所述存储器件从高阻态转变为易失性低阻 态， 并经过遗忘时间后所述存储器件从所述易失性低阻态恢复到所述高阻 态， 实现了短时存储功能；
通过控制所述第一电极层与所述第二电极层之间的电压为多个相隔第 二间隔时间的第一写脉冲， 使得所述存储器件从高阻态转变为非易失性低 阻态， 实现了长时存储功能； 其中， 第二间隔时间小于所述第一间隔时间。 作为本发明的一个实施例， 上述方法还包括：
通过控制所述第一电极层与所述第二电极层之间的电压为复位脉冲， 使得所述存储器件从易失性低阻态或非易失性低阻态恢复到高阻态， 实现 了复位功能。
图 6示出根据本发明的流程图， 在短时与长时存储器件中， 实现短时 记忆、 长时记忆和存储信息擦除功能。
当短时与长时存储器件初始处于 OFF态， 输入一个第一写脉冲、 或多 个相隔第一间隔时间的第一写脉冲后， 存储器件转变成易失性低阻态； 输 入一个第二写脉冲、 或多个相隔第二间隔时间的第一写脉冲后， 存储器件 转变成非易失性低阻态。
当短时与长时存储器件初始处于易失性低阻态， 不输入信号， 经过一 段时间， 器件转变成 OFF态， 或输入一个复位脉冲， 转变成 OFF态； 输入 多个相隔第二间隔时间的第一写脉冲、 或一个第二写脉冲后， 存储器件转 变成非易失性低阻态。
当短时与长时存储器件初始处于非易失性低阻态， 输入复位脉冲信号， 器件转变成 OFF态。
在本发明实施例中， 其它结构的器件（如 T型结构、 I型结构或金字塔 型结构）， 其它材料的第一电极， 包括钛钨 （TiW) 和钽 （Ta) 等惰性导电 金属， 其它材料的第二电极， 包括铜 （Cu) 等活泼导电金属， 其它材料的 硫系化合物功能材料， 包括包括锗 （Ge)、 锑 （Sb)、 碲 （Te) 锡、 硒和铋 (Bi) 等其中两种或两种以上的合金， 如 GeTe、 Ge2Sb2Te5、 Sb2Te3、 BiTe 和 AglnSbTe等，也能实现如上短时与长时存储的功能，在此不再一一详述。
本发明提供的短时与长时存储器件及存储方法均能同时模拟人脑的短 时记忆功能、 长时记忆功能和记忆消除功能。
本领域的技术人员容易理解， 以上所述仅为本发明的较佳实施例而已， 并不用以限制本发明， 凡在本发明的精神和原则之内所作的任何修改、 等 同替换和改进等， 均应包含在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种短时与长时存储器件， 其特征在于， 包括第一电极层、 与所述 第一电极层连接的功能材料层， 与所述功能材料层连接的第二电极层； 所 述第一电极层的材料为惰性导电金属， 所述第二电极层的材料为活泼导电 金属， 所述功能材料层的材料为硫系化合物。
2、 如权利要求 1所述的存储器件， 其特征在于， 所述第一电极层用于 接收外部的脉冲信号， 所述第二电极层用于接收外部的脉冲信号； 当施加 在所述第一电极层与所述第二电极层之间的电压为第一写脉冲时， 所述存 储器件从高阻态转变为易失性低阻态， 经过遗忘时间后所述存储器件从所 述易失性低阻态恢复到所述高阻态， 实现短时存储功能； 当施加在所述第 一电极层与所述第二电极层之间的电压为第二写脉冲， 所述存储器件从高 阻态转变为非易失性低阻态， 实现长时存储功能。
3、 如权利要求 2所述的存储器件， 其特征在于， 所述第一电极层用于 接收外部的脉冲信号， 所述第二电极层用于接收外部的脉冲信号； 当施加 在所述第一电极层与所述第二电极层之间的电压为多个相隔第一间隔时间 的第一写脉冲， 所述存储器件从高阻态转变为易失性低阻态， 经过遗忘时 间后所述存储器件从所述易失性低阻态恢复到所述高阻态， 实现短时存储 功能； 当施加在所述第一电极层与所述第二电极层之间的电压为多个相隔 第二间隔时间的第一写脉冲， 所述存储器件从高阻态转变为非易失性低阻 态， 实现长时存储功能； 所述第二间隔时间小于所述第一间隔时间。
4、 如权利要求 2或 3所述的存储器件， 其特征在于， 所述第一电极层 用于接收外部的脉冲信号， 所述第二电极层用于接收外部的脉冲信号； 当 施加在所述第一电极层与所述第二电极层之间的电压为复位脉冲， 所述存 储器件从易失性低阻态或非易失性低阻态恢复到高阻态， 实现复位功能。
5、 如权利要求 2-4任一项所述的存储器件， 其特征在于， 所述第一写 脉冲的电压幅值大于第一电压阈值且小于第二电压阈值； 所述第二写脉冲 的电压幅值大于所述第二电压阈值； 所述第一间隔时间大于时间阈值； 所 述第二间隔时间小于时间阈值。
6、 如权利要求 5所述的存储器件， 其特征在于， 所述第一电压阈值的 取值范围为 0.5~1.5V， 所述第二电压阈值的取值范围为 1.6~3V， 所述时间 阈值的取值范围为 lms~168h。
7、 如权利要求 1-6任一项所述的存储器件， 其特征在于， 所述第一电 极层、 所述功能材料层和所述第二电极层构成三明治叠层结构、 T型结构、 I型结构或金字塔型结构。
8、 如权利要求 1所述的存储器件， 其特征在于， 所述第一电极层的材 料为铂、 钛钨或钽。
9、 如权利要求 1所述的存储器件， 其特征在于， 所述功能材料层的材 料为由锗、 锑、 碲、 锡、 硒和铋中任意两种或两种以上的元素构成的合金。
10、 如权利要求 1 所述的存储器件， 其特征在于， 所述第二电极层的 材料为银或铜。
11、 一种短时与长时存储方法， 其特征在于， 包括下述步骤： 在第一电极层和第二电极层上施加脉冲信号；
通过控制所述第一电极层与所述第二电极层之间的电压为第一写脉冲 使得存储器件从高阻态转变为易失性低阻态， 并经过遗忘时间后所述存储 器件从所述易失性低阻态恢复到所述高阻态， 实现了短时存储功能；
通过控制所述第一电极层与所述第二电极层之间的电压为第二写脉冲 使得所述存储器件从高阻态转变为非易失性低阻态， 实现了长时存储功能。
12、 如权利要求 11所述的存储方法， 其特征在于， 所述方法还包括下 述步骤：
通过控制所述第一电极层与所述第二电极层之间的电压为多个相隔第 一间隔时间的第一写脉冲， 使得所述存储器件从高阻态转变为易失性低阻 态， 并经过遗忘时间后所述存储器件从所述易失性低阻态恢复到所述高阻 态， 实现了短时存储功能；
通过控制所述第一电极层与所述第二电极层之间的电压为多个相隔第 二间隔时间的第一写脉冲， 使得所述存储器件从高阻态转变为非易失性低 阻态， 实现了长时存储功能；
所述第二间隔时间小于所述第一间隔时间。
13、 如权利要求 11或 12所述的存储方法， 其特征在于， 所述方法还 包括下述步骤：
通过控制所述第一电极层与所述第二电极层之间的电压为复位脉冲， 使得所述存储器件从易失性低阻态或非易失性低阻态恢复到高阻态， 实现 了复位功能。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005010869A2 (en) * 2003-07-30 2005-02-03 M-Systems Flash Disk Pioneers Ltd. Method of archiving data
CN101006515A (zh) * 2004-08-17 2007-07-25 斯班逊有限公司 具有可变数据保持时间的聚合物存储器
CN101958399A (zh) * 2009-07-15 2011-01-26 旺宏电子股份有限公司 相变存储装置及其制造方法
CN102610750A (zh) * 2011-01-19 2012-07-25 旺宏电子股份有限公司 四元素镓碲锑为基的相变化材料及存储装置
US20120326111A1 (en) * 2011-06-23 2012-12-27 Macronix International Co., Ltd. Ge-RICH GST-212 PHASE CHANGE MEMORY MATERIALS

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9792985B2 (en) * 2011-07-22 2017-10-17 Virginia Tech Intellectual Properties, Inc. Resistive volatile/non-volatile floating electrode logic/memory cell
KR20130060065A (ko) * 2011-11-29 2013-06-07 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 이의 제조 방법
US9048415B2 (en) * 2012-01-11 2015-06-02 Micron Technology, Inc. Memory cells including top electrodes comprising metal silicide, apparatuses including such cells, and related methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005010869A2 (en) * 2003-07-30 2005-02-03 M-Systems Flash Disk Pioneers Ltd. Method of archiving data
CN101006515A (zh) * 2004-08-17 2007-07-25 斯班逊有限公司 具有可变数据保持时间的聚合物存储器
CN101958399A (zh) * 2009-07-15 2011-01-26 旺宏电子股份有限公司 相变存储装置及其制造方法
CN102610750A (zh) * 2011-01-19 2012-07-25 旺宏电子股份有限公司 四元素镓碲锑为基的相变化材料及存储装置
US20120326111A1 (en) * 2011-06-23 2012-12-27 Macronix International Co., Ltd. Ge-RICH GST-212 PHASE CHANGE MEMORY MATERIALS

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