Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
  • H01L29/151—Compositional structures
  • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
  • H01L29/155—Comprising only semiconductor materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
  • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
  • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
  • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
  • H01L29/7785—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

• Embodiments of the present invention generally relate to a thin film semiconductor having multiple semiconductor layers that are designed to make mobile electrons or holes move in a confined area formed along the interface between layers. The confinement can be thus be utilized to increase the Hall mobility of the semiconductor.
• TFTs thin film transistors
• LCDs liquid crystal active matrix displays
• OLEDs organic light emitting diodes
• TFTs TFTs for addressing the activity of the displays.
• One of the applications for the semiconductor is for the thin-film transistor traditionally used for displays.
• the current driven through the TFTs i.e., the on-current
• the channel material often referred to as the active material, semiconductor material or semiconductor active material
• the turn-on voltage is determined by the accumulation of the carrier in the channel area of the semiconductor layer which could change as the shift of the fixed charge in the semiconductor material or the charge trapping in interfaces and the threshold voltage shifts after bias temperature stress or current temperature stress.
• Silicon as the semiconductor material, has its limitations. Amorphous silicon has a low mobility. Polycrystalline silicon, while having a higher mobility than amorphous silicon, but is expensive to produce and necessitates an annealing process. [0005] Therefore, there is a need in the art for a TFT formed of a semiconductor material that has high mobility, yet can be produced at a low cost.
• the present invention generally relates to a thin film semiconductor device having multiple semiconductor layers.
• the layers can be tailored such that the Fermi level and the charge neutrality level are different in the layers.
• the electron trapping location can be selected so that the thin film semiconductor device has high mobility. While description will be made with reference to a TFT, it is to be understood that the invention has broader utility, such as with any thin film semiconductor device.
• a thin film semiconductor device comprises a first semiconductor layer having a first Fermi level and a first charge neutrality level; a second semiconductor layer having a second Fermi level different than the first Fermi level and a second charge neutrality level that is different than the first charge neutrality level; and a third semiconductor layer having a third Fermi level equal to the first Fermi level and a third charge neutrality level equal to the first charge neutrality level.
• Figure 1 is a cross-sectional schematic view of a PVD chamber according to one embodiment of the invention.
• Figures 2A-2C are schematic cross-sectional views of a TFT 200 at various stages of production.
• Figure 3 is a schematic illustration of the energy band diagram for three semiconductor layers where the Fermi and charge neutrality levels are different according to one embodiment.
• Figure 4 is a schematic illustration of the energy band diagram for three semiconductor layers where the Fermi and charge neutrality levels are different according to another embodiment.
• Figure 5 is a schematic illustration of the energy band diagram for three semiconductor layers where the Fermi and charge neutrality levels are different according to another embodiment.
• Figure 6 is a schematic illustration of the energy band diagram for three semiconductor layers of where the Fermi and charge neutrality levels are different according to another embodiment.
• the present invention generally relates to a thin film semiconductor device having multiple semiconductor layers.
• the layers can be tailored such that the Fermi level and the charge neutrality level are different in the layers.
• the electron trapping location can be selected so that the thin film semiconductor device has high mobility. While description will be made with reference to a TFT, it is to be understood that the invention has broader utility, such as with any thin film semiconductor device.
• the invention is illustratively described and may be used in a PVD chamber for processing large area substrates, such as a 4300 PVD chamber, available from AKT , a subsidiary of Applied Materials, Inc., Santa Clara, California.
• a 4300 PVD chamber available from AKT , a subsidiary of Applied Materials, Inc., Santa Clara, California.
• the sputtering target may have utility in other system configurations, including those systems configured to process large area round substrates and those systems produced by other manufacturers.
• FIG. 1 is a cross-sectional schematic view of a PVD chamber 100 according to one embodiment of the invention.
• the chamber 100 may be evacuated by a vacuum pump 1 14.
• a substrate 102 may be disposed opposite a target 104.
• the substrate may be disposed on a susceptor 106 within the chamber 100.
• the susceptor 106 may be elevated and lowered as shown by arrows "A" by an actuator 1 12.
• the susceptor 106 may be elevated to raise the substrate 102 to a processing position and lowered so that the substrate 102 may be removed from the chamber 100.
• Lift pins 108 elevate the substrate 102 above the susceptor 106 when the susceptor 106 is in the lowered position.
• Grounding straps 1 10 may ground the susceptor 106 during processing.
• the susceptor 106 may be raised during processing to aid in uniform deposition.
• the target 104 may comprise one or more targets 104.
• the target 104 may be bonded to a backing plate 1 16 by a bonding layer.
• cooling channels may be present in the backing plate 1 16.
• One or more magnetrons 1 18 may be disposed behind the backing plate 1 16. The magnetrons 1 18 may scan across the backing plate 1 16 in a linear movement or in a two dimensional path.
• the walls of the chamber may be shielded from deposition by a dark space shield 120 and a chamber shield 122.
• an anode 124 may be placed between the target 104 and the substrate
• the anode 124 may be bead blasted stainless steel coated with arc sprayed aluminum. In one embodiment, one end of the anode
• the anode 124 may be mounted to the chamber wall by a bracket 130.
• the anode 124 provides a charge in opposition to the target 104 so that charged ions will be attracted thereto rather than to the chamber walls which are typically at ground potential.
• the plasma may be more uniform, which may aid in the deposition.
• One or more gas introduction tubes 126 may also span the distance across the chamber 100 between the target 104 and the substrate 102.
• the gas introduction tubes 126 may introduce sputtering gases such as inert gases including argon as well as reactive gases such as oxygen, nitrogen, etc.
• the gases may be provided to the gas introduction tubes 126 from a gas panel 132 that may introduce one or more gases such as argon, oxygen, and nitrogen.
• the gas introduction tubes 126 may be disposed between the substrate 102 and the target 104 at a location below the one or more anodes 124.
• the anodes 124 may shield the gas introduction tubes 126 from deposition during processing. Shielding the gas introduction tubes 126 with the anodes 124 may reduce the amount of deposition that may cover or clog the gas outlets.
• the gas introduction tubes 126 may be coupled with the anodes 124 by one or more couplers 128.
• FIGS 2A-2C are schematic cross-sectional views of a TFT 200 at various stages of production.
• a gate electrode 204 is formed over a substrate 202.
• Suitable materials that may be utilized for the substrate 202 include, but not limited to, silicon, germanium, silicon- germanium, soda lime glass, glass, semiconductor, plastic, steel or stainless steel substrates.
• Suitable materials that may be utilized for the gate electrode 204 include, but are not limited to, chromium, copper, aluminum, tantalum, titanium, molybdenum, and combinations thereof, or transparent conductive oxides (TCO) such as indium tin oxide (ITO) or fluorine doped zinc oxide (ZnO:F) which are commonly used as transparent electrodes.
• TCO transparent conductive oxides
• ITO indium tin oxide
• ZnO:F fluorine doped zinc oxide
• the gate electrode 204 may be deposited by suitable deposition techniques such as PVD, MOCVD, a spin-on process and printing processes. The gate electrode 204 may be patterned using an etching process. [0023] Over the gate electrode 204, a gate dielectric layer 206 may be deposited. Suitable materials that may be used for the gate dielectric layer 206 include silicon dioxide, silicon oxynitride, silicon nitride, aluminum oxide or combinations thereof. The gate dielectric layer 206 may be deposited by suitable deposition techniques including plasma enhanced chemical vapor deposition (PECVD).
• PECVD plasma enhanced chemical vapor deposition
• Multiple semiconductor layers 208A-208C can be used then formed over the gate dielectric layer 206 as shown in Figure 2B as one type of thin film transistor.
• the semiconductor layers 208A-208C are oftentimes referred to as the channel layer, the active layer or the semiconductor active layer.
• the source electrode 210 and the drain electrode 212 are formed over the semiconductor layers 208A-208C.
• the exposed portion of the semiconductor layers 208A-208C between the source and drain electrodes 210, 212 is referred to as the active channel 214.
• Suitable materials for the source and drain electrodes 210, 212 include chromium, copper, aluminum, tantalum, titanium, molybdenum, and combinations thereof, or TCOs mentioned above.
• the source and drain electrodes 210, 212 may be formed by suitable deposition techniques, such as PVD followed by patterning through etching.
• the semiconductor layers 208A-208C may comprise oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, cadmium, indium, tin, and combinations thereof.
• the semiconductor layers 208A-208C may comprise oxygen, nitrogen, and one or more elements having a filled s orbital and a filled d orbital.
• the semiconductor layers 208A-208C may comprise oxygen, nitrogen, and one or more elements having a filled f orbital.
• the semiconductor layers 208A-208C may comprise oxygen, nitrogen, and one or more divalent elements.
• the semiconductor layers 208A-208C may comprise oxygen, nitrogen, and one or more trivalent elements.
• the semiconductor layers 208A-208C may comprise oxygen, nitrogen, and one or more tetravalent elements.
• the semiconductor layers 208A-208C may also comprise a dopant. Suitable dopants that may be used include Al, Sn, Ga, Ca, Si, Ti, Cu, Ge, In, Ni, Mn, Cr, V, Mg, Si x N y , Al x O y , and SiC.
• the dopant may also be a non- metallic species such as H, S, C, etc.
• the dopant comprises aluminum.
• the dopant comprises tin.
• Examples of semiconductor layers 208A-208C include the following: ZnO x N y , SnO x N y , lnO x N y , CdO x N y , GaO x N y , ZnSnO x N y , ZnlnO x N y , ZnCdO x N y , ZnGaO x N y , SnlnO x N y , SnCdO x N y , SnGaO x N y , lnCdO x N y , lnGaO x N y , CdGaO x N y , ZnSnlnO x N y , ZnSnCdO x N y , ZnSnGaO x N y , ZnlnCdO x N y , ZnlnGaO x N y
• Examples of semiconductor layer 208A-208C include the following doped materials: ZnO x N y :AI, ZnO x N y :Sn, SnO x N y :AI, lnO x N y :AI, lnO x N y :Sn, CdO x N y :AI, CdO x N y :Sn, GaO x N y :AI, GaO x N y :Sn, ZnSnO x N y :AI, ZnlnO x N y :AI, ZnlnO x N y :Sn, ZnCdO x N y :AI, ZnCdO x N y :Sn, ZnGaO x N y :AI, ZnGaO x N y :Sn, SnlnO x N y :AI, SnCdO x N y
• the semiconductor layers 208A-208C may be deposited by sputtering.
• the sputtering target comprises the metal such as zinc, gallium, tin, cadmium, indium, or combinations thereof.
• the sputtering target may additionally comprise a dopant.
• Oxygen containing gas and nitrogen containing gas are introduced into the chamber to deposit the semiconductor layers 208A-208C by reactive sputtering.
• the nitrogen containing gas comprises N 2 .
• the nitrogen containing gas comprises N 2 O, NH 3 , or combinations thereof.
• the oxygen containing gas comprises O2.
• the oxygen containing gas comprises N 2 O.
• the nitrogen of the nitrogen containing gas and the oxygen of the oxygen containing gas react with the metal from the sputtering target to form a semiconductor material comprising metal, oxygen, nitrogen, and optionally a dopant on the substrate.
• the nitrogen containing gas and the oxygen containing gas are separate gases.
• the nitrogen containing gas and the oxygen containing gas comprise the same gas. Additional additives such as B 2 H 6 , CO2, CO, CH 4 , and combinations thereof may also be provided to the chamber during the sputtering.
• the semiconductor layers 208A-208C may comprise multi-component metal oxides (i.e., multi-cation metal oxides such as an IGZO) single cation metal oxides such (i.e., zinc oxide), or multi-anion compounds that contain at least two anions and single cation system.
• the cations may be N, O, S, P, C, F, I, As, Se, and so on.
• the semiconductor layers 208A-208C may be selected from other semiconductor material such as metal oxides or metal nitrides.
• Each semiconductor layer 208A-208C may be different.
• the first semiconductor layer 208A and the third semiconductor layer 208C may be substantially identical while the second semiconductor layer 208B is different therefrom.
• the layers may be different in composition for example. Having different semiconductor layers 208A-208C leads to higher mobility. Higher mobility can be achieved with grapheme and other layered semiconductor material. However, by using quantum confinement through a combination of oxynitride semiconductors and metal oxide semiconductors with different bandgap, carrier concentration or Fermi level, mobility of greater than 100 can be achieved.
• Quantum wells are known using an AIGaAs/GaAs structure.
• creating a heterojunction of two different metal oxynitrides or metal nitrides or metal oxides or a metal oxynitride and other semiconductor material can produce a quantum well.
• high mobility can be achieved that will lead to achievement of high mobility TFTs and other thin film electronics.
• the film from the metal oxynitride can have one quantum well or more to form a superlattice.
• Each semiconductor layer 208A-208C will have various properties that contribute to the interaction with the respective other layers.
• Each semiconductor layer 208A-208C will have an energy level of vacuum (Ev), an energy level at the conduction band bottom (ECB), a charge neutrality level (ECNL), a Fermi level (EF), and an energy level at the valance band top (EVB).
• Ev energy level of vacuum
• ECB energy level at the conduction band bottom
• ECNL charge neutrality level
• EF Fermi level
• EVB energy level at the valance band top
• the location of the quantum well can be preselected.
• the quantum well can be formed to make the mobile electrons moving along a confinement around the interface of the layers.
• the quantum well can be formed to push the electrons in the second semiconductor layer 208B.
• the electronic confinement is achieved through abrupt composition changes of different films that are in contact. The confinement is created by barriers formed when the charge transfer takes place across the interfaces due to Fermi level differences and charge neutrality level differences.
• FIG 3 is a schematic illustration of the energy band diagram for three semiconductor layers of a TFT where the Fermi and charge neutrality levels are different according to one embodiment.
• the first semiconductor layer 208A has a semiconductor electron affinity X1 , Fermi level Y1 and a charge neutrality level Z1 .
• the second semiconductor layer 208B has a semiconductor electron affinity X2, Fermi level Y2 and a charge neutrality level Z2.
• the third semiconductor layer 208C has a semiconductor electron affinity X3, Fermi level Y3 and a charge neutrality level Z3.
• the first and third semiconductor layers 208A, 208C have substantially identical semiconductor electron affinity, Fermi levels and charge neutrality levels.
• the Fermi level of the second semiconductor layer 208B is lower than the Fermi level of both the first and third semiconductor layers 208A, 208C. As such the electrons are pushed from the first and third semiconductor layers 208A, 208C to the second semiconductor layer 208B.
• the charge neutrality level of the second semiconductor layer 208B is higher than the charge neutrality level of the first and third semiconductor layers 208A, 208C. Therefore, electrons are pushed from the second semiconductor layer 208B to the first and third semiconductor layers 208A, 208C.
• a positive dipole is present that is enhanced by the charge neutrality level.
• the positive dipole means that electrons get confined in the second semiconductor layer 208B.
• FIG 4 is a schematic illustration of the energy band diagram for three semiconductor layers of a TFT where the Fermi and charge neutrality levels are different according to another embodiment.
• the first and third semiconductor layers 208A, 208C have substantially identical semiconductor electron affinity, Fermi levels and charge neutrality levels.
• the Fermi level of the second semiconductor layer 208B is lower than the Fermi level of both the first and third semiconductor layers 208A, 208C.
• the charge neutrality level of the second semiconductor layer 208B is lower than the charge neutrality level of the first and third semiconductor layers 208A, 208C.
• FIG. 5 is a schematic illustration of the energy band diagram for three semiconductor layers of a TFT where the Fermi and charge neutrality levels are different according to another embodiment.
• the first and third semiconductor layers 208A, 208C have substantially identical semiconductor electron affinity, Fermi levels and charge neutrality levels.
• the Fermi level of the second semiconductor layer 208B is higher than the Fermi level of both the first and third semiconductor layers 208A, 208C. As such the electrons are pushed from the second semiconductor layer 208B to the first and third semiconductor layers 208A, 208C.
• the charge neutrality level of the second semiconductor layer 208B is lower than the charge neutrality level of the first and third semiconductor layers 208A, 208C.
• FIG. 6 is a schematic illustration of the energy band diagram for three semiconductor layers of a TFT where the Fermi and charge neutrality levels are different according to another embodiment.
• the first and third semiconductor layers 208A, 208C have substantially identical semiconductor electron affinity, Fermi levels and charge neutrality levels.
• the Fermi level of the second semiconductor layer 208B is higher than the Fermi level of both the first and third semiconductor layers 208A, 208C.
• the charge neutrality level of the second semiconductor layer 208B is higher than the charge neutrality level of the first and third semiconductor layers 208A, 208C.
• the semiconductor layers 208A-208C can be tailored to place a quantum well at a desired location such that the quantum well confines electrons in either the second semiconductor layer 208B or the first and third semiconductor layers 208A, 208C.
• the different Fermi and charge neutrality levels can be accomplished based upon deposition conditions or material.
• the semiconductor layers 208A- 208C may comprise the same semiconductor materials that are formed under different deposition conditions.
• all of the semiconductor layers 208A-208C may comprise zinc oxynitride, however, the layers may be deposited under different conditions such that the second semiconductor layer 208B has different Fermi and charge neutrality levels as compared to the first and third semiconductor layers 208A, 208C.
• the semiconductor layers 208A-208C may comprise different materials entirely.
• the second semiconductor layer 208B may comprise zinc oxynitride while the first and third semiconductor layers 208A, 208C comprise zinc oxide.
• the location of the quantum well, and the depth of the quantum well can affect the mobility. Therefore, by using a multi layer semiconductor active channel and tailoring the materials and deposition conditions, the mobility of the TFT can be increased.

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