WO2014101861A1

WO2014101861A1 - Mutual-capacitance detection circuit and mutual-capacitance detection array

Info

Publication number: WO2014101861A1
Application number: PCT/CN2013/090848
Authority: WO
Inventors: Long DING; Jie Zhang; Yun Yang
Original assignee: Shenzhen Byd Auto R&D Company Limited; Byd Company Limited
Priority date: 2012-12-30
Filing date: 2013-12-30
Publication date: 2014-07-03
Also published as: CN103914189A; CN103914189B

Abstract

A mutual-capacitance detection circuit and a mutual-capacitance detection array are provided. The mutual-capacitance detection circuit comprises: a first capacitor; a limited current transmitting module, connected with an input end of the first capacitor and configured to control the first capacitor to output a current signal having an alternate positive and negative amplitude; and a receiving module, connected with an output end of the first capacitor and configured to output a digital level pulse signal according to the amplitude of the current signal output from the first capacitor, in which a width of the digital level pulse signal is positively related with the amplitude of the current signal output from the first capacitor.

Description

MUTUAL-CAPACITANCE DETECTION CIRCUIT AND

MUTUAL -CAPACITANCE DETECTION ARRAY

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to, and benefits of Chinese Patent Application Serial No.

201210591341.1, filed with the State Intellectual Property Office of P. R. C. on December 30, 2012, the entire content of which is incorporated herein by reference.

FIELD

Exemplary embodiments of the present disclosure relate generally to a circuit design field, and more particularly to a mutual-capacitance detection circuit used in a capacitive touch device.

BACKGROUND

Among existing capacitive touch detection devices, a mutual-capacitance detection device can realize real multi-touch, but the mutual-capacitance detection has some problems such as a low signal-to-noise ratio (SNR) of an input signal and a high system cost when compared with the self-capacitance detection.

Fig. 1 shows a conventional mutual-capacitance detection circuit, which calculates a coordinate of each touch point by detecting an electric quantity variation of a two-dimensional capacitor of the touch screen when fingers touch the screen. The working principle of the mutual-capacitance detection circuit shown in Fig. 1 is as follows. When the screen is not touched, an external excitation voltage VIN jumps from a voltage VI to another voltage V2, and by controlling a switch SI to turn on or off, an input differential voltage of an operational amplifier 11 is driven by a negative feedback of a capacitor CI to transfer charges of a detected capacitor Cx to the capacitor CI . Thus, an output voltage of the operational amplifier 11 is VOUTl=VCOM- Cx*(V2- VI)/ CI . When the screen is touched, the detected capacitance is set to be Cx', and the external excitation voltage VFN jumps from the voltage VI to another voltage V2. Thus, the output voltage of the operational amplifier 11 is VOUT2=VCOM- Cx'*(V2- VI)/ CI . By comparing the output voltages of the operational amplifier 11 when the screen is touched and not touched, a difference between the two output voltages is obtained. Then, the difference is compared with a preset reference value to judge whether the difference is larger than the reference value, and if yes, it is determined that a touching occurs. Such a method detects the value of the mutual-capacitance by a voltage transmission way, which requires a voltage amplifier with a high precision.

Furthermore, when fingers touch the screen, a common-mode noise leakage path is caused since the human body is not common-grounded with the detection circuit. Therefore, the capacitive detection is not good at restraining the common-mode noise since the capacitive detection itself belongs to an open-type detection (not based on a same ground reference). When fingers touch the screen, the self-capacitance variation caused by the fact that fingers get close to the detection sensor is generally 10 to 100 times of the mutual-capacitance variation, the common-mode noise is leaked by this self-capacitance coupling, and the input SNR (signal to noise ratio) is easily reduced to a range from 1/1 to 1/10 when the amplifier has a large common-mode noise. Moreover, the use of stylus worsens the input SNR and is stricter on detecting the SNR. In order to solve the above problems, methods such as reducing the common-mode noise of the amplifier and performing ASP (Analog Signal Process) or DSP (Digital Signal Process) by the detection chip itself may be used. However, a system cost is increased when using these methods.

SUMMARY

Embodiments of the present disclosure seek to solve at least one of the problems existing in the related art to at least some extent.

According to embodiments of a first aspect of the present disclosure, a mutual-capacitance detection circuit is provided. The mutual-capacitance detection circuit comprises: a first capacitor; a limited current transmitting module, connected with an input end of the first capacitor and configured to control the first capacitor to output a current signal having an alternate positive and negative amplitude; and a receiving module, connected with an output end of the first capacitor and configured to output a digital level pulse signal according to the amplitude of the current signal output from the first capacitor, in which a width of the digital level pulse signal is positively related with the amplitude of the current signal output from the first capacitor.

According to embodiments of the present disclosure, the limited current transmitting module is used, thus reducing the amplitude and the bandwidth of the current signal. Compared with voltage transmission method, the method of transmitting the capacitance of the first capacitor by current transmission method according to the present disclosure reduces the requirement for the bandwidth of the amplifier, which is more easily to realize.

In some embodiments of the present disclosure, the receiving module comprises a current transmitting module and an ADC (analog to digital converting) module. The current transmitting module is connected with the output end of the first capacitor and configured to rectify the current signal output from the first capacitor. The ADC module comprises: a second capacitor, in which a first electrode plate of the second capacitor is connected with the current transmitting module; a comparator, connected with the first electrode plate of the second capacitor and configured to output a turnover level according to a voltage of the first electrode plate of the second capacitor; and a counter connected with the comparator and configured to count a width of the turnover level and output a digital level pulse signal with the width corresponding to the width of the turnover level.

According to some embodiments of the present disclosure, the ADC module adopts a delta-sigma regulator structure to integrate the ASP and ADC together. Thus, an influence of the common-mode noise is restrained, a high SNR is output in a case of low input SNR, a detection sensitivity is enhanced, and a size and power consumption are reduced, thus reducing a cost of the mutual-capacitance detection circuit.

In some embodiments of the present disclosure, the limited current transmitting module comprises a voltage amplifier, an input end of the voltage amplifier is connected with a working power supply via a first switch and via a first pull-up current source connected in series with the first switch, the input end of the voltage amplifier is also grounded via a second switch and via a first pull-down current source connected in series with the second switch, and an output end of the voltage amplifier is connected with the input end thereof via a third capacitor, in which the first switch is controlled to turn on or off by a first clock signal, the second switch is controlled to turn on or off by a second clock signal, and an effective level of the first clock signal is non-overlapped with an effective level of the second clock signal.

According to some embodiments of the present disclosure, by providing the first pull-up current source and the first pull-down current source, and providing the first clock signal and the second clock signal non-overlapped with each other, the voltage amplifier can be controlled to output a voltage having an alternate high and low level, thus making the first capacitor output the current signal having the alternate positive and negative amplitude.

In some embodiments of the present disclosure, the limited current transmitting module comprises an in-phase current amplifier and an inverting current amplifier, an input end of the in-phase current amplifier is connected with the output end of the first capacitor via a third switch, an input end of the inverting current amplifier is connected with the output end of the first capacitor via a fourth switch, and an output end of the in-phase current amplifier and the output end of the inverting current amplifier are connected with the first electrode plate of the second capacitor, in which the third switch is controlled to turn on or off by the first clock signal, and the fourth switch is controlled to turn on or off by the second clock signal.

According to some embodiments of the present disclosure, the current transmitting module uses the in-phase current amplifier and the inverting current amplifier to rectify and filter the current signal having the alternate positive and negative amplitude output from the first capacitor under a control of the first clock signal and the second clock signal.

In some embodiments of the present disclosure, the current transmitting module further comprises a first current amplifier, an input end of the first current amplifier is connected with the output end of the first capacitor, and an output end of the first current amplifier is connected with the third switch and the fourth switch respectively.

According to some embodiments of the present disclosure, the current transmitting module uses the first current amplifier to amplify the current signal output from the first capacitor, thus increasing the amplitude of the current signal.

In some embodiments of the present disclosure, the first electrode plate of the second capacitor is connected with a positive end of the comparator, a second electrode plate of the second capacitor is grounded, a negative end of the comparator is connected with a reference voltage, an output end of the comparator is connected with an input end of the counter, the first electrode plate of the second capacitor is grounded via a fifth switch connected in series with a second pull-down current source, and the fifth switch is controlled to turn on or off by a signal output from the output end of the comparator.

According to some embodiments of the present disclosure, the ADC module adopts a delta-sigma regulator structure, in which the second capacitor is used as an integrator, the comparator is used as a 1 bit quantizer, and the 1 bit data stream is converted by the counter into a multi-bit data stream for use in following elements. According to embodiments of the present disclosure, ASP and ADC are integrated together. Thus, the influence of the common-mode noise is restrained, the high SNR is output in a case of a low input SNR, the detection sensitivity is enhanced, and the size and power consumption are reduced.

In some embodiments of the present disclosure, the ADC module further comprises a trigger, an input end of the trigger is connected with the output end of the comparator, an output end of the trigger is connected with the input end of the counter, and the fifth switch is controlled to turn on or off by a signal output from the comparator.

According to some embodiments of the present disclosure, the ADC module adopts the trigger to filter noises in the signal output from the comparator.

In some embodiments of the present disclosure, the current transmitting module further comprises a third pull-down current source, a first end of the third pull-down current source is connected with the output end of the first capacitor, the output end of the first current amplifier or the first electrode plate of the second capacitor, and a second end of the second pull-down current source is grounded.

According to some embodiments of the present disclosure, by providing the third pull-down current source, a certain amount of charges are leaked, thus avoiding a saturation of the integrating circuit formed by the second capacitor.

In some embodiments of the present disclosure, the current transmitting module further comprises a second pull-up current source and a fourth pull-down current source connected with the output end of the first capacitor, the output end of the first current amplifier or the first electrode plate of the second capacitor and controlled to turn on or off by one of the first clock signal and the second clock signal.

According to some embodiments of the present disclosure, by providing the second pull-up current source and the fourth pull-down current source controlled to turn on or off by one of the first clock signal and the second clock signal, a certain current is poured into or pumped out from the circuit, thus counteracting the offset current and avoiding the saturation of the integrating circuit.

In some embodiments of the present disclosure, the mutual-capacitance detection circuit further comprises a DAC (digital to analog converting) module connected with the limited current transmitting module and the receiving module respectively and configured to control the first pull-up current source, the first pull-down current source, the third pull-down current resource, the second pull-up current source, the fourth pull-down current source and the third capacitor.

According to some embodiments of the present disclosure, by providing the DAC module, the output current of the first capacitor can be adjusted by adjusting the first pull-up current source, the first pull-down current source and the third capacitor, the charge leaking ability of the third pull-down current source can be adjusted by adjusting the current value of the third pull-down current source, and the ability of the second pull-up current source and the fourth pull-down current source to counteract the offset current can be adjusted by adjusting the current values of the second pull-up current source and the fourth pull-down current source.

Additional aspects and advantages of embodiments of present disclosure will be given in part in the following descriptions, become apparent in part from the following descriptions, or be learned from the practice of the embodiments of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and advantages of embodiments of the present disclosure will become apparent and more readily appreciated from the following descriptions made with reference to the drawings, in which:

Fig. 1 is a conventional schematic diagram of a mutual-capacitance detection circuit ;

Fig. 2 is a schematic diagram of a mutual-capacitance detection circuit according to an embodiment of the present disclosure; and

Fig. 3 is a schematic diagram showing waveforms at different nodes of a mutual-capacitance detection circuit according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

Reference will be made in detail to embodiments of the present disclosure. The embodiments described herein with reference to drawings are explanatory, illustrative, and used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure. The same or similar elements and the elements having same or similar functions are denoted by like reference numerals throughout the descriptions.

It is to be understood that phraseology and terminology used herein with reference to device or element orientation (such as, terms like "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside") are only used to simplify description of the present disclosure, and do not indicate or imply that the device or element referred to must have or operated in a particular orientation. They cannot be seen as limits to the present disclosure.

In the description, terms concerning attachments, coupling and the like, such as "connected" and "interconnected", refer to a relationship in which structures are secured or attached to one another through mechanical or electrical connection, or directly or indirectly through intervening structures, unless expressly described otherwise. Specific implications of the above phraseology and terminology may be understood by those skilled in the art according to specific situations.

According to embodiments of the present disclosure, a mutual-capacitance detection circuit is provided. As shown in Fig. 2, the mutual-capacitance detection circuit comprises a capacitor 109, a limited current transmitting module 200 connected with an input end of the capacitor 109 and a receiving module 201 connected with an output end of the capacitor 109. The capacitor 109 is a mutual capacitor. The limited current transmitting module 200 is configured to control the capacitor 109 to output a current signal having an alternate positive and negative amplitude. The capacitor 109 transmits the current signal to the receiving module 201. The receiving module 201 is configured to output a digital level pulse signal according to the amplitude of the current signal output from the capacitor 109. A width of the digital level pulse signal is positively related with the amplitude of the current signal output from the capacitor 109, i.e. the width of the digital level pulse signal changes in proportion to the amplitude of the current signal output from the capacitor 109. In other words, the width of the digital level pulse signal increases with the increasing of the amplitude of the current signal output from the capacitor 109, and the width of the digital level pulse signal decreases with the decreasing of the amplitude of the current signal output from the capacitor 109.

In this embodiment, as shown in Figs. 2 and 3, the limited current transmitting module 200 is connected with the input end of the capacitor 109 and configured to control the capacitor 109 to output the current signal having the alternate positive and negative amplitude under the control of a clock signal Φ1 and a clock signal Φ2. An effective level of the clock signal Φ1 is non-overlapped with the effective level of the clock signal Φ2. The effective level herein refers to a high level of the clock signal Φ1 or the clock signal Φ2. The receiving module 201 comprises a current transmitting module and an ADC (analog to digital converting) module. The ADC module comprises a capacitor 115, a comparator 116 and a counter 120. The current transmitting module is connected with the output end of the first capacitor 109 and configured to rectify the current signal output from the capacitor 109 and to transmit the rectified current signal to a first electrode plate of the capacitor 115, such that a voltage of the capacitor 115 is changed and a capacitance of the capacitor 109 can be determined by detecting the voltage of the capacitor 115. In this embodiment, the comparator 116 is connected with the first electrode plate of the capacitor 115 and configured to output a turnover level according to the voltage of the first electrode plate of the capacitor 115. In other words, the output level of the comparator 116 turns over according to the voltage of the capacitor 115. The counter 120 counts a width of the turnover level and outputs the digital level pulse signal with the width corresponding to the width of the turnover level.

In this embodiment, as shown in Fig. 2, the limited current transmitting module 200 comprises a voltage amplifier 108. An input end of the voltage amplifier 108 is connected with a working power supply 101 via a switch 103 and via a pull-up current source 102 connected in series with the switch 103. The input end of the voltage amplifier 108 is grounded via a switch 104 and via a pull-down current source 105 connected in series with the switch 104. The switch 103 is controlled to turn on or off by the clock signal Φ1, and the switch 104 is controlled to turn on or off by the clock signal Φ2. Specifically, when the clock signal Φ1 is at a high level, the switch 103 is turned on and the pull-up current source 102 is connected into the circuit; when the clock signal Φ1 is at a low level, the switch 103 is turned off and the pull-up current source 102 is disconnected from the circuit; when the clock signal Φ2 is at a high level, the switch 104 is turned on and the pull-down current source 105 is connected into the circuit; when the clock signal Φ2 is at a low level, the switch 104 is turned off and the pull-down current source 105 is disconnected from the circuit. As shown in Fig. 3, the effective level of the clock signal Φ1 is non-overlapped with the effective level of the clock signal Φ2, and the pull-up current source 102 and the pull-down current source 105 are alternately connected into the circuit. An output end of the voltage amplifier 108 is connected with its input end via a capacitance 107. It should be noted that the voltage amplifier 108 is operating in the linear region, and the two input ends of the voltage amplifier 108 are virtual-shorted. Thus, Fig. 3 only schematically shows one input end.

As shown in Fig. 2, the voltage amplifier 108 is a voltage-mode amplifier with a voltage-current negative feedback. Based on the differential characteristic of the capacitor I=d(V) / d(t)*C (in which I is the current flowing through the capacitor and C is the capacitance of the capacitor), the current flowing through the capacitor with a fixed capacitance C can be limited by only limiting the value of d(V) / d(t). Therefore, in this embodiment, in order to control the capacitor 109 to output the current signal having the stable and alternate positive and negative amplitude (as I (123) shown in Fig. 3), a slope of the input voltage of the capacitor 109 (i.e., the output voltage of the voltage amplifier 108) is required to be stable, i.e., the input current of the capacitor 107 is required to be stable. In this embodiment, the capacitor 107 is provided with a stable current via the pull-up current source 102 and the pull-down current source 105, and the slope of the output voltage is adjusted to be equal to that of the input voltage via the voltage-current negative feedback. As shown in Fig. 3, the slope of V(121) (the voltage waveform at the input end of the voltage amplifier 108) is equal to that of V(122) (the voltage waveform at the input end of the capacitor 109, i.e., the waveform of the voltage output from the voltage amplifier 108), thus limiting the output voltage of the voltage amplifier 108. The slope of the input voltage of the voltage amplifier 108 is equal to a value obtained from dividing the current of the pull-up current source 102 or the current of the pull-down current source 105 by the capacitance of the capacitor 107. In this embodiment, the mutual-capacitance detection circuit may further comprise a DAC (Digital to analog converting) module. The DAC module is connected with the limited current transmitting module 200 and the receiving module 201 respectively, and configured to control the pull-up current source 102, the first pull-down current source 105 and the third capacitor 107. The DAC module adjusts the slope of the output voltage of the voltage amplifier 108 by adjusting the current of the pull-up current source 102, the current of the pull-down current source 105 and the capacitance of the capacitor 107, thus adjusting the value of the output current of the capacitor 109. In the present disclosure, the direction of the current output from the capacitor 109 is adjusted by periodically connecting the pull-up current source 102 or the pull-down current source 105 into the circuit.

According to embodiments of the present disclosure, the limited current transmitting module 200 is used, thus reducing the amplitude and the bandwidth of the current signal and reducing requirements for the amplitude and the bandwidth of the following current amplifiers. Furthermore, by providing the pull-up current source 102 and the pull-down current source 105 and providing the clock signal Φ1 and the clock signal Φ2 non-overlapped with each other, the voltage amplifier 108 is controlled to output the voltage having an alternate high and low level, thus making the capacitor 109 output the current signal having the alternate positive and negative amplitude.

As shown in Fig. 2, in this embodiment, the current transmitting module comprises an in-phase current amplifier 113 and an inverting current amplifier 114. An input end of the in-phase current amplifier 113 is connected with the output end of the capacitor 109 via a switch 111. The switch 111 is controlled to turn on or off by the clock signal Φ1. An input end of the inverting current amplifier 114 is connected with the output end of the capacitor 109 via a switch 112. The switch 112 is controlled to turn on or off by the clock signal Φ2. An output end of the in-phase current amplifier 113 and the output end of the inverting current amplifier 114 are connected with the first electric plate of the capacitor 115.

In this embodiment, the current transmitting module further comprises a current amplifier 110, an input end of the current amplifier 110 is connected with the output end of the capacitor 109, and an output end of the current amplifier 110 is connected with the switch 111 and the switch 112 respectively. According to embodiments of the present disclosure, the current transmitting module adopts the current amplifier 110 to amplify the current signal output from the capacitor 109, thus increasing the amplitude of the current signal.

According to embodiments of the present disclosure, the current transmitting module transmits the current signal by the current amplifier 110, the in-phase current amplifier 113 and the inverting current amplifier 114. In some embodiments of the present disclosure, the current amplifier 110, the in-phase current amplifier 113 and the inverting current amplifier 114 may be designed as controllable gain current amplifiers to realize a compatibility with large input capacitance range. In another embodiment of the present disclosure, a trimming circuit may be provided to counteract the offset current. Specifically, a pull-up current source 131 and a pull-down current source 132 connected with the output end 123 of the first capacitor 109, the output end 124 of the first current amplifier 110 or the input node 125 of the second capacitor 115 are provided. The pull-up current source 131 and the pull-down current source 132 are controlled by one of the clock signal Φ1 and the clock signal Φ2. According to one embodiment of the present disclosure, by providing the pull-up current source 131 and the pull-down current source 132, a certain current can be poured into or pumped out from the circuit, thus counteracting the offset current. The current values and current directions of the pull-up current source 131 and the pull-down current source 132 can be adjusted, and the current values can be controlled by the DAC module. The DAC module adjusts the current values of the pull-up current source 131 and the pull-down current source 132, thus adjusting the ability of the pull-up current source 131 and the pull-down current source 132 to counteract the offset current. The current directions of the pull-up current source 131 and the pull-down current source 132 can be controlled by the clock signal Φ1 and the clock signal Φ2. Specifically, one of the pull-up current source 131 and the pull-down current source 132 is connected into the circuit during an effective period of the first clock signal Φ1 or the second clock signal Φ2. According to one embodiment of the present disclosure, the current transmitting module uses the in-phase current amplifier 113 and the inverting current amplifier 114 to rectify and filter the current signal having the alternate positive and negative amplitude output from the capacitor 109 under the control of the clock signal Φ1 and the clock signal Φ2, and obtain the processed current as 1(125) shown in Fig. 3. According to one embodiment of the present disclosure, by providing the pull-up current source 131 and the pull-down current source 132 controlled to turn on or off by one of the first clock signal Φ1 and the second clock signal Φ2, a certain current is poured into or pumped out from the circuit, thus counteracting the offset current and avoiding a saturation of the integrating circuit.

As shown in Fig. 2, in this embodiment, the ADC module comprises the capacitor 115, the counter 120 and the comparator 116. The first electrode plate of the capacitor 115 is connected with a positive end of the comparator 116, and a second electrode plate of the capacitor 115 is grounded. A negative end of the comparator 106 is connected with a reference voltage, and an output end of the comparator 116 is connected with an input end of the counter 120. The first electrode plate of the capacitor 115 is also grounded via a switch 118 and a pull-down current source 119 connected in series with the switch 118. The switch 118 is controlled to turn on or off by the signal output from the output end of the comparator 116.

In other embodiments of the present disclosure, the ADC module may further comprise a trigger 117. An input end of the trigger 117 is connected with the output end of the comparator 116, and an output end of the trigger 117 is connected with the input end of the counter 120. The trigger 117 may be any trigger having a function of filtering noises, including but not limited to a D-trigger or a schmitt trigger. In this embodiment, the trigger 117 is the D-trigger, and the switch 118 is controlled to turn on or off by the signal output from the output end of the trigger 117.

According to embodiments of the present disclosure, a delta-sigma regulator structure is used to realize the ADC module, in which the capacitor 115 is used as an integrator, the comparator 116 is used as a lbit quantizer, and the counter 120 is used to convert the lbit data stream into a multi-bit data stream for use in the following circuit. According to embodiments of the present disclosure, by integrating ASP and ADC together, the influence of the common-mode noise can be restrained, a high SNR can be output in a case of low input SNR, a detection sensitivity can be enhanced, and a size and power consumption can be reduced.

In some embodiments of the present disclosure, in order to avoid the saturation of the integrating circuit, a compensating circuit may be provided, specifically, an additional pull-down current source (not shown in drawings) may be provided. A first end of the additional pull-down current source may be connected with the output end of the capacitor 109, the output end of the current amplifier 110 or the first electrode plate of the capacitor 115, and a second end of the additional pull-down current source may be grounded.

According to some embodiments of the present disclosure, a certain amount of charges are leaked by the additional pull-down current source, thus avoiding the saturation of the integrating circuit formed by the capacitor 115.

In this embodiment of the present disclosure, the DAC module may further control the additional pull-down current source, the pull-up current source 131, the third pull-down current source 132 and the capacitor 107. Thus, the ability of the additional pull-down current source to leak charges can be adjusted by adjusting the current value of the additional pull-down current source, and the ability of the pull-up current source 131 and the pull-down current source 132 to counteract the offset current can be adjusted by adjusting the current values of the pull-up current source 131 and the pull-down current source 132.

In another embodiment of the present disclosure, the trimming circuit may be integrated together with the compensating circuit. In other words, the pull-up current source 131 and the pull-down current source 132 can realize both the trimming function and the compensation function. The detailed design can adopt the structure of the trimming circuit, and is omitted herein.

According to embodiments of the present disclosure, the limited current transmitting module

200 is used, thus reducing the amplitude and the bandwidth of the current signal. Compared with the voltage transmission method, the method of transmitting the capacitance of the capacitor 109 by current reduces the requirement for the bandwidth of the amplifier, which is more easily to realize. According to embodiments of the present disclosure, the ADC module adopts the delta-sigma regulator structure to integrate ASP and ADC together, thus restraining the influence of the common-mode noise, outputting the high SNR in a case of low input SNR, enhancing the detection sensitivity, and reducing the cost and the power consumption.

According to the embodiments of the present disclosure, the working process of the mutual-capacitance detection circuit is described as follows. Firstly, the mutual-capacitance detection circuit receives a detection starting signal to initiate the circuit. Then, the switch 103 and the switch 104 are turned on alternately under the control of the clock signal Φ1 and the clock signal Φ2, such that the pull-up current source 102 and the pull-down current source 105 are alternately connected with the input end of the voltage amplifier 108 (the current of the pull-up current source 102 is 1(102) as shown in Fig. 3, and the current of the pull-down current source 105 is 1(105) as shown in Fig. 3). Since the switch 103 and the switch 104 are turned on alternately, the voltage amplifier 108 outputs the voltage having the alternate high and low level. The slope of the output voltage of the voltage amplifier 108 is kept as a stable value by the voltage-current negative feedback of the capacitor 107. The slope of the output voltage of the voltage amplifier 108 is I(102)/C(107) when the switch 103 is turned on, the slope of the output voltage of the voltage amplifier 108 is I(105)/C(107) when the switch 104 is turned on. Thus, the capacitor 109 outputs the current signal having the alternate positive and negative amplitude based on the differential character of the capacitor 109, as 1(123) shown in Fig. 3.

During the effective period of the clock signal Φ1, the switch 111 is turned on, and the current at the output end of the current amplifier 110 is transferred to the first electrode plate of the capacitor 115 via the in-phase current amplifier 113. During the effective period of the clock signal Φ2, the switch 112 is turned on, and the current at the output end of the current amplifier 110 is transferred to the first electrode plate of the capacitor 115 via the inverting current amplifier 114. Thus, one positive and negative transmitting cycle is completed, and the current signal is rectified and filtered. In another embodiment of the present disclosure, a plurality of positive and negative transmitting cycles may be repeated several times to improve a filtering efficiency.

Furthermore, after the mutual-capacitance detection circuit receives the detection starting signal, the counter 120 is enabled, and the voltage of the capacitor 115 increases once a certain current flows into the first electrode plate (i.e., the positive electrode plate) of the capacitor 115, which causes the output level of the comparator 116 to turn over. The turnover level is transferred to the switch 1 18 and the counter 120 after being filtered by the D trigger 117, and the switch 118 is controlled to turn on by the level output from the D trigger 117. Then, the pull-down current source 119 discharges the upper electrode plate of the capacitor 115, so that the output level of the comparator 116 turns back to the state before turning over. The counter 120 counts the width of this turnover level. The waveform at the input end of the counter is as V(126) shown in Fig. 3.

In a condition that other parameters keep constant, the larger the capacitance of the capacitor 109 is, the larger the current output from the capacitor 109 is, the more the charges accumulated on the first electrode plate of the capacitor 115 are, the longer it takes the charges on the first electrode plate of the capacitor 115 to discharge via the pull-down current source 119, and the wider the turnover level output from the comparator 116 is. The pulse width of the turnover level has a fixed functional relationship with the capacitance of the capacitor 109, and the functional relationship is a monotonous positive correlation. The capacitance variation of the capacitor 109 may be obtained by processing the output value of the counter 120.

According to embodiments of the present disclosure, the current transmission method instead of the voltage transmission method is adopted, thus avoiding the strict requirement on the operational amplifier. Moreover, the limited current transmitting module is used, thus limiting the amplitude and the bandwidth of the current signal and reducing the requirements for the amplitude and the bandwidth of the current amplifier. Furthermore, the ADC module adopts the delta-sigma regulator structure to integrate ASP and ADC together, thus restraining the high noise without the need of more DSP designs, and reducing the size and power consumption.

According to embodiments of the present disclosure, a mutual-capacitance detection array is further provided. The mutual-capacitance detection array comprises a plurality of capacitors, one or more limited current transmitting modules 200 and a plurality of receiving modules 201. The one or more limited current transmitting modules 200 are connected with input ends of the plurality of capacitors respectively and configured to control each of the plurality of capacitors to output a current signal having an alternate positive and negative amplitude. The plurality of receiving modules 201 are connected with the plurality of capacitors respectively. Each receiving module 201 is configured to output a digital level pulse signal according to the amplitude of the current signal output from the connected capacitor, and a width of the digital level pulse signal is monotonicaHy and positively correlated with the amplitude of the current signal output from the connected capacitor.

In one embodiment, the mutual-capacitance detection array may comprise one limited current transmitting module 200 and N receiving modules 201 connected with the one limited current transmitting module 200, so that the N receiving modules 201 operate in parallel to detect a plurality of channels simultaneously. In another embodiment, the mutual-capacitance detection array may comprise N limited current transmitting modules 200 and N receiving modules 201, and each limited current transmitting module 200 is connected with one receiving module 201 independently. The N limited current transmitting modules 200 work in different time intervals and the N receiving modules 201 work in parallel or in different time intervals, thus realizing an array detection and improving the detection efficiency.

According to embodiments of the present disclosure, the mutual-capacitance detection array can restrain the influence of the common-mode noise, has a relatively high output SNR in a case of low input SNR, has a relatively high detection sensitivity and a relatively low cost. Moreover, the mutual-capacitance detection array according to the present disclosure can prevent a "jump-point" when the touch screen is touched, thus improving the touching effect of the touch screen. Furthermore, the limited current transmitting modules work in different time intervals and the receiving modules work in a parallel or in different time intervals, thus enhancing the detection efficiency.

Reference throughout this specification to "an embodiment," "some embodiments," "one embodiment", "another example," "an example," "a specific example," or "some examples," means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. Thus, the appearances of the phrases such as "in some embodiments," "in one embodiment", "in an embodiment", "in another example," "in an example," "in a specific example," or "in some examples," in various places throughout this specification are not necessarily referring to the same embodiment or example of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that the above embodiments cannot be construed to limit the present disclosure, and changes, alternatives, and modifications can be made in the embodiments without departing from spirit, principles and scope of the present disclosure.

Claims

WHAT IS CLAIMED IS:

1. A mutual-capacitance detection circuit, comprising:

a first capacitor;

a limited current transmitting module, connected with an input end of the first capacitor and configured to control the first capacitor to output a current signal having an alternate positive and negative amplitude; and

a receiving module, connected with an output end of the first capacitor and configured to output a digital level pulse signal according to the amplitude of the current signal output from the first capacitor, wherein a width of the digital level pulse signal is positively related with the amplitude of the current signal output from the first capacitor.

2. The mutual-capacitance detection circuit according to claim 1, wherein the limited current transmitting module comprises a voltage amplifier, an input end of the voltage amplifier is connected with a working power supply via a first switch and via a first pull-up current source connected in series with the first switch, the input end of the voltage amplifier is grounded via a second switch and via a first pull-down current source connected in series with the second switch, and an output end of the voltage amplifier is connected with the input end thereof via a third capacitor, in which the first switch is controlled to turn on or off by a first clock signal, the second switch is controlled to turn on or off by a second clock signal, and an effective level of the first clock signal is non-overlapped with an effective level of the second clock signal.

3. The mutual-capacitance detection circuit according to claim 1 or 2, wherein the receiving module comprises:

a current transmitting module, connected with the output end of the first capacitor and configured to rectify the current signal output from the first capacitor; and

an analog to digital converting module, comprising:

a second capacitor, in which a first electrode plate of the second capacitor is connected with the current transmitting module;

a comparator, connected with the first electrode plate of the second capacitor and configured to output a turnover level according to a voltage of the first electrode plate of the second capacitor; and

a counter connected with the comparator and configured to count a width of the turnover level and output the digital level pulse signal with the width corresponding to the width of the turnover level.

4. The mutual-capacitance detection circuit according to any of claims 1-3, wherein the limited current transmitting module comprises an in-phase current amplifier and an inverting current amplifier, an input end of the in-phase current amplifier is connected with the output end of the first capacitor via a third switch, an input end of the inverting current amplifier is connected with the output end of the first capacitor via a fourth switch, and an output end of the in-phase current amplifier and the output end of the inverting current amplifier are connected with the first electrode plate of the second capacitor, in which the third switch is controlled to turn on or off by the first clock signal, and the fourth switch is controlled to turn on or off by the second clock signal.

5. The mutual-capacitance detection circuit according to any of claims 1-4, wherein the current transmitting module further comprises a first current amplifier, an input end of the first current amplifier is connected with the output end of the first capacitor, and an output end of the first current amplifier is connected with the third switch and the fourth switch respectively.

6. The mutual-capacitance detection circuit according to any of claims 1-3, wherein the first electrode plate of the second capacitor is connected with a positive end of the comparator, a second electrode plate of the second capacitor is grounded, a negative end of the comparator is connected with a reference voltage, an output end of the comparator is connected with an input end of the counter, the first electrode plate of the second capacitor is grounded via a fifth switch connected in series with a second pull-down current source, and the fifth switch is controlled to turn on or off by a signal output from the output end of the comparator.

7. The mutual-capacitance detection circuit according to any of claims 1-6, wherein the analog to digital converting module further comprises a trigger, an input end of the trigger is connected with the output end of the comparator, and an output end of the trigger is connected with the input end of the counter.

8. The mutual-capacitance detection circuit according to any of claims 1-5, wherein the current transmitting module further comprises a third pull-down current source, a first end of the third pull-down current source is connected with the output end of the first capacitor, the output end of the first current amplifier or the first electrode plate of the second capacitor, and a second end of the second pull-down current source is grounded.

9. The mutual-capacitance detection circuit according to any of claims 1-5, wherein the current transmitting module further comprises a second pull-up current source and a fourth pull-down current source connected with the output end of the first capacitor, the output end of the first current amplifier or the first electrode plate of the second capacitor and controlled to turn on or off by one of the first clock signal and the second clock signal.

10. The mutual-capacitance detection circuit according to claim 1, further comprising:

a digital to analog converting module connected with the limited current transmitting module and the receiving module respectively and configured to control the first pull-up current source, the first pull-down current source, the third pull-down current resource, the second pull-up current source, the fourth pull-down current source and the third capacitor.

11. A mutual-capacitance detection array, comprising:

a plurality of capacitors;

one or more limited current transmitting modules connected with input ends of the plurality of capacitors respectively and configured to control each of the plurality of capacitors to output a current signal having an alternate positive and negative amplitude; and

a plurality of receiving modules, wherein the plurality of receiving modules are connected with the plurality of capacitors respectively and each receiving module is configured to output a digital level pulse signal according to the amplitude of the current signal output from the connected capacitor, and a width of the digital level pulse signal is positively related with the amplitude of the current signal output from the connected capacitor.