WO2014086010A1 - 超结的制作方法 - Google Patents

超结的制作方法 Download PDF

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Publication number
WO2014086010A1
WO2014086010A1 PCT/CN2012/085993 CN2012085993W WO2014086010A1 WO 2014086010 A1 WO2014086010 A1 WO 2014086010A1 CN 2012085993 W CN2012085993 W CN 2012085993W WO 2014086010 A1 WO2014086010 A1 WO 2014086010A1
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Prior art keywords
heavily doped
type heavily
type
doped substrate
doped region
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PCT/CN2012/085993
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English (en)
French (fr)
Inventor
张文亮
朱阳军
卢烁今
田晓丽
褚为利
Original Assignee
中国科学院微电子研究所
江苏中科君芯科技有限公司
江苏物联网研究发展中心
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Application filed by 中国科学院微电子研究所, 江苏中科君芯科技有限公司, 江苏物联网研究发展中心 filed Critical 中国科学院微电子研究所
Priority to PCT/CN2012/085993 priority Critical patent/WO2014086010A1/zh
Priority to EP12889660.2A priority patent/EP2930739B1/en
Publication of WO2014086010A1 publication Critical patent/WO2014086010A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/261—Bombardment with radiation to produce a nuclear reaction transmuting chemical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and more particularly to a method of fabricating a super junction.
  • the essence of the superjunction theory lies in the principle of charge balance, or the principle of charge complementation.
  • the conventional low-doped withstand voltage structure is replaced by alternately arranged pn structures (as shown in Figure 1).
  • Conventional superjunction manufacturing processes are ion implantation or grooved filling.
  • the ion implantation process mainly includes two schemes of high energy ion implantation and multiple epitaxy multiple implantation; the groove filling process mainly includes two schemes: deep reaction ion etching and multiple epitaxial multiple groove refilling.
  • the above method of making a super junction is very complicated, so the super junction is relatively expensive to manufacture.
  • an embodiment of the present invention provides a method for fabricating a super-junction, which reduces the manufacturing cost by the process of forming a super-junction.
  • the method of making the super knot includes:
  • the lightly doped substrate is made of silicon, or silicon carbide, or gallium arsenide, or indium antimonide.
  • the process of forming a P-type heavily doped region in the lightly doped substrate by using a enthalpy doping process comprising: providing a photon source to form a high energy photon beam; using the high energy photon beam to the lightly doped lining The bottom is subjected to particle irradiation to initiate a nuclear reaction, and a P-type heavily doped region is formed in the lightly doped substrate.
  • the photon source is an electron linear accelerator photon source, and the high energy photon beam has an energy of 17.5 MeV to 22.5 MeV, and the first mask is made of a high energy photon absorber.
  • the process of forming an N-type heavily doped region in the lightly doped substrate using a enthalpy doping process comprising: providing a neutron source to form a neutron beam; and using the neutron beam to lightly dope
  • the substrate is subjected to particle irradiation to initiate a nuclear reaction, and an N-type heavily doped region is formed in the lightly doped substrate.
  • the neutron source is a radioisotope neutron source, or an accelerator neutron source, or a reactor neutron source, and the second mask is made of a neutron absorber.
  • a method of making a super knot comprising:
  • the first type of heavily doped substrate is P-type heavily doped
  • the second type of heavily doped region is N-type heavily doped.
  • the first type of heavily doped substrate is made of silicon, or silicon carbide, or gallium arsenide, or indium antimonide.
  • the process of forming a second type of heavily doped region in the first type of heavily doped substrate using a enthalpy doping process comprising: providing a neutron source to form a neutron beam; using the neutron beam pair
  • the first type of heavily doped substrate is subjected to particle irradiation to initiate a nuclear reaction, and a second type of heavily doped region is formed in the first type of heavily doped substrate.
  • the first type of heavily doped substrate is N-type heavily doped
  • the second type of heavily doped region is P-type heavily doped.
  • the first type of heavily doped substrate is made of silicon, or silicon carbide, or diamond, or germanium, or gallium arsenide, or indium antimonide.
  • the process of forming a second type of heavily doped region in the first type of heavily doped substrate using a enthalpy doping process comprising: providing a photon source to form a high energy photon Beaming the first type of heavily doped substrate with the high energy photon beam to initiate a nuclear reaction, forming a second type of heavily doped region in the first type of heavily doped substrate.
  • the first type of heavily doped substrate is made of germanium.
  • the process of forming a second type of heavily doped region in the first type of heavily doped substrate using a enthalpy doping process comprising: providing a neutron source to form a neutron beam; using the neutron beam pair
  • the first type of heavily doped substrate is subjected to particle irradiation to initiate a nuclear reaction, and a second type of heavily doped region is formed in the first type of heavily doped substrate.
  • a superjunction the superjunction being a superjunction produced by the method of any of the above.
  • a P-type heavily doped region and an N-type heavily doped region are formed in a lightly doped substrate by a enthalpy doping process, or a enthalpy doping process is used in the first type of heavy
  • a second type of heavily doped substrate is formed within the doped substrate. Since the enthalpy doping process is a doped region formed in the substrate by a nuclear reaction, that is, only superheating can be obtained by particle irradiation and annealing. In the prior art, it is formed by multiple epitaxy, multiple injection or multiple epitaxy, and multiple engraving. Therefore, compared with the prior art, the manufacturing method of the super-junction provided by the present application reduces the production cost and reduces the production cost.
  • Figure 1 is a schematic diagram of a conventional super junction
  • FIG. 2 is a flow chart of manufacturing a super junction according to an embodiment of the present invention.
  • FIG. 3 and FIG. 4 are schematic diagrams of a superjunction doping process according to another embodiment of the present invention.
  • FIG. 5 is a flow chart of another super junction process according to another embodiment of the present invention.
  • FIG. 6 is a schematic diagram of still another super-junction doping process according to another embodiment of the present invention.
  • the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • This embodiment discloses a method for fabricating a super junction, as shown in FIG. 2, including:
  • Step S11 providing a lightly doped substrate
  • the lightly doped substrate is an N-type lightly doped or P-type lightly doped or lightly doped substrate close to the intrinsic semiconductor, and the material is made of semiconductor
  • the device is made of silicon, or silicon carbide, or gallium arsenide, or indium antimonide.
  • Step S12 using a first mask having a P-type heavily doped region pattern as a mask, and forming a P-type heavily doped region in the lightly doped substrate by a enthalpy doping process.
  • Step S13 forming a N-type heavily doped region in the lightly doped substrate by using a enthalpy doping process using a second mask having an N-type heavily doped region pattern as a mask.
  • the P-type heavily doped region and the N-type heavily doped region are alternately arranged in the lightly doped substrate, and the front side of the P-type heavily doped region and the N-type heavily doped region are The front side of the lightly doped substrate is flush, and the back side of the P-type heavily doped region and the N-type heavily doped region are flush with the back side of the lightly doped substrate.
  • Step S14 annealing treatment to restore the electrical properties of the lightly doped substrate, wherein the annealing temperature of the annealing treatment is 800 ° C to 900 ° C.
  • the enthalpy doping process is a doped region formed in the substrate by a nuclear reaction, it is only necessary to obtain super-junction by particle irradiation and annealing. In the prior art, it is formed by multiple epitaxy, multiple injection or multiple epitaxy, and multiple engraving. Therefore, compared with the prior art, the production of the super junction provided by the present application is The method streamlines the production process and reduces production costs.
  • the particle beam used in the enthalpy doping process has a strong penetrating ability and thus can be applied to a thicker substrate, so that the super junction formed by the method of the present embodiment is suitable for all semiconductor devices of withstand voltage levels.
  • the path of the particles in the lightly doped substrate is almost straight, so that a uniform doping profile is formed in the lightly doped substrate, the doped regions are distinct, and the concentration can be precisely controlled.
  • step S12 and step S13 is interchangeable.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • This embodiment discloses another method for fabricating a super junction, including:
  • Step S21 providing a lightly doped substrate, the lightly doped substrate being N-type lightly doped or P-type lightly doped or lightly doped substrate close to the intrinsic semiconductor, and the material is made of semiconductor
  • the device is made of silicon, or silicon carbide, or gallium arsenide, or indium antimonide.
  • Step S22 forming a P-type heavily doped region in the lightly doped substrate, comprising: Step S221: Providing a photon source to form a high-energy photon beam.
  • the photon source described in this embodiment is preferably an electron linear accelerator photon source.
  • the resulting high energy photon beam has an energy of 17.5 MeV to 22.5 MeV.
  • the direction of photon motion in the photon beam generated by the photon source needs to be parallel to each other, i.e., a photon beam similar to parallel light (at least also having a certain degree of parallelism).
  • Step S222 Perform particle irradiation on the lightly doped substrate by using the high energy photon beam to initiate a nuclear reaction, and form a P-type heavily doped region in the lightly doped substrate.
  • the above method uses photon irradiation to dope the material. Since the high-energy electrons have a small attenuation coefficient of 4 in silicon, deep doping of the semiconductor can be achieved. Moreover, the distribution of the isotope atoms in the crystal is very uniform, so that the lightly doped substrate is irradiated with particles by the high-energy photon beam, and the doping formed by the enthalpy of the element is very uniform.
  • P-type impurities can be formed by initiating a nuclear reaction.
  • silicon 30 absorbs a photon and becomes silicon 27, and releases a neutron. After a half-life of 4.2 s, it releases a positron and turns into aluminum 27.
  • the specific nuclear reaction is:
  • the stable A1 produced by this reaction is the donor element that P-type silicon needs to be incorporated.
  • the photon energy in the high energy photon beam of this embodiment is 17.5 MeV ⁇ 22.5 MeV, preferably 20 MeV.
  • P-type impurities can also be formed by initiating a nuclear reaction after irradiation with a high-energy photon beam.
  • the nuclear reaction process of silicon in silicon carbide is the same as that of the above silicon.
  • P-type impurities can also be formed by initiating a nuclear reaction after irradiation with a high-energy photon beam.
  • the first mask used to form the P-type heavily doped region is made of a photon absorber to block unwanted particle ray. Photo.
  • the high-energy photon absorber comprises: a simple substance or a compound of a heavy metal element; and at least one of a titanate or a silane coupling agent, and other substances capable of effectively absorbing photons.
  • Step 23 forming an N-type heavily doped region in the lightly doped substrate, including:
  • Step S231 providing a neutron source to form a neutron beam. Since free neutrons are unstable, they can decay into protons emitting electrons and anti-electric neutrinos. The average lifetime is only 15 minutes and cannot be stored for a long time. Therefore, it needs to be supplied by appropriate sources.
  • the neutron source has the following three types:
  • Radioactive isotope neutron source comprises: ( ⁇ , ⁇ ) neutron source, which uses a nuclear reaction 9Be+a ⁇ 12C+n+5.701 MeV, and emits a radiant a-beam 238 Pu, 226 Ra or 241 Am with metal cerium powder. a certain proportion of uniformly mixed and pressed into a small cylinder and sealed in a metal shell; ( ⁇ , n ) neutron source, which uses gamma rays emitted from the nuclear reaction to generate neutrons, 24 Na-Be source, 124 Sb-Be source, etc.
  • the radioactive isotope neutron source has a small volume, and is easy to use.
  • the accelerator neutron source bombards an appropriate target nucleus by charged particles accelerated by an accelerator, and generates neutrons through a nuclear reaction.
  • the most common nuclear reactions are (d, n), (p, n) and ( ⁇ , ⁇ ), etc.
  • the intensity is much larger than that of the radioisotope neutron source, and single-energy neutrons can be obtained in the energy region of the ⁇ width.
  • the accelerator can be pulsed neutrons after pulse modulation.
  • the reactor neutron source generates a large number of neutrons using a nuclear fission reactor.
  • the reactor is the strongest source of thermal neutrons. By opening holes in the walls of the reactor, the neutrons can be extracted and the resulting neutron energy is continuously distributed, 4 ⁇ close to the Maxwell distribution. Take certain measures to obtain a neutron beam of various energies.
  • Step S232 Perform particle irradiation on the lightly doped substrate by using the neutron beam to initiate a nuclear reaction, and form a P-type heavily doped region in the lightly doped substrate.
  • the above method uses neutron irradiation to dope the material. Since the distribution of isotopic atoms in the crystal is very uniform, and the penetration depth of the neutrons in the semiconductor material is large (about 100 cm), the lightly doped substrate is subjected to particles by the neutron beam. Irradiation, the doping by the enthalpy of the elements is very uniform, which is useful for the fabrication of high power semiconductor devices and radiation detector devices.
  • an N-type impurity can be formed by initiating a nuclear reaction. That is, after the silicon 30 absorbs a neutron, it becomes silicon 31, and a photon is released, and after a half life of 2.6 h, an electron is released and becomes phosphorus 31.
  • the specific nuclear reaction is:
  • the stable P produced by this reaction is the donor element that N-type silicon needs to be incorporated.
  • the P concentration N D (unit: cm- 3 ) reached after irradiation can be calculated by the following formula:
  • the distribution of 3G Si in silicon is naturally uniform, so that the distribution of 31 P produced by the enthalpy is uniform, that is, the distribution of impurities in the N-type silicon is uniform.
  • a metal flux homogenizer can be used to obtain a flux neutron beam with a uniform flux distribution.
  • silicon carbide For lightly doped substrates made of silicon carbide, similar to silicon, after irradiation with neutron beams, silicon
  • N-type impurities can also be formed by initiating a nuclear reaction after irradiation with a neutron beam. Since the above-mentioned particle irradiation process is a partial enthalpy doping by using a neutron beam, the second mask used to form the N-type heavily doped region is made of a neutron absorber to block unwanted particle radiation. Photo.
  • an effective neutron absorber is a radioisotope that can generate a stable nucleus by absorbing a neutron.
  • ⁇ 135 half-life of about 9.1 hours
  • the ⁇ 135 can be fissioned in the nuclear reactor through the uranium 235, uranium 233 and ⁇ 239 nucleus, accompanied by the production of iodine 135.
  • the iodine 135 can decay rapidly, emitting a beta particle (high-energy electron) and producing ⁇ 135.
  • the neutron absorber may be at least one of the above isotopes.
  • neutron absorbers include the ⁇ 3 isotope, which absorbs neutrons to produce cesium (a heavier isotope of hydrogen); boron 10, which absorbs neutrons, produces lithium and ruthenium nucleus; ⁇ 149 is also a An effective neutron absorber that produces a stable isotope ⁇ 150 after neutron absorption.
  • neutron absorbers used in control rods in nuclear reactors include cadmium, lanthanum and rare earth metal lanthanum, which contain several isotopes, some of which are very efficient neutron absorbers.
  • Second mask version Moreover, by selecting a suitable material and a second mask which is of sufficient thickness, the neutron can be effectively absorbed to achieve the effect of the mask and achieve local doping.
  • Figures 3 and 4 show the specific process of the above doping.
  • a first mask 102 having a ⁇ -type heavily doped region pattern is overlaid on the lightly doped substrate 101 and aligned, and then perpendicular to the surface of the lightly doped substrate 101 through the incident direction.
  • the lightly doped substrate 101 is irradiated by the high energy photon beam.
  • the high energy photon beam is absorbed by the first mask 102 without being blocked by the first mask 102.
  • the high-energy photon beam can be directly injected into the interior of the lightly doped substrate 101, and a nuclear reaction occurs (for example, silicon germanium becomes aluminum) to obtain a germanium-type heavily doped region 10.
  • the lightly doped substrate 101 is covered with a second mask having a ⁇ -type heavily doped region pattern.
  • the film 103 is aligned and then irradiated to the lightly doped substrate 101 by a neutron beam perpendicular to the surface of the lightly doped substrate 101 in an incident direction, at a portion blocked by the second mask 103, The neutron beam is absorbed by the second mask 103, and the neutron beam can be directly injected into the lightly doped substrate 101 in a region that is not blocked by the second mask 103, and a nuclear reaction occurs (for example, silicon germanium becomes phosphorus). An N-type heavily doped region 11 is obtained.
  • the P-type heavily doped region 10 and the N-type heavily doped region 11 are alternately arranged in the lightly doped substrate 101, and the P-type heavily doped region 10 and the N-type heavily doped region 11 are The front surface is flush with the front surface of the lightly doped substrate 101, and the back surface of the P-type heavily doped region 10 and the N-type heavily doped region 11 is flush with the back surface of the lightly doped substrate 101.
  • Step S24 annealing treatment.
  • the above method causes many irradiation defects in the lightly doped substrate, the physical properties of the lightly doped substrate are significantly changed. Therefore, in order to restore the electrical properties of the lightly doped substrate, it is also necessary to anneal it, wherein the annealing temperature is preferably 800 ° C ⁇ 900 ° C.
  • a P-type heavily doped region and an N-type heavily doped region are formed in a lightly doped substrate by a enthalpy doping process. Since the enthalpy doping process is a doped region formed in the substrate by a nuclear reaction, that is, only superheating can be obtained by particle irradiation and annealing. In the prior art, it is formed by multiple epitaxy, multiple injection or multiple epitaxy, and multiple engraving. Therefore, compared with the prior art, the manufacturing method of the super-junction provided by the present application reduces the production cost and reduces the production cost.
  • the particle beam used in the enthalpy doping process has a strong penetrating ability and thus can be applied to a thicker substrate, so that the super junction formed by the method of the present embodiment is suitable for all semiconductor devices of withstand voltage levels.
  • the path of the particles in the lightly doped substrate is almost straight, so that a uniform doping profile is formed in the lightly doped substrate, the doped regions are distinct, and the concentration can be precisely controlled.
  • step S22 and step S23 is interchangeable.
  • Embodiment 3 discloses another method for fabricating a super junction. As shown in FIG. 5, the method includes the following steps: Step S31: providing a first type of heavily doped substrate, the first type of heavily doped substrate being N-type heavily doped A hetero- or P-type heavily doped substrate.
  • Step S32 using a third mask having a pattern of the heavily doped region of the second type as a mask, forming a second type of heavily doped region in the first type of heavily doped substrate by using a enthalpy doping process.
  • the region other than the second type heavily doped region is the first type heavily doped region.
  • the first type of heavily doped regions and the second type of heavily doped regions are alternately arranged.
  • Step S33 annealing processing to restore electrical properties of the first type of heavily doped substrate, wherein the annealing temperature of the annealing process is 800 ° C to 900 ° C.
  • This embodiment uses a enthalpy doping process to form a second type of heavily doped substrate in a first type of heavily doped substrate. Since the enthalpy doping process is a doped region formed in the substrate by a nuclear reaction, that is, only superheating can be obtained by particle irradiation and annealing. In the prior art, it is formed by multiple epitaxy, multiple injection or multiple epitaxy, and multiple engraving. Therefore, compared with the prior art, the method for manufacturing the super-junction provided by the present application reduces the production process and reduces the production cost.
  • the particle beam used in the enthalpy doping process has a strong penetrating ability and thus can be applied to a thicker substrate, so that the super junction formed by the method of the present embodiment is suitable for all semiconductor devices of withstand voltage levels.
  • the path of the particles in the lightly doped substrate is almost straight, so that a uniform doping profile is formed in the lightly doped substrate, the doped regions are distinct, and the concentration can be precisely controlled.
  • Embodiment 4 Further, compared with the above embodiment, the present embodiment further refines the manufacturing method of the super junction, which reduces the production cost.
  • Embodiment 4 :
  • This embodiment discloses another method for fabricating a super junction, including:
  • Step S41 providing a first type of heavily doped substrate, the first type of heavily doped substrate is P-type heavily doped, and the material is made of silicon, or silicon carbide, or gallium arsenide, which can be used for semiconductor device fabrication. , or materials such as indium telluride.
  • Step S42 forming a second type of heavily doped region in the first type of heavily doped substrate, and a region outside the second type of heavily doped region is a first type of heavily doped region. Wherein the second type of heavily doped region is N-type heavily doped, and the first type of heavily doped region is the same as the doping type of the first type of heavily doped substrate, so the first type is heavily The doped region is heavily doped with P-type.
  • Step S42 includes: Step S421: Providing a neutron source to form a neutron beam. Step S422, performing particle irradiation on the first type of heavily doped substrate by using the neutron beam to initiate a nuclear reaction, forming an N-type impurity in the first type of heavily doped substrate, and obtaining a second type of heavy Doped area. Since the above method uses local neutron irradiation to locally dope doping of the material, it is necessary to use a third mask having a pattern of the second type heavily doped region as a mask, and the third mask The material of the film is a neutron absorber.
  • Step S43 annealing processing to restore electrical properties of the first type of heavily doped substrate, wherein the annealing temperature of the annealing process is 800 ° C to 900 ° C.
  • the annealing temperature of the annealing process is 800 ° C to 900 ° C.
  • This embodiment discloses another method for fabricating a super junction, including:
  • Step S51 providing a first type of heavily doped substrate, the first type of heavily doped substrate is N-type heavily doped, and the material is made of silicon, or silicon carbide, or diamond, which can be used for semiconductor device fabrication, or Materials such as germanium, or gallium arsenide, or indium antimonide.
  • Step S52 forming a second type of heavily doped region in the first type of heavily doped substrate, and a region outside the second type of heavily doped region is a first type of heavily doped region.
  • the second type of heavily doped region is P-type heavily doped, and since the doping type of the first type heavily doped region is the same as that of the first type heavily doped substrate, the first type is heavily
  • the doped region is heavily doped with an N-type.
  • Step S52 includes: Step S521, providing a photon source to form a high-energy photon beam. Step S522, performing particle irradiation on the first type of heavily doped substrate by using the high-energy photon beam to initiate a nuclear reaction, forming a P-type impurity in the first type of heavily doped substrate, and obtaining a second type of heavy Doped area.
  • P-type impurities can also be formed by initiating a nuclear reaction after irradiation with a high-energy photon beam. That is, after carbon 12 absorbs a photon, it becomes boron 11 and releases a proton.
  • the specific nuclear reaction is:
  • carbon 12 absorbs a photon, it becomes carbon 11 and releases a proton, then carbon.
  • Figure 6 shows the specific process of the above doping.
  • a third mask 202 having a second type of heavily doped region pattern is overlaid on the first type heavily doped substrate 201 and aligned, and then perpendicular to the surface of the first type heavily doped substrate 201 by the incident direction
  • the neutron beam irradiates the light first type heavily doped substrate 201, and at the portion blocked by the third mask 203, the high energy photon beam is absorbed by the third mask 202 without being masked by the third mask.
  • the high-energy photon beam can be directly injected into the first type of heavily doped substrate 201, a nuclear reaction occurs (for example, carbon enthalpy becomes boron), a second type heavily doped region 21 is obtained, and the second Type heavy doping
  • the region outside the region 21 is the first type heavily doped region 20.
  • Step S53 annealing processing to restore the electrical properties of the first type of heavily doped substrate, wherein the annealing temperature of the annealing process is 800 ° C ⁇ 900 ° C.
  • the annealing temperature of the annealing process is 800 ° C ⁇ 900 ° C.
  • This embodiment discloses another method for fabricating a super junction, including:
  • Step S61 providing a first type of heavily doped substrate, the first type of heavily doped substrate is N-type heavily doped, and the material is made of germanium.
  • Step S62 forming a second type of heavily doped region in the first type of heavily doped substrate, and a region outside the second type of heavily doped region is a first type of heavily doped region.
  • the second type of heavily doped region is P-type heavily doped, and since the doping type of the first type heavily doped region is the same as that of the first type heavily doped substrate, the first type is heavily
  • the doped region is heavily doped with an N-type.
  • Step S62 includes: Step S621: Providing a neutron source to form a neutron beam. Step S622, performing particle irradiation on the first type of heavily doped substrate by using the neutron beam to initiate a nuclear reaction, forming a P-type impurity in the first type of heavily doped substrate, and obtaining a second type of heavy Doped area. Since the above method uses local neutron irradiation to locally dope doping of the material, it is necessary to use a third mask having a pattern of the second type heavily doped region as a mask, and the third mask The material of the film is a neutron absorber.
  • Annealing treatment to restore the electrical properties of the first type of heavily doped substrate wherein the annealing treatment has an annealing temperature of 800 ° C to 900 ° C.
  • Embodiment 6 This embodiment discloses a super junction formed by the method described in any of the above embodiments, that is, the super junction is formed by a enthalpy doping process.
  • the super junction formed by the method provided by this embodiment is applicable to all semiconductor devices with withstand voltage levels. Moreover, the doped regions of the super junction are distinct, the concentration can be precisely controlled, and have a uniform doping profile.
  • Example 7
  • This embodiment discloses a super junction semiconductor device in which the super junction is the super junction disclosed in the above embodiment.
  • the super junction can be implemented between the fabrication processes of other structures of the superjunction semiconductor device, so that the super junction and the other structures of the super junction semiconductor device share an annealing process to further compress the super junction semiconductor device Production, reducing production costs.
  • the method includes:
  • the region other than the heavily doped region is a first type of heavily doped region, wherein the first type of heavily doped region and the second type of heavily doped region are alternately arranged;
  • a positive structure such as a well region, an emitter region, a gate, and a front metal on the first type heavily doped layer formed with the first type heavily doped region and the second type heavily doped region, completing the super junction IGBT front structure Production
  • Annealing recovering the electrical properties of the first type of heavily doped layer, and activating dopant ions in the well region, the emitter region, and the like, wherein the annealing temperature of the annealing treatment is 800 ° C to 900 ° C;
  • the super junction semiconductor device may also be a semiconductor device such as a super junction VDMOS or a super junction PIN diode.
  • the irradiated particles in the various embodiments of the present application may also use other charged particles or uncharged particles to achieve the enthalpy doping.
  • the irradiation energy of the particles is at least capable of inducing a nuclear reaction, and the irradiation dose needs to be pre-calculated according to actual needs.
  • a superjunction can be formed by this method as long as the corresponding doping type can be formed, and the formed superjunction can also be used to fabricate any semiconductor device, which is not listed here.
  • the method of manufacturing the super junction provided by the present application can further improve the production efficiency.
  • the lightly doped substrate or the lightly doped substrate needs to be cooled by radiation for a certain period of time before being used as a non-radioactive material.

Abstract

提供了一种超结的制造方法，包括：提供一轻掺杂衬底（S11），采用嬗变掺杂工艺形成P型重掺杂区（S12）或N型重掺杂区（S13），退火处理（S14）；或提供第一类型重掺杂衬底，采用嬗变掺杂工艺形成第二类型重掺杂区，退火处理。由此，简化了制作流程，降低了生产成本。

Description

超结的制作方法
技术领域 本发明涉及半导体制造技术领域，更具体地说，涉及一种超结的制作方法。
背景技术
随着超结理论的提出， 采用超结的半导体器件的耐压水平也相应的提高 了。
其中， 所述超结理论的精髓在于电荷平衡原理， 或者说电荷互补原理。 是 将传统的低掺杂耐压结构用交替排列的 pn结构代替（如图 1所示）。 传统的超结制造工艺为离子注入或刻槽填充。其中离子注入工艺主要包括 了高能离子注入和多次外延多次注入两种方案；刻槽填充工艺主要包括了深反 应离子刻蚀和多次外延多次刻槽再填充两种方案。 以上制作超结的方法非常复杂， 所以超结制造成本较高。
发明内容
为解决上述技术问题， 本发明实施例提供了一种超结的制作方法， 以筒化 超结的制作工艺， 降低制作成本。 该超结的制作方法， 包括：
提供一轻掺杂衬底； 以具有 P型重掺杂区图形的第一掩膜版为掩膜，采用 嬗变掺杂工艺在所述轻掺杂衬底内形成 P型重掺杂区； 以具有 N型重掺杂区 图形的第二掩膜版为掩膜， 采用嬗变掺杂工艺在所述轻掺杂衬底内形成 N型 重掺杂区； 退火处理。
优选的， 所述轻掺杂衬底的制作材料为硅、 或碳化硅、 或砷化镓、 或锑化 铟。所述采用嬗变掺杂工艺在所述轻掺杂衬底内形成 P型重掺杂区的过程， 包 括： 提供光子源， 形成高能光子束； 利用所述高能光子束对所述轻掺杂衬底进 行粒子辐照， 引发核反应， 在所述轻掺杂衬底内形成 P型重掺杂区。 所述光子 源为电子线性加速器光子源， 所述高能光子束的能量为 17.5MeV~22.5MeV, 所述第一掩膜版的制作材料为高能光子吸收剂。所述采用嬗变掺杂工艺在所述 轻掺杂衬底内形成 N型重掺杂区的过程， 包括： 提供中子源， 形成中子束； 利用所述中子束对所述轻掺杂衬底进行粒子辐照， 引发核反应，在所述轻掺杂 衬底内形成 N型重掺杂区。 所述中子源为放射性同位素中子源、 或加速器中 子源、 或反应堆中子源， 所述第二掩膜版的制作材料为中子吸收剂。
一种超结的制作方法， 包括：
提供第一类型重掺杂衬底；以具有第二类型重掺杂区图形的第三掩膜版为 掩膜， 采用嬗变掺杂工艺在所述第一类型重掺杂衬底内形成第二类型重掺杂 区， 所述第二类型重掺杂区之外的区域为第一类型重掺杂区； 退火处理。
优选的，所述第一类型重掺杂衬底为 P型重掺杂，所述第二类型重掺杂区 为 N型重掺杂。 所述第一类型重掺杂衬底的制作材料为硅、 或碳化硅、 或砷 化镓、或锑化铟。所述采用嬗变掺杂工艺在所述第一类型重掺杂衬底内形成第 二类型重掺杂区的过程， 包括： 提供中子源， 形成中子束； 利用所述中子束对 所述第一类型重掺杂衬底进行粒子辐照， 引发核反应，在所述第一类型重掺杂 衬底内形成第二类型重掺杂区。
优选的， 所述第一类型重掺杂衬底为 N型重掺杂， 所述第二类型重掺杂 区为 P型重掺杂。 所述第一类型重掺杂衬底的制作材料为硅、 或碳化硅、 或金 刚石、 或锗、 或砷化镓、 或锑化铟。 所述采用嬗变掺杂工艺在所述第一类型重 掺杂衬底内形成第二类型重掺杂区的过程， 包括： 提供光子源， 形成高能光子 束； 利用所述高能光子束对所述第一类型重掺杂衬底进行粒子辐照， 引发核反 应， 在所述第一类型重掺杂衬底内形成第二类型重掺杂区。
优选的， 所述第一类型重掺杂衬底的制作材料为锗。所述采用嬗变掺杂工 艺在所述第一类型重掺杂衬底内形成第二类型重掺杂区的过程， 包括： 提供中 子源，形成中子束；利用所述中子束对所述第一类型重掺杂衬底进行粒子辐照， 引发核反应， 在所述第一类型重掺杂衬底内形成第二类型重掺杂区。
一种超结， 所述超结为采用上述任意一项所述方法制作的超结。
一种超结半导体器件， 所述超结半导体器件中的超结上述超结。 与现有技术相比， 上述技术方案具有以下优点：
本发明实施例所提供的技术方案，采用嬗变掺杂工艺在一轻掺杂衬底内形 成 P型重掺杂区和 N型重掺杂区， 或者， 采用嬗变掺杂工艺在第一类型重掺 杂衬底内形成第二类型重掺杂衬底。由于嬗变掺杂工艺是通过核反应在衬底内 形成的掺杂区， 即只需要通过粒子辐照和退火便可得到超结。 而现有技术中是 通过多次外延、 多次注入或多次外延、 多次刻槽形成的。 所以， 与现有技术相 比， 本申请所提供的超结的制作方法筒化了制作流程， 降低了生产成本。 附图说明
图 1为现有的超结示意图；
图 2为本发明实施例提供的一种超结的制作流程图；
图 3和图 4为本发明另一实施例提供的一种超结掺杂流程示意图;
图 5为本发明又一实施例提供的另一种超结制作流程图；
图 6为本发明又一实施例提供的又一种超结掺杂流程示意图。 具体实施方式 为使本发明的上述目的、特征和优点能够更为明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。
在以下描述中阐述了具体细节以便于充分理解本发明。但是本发明能够以 多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明 内涵的情况下做类似推广。 因此本发明不受下面公开的具体实施的限制。
实施例一：
本实施例公开了一种超结的制作方法， 如图 2所示， 包括：
步骤 Sll、提供一轻掺杂衬底，所述轻掺杂衬底为 N型轻掺杂或 P型轻掺 杂或接近于本征半导体的轻掺杂衬底，其制作材料为可用于半导体器件制作的 硅、 或碳化硅、 或砷化镓、 或锑化铟等材料。
步骤 S12、 以具有 P型重掺杂区图形的第一掩膜版为掩膜， 采用嬗变掺杂 工艺在所述轻掺杂衬底内形成 P型重掺杂区。
步骤 S13、 以具有 N型重掺杂区图形的第二掩膜版为掩膜，采用嬗变掺杂 工艺在所述轻掺杂衬底内形成 N型重掺杂区。
其中， 所述 P型重掺杂区与 N型重掺杂区交替排列在所述轻掺杂衬底内， 且所述 P型重掺杂区与 N型重掺杂区的正面与所述轻掺杂衬底的正面齐平， 所述 P型重掺杂区与 N型重掺杂区的背面与所述轻掺杂衬底的背面齐平。
步骤 S14、 退火处理， 恢复所述轻掺杂衬底的电学性能， 其中， 所述退火 处理的退火温度为 800°C~900°C。
由于嬗变掺杂工艺是通过核反应在衬底内形成的掺杂区，即只需要通过粒 子辐照和退火便可得到超结。 而现有技术中是通过多次外延、 多次注入或多次 外延、 多次刻槽形成的。 所以， 与现有技术相比， 本申请所提供的超结的制作 方法筒化了制作流程， 降低了生产成本。
此外，嬗变掺杂工艺所用的粒子束具有很强的穿透能力， 因此可以应用于 较厚的衬底，故本实施例所提供的方法形成的超结适用于所有耐压水平的半导 体器件。 而且粒子在轻掺杂衬底中的路径几乎是直线， 因此在轻掺杂衬底内几 乎形成了一致的掺杂分布， 掺杂的区域分明， 浓度可以精确控制。
需要说明的是， 本实施例中， 步骤 S12和步骤 S13的顺序是可以互换的。
实施例二：
本实施例公开了另一种超结的制作方法， 包括：
步骤 S21、提供一轻掺杂衬底，所述轻掺杂衬底为 N型轻掺杂或 P型轻掺 杂或接近于本征半导体的轻掺杂衬底，其制作材料为可用于半导体器件制作的 硅、 或碳化硅、 或砷化镓、 或锑化铟等材料。
步骤 S22、 在所述轻掺杂衬底内形成 P型重掺杂区， 包括： 步骤 S221、 提供光子源， 形成高能光子束。
由于高能光子束可以由来自电子线性加速器的韧致辐射所产生， 所以， 本 实施例所述光子源优选为电子线性加速器光子源。产生的高能光子束的能量为 17.5MeV~22.5MeV。
为了能实现局部的掺杂，所述光子源产生的光子束中的光子运动方向需要 相互平行， 即类似平行光的光子束（至少也是有一定的平行度要求）。
步骤 S222、 利用所述高能光子束对所述轻掺杂衬底进行粒子辐照， 引发 核反应， 在所述轻掺杂衬底衬底内形成 P型重掺杂区。
上述方法是采用光子辐照的办法来对材料进行的掺杂。 由于高能的电子在硅中的衰减系数 4艮小，故可以实现半导体的深掺杂。且 同位素原子在晶体中的分布是非常均勾的，所以利用所述高能光子束对所述轻 掺杂衬底进行粒子辐照， 通过元素的嬗变形成的掺杂非常均匀。
并且， 对于以硅为材料的轻掺杂衬底， 在用高能光子束辐照后， 可以通过 引发核反应形成 P型的杂质。
即， 硅 30吸收一个光子后， 变成了铝 27, 并释放出一个质子， 具体的核 反应为：
或者， 硅 30吸收一个光子后变成了硅 27, 并释放出一个中子， 然后经过 4.2s的半衰期后放出一个正电子后变成了铝 27, 具体的核反应为：
Figure imgf000007_0001
此反应生成的稳定 A1就是 P型硅所需要掺入的施主元素。
其中， 虽然核反应的阈值光子能量为 11.6MeV , 但是当光子能量在 17.5MeV~22.5MeV之间时， 巨大的共振会产生最大的光子俘获截面， 因此， 本实施例高能光子束中的光子能量为 17.5MeV~22.5MeV, 优选为 20MeV。
对于以碳化硅为材料的轻掺杂衬底，在用高能光子束辐照后，也可以通过 引发核反应形成 P型的杂质。
即， 碳 12吸收一个光子后， 变成了硼 11 , 并释放出一个质子， 具体的核 反应为： : 或者， 碳 12吸收一个光子后， 变成了碳 11 , 并释放出一个质子， 然后碳 11放出一个正电子后变成了硼 11 , 具体的核反应为：
，
碳化硅中的硅的核反应过程与上述硅的反应相同。
此外， 对于砷化镓或锑化铟材料的轻掺杂衬底， 在用高能光子束辐照后， 也可以通过引发核反应形成 P型的杂质。
由于所述粒子辐照过程是利用高能光子束实现的局部嬗变掺杂，所以形成 P型重掺杂区所用到的第一掩膜版的制作材料为光子吸收剂， 以阻挡不需要的 粒子辐照。
其中， 所述高能光子吸收剂包括： 重金属元素的单质或化合物以及钛酸酯 或硅烷类偶联剂中的至少一种， 以及其他的能够有效吸收光子的物质。
步骤 23、 在所述轻掺杂衬底内形成 N型重掺杂区， 包括：
步骤 S231、 提供中子源， 形成中子束。 由于自由中子是不稳定的， 它可以衰变为质子放出电子和反电中微子， 平 均寿命只有 15分钟， 无法长期储存， 所以需要由适当的产生方法源源供应。 所述中子源有以下 3种：
1、放射性同位素中子源。 所述放射性同位素中子源包括： ( α, η )中子源， 其利用核反应 9Be+a→12C+n+5.701 MeV, 将放射 a射线的 238Pu、 226Ra或 241Am同金属铍粉末按一定比例均匀混合后压制成小圓柱体， 并密封在金属壳 中得到的；（ γ , n )中子源，其利用核反应中发出的 γ射线来产生中子，有 24Na-Be 源， 124Sb-Be源等。 所述放射性同位素中子源的体积小， 制备筒单， 使用方便。 2、 加速器中子源。 所述加速器中子源利用加速器加速的带电粒子轰击适 当的靶核， 通过核反应产生中子， 最常用的核反应有（d, n )、 （p, n )和（γ, η ) 等 ， 其中子强度比放射性同位素中子源大得多， 可以在艮宽的能区上获 得单能中子。 而且， 加速器采用脉沖调制后， 可成为脉沖中子。
3、 反应堆中子源。 所述反应堆中子源利用原子核裂变反应堆产生大量中 子。 反应堆是最强的热中子源， 通过在反应堆的壁上开孔， 即可把中子引出， 且所得的中子能量是连续分布的， 4艮接近麦克斯韦分布。 采取一定的措施， 可 获得各种能量的中子束。
当然， 和对光子束的要求一样，我们也需要所述中子束中中子的运动方向 相互平行（至少也是有一定的平行度要求；)。
步骤 S232、 利用所述中子束对所述轻掺杂衬底进行粒子辐照， 引发核反 应， 在所述轻掺杂衬底内形成 P型重掺杂区。
上述方法是采用中子辐照的办法来对材料进行的掺杂。由于同位素原子在 晶体中的分布是非常均匀的， 而且中子在半导体材料内的穿透深度又很大 (约 为 100cm), 所以利用所述中子束对所述轻掺杂衬底进行粒子辐照， 通过元素 的嬗变形成的掺杂非常均匀，这对于大功率半导体器件和辐射探测器件的制作 是很有用的。
并且， 对于以硅为材料的轻掺杂衬底， 在用中子束辐照后， 可以通过引发 核反应形成 N型的杂质。 即， 硅 30吸收一个中子后变成了硅 31 , 并释放出一 个光子， 然后经过 2.6h的半衰期后放出一个电子后变成了磷 31 , 具体的核反 应为：
' ¾s p 此反应生成的稳定 P就是 N型硅所需要掺入的施主元素。
经照射后达到的 P浓度 ND (单位： cm-3 )可用以下公式计算：
式中， Nsi3。为硅中 3GSi的丰度（单位： cm—3 ); σ为 Si原子对于热中子的 辐射俘获截面 (σ =0.11靶恩)； ψ为热中子的辐照剂量（单位： cm^s ); t为照 射时间 （单位： s )。
由于在一特定的轻掺杂衬底内， 3GSi的丰度 Nsi3。是固定的， 而且 Si原子 对于热中子的辐射俘获截面 σ也是一定值， 则通过控制热中子的辐照剂量 ψ 和照射时间 t即可精确控制 Ν型硅中杂质的掺杂浓度。 并且， 上述反应只产生 一种元素 （P ), 则不会出现嬗变引起的补偿。
另外， 3GSi在硅中的分布天然地均匀， 从而嬗变产生的 31P的分布也均匀， 即 N型硅中的杂质分布均匀。
此外， 为避免中子束通量不均匀分布的影响， 可采用金属通量均匀器， 以 得到通量均勾分布的中子束。
对于以碳化硅为材料的轻掺杂衬底， 与硅类似， 在用中子束辐照后， 硅
30吸收一个中子后变成了硅 31 , 并释放出一个光子， 然后经过 2.6h的半衰期 后放出一个电子后变成了磷 31 ,从而在碳化硅中出现施主磷，使碳化硅成为 N 型掺杂的碳化硅。
此外， 对于砷化镓或锑化铟材料的轻掺杂衬底， 在用中子束辐照后， 也可 以通过引发核反应形成 N型的杂质。 由于上述粒子辐照过程是利用中子束实现的局部嬗变掺杂， 所以形成 N 型重掺杂区所用到的第二掩膜版的制作材料为中子吸收剂，以阻挡不需要的粒 子辐照。
其中，有效的中子吸收剂是可以通过吸收一个中子产生稳定原子核的放射 性同位素。 例如， 氙 135 (半衰期约 9.1小时） ， 可以吸收一个中子变成稳定 的氙 136。 而氙 135可以在核反应堆里通过铀 235 , 铀 233和钚 239核裂变， 伴随产生碘 135 ,碘 135又可以迅速发生衰变，放射出一粒 β粒子（高能电子） 并产生氙 135。 所述中子吸收剂可以为上述同位素中的至少一种。
其他主要的中子吸收剂还包括氦 3同位素， 它吸收中子后可以产生氚（氢 的一种较重同位素）； 硼 10, 它吸收中子后可以产生锂和氦核； 钐 149也是一 种有效的中子吸收剂， 吸收中子后产生稳定的同位素钐 150。
另外一些在核反应堆里的控制棒所使用的中子吸收剂包括镉、铪和稀土金 属钆， 这些都含有若干种同位素， 有一些还是非常高效的中子吸收剂。 第二掩膜版。 而且， 通过选出合适的材料及足够的厚度的掩第二膜版， 可以有 效的吸收中子， 而达到掩膜的效果， 实现局部的掺杂。
另外， 为了便于理解， 图 3和图 4示出了上述掺杂的具体过程。
如图 3所示，在轻掺杂衬底 101上覆盖具有 Ρ型重掺杂区图形的第一掩膜 版 102, 并进行对准， 之后通过入射方向垂直于轻掺杂衬底 101表面的高能光 子束对所述轻掺杂衬底 101进行辐照，在第一掩膜版 102遮挡的部位， 高能光 子束被第一掩膜版 102吸收， 而未被第一掩膜版 102遮挡的区域， 高能光子束 可以直接注入到轻掺杂衬底 101 内部， 发生核反应 （例如硅嬗变为铝）， 得到 Ρ型重掺杂区 10。
如图 4所示， 在轻掺杂衬底 101上覆盖具有 Ν型重掺杂区图形的第二掩 膜版 103 , 并进行对准， 之后通过入射方向垂直于轻掺杂衬底 101表面的中子 束对所述轻掺杂衬底 101进行辐照，在第二掩膜版 103遮挡的部位， 中子束被 第二掩膜版 103吸收， 而未被第二掩膜版 103遮挡的区域， 中子束可以直接注 入到轻掺杂衬底 101内部， 发生核反应 （例如硅嬗变为磷）， 得到 N型重掺杂 区 11。
其中， 所述 P型重掺杂区 10与 N型重掺杂区 11交替排列在所述轻掺杂 衬底 101 内， 且所述 P型重掺杂区 10与 N型重掺杂区 11的正面与所述轻掺 杂衬底 101的正面齐平， 所述 P型重掺杂区 10与 N型重掺杂区 11的背面与 所述轻掺杂衬底 101的背面齐平。
步骤 S24、 退火处理。
由于上述方法会在轻掺杂衬底中造成许多辐照缺陷，使所述轻掺杂衬底的 物理性能发生显著变化。 因此， 为恢复所述轻掺杂衬底的电学性能， 还需要对 其进行退火处理， 其中， 退火温度优选为 800°C ~ 900°C。
本发明实施例所提供的技术方案，采用嬗变掺杂工艺在轻掺杂衬底内形成 P型重掺杂区和 N型重掺杂区。由于嬗变掺杂工艺是通过核反应在衬底内形成 的掺杂区， 即只需要通过粒子辐照和退火便可得到超结。 而现有技术中是通过 多次外延、 多次注入或多次外延、 多次刻槽形成的。 所以， 与现有技术相比， 本申请所提供的超结的制作方法筒化了制作流程， 降低了生产成本。
此外，嬗变掺杂工艺所用的粒子束具有很强的穿透能力， 因此可以应用于 较厚的衬底，故本实施例所提供的方法形成的超结适用于所有耐压水平的半导 体器件。 而且粒子在轻掺杂衬底中的路径几乎是直线， 因此在轻掺杂衬底内几 乎形成了一致的掺杂分布， 掺杂的区域分明， 浓度可以精确控制。
需要说明的是， 本实施例中， 步骤 S22和步骤 S23的顺序是可以互换的。
实施例三： 本实施例公开了又一种超结的制作方法， 如图 5所示， 包括： 步骤 S31、提供第一类型重掺杂衬底，所述第一类型重掺杂衬底为 N型重 掺杂或 P型重掺杂的衬底。
步骤 S32、 以具有第二类型重掺杂区图形的第三掩膜版为掩膜， 采用嬗变 掺杂工艺在所述第一类型重掺杂衬底内形成第二类型重掺杂区，所述第二类型 重掺杂区之外的区域为第一类型重掺杂区。
其中， 所述第一类型重掺杂区与第二类型重掺杂区交替排列。
步骤 S33、 退火处理， 恢复所述第一类型重掺杂衬底的电学性能， 其中， 所述退火处理的退火温度为 800°C~900°C。
本实施例是采用嬗变掺杂工艺在第一类型重掺杂衬底内形成第二类型重 掺杂衬底。 由于嬗变掺杂工艺是通过核反应在衬底内形成的掺杂区， 即只需要 通过粒子辐照和退火便可得到超结。 而现有技术中是通过多次外延、 多次注入 或多次外延、 多次刻槽形成的。 所以， 与现有技术相比， 本申请所提供的超结 的制作方法筒化了制作流程， 降低了生产成本。
此外，嬗变掺杂工艺所用的粒子束具有很强的穿透能力， 因此可以应用于 较厚的衬底，故本实施例所提供的方法形成的超结适用于所有耐压水平的半导 体器件。 而且粒子在轻掺杂衬底中的路径几乎是直线， 因此在轻掺杂衬底内几 乎形成了一致的掺杂分布， 掺杂的区域分明， 浓度可以精确控制。
另外， 与上述实施例相比， 本实施例进一步的筒化了超结的制作方法， 降 低了生产成本。 实施例四：
本实施例公开了又一种超结的制作方法， 包括：
步骤 S41、 提供第一类型重掺杂衬底， 所述第一类型重掺杂衬底为 P型重 掺杂， 其制作材料为可用于半导体器件制作的硅、 或碳化硅、 或砷化镓、 或锑 化铟等材料。 步骤 S42、 在所述第一类型重掺杂衬底内形成第二类型重掺杂区， 所述第 二类型重掺杂区之外的区域为第一类型重掺杂区。其中， 所述第二类型重掺杂 区为 N型重掺杂， 由于所述第一类型重掺杂区与第一类型重掺杂衬底的掺杂 类型相同， 故所述第一类型重掺杂区为 P型重掺杂。
步骤 S42包括： 步骤 S421、 提供中子源， 形成中子束。 步骤 S422、 利用所述中子束对所述第一类型重掺杂衬底进行粒子辐照， 引发核反应， 在所述第一类型重掺杂衬底内形成 N型杂质， 得到第二类型重 掺杂区。 由于上述方法是采用中子辐照的办法来对材料进行的局部嬗变掺杂， 因 此， 需要采用具有第二类型重掺杂区图形的第三掩膜版作为掩膜，且所述第三 掩膜版的制作材料为中子吸收剂。
步骤 S43、 退火处理， 恢复所述第一类型重掺杂衬底的电学性能， 其中， 所述退火处理的退火温度为 800°C~900°C。 实施例五：
本实施例公开了又一种超结的制作方法， 包括：
步骤 S51、提供第一类型重掺杂衬底，所述第一类型重掺杂衬底为 N型重 掺杂，其制作材料为可用于半导体器件制作的硅、或碳化硅、或金刚石、或锗、 或砷化镓、 或锑化铟等材料。
步骤 S52、 在所述第一类型重掺杂衬底内形成第二类型重掺杂区， 所述第 二类型重掺杂区之外的区域为第一类型重掺杂区。其中， 所述第二类型重掺杂 区为 P型重掺杂，由于所述第一类型重掺杂区与第一类型重掺杂衬底的掺杂类 型相同， 故所述第一类型重掺杂区为 N型重掺杂。
步骤 S52包括： 步骤 S521、 提供光子源， 形成高能光子束。 步骤 S522、 利用所述高能光子束对所述第一类型重掺杂衬底进行粒子辐 照， 引发核反应， 在所述第一类型重掺杂衬底内形成 P型杂质， 得到第二类型 重掺杂区。
对于以金刚石为材料的第一类型重掺杂衬底， 在用高能光子束辐照后，也 可以通过引发核反应形成 P型的杂质。 即， 碳 12吸收一个光子后， 变成了硼 11 , 并释放出一个质子， 具体的核 反应为：
或者， 碳 12吸收一个光子后， 变成了碳 11 , 并释放出一个质子， 然后碳
11放出一个正电子后变成了硼 11 , 具体的核反应为：
¾e 2 ≤， 由于上述方法是采用光子辐照的办法来对材料进行的局部嬗变掺杂， 因 此， 需要采用具有第二类型重掺杂区图形的第三掩膜版作为掩膜，且所述第三 掩膜版的制作材料为高能光子吸收剂。
为了便于理解， 图 6示出了上述掺杂的具体过程。
在第一类型重掺杂衬底 201 上覆盖具有第二类型重掺杂区图形的第三掩 膜版 202 , 并进行对准， 之后通过入射方向垂直于第一类型重掺杂衬底 201表 面的中子束对所述轻第一类型重掺杂衬底 201 进行辐照， 在第三掩膜版 203 遮挡的部位， 高能光子束被第三掩膜版 202吸收， 而未被第三掩膜版 202遮挡 的区域， 高能光子束可以直接注入到第一类型重掺杂衬底 201内部，发生核反 应 （例如碳嬗变为硼）， 得到第二类型重掺杂区 21 , 并且所述第二类型重掺杂 区 21之外的区域为第一类型重掺杂区 20。 步骤 S53、 退火处理， 恢复所述第一类型重掺杂衬底的电学性能， 其中， 所述退火处理的退火温度为 800°C~900°C。 实施例六：
本实施例公开了又一种超结的制作方法， 包括：
步骤 S61、提供第一类型重掺杂衬底，所述第一类型重掺杂衬底为 N型重 掺杂， 其制作材料为锗。
步骤 S62、 在所述第一类型重掺杂衬底内形成第二类型重掺杂区， 所述第 二类型重掺杂区之外的区域为第一类型重掺杂区。其中， 所述第二类型重掺杂 区为 P型重掺杂，由于所述第一类型重掺杂区与第一类型重掺杂衬底的掺杂类 型相同， 故所述第一类型重掺杂区为 N型重掺杂。
步骤 S62包括： 步骤 S621、 提供中子源， 形成中子束。 步骤 S622、 利用所述中子束对所述第一类型重掺杂衬底进行粒子辐照， 引发核反应，在所述第一类型重掺杂衬底内形成 P型杂质，得到第二类型重掺 杂区。 由于上述方法是采用中子辐照的办法来对材料进行的局部嬗变掺杂， 因 此， 需要采用具有第二类型重掺杂区图形的第三掩膜版作为掩膜，且所述第三 掩膜版的制作材料为中子吸收剂。
退火处理， 恢复所述第一类型重掺杂衬底的电学性能， 其中， 所述退火处 理的退火温度为 800°C~900°C。 实施例六 本实施例公开了一种超结， 所述超结采用上述任一实施例所述方法形成， 即所述超结采用嬗变掺杂工艺形成。
则本实施例所提供的方法形成的超结适用于所有耐压水平的半导体器件。 而且所述超结的掺杂区域分明， 浓度可以精确控制， 且具有一致的掺杂分布。 实施例七：
本实施例公开了一种超结半导体器件，所述超结半导体器件中的超结为上 述实施例所公开的超结。
其中， 所述超结可以在超结半导体器件其他结构的制作过程之间实现， 以 使所述超结与超结半导体器件其他结构的共用一的退火过程，进一步筒化所述 超结半导体器件的制作， 降低生产成本。
以超结 IGBT ( Insulated Gate Bipolar Transistor, 绝缘栅双极晶体管）的制 作方法为例， 该方法包括：
提供一重掺杂衬底；
在所述重掺杂衬底表面外延生长第一类型重掺杂层；
以具有第二类型重掺杂区图形的第三掩膜版为掩膜，采用嬗变掺杂工艺在 所述第一类型重掺杂层内形成第二类型重掺杂区，所述第二类型重掺杂区之外 的区域为第一类型重掺杂区， 其中， 所述第一类型重掺杂区与第二类型重掺杂 区交替排列；
在形成有第一类型重掺杂区与第二类型重掺杂区的第一类型重掺杂层上 形成阱区、 发射区、 栅和正面金属等正面结构， 完成所述超结 IGBT正面结构 的制作；
退火处理， 恢复所述第一类型重掺杂层的电学性能， 并激活阱区、 发射区 等结构内的掺杂离子， 其中， 所述退火处理的退火温度为 800°C~900°C ;
在所述重掺杂衬底背面形成集电区和背面金属， 完成所述超结 IGBT背面 结构的制作。 此外， 所述超结半导体器件还可以为超结 VDMOS或超结 PIN二极管等 半导体器件。
需要说明的是，本申请各个实施例中的辐照粒子还可以选用其他的带电粒 子或不带电粒子， 以能够实现嬗变掺杂为准。 而且粒子辐照能量是至少要能引 发核反应， 辐照剂量需要根据实际需求预先计算。对于其它的半导体材料和辐 照粒子， 只要能形成相应的掺杂类型都可用此方法形成超结， 而所形成的超结 也可以用于制作任何半导体器件， 在此不一一列出。
另外， 由于某些材料或粒子的辐照时间比传统通过扩散所用的时间要短， 因此， 本申请所提供的超结的制作方法还可以更进一步的提高生产效率。
此外， 需要注意的是， 由于半导体核嬗变掺杂具有残余放射性， 因此， 在 粒子照射后， 轻掺杂衬底或轻掺杂衬底需经一定时间的辐射冷却， 方可作为非 放射性材料进行后续操作。
本说明书中的附图为示意图， 并不代表真实比例。 而且， 本说明书中各个 部分采用递进的方式描述， 每个部分重点说明的都是与其他部分的不同之处， 各个部分之间相同相似部分互相参见即可。 对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本 发明。 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见 的， 本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下， 在 其它实施例中实现。 因此， 本发明将不会被限制于本文所示的实施例， 而是要 符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims

权 利 要 求
1、 一种超结的制作方法， 其特征在于， 包括：
提供一轻掺杂衬底；
以具有 P型重掺杂区图形的第一掩膜版为掩膜，采用嬗变掺杂工艺在所述 轻掺杂衬底内形成 P型重掺杂区；
以具有 N型重掺杂区图形的第二掩膜版为掩膜， 采用嬗变掺杂工艺在所 述轻掺杂衬底内形成 N型重掺杂区；
退火处理。
2、 根据权利要求 1所述方法， 其特征在于， 所述轻掺杂衬底的制作材料 为硅、 或碳化硅、 或砷化镓、 或锑化铟。
3、 根据权利要求 2所述方法， 其特征在于， 所述采用嬗变掺杂工艺在所 述轻掺杂衬底内形成 P型重掺杂区的过程， 包括：
提供光子源， 形成高能光子束；
利用所述高能光子束对所述轻掺杂衬底进行粒子辐照， 引发核反应，在所 述轻掺杂衬底内形成 P型重掺杂区。
4、 根据权利要求 3所述方法， 其特征在于， 所述光子源为电子线性加速 器光子源。
5、 根据权利要求 3 所述方法， 其特征在于， 所述高能光子束的能量为 17.5MeV~22.5MeV。
6、 根据权利要求 3所述的方法， 其特征在于， 所述高能光子束中光子的 运动方向相互平行。
7、 根据权利要求 3所述的方法， 其特征在于， 所述第一掩膜版的制作材 料为高能光子吸收剂。
8、 根据权利要求 7所述的方法， 其特征在于， 所述高能光子吸收剂包括 重金属元素的单质或化合物以及钛酸酯或硅烷类偶联剂中的至少一种。
9、 根据权利要求 2所述的方法， 其特征在于， 所述采用嬗变掺杂工艺在 所述轻掺杂衬底内形成 N型重掺杂区的过程， 包括：
提供中子源， 形成中子束；
利用所述中子束对所述轻掺杂衬底进行粒子辐照， 引发核反应，在所述轻 掺杂衬底内形成 N型重掺杂区。
10、 根据权利要求 9所述的方法， 其特征在于， 所述中子源为放射性同位 素中子源、 或加速器中子源、 或反应堆中子源。
11、 根据权利要求 9所述方法， 其特征在于， 所述中子束中的中子运动方 向相互平行。
12、 根据权利要求 9所方法， 其特征在于， 所述第二掩膜版的制作材料为 中子吸收剂。
13、 根据权利要求 12所述方法， 其特征在于， 所述中子吸收剂包括： 氙 135、 或氦 3同位素、 或硼 10、 或钐 149中的至少一种。
14、 一种超结的制作方法， 其特征在于， 包括：
提供第一类型重掺杂衬底；
以具有第二类型重掺杂区图形的第三掩膜版为掩膜，采用嬗变掺杂工艺在 所述第一类型重掺杂衬底内形成第二类型重掺杂区，所述第二类型重掺杂区之 外的区域为第一类型重掺杂区；
退火处理。
15、 根据权利要求 14所述方法， 其特征在于， 所述第一类型重掺杂衬底 为 P型重掺杂， 所述第二类型重掺杂区为 N型重掺杂。
16、 根据权利要求 15所述方法， 其特征在于， 所述第一类型重掺杂衬底 的制作材料为硅、 或碳化硅、 或砷化镓、 或锑化铟。
17、 根据权利要求 16所述方法， 其特征在于， 所述采用嬗变掺杂工艺在 所述第一类型重掺杂衬底内形成第二类型重掺杂区的过程， 包括： 提供中子源， 形成中子束；
利用所述中子束对所述第一类型重掺杂衬底进行粒子辐照， 引发核反应， 在所述第一类型重掺杂衬底内形成第二类型重掺杂区。
18、 根据权利要求 17所述方法， 其特征在于， 所述第三掩膜版的制作材 料为中子吸收剂。
19、 根据权利要求 14所述方法， 其特征在于， 所述第一类型重掺杂衬底 为 N型重掺杂， 所述第二类型重掺杂区为 P型重掺杂。
20、 根据权利要求 19所述方法， 其特征在于， 所述第一类型重掺杂衬底 的制作材料为硅、 或碳化硅、 或金刚石、 或锗、 或砷化镓、 或锑化铟。
21、 根据权利要求 20所述方法， 其特征在于， 所述采用嬗变掺杂工艺在 所述第一类型重掺杂衬底内形成第二类型重掺杂区的过程， 包括：
提供光子源， 形成高能光子束；
利用所述高能光子束对所述第一类型重掺杂衬底进行粒子辐照，引发核反 应， 在所述第一类型重掺杂衬底内形成第二类型重掺杂区。
22、 根据权利要求 21所述方法， 其特征在于， 所述第三掩膜版的制作材 料为高能光子吸收剂。
23、 根据权利要求 19所述方法， 其特征在于， 所述第一类型重掺杂衬底 的制作材料为锗。
24、 根据权利要求 23所述方法， 其特征在于， 所述采用嬗变掺杂工艺在 所述第一类型重掺杂衬底内形成第二类型重掺杂区的过程， 包括：
提供中子源， 形成中子束；
利用所述中子束对所述第一类型重掺杂衬底进行粒子辐照， 引发核反应， 在所述第一类型重掺杂衬底内形成第二类型重掺杂区。
25、 根据权利要求 24所述方法， 其特征在于， 所述第三掩膜版的制作材 料为中子吸收剂。
26、 根据权利要求 1或 14所述方法， 其特征在于， 所述退火处理的退火 温度为 800°C~900°C。
27、 一种超结， 其特征在于， 所述超结为采用权利要求 1或 14所述方法 制作的超结。
28、 一种超结半导体器件， 其特征在于， 所述超结半导体器件中的超结为 权利要求 27所述的超结。
29、 根据权利要求 28所述方法， 其特征在于， 所述超结半导体器件为超 结 IGBT、 或超结 VDMOS、 或超结 PIN。
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