WO2014075545A1 - Usb低速设备数据传输控制方法及控制器 - Google Patents

Usb低速设备数据传输控制方法及控制器 Download PDF

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Publication number
WO2014075545A1
WO2014075545A1 PCT/CN2013/085995 CN2013085995W WO2014075545A1 WO 2014075545 A1 WO2014075545 A1 WO 2014075545A1 CN 2013085995 W CN2013085995 W CN 2013085995W WO 2014075545 A1 WO2014075545 A1 WO 2014075545A1
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Prior art keywords
signal line
transmission
data
module
packet
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PCT/CN2013/085995
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English (en)
French (fr)
Inventor
张妍彦
赵远鸿
康利云
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中兴通讯股份有限公司
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Publication of WO2014075545A1 publication Critical patent/WO2014075545A1/zh

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation

Definitions

  • the present invention relates to the field of mobile communications, and in particular, to a universal serial bus (USB, Universal Serial Bus) low-speed device data transmission control method and controller.
  • USB Universal Serial Bus
  • USB is a well-known data transmission interface. Since the first draft was born in November 1994, the USB interface has become almost all with its plug-and-play (Plug & Play), simple interface circuit, low cost, and fast transmission speed. Standard equipment for electronic equipment that requires data transmission; applications include fast synchronization and instant transmission of personal computers, consumer and mobile products; USB interface is the most widely used today, USB2.0 and USB3.0, USB3 .0 is backward compatible with USB 2.0, the performance of the two is shown in Table 1:
  • USB device class (device class) will show some basic features of USB, but the USB device can still be divided into some common types, the same type of device can be To have some common behavioral characteristics and work agreements, Table 2 lists some basic USB device types.
  • the USB Human Interface Device (HID) class is a relatively large class.
  • the USB HID class is mainly used for some aspects of computer operations, such as: USB mouse, USB keyboard, USB game Joystick, USB touchpad, USB trackball, telephone dialing device, VCR, Video Cassette Recorder, etc.; HID exchange data is stored in a structure called a report.
  • the host sends and requests reports in the control transmission and interrupt transmission to send and receive data.
  • the format of the report is very flexible and can handle any type of data.
  • the device can send information to the host at an unexpected time, for example: Or the movement of the mouse, so the host will periodically poll the device to get the latest data; for HID, its transmission speed is 1.5Mbps, which belongs to low-speed peripherals; in most USB2.0 devices, low-speed peripherals They all exist as compatible devices, but for HID, only low-speed device devices are required, so they are extracted on the basis of USB2.0.
  • USB's low-speed peripherals remove USB high-speed, full-speed, and feature-limited host (OTG) features, making USB's low-speed peripherals smaller and more efficient; designing a low-speed (LS) transmission peripheral
  • OTG feature-limited host
  • the specific application objectives of the USB LS transmission peripheral device include: Implementing the LS peripheral transmission control of the protocol layer, performing control and error detection during data transmission through the UTMI (USB2.0 Transceiver Macrocell Interface) interface and the physical layer, and performing physical
  • the data exchange between the layer and the internal buffer register (buffer) is performed by communicating with the core controller through the advanced high performance bus (AHB, Advanced High Performance Bus) interface of the Advanced Microcontroller Bus Architecture (AMBA).
  • ABA Advanced Microcontroller Bus Architecture
  • FIG. 1 is a schematic diagram of a USB LS module in the prior art, as shown in FIG. 1 , which mainly includes a UTM data synchronization module, a packet decoding and decoding module, a RAM control module, a data transmission channel (EP) control module, and a CPU interface.
  • UTM data synchronization module mainly includes a UTM data synchronization module, a packet decoding and decoding module, a RAM control module, a data transmission channel (EP) control module, and a CPU interface.
  • the data is first synchronized by the UTM data synchronization module, and then the packet decoding and decoding module processes the transport packet, including packet header processing and data transmission.
  • EP is the data transmission pipeline in USB
  • EP control module control is divided into two parts: general EP control and EP0 control, EP control during data transmission;
  • CPU interface allows CPU
  • the CPU interface can support 32-bit data through the bus's internal control, status registers, and the EP's first-in, first-out queue (FIFO).
  • the RAM control module controls single-port RAM access between the USB and the CPU.
  • USB 2.0 controller can support high speed, full speed / low speed, and can be used as a host (HOST) and device (DEVICE), or a function limited host (OTG), such a controller can complete USB2.0
  • HOST host
  • DEVICE device
  • OGT function limited host
  • the main functions specified in the protocol, the basic control state machine steps are as follows (exceptions are not listed):
  • Step 1 When the transmission starts, the D+/D- signal line is detected. If the two are in an idle state, check Measure its own ID. According to the data provided by the physical layer (PHY, PHYsical layer), it can be judged whether the controller itself is DEVICE or HOST. If it is HOST, go to step 2; otherwise, go to step 5; where D+ signal line and D- The signal line is the differential line for USB user data transmission.
  • PHY PHYsical layer
  • Step 2 HOST connects to the DEVICE by controlling the UTMI signal line and pulling and lowering the D+/D- line through the PHY;
  • Step 3 After the connection is successful, the reset operation is performed.
  • the process of resetting can determine the speed of the DEVICE through the operation of the D+/D- line on the DEVICE side; go to step 4;
  • Step 4 After the reset is completed, the controller transmits the control information and the data packet according to the determined speed; the transmission ends, returns to the IDLE state, and waits for the next transmission;
  • Step 5 If the controller is detected as DEVICE, it will enter the OTG mode, initiate SRP (Wake-up part in the OTG protocol of USB2.0), and wake up the HOST side. When the host is successfully woken up, the controller exits the OTG. Mode, connect with HOST side; go to step 6; Step 6, host and DEVICE connection, DEVICE reset according to the speed of register configuration, if it is high speed, then DEVCIE will first raise D- line, indicating high speed reset, if yes Full speed and low speed, then DEVICE will first raise the D+ line, indicating full speed / low speed reset; go to step 7;
  • Step 7 After the reset is completed, the HOST transmits the control information and the data packet according to the determined speed; the DEVIE controller receives the command token packet and responds according to the command token packet, for example, transmitting a data packet or a handshake, etc.
  • the judgment of the correct transmission of the data packet includes: CRC check, whether the transmission data packet meets the requirements of the transmission type in the protocol, etc.; after the transmission ends, it returns to the IDLE state and waits for the next transmission.
  • the embodiment of the invention provides a USB low-speed device data transmission control method and controller, which solves the problem that the USB LS device wastes a lot of design in the prior art due to the completion of the control of the USB LS and the full-speed and high-speed control. The problem of resources.
  • An embodiment of the present invention provides a USB low-speed device data transmission control method, including: detecting a D+ signal line and a D-signal line of a USB low-speed device at the beginning of transmission, if the D+ signal line and the D-signal line are in an idle state, Then pull up the D+ signal line; after the D+ signal line is pulled low on the host side, directly enter the reset state and pull up the D+ signal line; after the host side reset is completed, control the data transmission channel EP and perform data transmission with the host side. After the transfer is completed, the D+ signal line and the D-signal line are both set to the idle state.
  • the controlling the EP comprises: Step 1: determining whether the EP is ready to receive the command token packet, if the determination is yes, performing step 2, if the determination is no, setting the EP to the idle state; Step 2, updating the EP
  • the data stored in the FIFO receives the command token packet, and decodes and parses the command token packet.
  • Step 3 Determine whether the command token packet carries the data packet. If the determination is yes, go to step 4. Otherwise, go to step 5.
  • Step 4 processing the command token packet, returning the correct response, and setting the EP to the idle state;
  • Step 5 processing the command token packet, if the command token packet is an IN transaction transmission token, then setting the EP to send Status; If the command token packet is an OUT transaction transfer token, the EP is set to the receive state.
  • performing data transmission with the host side includes: determining whether the EP is ready to send the data packet, and if the determination is yes, receiving the OUT token packet, and sending the data packet, and generating the sending data interrupt at the same time. On the host side, otherwise, the end is sent, and the host side is notified.
  • performing data transmission with the host side includes: determining whether the EP is ready to receive the data packet, and if the determination is yes, receiving the IN token packet, and sending the data packet, and generating the sending data interruption On the host side, otherwise, the reception ends and the host side is notified.
  • the above method further comprises: pre-configuring the number of EPs, and the FIFO of each EP And/or, automatically detecting errors during data transmission, notifying the host side and generating an interrupt; and/or, after a predetermined time of data transmission stop, generating a pause interrupt, entering a pause mode, and notifying the physical layer by a pause signal Enter the pause mode, exit the pause mode after detecting the wake-up signal or reset signal, and notify the physical layer to exit the pause mode.
  • the embodiment of the invention further provides a controller for controlling data transmission of the USB low-speed device, comprising: a detecting module configured to detect the D+ signal line and the D-signal line of the USB low-speed device when the transmission starts, if D+ When the signal line and the D-signal line are in an idle state, the D+ signal line is pulled up; the reset module is configured to directly enter the reset state and pull up the D+ signal line after the D+ signal line is pulled low on the host side; It is configured to control the EP and perform data transmission with the host side after the host side reset is completed. After the transmission ends, the D+ signal line and the D-signal line are all set to the idle state.
  • the transmission module includes: a first determining submodule configured to determine whether the EP is ready to receive the command token packet, and if the determination is yes, the update submodule is invoked, and if the determination is no, the EP is set to an idle state;
  • the update submodule is configured to update data stored in the EP first-in first-out queue FIFO;
  • the receiving submodule is configured to receive the command token packet;
  • the first processing submodule is configured to decode and parse the command token packet;
  • the second determining sub-module is configured to determine, according to the processing result of the first processing sub-module, whether the command token packet carries the data packet, if the determination is yes, the second processing sub-module is invoked, otherwise, the third processing sub-module is invoked;
  • Processing submodule configured to process the command token packet, returning the correct response, and setting the EP to an idle state;
  • the third processing submodule configured to process the command token packet, if the command token packet is an IN transaction transmission token
  • the transmission module further includes: a third determining submodule configured to determine, when the EP is in a transmitting state, whether the EP is ready to send a data packet, and if the determination is yes, invoke the first sending submodule, otherwise, end the sending, And notifying the host side; the first sending submodule, configured to receive OUT The token packet, and the data packet is sent, and the sending data is interrupted to the host side.
  • a third determining submodule configured to determine, when the EP is in a transmitting state, whether the EP is ready to send a data packet, and if the determination is yes, invoke the first sending submodule, otherwise, end the sending, And notifying the host side
  • the first sending submodule configured to receive OUT The token packet, and the data packet is sent, and the sending data is interrupted to the host side.
  • the transmission module further includes: a fourth determining submodule configured to determine whether the EP is ready to receive the data packet when the EP is in the receiving state, and if the determination is yes, the second sending submodule is invoked, otherwise, the receiving is ended. And notifying the host side; the second sending submodule is configured to receive the IN token packet, and send the data packet, and simultaneously generate the sending data interrupt to the host side.
  • a fourth determining submodule configured to determine whether the EP is ready to receive the data packet when the EP is in the receiving state, and if the determination is yes, the second sending submodule is invoked, otherwise, the receiving is ended. And notifying the host side; the second sending submodule is configured to receive the IN token packet, and send the data packet, and simultaneously generate the sending data interrupt to the host side.
  • the controller further includes: a configuration module configured to configure a number of EPs and a size of a FIFO of each EP; and/or an error correction module configured to automatically detect errors during data transmission, notify the host side and And generating an interrupt; and/or, suspending the module, configured to generate a pause interrupt after the data transmission stops for a predetermined time, enter a pause mode, and notify the physical layer to enter the pause mode by a pause signal, and exit after detecting the wake-up signal or the reset signal Pause mode, and notify the physical layer to exit the pause mode.
  • a configuration module configured to configure a number of EPs and a size of a FIFO of each EP
  • an error correction module configured to automatically detect errors during data transmission, notify the host side and And generating an interrupt
  • suspending the module configured to generate a pause interrupt after the data transmission stops for a predetermined time, enter a pause mode, and notify the physical layer to enter the pause mode by a pause signal, and exit after detecting the wake-
  • USB low-speed USB device only supports USB low-speed peripheral functions, and the controller area is reduced by 50%. According to the USB protocol requirements, the interface communication transmission between the physical layers and the detection handshake of the transmission channel are correctly realized.
  • FIG. 1 is a schematic diagram of a module of a USB LS in the prior art
  • FIG. 2 is a flowchart of a USB low-speed device data transmission control method according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a connection scheme of a USB2.0 LS peripheral verification environment in the embodiment of the present invention
  • FIG. 5 is a flow chart showing control when the EP0 is in the IDLE mode according to the embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a waveform of a reset at the time of initialization according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a waveform when EP0 performs control IN control transmission according to an embodiment of the present invention
  • FIG. 10 is a schematic diagram of waveforms when EP4 performs OUT transmission according to an embodiment of the present invention
  • FIG. 11 is a schematic structural diagram of a controller according to an embodiment of the present invention.
  • the embodiment of the present invention provides a data transmission control of the USB low speed device.
  • the method and the controller, in the embodiment of the present invention based on the structure and principle of the USB2.0, are improved on the basis of the original, so that the original USB low-speed USB 2.0 device only supports the USB low-speed peripheral function, so that the original
  • the USB 2.0 device can only perform USB low-speed peripheral functions, reducing the area by 50%, and following the USB protocol. It is required to correctly implement the interface communication transmission between the physical layers and the detection handshake of the transmission channel.
  • FIG. 2 is a flowchart of a USB low-speed device data transmission control method according to an embodiment of the present invention.
  • the USB low-speed device data transmission control method includes the following processing: Step 201: When the transmission starts, detecting the D+ signal line and the D-signal line of the USB low-speed device, if the D+ signal line and the D-signal line are both in an idle state, the height is raised. D+ signal line;
  • Step 202 After the D+ signal line is pulled low on the host side, directly enter the reset state, and pull the D+ signal line high;
  • Step 203 After the host side reset is completed, control the EP and perform data transmission with the host side, and after the end of the transmission, set the D+ signal line and the D-signal line to an idle state.
  • step 203 the controlling the EP specifically includes:
  • Step 1 Determine whether the EP is ready to receive the command token packet. If the determination is yes, execute step 2, if the determination is no, set the EP to the idle state;
  • Step 2 Update the data stored in the EP FIFO, receive the command token packet, and decode and parse the command token packet;
  • Step 3 Determine whether the command token packet carries a data packet. If the determination is yes, go to step 4. Otherwise, go to step 5.
  • Step 4 Processing the command token packet, returning the correct response, and setting the EP to the idle state; Step 5, processing the command token packet, if the command token packet is an IN transaction transmission token, setting the EP to the sending state If the command token packet is a token for the OUT transaction, the EP is set to the receiving state.
  • performing data transmission with the host side specifically includes: determining whether the EP is Ready to send the data packet. If the judgment is yes, the OUT token packet is received, and the data packet is sent, and the transmission data is interrupted to the host side. Otherwise, the transmission is terminated and the host side is notified.
  • performing data transmission with the host side specifically includes: determining whether the EP is ready to receive the data packet, and if the determination is yes, receiving the IN token packet, and transmitting the data packet, and generating the sending data interruption to the host side , otherwise, end the reception, and notify the host side.
  • the number of EPs and the size of the FIFO of each EP may be pre-configured; the error in the data transmission process may be automatically detected, the host side is notified and an interrupt is generated; after the data transmission stops for a predetermined time The pause interrupt is generated, enters the pause mode, and the PHY is notified to enter the pause mode by the pause signal. After detecting the wake-up signal or the reset signal, the pause mode is exited, and the PHY is notified to exit the pause mode.
  • FIG. 3 is a schematic diagram of a connection scheme of the USB2.0 LS peripheral verification environment in the embodiment of the present invention. As shown in FIG. 3, when the controller is connected to the PHY, only the map is needed.
  • the MiniAB interface in 3 is replaced with the VIP interface of HOST, and it can be connected to the CPU through the bus interface (AHB interface) on the controller side.
  • the controller device of the embodiment of the invention can encode, decode, correct and control all the transmitted and received USB data packets, and the control data stream of the IN transmission is performed through the peripheral transmit FIFO, and the control data stream of the OUT transmission is passed outside.
  • the receiving FIFO is provided; the controller of the embodiment of the invention supports the dynamic FIFO.
  • the embodiment of the present invention supports the number of configurable EPs, and the number of EPs is 0 ⁇ 4, which can be configured according to transmission requirements, for example: For the BULK OUT operation, the EP can be set to the RX endpoint, and for the BULK IN operation, the EP can be set to the TX endpoint.
  • the EP FIFO can be configured to different sizes to meet different transmission requirements, diversify the transmission capability; can accept SOF packets issued by the HOST party, and generate SOF interrupts; and generate corresponding control interrupts in data transmission.
  • the controller of the embodiment of the invention also supports the DEVICE mode pause (SUSPEND) operation.
  • the controller can generate the SUSPEND interrupt and enter the SUSPEND mode.
  • the controller passes the SUSPEND signal.
  • the PHY is notified to enter the SUSPEND mode.
  • the PHY clock is turned off.
  • the controller exits the SUSPEND mode and notifies the PHY through the SUSPEND signal, and the PHY exits the SUSPEND state.
  • the controller of the embodiment of the invention also supports the CRC of data, has data error correction capability, can automatically detect protocol errors during USB transmission, returns a STALL packet, and generates an interrupt. When the CPU receives the interrupt, the current terminal can be terminated. Transfer, clear the STALL interrupt bit, the controller automatically returns to the IDLE state.
  • Step 1 When the transmission starts, the D+/D- signal line is detected. If the two are in the idle state, the SRP operation is initiated, that is, the D+ line is pulled up; waiting for the HOST side response;
  • Step 2 The HOST side pulls the D+ line low, indicating that it is awakened, and the DEVICE jumps out of the SRP state and directly enters the reset state, pulling up the D+ line;
  • Step 3 In this state, the reset of FS and LS is the same. Both pull D+ line high. After HOST receives the reset signal, it starts the reset operation. After the reset is completed, HOST starts to transmit the data packet and command information. Go to step 4;
  • Step 4 During the data transmission process, the low-speed device judges the state of the D+/D- line and the full speed. In contrast to the high speed, the conventional controller distinguishes between full speed and low speed by judging the state of the signal linstate of the UTMI, and the embodiment of the present invention does not need to perform speed determination;
  • Step 5 The transfer ends and returns to the IDLE state, waiting for the next transfer.
  • the embodiment of the present invention removes most of the control state and the judgment portion, and achieves the purpose of reducing circuit resources.
  • the USB2.0 controller also needs to complete the control of the EP.
  • the EP establishes a connection between the EPs to form a pipeline for data transmission.
  • the embodiment of the present invention extracts the low speed of the USB based on the USB2.0.
  • the internal state machine is controlled, including the main state machine, to control the overall operation of the USB device, and complete control of the internal EP of the USB device.
  • a separate control state machine is used for the control of the EP to control the data channel of a single EP.
  • EP0 is a special one in the EP, and is used to complete the initialization operation of the LINK-UP, and the control transmission of the EP0 is taken as an example. The control process of the device to the EP.
  • FIG. 4 is a flowchart of the control main state transition of the EP0 according to the embodiment of the present invention. As shown in FIG. 4, the flow of controlling the main state transition of the EP0 according to the embodiment of the present invention includes the following steps:
  • Step 1 read the EP0 status register
  • Step 2 determining whether to send a pending token packet, if yes, proceeding to step 3, if not, executing step 4;
  • Step 3 clear the send pending state in the status register, the EP0 control state returns to the IDLE state, and step 4 is performed;
  • Step 4 it is determined whether the establishment process is finished, if yes, step 5 is performed, and if not, step 6 is performed;
  • Step 5 Set the setup process in the status register, and the EP0 control state returns to the IDLE state
  • Step 6 it is determined whether it is in the IDLE state, if yes, step 7 is performed, if no, step 8 is performed; Step 7, maintaining the IDLE state;
  • Step 8 determining whether it is in the sending state, if yes, executing step 9, if no, executing step 10;
  • Step 9 keep the sending mode
  • Step 10 it is determined whether it is receiving the loading, if yes, step 11 is performed, if no, step 12 is performed;
  • Step 11 maintaining the receiving mode
  • Step 12 Keep the default state.
  • the conventional USB controller is software to determine whether EP0 is idle by reading the EP0 status register, and if so, can suspend, or send a SETUP token packet; then enter the IDLE state;
  • the embodiment can also read the state of the EP0 by software, but does not initiate the SETUP token packet, because the command token packet can only be issued by the HOST; the EP0 of the embodiment of the present invention is directly in the IDLE state; after that, the conventional USB controller is The EP0 can enter the sending or receiving mode through software configuration.
  • the embodiment of the present invention waits to receive the token packet on the HOST side. If it is an IN operation, the EP enters the sending state. If it is an OUT operation, the shell enters the receiving state.
  • FIG. 5 is a control flow chart when the EP0 is in the IDLE mode according to the embodiment of the present invention.
  • the EP when powering up and resetting, the EP enters the IDLE mode; in the main state machine, when Perform SETUP transmission, that is, when USB is enumerated, enter IDLE mode; after entering IDLE mode, perform the following steps:
  • Step 1 ready to receive the data packet or command token packet, if not ready, return to the IDLE state, ready, go to step 2;
  • Step 2 updating data stored in the FIFO, and receiving a command token packet
  • Step 3 After receiving the command token packet, perform decoding, parse the command, and determine whether the command token packet carries a data packet according to the protocol of USB2.0, if no packet is entered into step 4, Then proceed to step 5;
  • Step 4 processing the command token package, setting the data, and returning the correct response, returning to the IDLE state;
  • Step 5 processing the command token packet, setting data; determining whether it is an IN transaction transmission token, if yes, entering the transmission mode (Fig. 6), if not, proceeding to step 6;
  • Step 6 enter the OUT transaction transmission, enter the receiving mode ( Figure 7).
  • FIG. 6 is a control flow chart of the EP0 entering the transmission mode according to the embodiment of the present invention.
  • the conventional USB controller can send and receive the OUT token packet, in the embodiment of the present invention, the USB The controller can only receive OUT token packets; all received IN token packets will be treated as data. If the USB controller receives the SETUP command or the OUT token packet at this time, the condition of SETUPEND will be generated, and EP0 exits TX. Mode, in addition, if the length of the transmitted data packet is less than the maximum packet length configured by EP0, or the empty packet is received, the USB exits the state; the TX mode of other EPs is similar, and the processing steps are as follows:
  • Step 1 ready to send a packet judgment, if not ready, directly end the transmission, return a STALL response, indicating that the data is not ready, otherwise go to step 2;
  • Step 2 receiving an OUT token packet, sending a DATA0 data packet, and simultaneously generating a transmission data interrupt to the CPU;
  • Step 3 the OUT transaction ends.
  • the EP0 is in the RX mode, and the conventional USB controller can send and receive the IN token packet.
  • the USB is used.
  • the controller can only receive the IN token packet; all received OUT token packets will be treated as data. If the USB controller receives the SETUP or OUT token packet, the SETUPEND condition will be generated and the RX mode will be terminated. If the end sends an invalid token or empty packet, or if the length of the sent packet is less than the maximum packet length, the SETUPEND condition will also be generated.
  • the TX mode of the EP is similar.
  • the processing steps are as follows: Step 1, ready to receive the packet judgment, if not ready, directly end the transmission, return to the STALL response, indicating that the data is not ready, otherwise proceed to step 2;
  • Step 2 After receiving the IN token packet, the data packet is sent, and the sending data interrupt is generated to the CPU; Step 3, the IN transaction ends.
  • the state of the controller is controlled by the PHY interface signal, mainly the control of the DP/DM signal, and is expressed as two states, a K state and a J state; the state is represented by a linestate of the UTMI signal interface.
  • FIG. 8 is a schematic diagram of a waveform of a reset at the time of initialization according to an embodiment of the present invention. As shown in FIG. 8, the dm signal is pulled high, dp is unchanged, and the dm signal is pulled high after the SE0 state;
  • FIG. 9 is an EP0 control according to an embodiment of the present invention.
  • the waveform of the IN control transmission is as shown in FIG. 9.
  • One of the SETADDR data packets is as follows: the HOST terminal sets the address to 5b, the controller response token packet is d2, and the CLK is 1.5 Mbps.
  • FIG. 10 is an embodiment of the present invention.
  • the waveform diagram of EP4 when performing OUT transmission, as shown in Figure 10, has a data length of 64.
  • the technical solution of the embodiment of the present invention solves the problem that the control of the USB LS is completed together with the control of the full speed and the high speed in the prior art by removing the control of the full speed and the high speed in the controller.
  • the USB LS device wastes a lot of design resources, making the original USB-compatible USB low-speed USB device only support USB low-speed peripheral functions, reducing the controller area by 50%, and correctly implementing the physical layer according to the USB protocol requirements.
  • FIG. 11 is a schematic structural diagram of a controller according to an embodiment of the present invention. As shown in FIG. The controller includes: a detection module 110, a reset module 112, and a transmission module 114.
  • a detection module 110 a detection module 110
  • a reset module 112 a reset module 112
  • a transmission module 114 a transmission module 114.
  • the detecting module 110 is configured to detect the D+ signal line of the USB low speed device at the beginning of the transmission And the D-signal line, if the D+ signal line and the D-signal line are both in an idle state, the D+ signal line is pulled up;
  • the reset module 112 is configured to directly enter the reset state and pull up the D+ signal line after the D+ signal line is pulled low on the host side;
  • the transmission module 114 is configured to control the EP and perform data transmission with the host side after the host side reset is completed, and set the D+ signal line and the D-signal line to an idle state after the end of the transmission.
  • the transmission module 114 specifically includes:
  • the first determining sub-module is configured to determine whether the EP is ready to receive the command token packet. If the determination is yes, the update sub-module is invoked. If the determination is no, the EP is set to the idle state; the update sub-module is configured to be updated. Data stored in the EP FIFO;
  • a receiving submodule configured to receive a command token packet
  • a first processing submodule configured to decode and parse the command token packet
  • the second determining sub-module is configured to determine, according to the processing result of the first processing sub-module, whether the command token packet carries a data packet, and if the determination is yes, the second processing sub-module is invoked; otherwise, the third processing sub-module is invoked;
  • a second processing submodule configured to process the command token packet, return the correct response, and set the EP to an idle state
  • the third processing submodule is configured to process the command token packet, and if the command token packet is an IN transaction transmission token, the EP is set to a sending state; if the command token packet is an OUT transaction transmission token, the EP is set To receive status.
  • the transmission module 114 further includes:
  • the third determining sub-module is configured to determine whether the EP is ready to send the data packet when the EP is in the sending state, and if the judgment is yes, the first sending sub-module is invoked; otherwise, the sending is ended, and the host side is notified;
  • a first sending submodule configured to receive an OUT token packet and send the data packet simultaneously Send data interrupt to the host side
  • the fourth determining sub-module is configured to determine whether the EP is ready to receive the data packet when the EP is in the receiving state, and if the judgment is yes, the second sending sub-module is invoked; otherwise, the receiving is ended, and the host side is notified;
  • the second sending submodule is configured to receive the IN token packet, and send the data packet, and generate a transmission data interrupt to the host side.
  • the controller further includes:
  • the configuration module is configured to configure the number of EPs and the size of each EP FIFO;
  • the error correction module is configured to automatically detect errors during data transmission, notify the host side and generate an interrupt;
  • the pause module is configured to generate a pause interrupt after the data transmission stops for a predetermined time, enter a pause mode, and notify the physical layer to enter the pause mode by a pause signal, exit the pause mode after detecting the wake-up signal or the reset signal, and notify the physical layer Exit the pause mode.
  • the detection module, the reset module, the transmission module, the configuration module, the error correction module, and the pause module may be specifically implemented by a central processing unit (CPU) in the controller, and a digital signal processor (DSP). Or programmable logic array (FPGA, Field - Programmable Gate Array) implementation.
  • CPU central processing unit
  • DSP digital signal processor
  • FPGA programmable logic array
  • FIG. 3 is a schematic diagram of a connection scheme of the USB2.0 LS peripheral verification environment in the embodiment of the present invention. As shown in FIG. 3, when the controller is connected to the PHY, only the map is needed.
  • the MiniAB interface in 3 is replaced with the VIP interface of HOST, and it can be connected to the CPU through the bus interface (AHB interface) on the controller side.
  • the controller device of the embodiment of the invention can encode, decode, correct and control all the transmitted and received USB data packets, and the control data stream of the IN transmission is performed through the peripheral transmit FIFO.
  • the control data stream transmitted by the OUT is performed through the receiving FIFO of the peripheral; the controller of the embodiment of the present invention supports the dynamic FIFO.
  • the embodiment of the present invention supports the number of configurable EPs, and the number of EPs is 0 ⁇ 4, which can be configured according to transmission requirements, for example: For the BULK OUT operation, the EP can be set to the RX endpoint, and for the BULK IN operation, the EP can be set to the TX endpoint.
  • the EP FIFO can be configured to different sizes to meet different transmission requirements, diversify the transmission capability; can accept SOF packets issued by the HOST party, and generate SOF interrupts; and generate corresponding control interrupts in data transmission.
  • the controller of the embodiment of the invention also supports the DEVICE mode pause (SUSPEND) operation. For example, when there is no data transmission on the USB for 3ms, the controller can generate the SUSPEND interrupt and enter the SUSPEND mode. In the SUSPEND mode, the controller passes the SUSPEND signal. The PHY is notified to enter the SUSPEND mode. At this time, the PHY clock is turned off. Until the wake-up or reset signal is detected on the bus, the controller exits the SUSPEND mode and notifies the PHY through the SUSPEND signal, and the PHY exits the SUSPEND state.
  • SUSPEND DEVICE mode pause
  • the controller of the embodiment of the invention further supports data as CRC, has data error correction capability, can automatically detect protocol errors in the USB transmission process, and returns a STALL packet, and generates an interrupt, which can be terminated when the CPU receives the interrupt. Current transfer, clear the STALL interrupt bit, the controller automatically returns to the IDLE state.
  • Step 1 When the transmission starts, the D+/D- signal line is detected. If the two are in the idle state, Start the SRP operation, that is, pull up the D+ line; wait for the HOST side to respond;
  • Step 2 The HOST side pulls the D+ line low, indicating that it is awakened, and the DEVICE jumps out of the SRP state and directly enters the reset state, pulling up the D+ line;
  • Step 3 In this state, the reset of FS and LS is the same. Both pull D+ line high. After HOST receives the reset signal, it starts the reset operation. After the reset is completed, HOST starts to transmit the data packet and command information. Go to step 4;
  • Step 4 In the data transmission process, the state of the D+/D-line is judged to be opposite to the full speed and the high speed of the low-speed device.
  • the conventional controller distinguishes the full speed and the low speed by determining the state of the signal linstate of the UTMI, and the embodiment of the present invention does not need to be performed. Speed judgment
  • Step 5 The transfer ends and returns to the IDLE state, waiting for the next transfer.
  • the embodiment of the present invention removes most of the control state and the judgment portion, and achieves the purpose of reducing circuit resources.
  • the USB2.0 controller also needs to complete the control of the EP.
  • the EP establishes a connection between the EPs to form a pipeline for data transmission.
  • the embodiment of the present invention extracts the low speed of the USB based on the USB2.0.
  • the internal state machine is controlled, including the main state machine, to control the overall operation of the USB device, and complete control of the internal EP of the USB device.
  • a separate control state machine is used for the control of the EP to control the data channel of a single EP.
  • EP0 is a special one in the EP, and is used to complete the initialization operation of the LINK-UP, and the control transmission of the EP0 is taken as an example. The control process of the device to the EP.
  • the conventional USB controller is software that reads whether the EP0 is idle by reading the EP0 status register, and if so, can suspend or send a SETUP token.
  • the packet enters the IDLE state; the embodiment of the present invention can also read the state of the EP0 by software, but does not initiate the SETUP token packet, because the command token packet can only be sent by the HOST; the EP0 of the embodiment of the present invention is directly in the IDLE state.
  • the traditional USB controller can be configured by software to make EP0 enter the transmit or receive mode;
  • the embodiment of the present invention waits to receive the token packet on the HOST side. If it is an IN operation, the EP enters a transmission state, and if it is an OUT operation, the EP enters a reception state.
  • FIG. 5 is a control flow chart when the EP0 is in the IDLE mode according to the embodiment of the present invention.
  • the EP when powering up and resetting, the EP enters the IDLE mode; in the main state machine, when Perform SETUP transmission, that is, when USB is enumerated, enter IDLE mode; after entering IDLE mode, perform the following steps:
  • Step 1 ready to receive the data packet or command token packet, if not ready, return to the IDLE state, ready, go to step 2;
  • Step 2 updating data stored in the FIFO, and receiving a command token packet
  • Step 3 After receiving the command token packet, perform decoding, parse the command, and determine whether the command token packet carries a data packet according to the protocol of USB2.0. If no packet is entered, proceed to step 4, otherwise enter the step. 5;
  • Step 4 processing the command token package, setting the data, and returning the correct response, returning to the IDLE state;
  • Step 5 processing the command token packet, setting data; determining whether it is an IN transaction transmission token, if yes, entering the transmission mode (Fig. 6), if not, proceeding to step 6;
  • Step 6 enter the OUT transaction transmission, enter the receiving mode ( Figure 7).
  • FIG. 6 is a control flow chart of the EP0 entering the transmission mode according to the embodiment of the present invention.
  • the conventional USB controller can send and receive the OUT token packet, in the embodiment of the present invention, the USB The controller can only receive OUT token packets; all received IN token packets will be treated as data. If the USB controller receives the SETUP command or the OUT token packet at this time, the condition of SETUPEND will be generated, and EP0 exits TX. Mode, in addition, if the length of the transmitted data packet is less than the maximum packet length configured by EP0, or the empty packet is received, the USB exits the state; the TX mode of other EPs is similar, and the processing steps are as follows:
  • Step 1 Prepare to send the packet judgment. If not ready, end the transmission directly and return to STALL. Response, indicating that the data is not ready, otherwise proceed to step 2;
  • Step 2 receiving an OUT token packet, sending a DATA0 data packet, and simultaneously generating a transmission data interrupt to the CPU;
  • Step 3 the OUT transaction ends.
  • the EP0 is in the RX mode, and the conventional USB controller can send and receive the IN token packet.
  • the USB is used.
  • the controller can only receive the IN token packet; all received OUT token packets will be treated as data. If the USB controller receives the SETUP or OUT token packet, the SETUPEND condition will be generated and the RX mode will be terminated. If the end sends an invalid token or empty packet, or if the length of the sent packet is less than the maximum packet length, the SETUPEND condition will also be generated.
  • the TX mode of the EP is similar. The processing steps are as follows:
  • Step 1 ready to receive the packet judgment, if not ready, directly end the transmission, return a STALL response, indicating that the data is not ready, otherwise go to step 2;
  • Step 2 After receiving the IN token packet, the data packet is sent, and the sending data interrupt is generated to the CPU; Step 3, the IN transaction ends.
  • the state of the controller is controlled by the PHY interface signal, mainly the control of the DP/DM signal, and is expressed as two states, a K state and a J state; the state is represented by a linestate of the UTMI signal interface.
  • FIG. 8 is a schematic diagram of a waveform of a reset at the time of initialization according to an embodiment of the present invention. As shown in FIG. 8, the dm signal is pulled high, dp is unchanged, and the dm signal is pulled high after the SE0 state;
  • FIG. 9 is an EP0 control according to an embodiment of the present invention.
  • the waveform of the IN control transmission is as shown in FIG. 9.
  • One of the SETADDR data packets is as follows: the HOST terminal sets the address to 5b, the controller response token packet is d2, and the CLK is 1.5 Mbps.
  • FIG. 10 is an embodiment of the present invention.
  • the waveform diagram of EP4 when performing OUT transmission, as shown in Figure 10, has a data length of 64.
  • the speed and high speed control solves the problem that the USB LS device wastes a lot of design resources due to the control of the USB LS and the full speed and high speed control in the prior art, so that the original USB low speed USB device is compatible. Only support USB low-speed peripheral functions, the controller area is reduced by 50%, and the interface communication transmission between the physical layers and the detection handshake of the transmission channel are correctly implemented according to the USB protocol requirements.
  • modules in the devices of the embodiments can be adaptively changed and placed in one or more devices different from the embodiment.
  • the modules or units or components of the embodiments may be combined into one module or unit or component, and In addition, they can be divided into multiple sub-modules or sub-units or sub-components.
  • any combination of the features disclosed in the specification, including the accompanying claims, the abstract and the drawings, and any methods so disclosed, or All processes or units of the device are combined.
  • Each feature disclosed in the specification (including the accompanying claims, the abstract and the drawings) may be replaced by alternative features that provide the same, equivalent, or similar purpose, unless otherwise stated.
  • the various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof.
  • a microprocessor or digital signal processor may be used in practice to implement some or all of the functionality of some or all of the components of the controller in accordance with embodiments of the present invention.
  • the invention can also be implemented as a device or device program (e.g., a computer program and a computer program product) for performing some or all of the methods described herein.
  • a program implementing the present invention may be stored on a computer readable medium or may be in the form of one or more signals. Such signals may be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.
  • any reference signs placed between parentheses shall not be construed as a limitation.
  • the word “comprising” does not exclude the presence of the elements or steps that are not in the claims.
  • the word “a” or “an” preceding a component does not exclude the presence of a plurality of such elements.
  • the invention can be implemented by means of hardware comprising several distinct elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means can be embodied by the same hardware item.
  • the use of the words first, second, and third does not indicate any order. These words can be interpreted as names.

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Abstract

本发明公开了一种USB低速设备数据传输控制方法及控制器。该方法包括:在传输开始时,检测USB低速设备的D+信号线和D-信号线,如果D+信号线和D-信号线均处于空闲状态,则拉高D+信号线;在主机侧将D+信号线拉低后,直接进入复位状态,并拉高D+信号线;在主机侧复位完成后,控制数据传输通道EP并与主机侧进行数据传输,在传输结束后,将D+信号线和D-信号线均设置为空闲状态。借助于本发明的技术方案,使原兼容USB低速的USB装置仅支持USB低速的外设功能,控制器的面积减少了50%,并按照USB的协议要求正确实现了物理层之间的接口通信传输及传输中通道的检测握手。

Description

USB低速设备数据传输控制方法及控制器 技术领域
本发明涉及移动通讯领域, 特别是涉及一种通用串行总线 (USB, Universal Serial Bus )低速设备数据传输控制方法及控制器。 背景技术
USB是家喻户晓的数据传输接口, 自 1994年 11月诞生第一个草案至 今, USB接口以其即插即用 (Plug&Play )、 接口电路简单、 成本低、 以及 传输速度快的特点, 已成为几乎所有需要进行数据传输的电子设备的标准 配备; 应用领域包括个人计算机、 消费及移动类产品的快速同步即时传输; USB接口发展到今天应用最广的是 USB2.0和 USB3.0两个版本, USB3.0 向下兼容 USB2.0, 二者的性能对比如表 1所示:
Figure imgf000003_0001
表 1
在现有技术中, USB的设备类型 (device class )都会表现出一些 USB 的基本特征, 但 USB设备还是可以分成一些共同的类型, 同类型的设备可 以拥有一些共同的行为特征和工作协议, 表 2为一些基本的 USB的设备类 型分类。
Figure imgf000004_0001
表 2
从表 2中可以看出, USB人机接口设备( HID, Human Interface Device ) 类是一个比较大的类, USB HID类主要用于计算机操作的一些方面, 例如: USB鼠标、 USB键盘、 USB游戏操作杆、 USB触摸板、 USB轨迹球、 电 话拨号设备、 模拟式磁带录放机 ( VCR, Video Cassette Recorder )遥控等 设备; HID的交换数据存储在称为报表(report ) 的结构内。 主机在控制传 输和中断传输中发送及请求报表, 从而发送和接收数据, 报表的格式非常 有弹性, 可以处理任何类型的数据; 设备可以在未预期的时间发送信息给 主机, 例如: 键盘的按键或是鼠标的移动, 所以主机会定时轮询设备, 来 取得最新的数据; 对于 HID来说, 其传输速度为 1.5Mbps, 属于低速外设; 在大部分的 USB2.0装置中, 低速外设都是作为可兼容的装置存在, 但是对 于 HID来说, 只需要低速的设备装置即可, 因此在 USB2.0的基础上提取 USB的低速外设部分, 去除 USB高速、 全速、 以及功能受限主机(OTG ) 的功能,使得 USB的低速外设装置面积更小,效率更高;设计一种低速( LS ) 的传输外设装置是一种理想的方案。
USB LS的传输外设装置的具体应用目标包括: 实现协议层的 LS外设 传输控制, 通过 UTMI ( USB2.0 Transceiver Macrocell Interface )接口和物 理层进行数据传输过程中的控制和检错, 进行物理层和内部緩冲寄存器 ( buffer ) 的数据交换, 通过高级微控制器总线 ( AMBA, Advanced Microcontroller Bus Architecture )的高级高性能总线 ( AHB, Advanced High performance Bus )接口和核控制器进行通信,从而完成基本的 bulk IN/OUT, 控制传输、 以及中断传输等。
图 1是现有技术中 USB LS的模块示意图,如图 1所示,主要包括 UTM 数据同步模块、 包解码和译码模块、 RAM控制模块、 数据传输通道(EP ) 控制模块、 CPU接口五个部分; 由于通常物理层的时钟和控制器的时钟不 属于同一个时钟域, 所以数据首先由 UTM数据同步模块进行数据同步, 随 后包解码和译码模块处理传输包, 包括包头的处理、 数据传输以及循环冗 余校验 ( CRC, Cyclic Redundancy Check ); EP是 USB中的数据传输管道, EP控制模块控制分为一般 EP控制和 EP0控制两部分, 进行数据传输时的 EP控制; CPU接口允许 CPU通过总线访问装置内部的控制、 状态寄存器, 以及每个 EP的先入先出队列 ( FIFO ), CPU接口可以支持 32bit的数据; RAM控制模块控制 USB和 CPU之间的单端口 RAM的访问。
现有技术中的 USB2.0 的控制器可以支持高速、 全速 /低速, 并且可以 作为主机(HOST )和设备(DEVICE ), 或者功能受限主机 ( OTG ), 这样 的控制器可以完成 USB2.0协议规定的主要功能,其基本的控制状态机步骤 如下 (异常未列出):
步骤 1、 传输开始时, 检测 D+/D-信号线, 如果二者处于空闲状态, 检 测自身的 ID, 根据物理层 (PHY, PHYsical layer )提供的数据, 可以判断 控制器自身是 DEVICE还是 HOST, 如果是 HOST, 进入步骤 2; 否则, 进 入步骤 5; 其中, D+信号线和 D-信号线是 USB用户数据传输的差分线。
步骤 2、 HOST通过控制 UTMI信号线, 通过 PHY对 D+/D-线进行拉 高和拉低的操作, 与 DEVICE进行连接; 进入步骤 3 ;
步骤 3、 连接成功后进行复位操作, 复位的过程可以通过 DEVICE端 对 D+/D-线上的操作判断 DEVICE是哪一种速度; 进入步骤 4;
步骤 4、 复位完成后,控制器按照判断好的速度进行控制信息和数据包 的传递; 传输结束, 回到 IDLE状态, 等待下一次传输;
步骤 5、如果检测到控制器为 DEVICE,会进入 OTG的模式,发起 SRP ( USB2.0的 OTG协议中的唤醒部分), 对 HOST方进行唤醒操作, 当主机 被成功唤醒后,控制器退出 OTG模式, 与 HOST侧进行连接; 进入步骤 6; 步骤 6、主机和 DEVICE连接, DEVICE按照寄存器配置的速度进行复 位操作, 如果是高速, 那么 DEVCIE会首先拉高 D-线, 表示高速复位, 如 果是全速和低速,那么 DEVICE会首先拉高 D+线,表示全速 /低速复位; 进 入步骤 7;
步骤 7、 复位完成后, HOST按照判断好的速度进行控制信息和数据包 的传递; DEVIE控制器接收命令令牌包, 按照命令令牌包做出响应, 例如, 传输数据包或者握手等信息, 同时进行数据包正确传输的判断, 包括: CRC 检验,传输数据包是否符合协议中传输类型的要求等;传输结束,回到 IDLE 状态, 等待下一次传输。
从上述处理可以看出, 在现有技术中, USB LS的控制都是和全速的状 态机在一起完成的, 这样对于只要求 LS的设备浪费了大量的设计资源, 对 于仅需要运用 USB的 LS的外设而言, 并不需要全速和高速的功能。 发明内容
本发明实施例提供一种 USB低速设备数据传输控制方法及控制器, 以 解决现有技术中由于 USB LS的控制与全速和高速的控制在一起完成而导 致的 USB LS的设备浪费了大量的设计资源的问题。
本发明实施例提供一种 USB低速设备数据传输控制方法, 包括: 在传 输开始时,检测 USB低速设备的 D+信号线和 D-信号线,如果 D+信号线和 D-信号线均处于空闲状态, 则拉高 D+信号线; 在主机侧将 D+信号线拉低 后, 直接进入复位状态, 并拉高 D+信号线; 在主机侧复位完成后, 控制数 据传输通道 EP并与主机侧进行数据传输, 在传输结束后, 将 D+信号线和 D-信号线均设置为空闲状态。
优选地, 控制 EP包括: 步骤 1, 判断 EP是否准备好接收命令令牌包, 如果判断为是, 则执行步骤 2, 如果判断为否, 则将 EP设置为空闲状态; 步骤 2, 更新 EP的 FIFO中存储的数据, 接收命令令牌包, 并对命令令牌 包进行译码解析; 步骤 3, 判断命令令牌包是否携带有数据包, 如果判断为 是, 执行步骤 4, 否则执行步骤 5; 步骤 4, 处理命令令牌包, 返回正确的 响应, 并将 EP设置为空闲状态; 步骤 5, 处理命令令牌包, 如果命令令牌 包为 IN事务传输令牌, 则将 EP设置为发送状态; 如果命令令牌包为 OUT 事务传输令牌, 则将 EP设置为接收状态。
优选地, 当 EP为发送状态时, 与主机侧进行数据传输包括: 判断 EP 是否准备好发送数据包, 如果判断为是, 则接收 OUT令牌包, 并发送数据 包, 同时产生发送数据中断给主机侧, 否则, 结束发送, 并通知主机侧。
优选地, 当 EP为接收状态时, 与主机侧进行数据传输包括: 判断 EP 是否准备好接收数据包,如果判断为是,则接收 IN令牌包,并发送数据包, 同时产生发送数据中断给主机侧, 否则, 结束接收, 并通知主机侧。
优选地, 上述方法还包括: 预先配置 EP的数目、 以及各 EP的 FIFO 的大小; 和 /或, 自动探测数据传输过程中的错误, 通知主机侧并产生中断; 和 /或, 在数据传输停止预定时间后, 产生暂停中断, 进入暂停模式, 并通 过暂停信号通知物理层进入暂停模式, 在检测到唤醒信号或复位信号后, 退出暂停模式, 并通知物理层退出暂停模式。
本发明实施例还提供了一种控制器, 用于控制 USB低速设备的数据传 输, 包括: 检测模块, 配置为在传输开始时, 检测 USB低速设备的 D+信 号线和 D-信号线, 如果 D+信号线和 D-信号线均处于空闲状态, 则拉高 D+ 信号线; 复位模块, 配置为在主机侧将 D+信号线拉低后, 直接进入复位状 态, 并拉高 D+信号线; 传输模块, 配置为在主机侧复位完成后, 控制 EP 并与主机侧进行数据传输,在传输结束后,将 D+信号线和 D-信号线均设置 为空闲状态。
优选地, 传输模块包括: 第一判断子模块, 配置为判断 EP是否准备好 接收命令令牌包, 如果判断为是, 则调用更新子模块, 如果判断为否, 则 将 EP设置为空闲状态; 更新子模块, 配置为更新 EP的先入先出队列 FIFO 中存储的数据; 接收子模块, 配置为接收命令令牌包; 第一处理子模块, 配置为对命令令牌包进行译码解析; 第二判断子模块, 配置为根据第一处 理子模块的处理结果判断命令令牌包是否携带有数据包, 如果判断为是, 调用第二处理子模块, 否则, 调用第三处理子模块; 第二处理子模块, 配 置为处理命令令牌包, 返回正确的响应, 并将 EP设置为空闲状态; 第三处 理子模块, 配置为处理命令令牌包, 如果命令令牌包为 IN事务传输令牌, 则将 EP设置为发送状态; 如果命令令牌包为 OUT事务传输令牌, 则将 EP 设置为接收状态。
优选地, 传输模块还包括: 第三判断子模块, 配置为在 EP为发送状态 时, 判断 EP是否准备好发送数据包, 如果判断为是, 则调用第一发送子模 块, 否则, 结束发送, 并通知主机侧; 第一发送子模块, 配置为接收 OUT 令牌包, 并发送数据包, 同时产生发送数据中断给主机侧。
优选地, 传输模块还包括: 第四判断子模块, 配置为在 EP为接收状态 时, 判断 EP是否准备好接收数据包, 如果判断为是, 则调用第二发送子模 块, 否则, 结束接收, 并通知主机侧; 第二发送子模块, 配置为接收 IN令 牌包, 并发送数据包, 同时产生发送数据中断给主机侧。
优选地, 上述控制器还包括: 配置模块, 配置为配置 EP的数目、 以及 各 EP的 FIFO的大小; 和 /或, 纠错模块, 配置为自动探测数据传输过程中 的错误, 通知主机侧并产生中断; 和 /或, 暂停模块, 配置为在数据传输停 止预定时间后, 产生暂停中断, 进入暂停模式, 并通过暂停信号通知物理 层进入暂停模式, 在检测到唤醒信号或复位信号后, 退出暂停模式, 并通 知物理层退出暂停模式。
本发明实施例有益效果如下:
通过去除控制器中对全速和高速的控制, 解决了现有技术中由于 USB LS的控制与全速和高速的控制在一起完成而导致的 USB LS的设备浪费了 大量的设计资源的问题, 使原兼容 USB低速的 USB装置仅支持 USB低速 的外设功能, 控制器的面积减少了 50%, 并按照 USB的协议要求正确实现 了物理层之间的接口通信传输及传输中通道的检测握手。
上述说明仅是本发明技术方案的概述, 为了能够更清楚了解本发明的 技术手段, 而可依照说明书的内容予以实施, 并且为了让本发明的上述和 其它目的、 特征和优点能够更明显易懂, 以下特举本发明的具体实施方式。 附图说明
通过阅读下文优选实施方式的详细描述, 各种其他的优点和益处对于 本领域普通技术人员将变得清楚明了。 附图仅用于示出优选实施方式的目 的, 而并不认为是对本发明的限制。 而且在整个附图中, 用相同的参考符 号表示相同的部件。 在附图中: 图 1是现有技术中 USB LS的模块示意图;
图 2是本发明实施例的 USB低速设备数据传输控制方法的流程图; 图 3是本发明实施例的 USB2.0 LS 外设验证环境搭建时的一种可借 鉴方案的连接示意图;
图 4是本发明实施例的 EP0的控制主状态转移的流程图;
图 5是本发明实施例的 EP0为 IDLE模式时的控制流程图;
图 6是本发明实施例的 EP0进入发送模式后的控制流程图;
图 7是本发明实施例的 EP0进入接收模式后的控制流程图;
图 8是本发明实施例的初始化时复位的波形示意图;
图 9是本发明实施例的 EP0进行控制 IN控制传输时的波形示意图; 图 10是本发明实施例的 EP4进行 OUT传输时的波形示意图; 图 11是本发明实施例的控制器的结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。 虽然附图中显 示了本公开的示例性实施例, 然而应当理解, 可以以各种形式实现本公开 而不应被这里阐述的实施例所限制。 相反, 提供这些实施例是为了能够更 透彻地理解本公开, 并且能够将本公开的范围完整的传达给本领域的技术 人员。
为了解决现有技术中由于 USB LS的控制与全速和高速的控制在一起 完成而导致的 USB LS的设备浪费了大量的设计资源的问题,本发明实施例 提供了一种 USB低速设备数据传输控制方法及控制器,在本发明实施例中, 基于 USB2.0的结构和原理, 在原有基础上进行改进, 使原兼容 USB低速 的 USB2.0装置仅支持 USB低速的外设功能,使得原来的 USB2.0装置可以 仅完成 USB低速的外设功能, 使得面积减少了 50%, 并按照 USB的协议 要求正确实现了物理层之间的接口通信传输及传输中通道的检测握手。 以 下结合附图以及实施例, 对本发明进行进一步详细说明。 应当理解, 此处 所描述的具体实施例仅仅用以解释本发明, 并不限定本发明。
方法实施例
根据本发明的实施例, 提供了一种 USB低速设备数据传输控制方法, 图 2是本发明实施例的 USB低速设备数据传输控制方法的流程图, 如图 2 所示,根据本发明实施例的 USB低速设备数据传输控制方法包括如下处理: 步骤 201, 在传输开始时, 检测 USB低速设备的 D+信号线和 D-信号 线, 如果 D+信号线和 D-信号线均处于空闲状态, 则拉高 D+信号线;
步骤 202, 在主机侧将 D+信号线拉低后, 直接进入复位状态, 并拉高 D+信号线;
步骤 203, 在主机侧复位完成后, 控制 EP并与主机侧进行数据传输, 在传输结束后, 将 D+信号线和 D-信号线均设置为空闲状态。
在步骤 203中, 控制 EP具体包括:
步骤 1, 判断 EP是否准备好接收命令令牌包, 如果判断为是, 则执行 步骤 2, 如果判断为否, 则将 EP设置为空闲状态;
步骤 2, 更新 EP的 FIFO中存储的数据, 接收命令令牌包, 并对命令 令牌包进行译码解析;
步骤 3, 判断命令令牌包是否携带有数据包, 如果判断为是, 执行步骤 4, 否则执行步骤 5;
步骤 4, 处理命令令牌包,返回正确的响应, 并将 EP设置为空闲状态; 步骤 5, 处理命令令牌包, 如果命令令牌包为 IN事务传输令牌, 则将 EP设置为发送状态; 如果命令令牌包为 OUT事务传输令牌, 则将 EP设置 为接收状态。
在 EP为发送状态时, 与主机侧进行数据传输具体包括: 判断 EP是否 准备好发送数据包, 如果判断为是, 则接收 OUT令牌包, 并发送数据包, 同时产生发送数据中断给主机侧, 否则, 结束发送, 并通知主机侧。
在 EP为接收状态时, 与主机侧进行数据传输具体包括: 判断 EP是否 准备好接收数据包, 如果判断为是, 则接收 IN令牌包, 并发送数据包, 同 时产生发送数据中断给主机侧, 否则, 结束接收, 并通知主机侧。
优选地, 在本发明实施例中, 可以预先配置 EP的数目、 以及各 EP的 FIFO的大小; 还可以自动探测数据传输过程中的错误, 通知主机侧并产生 中断; 在数据传输停止预定时间后, 产生暂停中断, 进入暂停模式, 并通 过暂停信号通知 PHY进入暂停模式, 在检测到唤醒信号或复位信号后, 退 出暂停模式, 并通知 PHY退出暂停模式。
从上述处理可以看出, 在本发明实施例中, 控制器通过 UTMI接口和 PHY进行数据交换, 同步控制器的 PHY的时钟域, 这样控制器内部就可以 工作在总线时钟下, 而不需要和 PHY保持一致; 图 3 是本发明实施例的 USB2.0 LS 外设验证环境搭建时的一种可借鉴方案的连接示意图, 如图 3 所示,在控制器与 PHY连接时,只需要把图 3中的 MiniAB接口换成 HOST 的 VIP接口, 在控制器端通过总线接口 ( AHB接口)和 CPU相连接即可。
本发明实施例的控制器装置能够编码、 译码、 纠错和控制所有发送和 接收到的 USB数据包, IN传输的控制数据流通过外设的发送 FIFO进行, OUT传输的控制数据流通过外设的接收 FIFO进行; 本发明实施例的控制 器支持动态 FIFO。
此外, 本发明实施例支持可配置的 EP数目, EP数目是 0~4, 均可按照 传输要求配置, 例如: 对于 BULK OUT操作 EP可设置为 RX endpoint, 对 于 BULK IN操作 EP可设置为 TX endpoint; 另外, EP的 FIFO可以配置为 不同的大小, 满足不同传输的要求, 使传输能力多样化; 能够接受 HOST 方发出的 SOF包,并产生 SOF中断;并在数据传输中产生相应的控制中断。 本发明实施例的控制器还支持 DEVICE模式的暂停( SUSPEND )操作, 例如, 当 USB上没有数据传输 3ms时, 控制器可以产生 SUSPEND中断, 进入 SUSPEND模式,在 SUSPEND模式下,控制器通过 SUSPEND信号通 知 PHY进入 SUSPEND模式, 此时 PHY时钟关断, 直到总线上监测到唤 醒或者复位信号, 控制器退出 SUSPEND模式并通过 SUSPEND信号通知 PHY, PHY退出 SUSPEND 犬态。
本发明实施例的控制器还支持数据的 CRC, 具有数据纠错能力, 能够 自动探测 USB传输过程中的协议错误, 并返回 STALL包, 并产生中断, 当 CPU接收到该中断时, 可以终止当前传输, 清除 STALL的中断位, 控 制器自动返回 IDLE状态。
以下结合附图, 以 USB2.0版本为例, 对本发明实施例的上述技术方案 进行详细的说明。
在现有技术中, 针对低速装置, USB控制器中的很多功能是不需要的, 例如, HOST功能、 高速部分、 以及 OTG功能等; 本发明实施例为了实现 对基于 USB2.0低速装置的传输控制,保留了低速部分 DEVICE的控制部分, 以及 CRC和协议判断的部分, 去除了 HOST功能, 高速部分以及 OTG的 部分功能; 本发明实施例的基本的控制状态机步骤如下 (异常未列出): 步骤 1、 传输开始时, 检测 D+/D-信号线, 如果二者处于空闲状态, 发 起 SRP操作, 即拉高 D+线; 等待 HOST侧响应;
步骤 2、 HOST侧将 D+线拉低, 表示被唤醒, DEVICE跳出 SRP状态 直接进入复位状态, 拉高 D+线; 进入步骤 3;
步骤 3、在本状态中, FS和 LS的复位是一致的,都是拉高 D+线, HOST 接收到复位信号后, 开始复位操作, 复位完成后, HOST开始进行数据包和 命令信息的传输; 进入步骤 4;
步骤 4、 在数据传输过程中, 低速设备对于 D+/D-线的状态判断与全速 和高速相反, 传统的控制器通过判断 UTMI的信号 linstate的状态区分全速 和低速, 本发明实施例不需要进行速度判断;
步骤 5、 传输结束, 回到 IDLE状态, 等待下一次传输。
通过上述控制器的主状态机的说明, 可以看出本发明实施例去掉了大 部分的控制状态和判断部分, 达到了缩减电路资源的目的。
基本的, USB2.0控制器还需要完成对 EP的控制, 按照 USB2.0协议, EP之间建立连接, 形成数据传输的管道; 本发明实施例在 USB2.0的基础 上提取 USB的低速外设, 并对内部状态机进行控制, 包括主状态机, 以控 制 USB装置的整体工作, 完成对 USB装置内部 EP的控制。 本发明实施例 对于 EP的控制采用单独的控制状态机, 控制单个 EP的数据通道, EP0是 EP中比较特殊的一个, 用来完成 LINK— UP等初始化的操作, 以 EP0的控 制传输为例说明本装置对 EP的控制过程。
图 4是本发明实施例的 EP0的控制主状态转移的流程图,如图 4所示, 本发明实施例的 EP0的控制主状态转移的流程包括以下步骤:
步骤 1, 读 EP0状态寄存器;
步骤 2, 判断是否发送挂起令牌包, 如果是, 则执行步骤 3, 如果否, 则执行步骤 4;
步骤 3, 清除状态寄存器中的发送挂起状态, EP0控制状态回到 IDLE状 态, 执行步骤 4;
步骤 4, 判断建立过程是否结束, 如果是, 则执行步骤 5, 如果否, 则 执行步骤 6;
步骤 5, 将状态寄存器中的建立过程置位, EP0控制状态回到 IDLE状 态;
步骤 6, 判断是否处于 IDLE状态, 如果是, 则执行步骤 7, 如果否, 则执行步骤 8; 步骤 7, 保持 IDLE状态;
步骤 8, 判断是否处于发送状态, 如果是, 则执行步骤 9, 如果否, 则 执行步骤 10;
步骤 9, 保持发送模式;
步骤 10, 判断是否处于接收装填, 如果是, 则执行步骤 11, 如果否, 则执行步骤 12;
步骤 11, 保持接收模式;
步骤 12, 保持默认状态。
从上面的描述中可以看出,传统的 USB控制器是软件通过读 EP0状态 寄存器, 判断 EP0是否处于空闲, 如果是, 则可以挂起, 或者发送 SETUP 令牌包; 然后进入 IDLE状态; 本发明实施例也可以通过软件读 EP0的状 态, 但不会发起 SETUP令牌包, 因为命令令牌包只能由 HOST发出; 本发 明实施例的 EP0直接处于 IDLE状态; 之后, 传统的 USB控制器是可以通 过软件配置, 使 EP0 进入发送或者接收模式; 本发明实施例会等待接收 HOST侧的令牌包, 如果是 IN操作, 则 EP进入发送状态, 如果是 OUT操 作, 贝' J EP进入接收状态。
图 5是本发明实施例的 EP0为 IDLE模式时的控制流程图, 如图 5所 示, 在本发明实施例中, 当上电和复位时, EP进入 IDLE模式; 在主状态 机中, 当进行 SETUP传输, 即 USB进行枚举状态时, 进入 IDLE模式; 进 入 IDLE模式后, 执行以下步骤:
步骤 1,准备接收数据包或者命令令牌包,如果没有准备好,回到 IDLE 状态, 准备好后, 进入步骤 2;
步骤 2, 更新 FIFO中存储的数据, 接收命令令牌包;
步骤 3, 收到命令令牌包后, 进行译码,对命令进行解析,按照 USB2.0 的协议判断命令令牌包是否带有数据包, 如果不带有数据包进入步骤 4, 否 则进入步骤 5;
步骤 4, 处理命令令牌包, 设置数据, 并返回正确的响应, 回到 IDLE 状态;
步骤 5, 处理命令令牌包, 设置数据; 判断是否是 IN事务传输令牌, 是的话进入发送模式(图 6 ), 不是则进入步骤 6;
步骤 6, 进入 OUT事务传输, 进入接收模式(图 7 )。
图 6是本发明实施例的 EP0进入发送模式后的控制流程图, 如图 6所 示, 如果 EP0为 TX模式, 传统的 USB控制器可以发送和接收 OUT令牌 包, 本发明实施例中 USB控制器只能够接收 OUT令牌包; 所有接收到的 IN令牌包都会被当作数据处理, 如果此时 USB控制器接收到 SETUP命令 或者 OUT令牌包, 会产生 SETUPEND的条件, EP0退出 TX模式, 另夕卜, 如果传输的数据包的长度小于 EP0配置的最大包长度, 或者接收到空包, USB 退出该状态; 其它 EP的 TX模式与此类似, 处理步骤如下:
步骤 1,准备发送包判断,如果没有准备好,直接结束发送,返回 STALL 响应, 表示数据没有准备好, 否则进入步骤 2;
步骤 2,接收 OUT令牌包, 发送 DATA0数据包, 同时产生发送数据中 断给 CPU;
步骤 3, OUT事务结束。
图 7是本发明实施例的 EP0进入接收模式后的控制流程图, 如图 7所 示, EP0在 RX模式是, 传统的 USB控制器可以发送和接收 IN令牌包, 本 发明实施例中 USB控制器只能够接收 IN令牌包; 所有接收到的 OUT令牌 包都会被当作数据处理,如果 USB控制器接收到 SETUP或者 OUT令牌包, 会产生 SETUPEND条件, RX模式终止; 另外如果主机端发送无效的令牌 包或者空包, 又或者发送的包长度小于最大包长度, 也会产生 SETUPEND 条件; 它 EP的 TX模式与此类似, 处理步骤如下: 步骤 1,准备接收包判断,如果没有准备好,直接结束发送,返回 STALL 响应, 表示数据没有准备好, 否则进入步骤 2;
步骤 2,接收 IN令牌包后,发送数据包,同时产生发送数据中断给 CPU; 步骤 3, IN事务结束。
在本发明实施例中, 该控制器的状态受 PHY接口信号的控制, 主要是 DP/DM信号的控制, 表示为两种状态, K状态和 J状态; 该状态由 UTMI 信号接口的 linestate表示, 具体 口下: assign j=linestate[l] &〜 linestate[0]; assign k=~ linestate[l] & linestate[0]。图 8是本发明实施例的初始化时复位的 波形示意图, 如图 8所示, dm信号拉高, dp不变, 经过 SE0状态后 dm信 号拉高;图 9是本发明实施例的 EP0进行控制 IN控制传输时的波形示意图, 如图 9所示, 其中一个 SETADDR的数据包如下: HOST端设置地址为 5b, 控制器回应令牌包为 d2, CLK为 1.5Mbps; 图 10是本发明实施例的 EP4 进行 OUT传输时的波形示意图, 如图 10所示, 数据长度为 64。
综上所述, 借助于本发明实施例的技术方案, 通过去除控制器中对全 速和高速的控制,解决了现有技术中由于 USB LS的控制与全速和高速的控 制在一起完成而导致的 USB LS的设备浪费了大量的设计资源的问题,使原 兼容 USB低速的 USB装置仅支持 USB低速的外设功能, 控制器的面积减 少了 50%, 并按照 USB的协议要求正确实现了物理层之间的接口通信传输 及传输中通道的检测握手。
装置实施例
根据本发明的实施例, 提供了一种控制器, 用于控制 USB低速设备的 数据传输, 图 11是本发明实施例的控制器的结构示意图, 如图 11所示, 根据本发明实施例的控制器包括: 检测模块 110、 复位模块 112、 以及传输 模块 114, 以下对本发明实施例的各个模块进行详细的说明。
检测模块 110, 配置为在传输开始时, 检测 USB低速设备的 D+信号线 和 D-信号线, 如果 D+信号线和 D-信号线均处于空闲状态, 则拉高 D+信号 线;
复位模块 112, 配置为在主机侧将 D+信号线拉低后, 直接进入复位状 态, 并拉高 D+信号线;
传输模块 114, 配置为在主机侧复位完成后, 控制 EP并与主机侧进行 数据传输, 在传输结束后, 将 D+信号线和 D-信号线均设置为空闲状态。
传输模块 114具体包括:
第一判断子模块, 配置为判断 EP是否准备好接收命令令牌包, 如果判 断为是, 则调用更新子模块, 如果判断为否, 则将 EP设置为空闲状态; 更新子模块, 配置为更新 EP的 FIFO中存储的数据;
接收子模块, 配置为接收命令令牌包;
第一处理子模块, 配置为对命令令牌包进行译码解析;
第二判断子模块, 配置为根据第一处理子模块的处理结果判断命令令 牌包是否携带有数据包, 如果判断为是, 调用第二处理子模块, 否则, 调 用第三处理子模块;
第二处理子模块, 配置为处理命令令牌包, 返回正确的响应, 并将 EP 设置为空闲状态;
第三处理子模块, 配置为处理命令令牌包, 如果命令令牌包为 IN事务 传输令牌, 则将 EP设置为发送状态; 如果命令令牌包为 OUT事务传输令 牌, 则将 EP设置为接收状态。
传输模块 114, 还包括:
第三判断子模块, 配置为在 EP为发送状态时, 判断 EP是否准备好发 送数据包, 如果判断为是, 则调用第一发送子模块, 否则, 结束发送, 并 通知主机侧;
第一发送子模块, 配置为接收 OUT令牌包, 并发送数据包, 同时产生 发送数据中断给主机侧;
第四判断子模块, 配置为在 EP为接收状态时, 判断 EP是否准备好接 收数据包, 如果判断为是, 则调用第二发送子模块, 否则, 结束接收, 并 通知主机侧;
第二发送子模块, 配置为接收 IN令牌包, 并发送数据包, 同时产生发 送数据中断给主机侧。
优选地, 在本发明实施例中, 控制器进一步包括:
配置模块, 配置为配置 EP的数目、 以及各 EP的 FIFO的大小; 纠错模块, 配置为自动探测数据传输过程中的错误, 通知主机侧并产 生中断;
暂停模块, 配置为在数据传输停止预定时间后, 产生暂停中断, 进入 暂停模式, 并通过暂停信号通知物理层进入暂停模式, 在检测到唤醒信号 或复位信号后, 退出暂停模式, 并通知物理层退出暂停模式。
实际应用时, 检测模块、 复位模块、 传输模块、 配置模块、 纠错模块、 暂停模块具体可由控制器中的中央处理器(CPU, Central Processing Unit ), 数字信号处理器( DSP, Digital Signal Processor )或可编程逻辑阵列( FPGA, Field - Programmable Gate Array ) 实现。
从上述处理可以看出, 在本发明实施例中, 控制器通过 UTMI接口和 PHY进行数据交换, 同步控制器的 PHY的时钟域, 这样控制器内部就可以 工作在总线时钟下, 而不需要和 PHY保持一致; 图 3 是本发明实施例的 USB2.0 LS 外设验证环境搭建时的一种可借鉴方案的连接示意图, 如图 3 所示,在控制器与 PHY连接时,只需要把图 3中的 MiniAB接口换成 HOST 的 VIP接口, 在控制器端通过总线接口 ( AHB接口)和 CPU相连接即可。
本发明实施例的控制器装置能够编码、 译码、 纠错和控制所有发送和 接收到的 USB数据包, IN传输的控制数据流通过外设的发送 FIFO进行, OUT传输的控制数据流通过外设的接收 FIFO进行; 本发明实施例的控制 器支持动态 FIFO。
此外, 本发明实施例支持可配置的 EP数目, EP数目是 0~4, 均可按照 传输要求配置, 例如: 对于 BULK OUT操作 EP可设置为 RX endpoint, 对 于 BULK IN操作 EP可设置为 TX endpoint; 另外, EP的 FIFO可以配置为 不同的大小, 满足不同传输的要求, 使传输能力多样化; 能够接受 HOST 方发出的 SOF包,并产生 SOF中断;并在数据传输中产生相应的控制中断。
本发明实施例的控制器还支持 DEVICE模式的暂停( SUSPEND )操作, 例如, 当 USB上没有数据传输 3ms时, 控制器可以产生 SUSPEND中断, 进入 SUSPEND模式,在 SUSPEND模式下,控制器通过 SUSPEND信号通 知 PHY进入 SUSPEND模式, 此时 PHY时钟关断, 直到总线上监测到唤 醒或者复位信号, 控制器退出 SUSPEND模式并通过 SUSPEND信号通知 PHY, PHY退出 SUSPEND 犬态。
本发明实施例的控制器还支持数据的为 CRC, 具有数据纠错能力, 能 够自动探测 USB传输过程中的协议错误, 并返回 STALL包, 并产生中断, 当 CPU接收到该中断时, 可以终止当前传输, 清除 STALL的中断位, 控 制器自动返回 IDLE状态。
以下结合附图, 以 USB2.0版本为例, 对本发明实施例的上述技术方案 进行详细的说明。
在现有技术中, 针对低速装置, USB控制器中的很多功能是不需要的, 例如, HOST功能、 高速部分、 以及 OTG功能等; 本发明实施例为了实现 对基于 USB2.0低速装置的传输控制,保留了低速部分 DEVICE的控制部分, 以及 CRC和协议判断的部分, 去除了 HOST功能, 高速部分以及 OTG的 部分功能; 本发明实施例的基本的控制状态机步骤如下 (异常未列出): 步骤 1、 传输开始时, 检测 D+/D-信号线, 如果二者处于空闲状态, 发 起 SRP操作, 即拉高 D+线; 等待 HOST侧响应;
步骤 2、 HOST侧将 D+线拉低, 表示被唤醒, DEVICE跳出 SRP状态 直接进入复位状态, 拉高 D+线; 进入步骤 3;
步骤 3、在本状态中, FS和 LS的复位是一致的,都是拉高 D+线, HOST 接收到复位信号后, 开始复位操作, 复位完成后, HOST开始进行数据包和 命令信息的传输; 进入步骤 4;
步骤 4、 在数据传输过程中, 低速设备对于 D+/D-线的状态判断与全速 和高速相反, 传统的控制器通过判断 UTMI的信号 linstate的状态区分全速 和低速, 本发明实施例不需要进行速度判断;
步骤 5、 传输结束, 回到 IDLE状态, 等待下一次传输。
通过上述控制器的主状态机的说明, 可以看出本发明实施例去掉了大 部分的控制状态和判断部分, 达到了缩减电路资源的目的。
基本的, USB2.0控制器还需要完成对 EP的控制, 按照 USB2.0协议, EP之间建立连接, 形成数据传输的管道; 本发明实施例在 USB2.0的基础 上提取 USB的低速外设, 并对内部状态机进行控制, 包括主状态机, 以控 制 USB装置的整体工作, 完成对 USB装置内部 EP的控制。 本发明实施例 对于 EP的控制采用单独的控制状态机, 控制单个 EP的数据通道, EP0是 EP中比较特殊的一个, 用来完成 LINK— UP等初始化的操作, 以 EP0的控 制传输为例说明本装置对 EP的控制过程。
图 4是本发明实施例的 EP0的控制主状态转移的流程图, 传统的 USB 控制器是软件通过读 EP0状态寄存器, 判断 EP0是否处于空闲, 如果是, 则可以挂起, 或者发送 SETUP令牌包; 然后进入 IDLE状态; 本发明实施 例也可以通过软件读 EP0的状态,但不会发起 SETUP令牌包, 因为命令令 牌包只能由 HOST发出; 本发明实施例的 EP0直接处于 IDLE状态; 之后, 传统的 USB控制器是可以通过软件配置, 使 EP0进入发送或者接收模式; 本发明实施例会等待接收 HOST侧的令牌包, 如果是 IN操作, 则 EP进入 发送状态, 如果是 OUT操作, 则 EP进入接收状态。
图 5是本发明实施例的 EP0为 IDLE模式时的控制流程图, 如图 5所 示, 在本发明实施例中, 当上电和复位时, EP进入 IDLE模式; 在主状态 机中, 当进行 SETUP传输, 即 USB进行枚举状态时, 进入 IDLE模式; 进 入 IDLE模式后, 执行以下步骤:
步骤 1,准备接收数据包或者命令令牌包,如果没有准备好,回到 IDLE 状态, 准备好后, 进入步骤 2;
步骤 2, 更新 FIFO中存储的数据, 接收命令令牌包;
步骤 3, 收到命令令牌包后, 进行译码,对命令进行解析,按照 USB2.0 的协议判断命令令牌包是否带有数据包, 如果不带有数据包进入步骤 4, 否 则进入步骤 5;
步骤 4, 处理命令令牌包, 设置数据, 并返回正确的响应, 回到 IDLE 状态;
步骤 5, 处理命令令牌包, 设置数据; 判断是否是 IN事务传输令牌, 是的话进入发送模式(图 6 ), 不是则进入步骤 6;
步骤 6, 进入 OUT事务传输, 进入接收模式(图 7 )。
图 6是本发明实施例的 EP0进入发送模式后的控制流程图, 如图 6所 示, 如果 EP0为 TX模式, 传统的 USB控制器可以发送和接收 OUT令牌 包, 本发明实施例中 USB控制器只能够接收 OUT令牌包; 所有接收到的 IN令牌包都会被当作数据处理, 如果此时 USB控制器接收到 SETUP命令 或者 OUT令牌包, 会产生 SETUPEND的条件, EP0退出 TX模式, 另夕卜, 如果传输的数据包的长度小于 EP0配置的最大包长度, 或者接收到空包, USB 退出该状态; 其它 EP的 TX模式与此类似, 处理步骤如下:
步骤 1,准备发送包判断,如果没有准备好,直接结束发送,返回 STALL 响应, 表示数据没有准备好, 否则进入步骤 2;
步骤 2,接收 OUT令牌包, 发送 DATA0数据包, 同时产生发送数据中 断给 CPU;
步骤 3, OUT事务结束。
图 7是本发明实施例的 EP0进入接收模式后的控制流程图, 如图 7所 示, EP0在 RX模式是, 传统的 USB控制器可以发送和接收 IN令牌包, 本 发明实施例中 USB控制器只能够接收 IN令牌包; 所有接收到的 OUT令牌 包都会被当作数据处理,如果 USB控制器接收到 SETUP或者 OUT令牌包, 会产生 SETUPEND条件, RX模式终止; 另外如果主机端发送无效的令牌 包或者空包, 又或者发送的包长度小于最大包长度, 也会产生 SETUPEND 条件; 它 EP的 TX模式与此类似, 处理步骤如下:
步骤 1,准备接收包判断,如果没有准备好,直接结束发送,返回 STALL 响应, 表示数据没有准备好, 否则进入步骤 2;
步骤 2,接收 IN令牌包后,发送数据包,同时产生发送数据中断给 CPU; 步骤 3, IN事务结束。
在本发明实施例中, 该控制器的状态受 PHY接口信号的控制, 主要是 DP/DM信号的控制, 表示为两种状态, K状态和 J状态; 该状态由 UTMI 信号接口的 linestate表示, 具体 口下: assign j=linestate[l] &〜 linestate[0]; assign k=~ linestate[l] & linestate[0]。图 8是本发明实施例的初始化时复位的 波形示意图, 如图 8所示, dm信号拉高, dp不变, 经过 SE0状态后 dm信 号拉高;图 9是本发明实施例的 EP0进行控制 IN控制传输时的波形示意图, 如图 9所示, 其中一个 SETADDR的数据包如下: HOST端设置地址为 5b, 控制器回应令牌包为 d2, CLK为 1.5Mbps; 图 10是本发明实施例的 EP4 进行 OUT传输时的波形示意图, 如图 10所示, 数据长度为 64。
综上所述, 借助于本发明实施例的技术方案, 通过去除控制器中对全 速和高速的控制,解决了现有技术中由于 USB LS的控制与全速和高速的控 制在一起完成而导致的 USB LS的设备浪费了大量的设计资源的问题,使原 兼容 USB低速的 USB装置仅支持 USB低速的外设功能, 控制器的面积减 少了 50%, 并按照 USB的协议要求正确实现了物理层之间的接口通信传输 及传输中通道的检测握手。
在此提供的算法和显示不与任何特定计算机、 虚拟系统或者其它设备 固有相关。 各种通用系统也可以与基于在此的示教一起使用。 根据上面的 描述, 构造这类系统所要求的结构是显而易见的。 此外, 本发明也不针对 任何特定编程语言。 应当明白, 可以利用各种编程语言实现在此描述的本 发明的内容, 并且上面对特定语言所做的描述是为了披露本发明的最佳实 施方式。
在此处所提供的说明书中, 说明了大量具体细节。 然而, 能够理解, 并未详细示出公知的方法、 结构和技术, 以便不模糊对本说明书的理解。
类似地, 应当理解, 为了精简本公开并帮助理解各个发明方面中的一 个或多个, 在上面对本发明的示例性实施例的描述中, 本发明的各个特征 有时被一起分组到单个实施例、 图、 或者对其的描述中。 然而, 并不应将 该公开的方法解释成反映如下意图: 即所要求保护的本发明要求比在每个 权利要求中所明确记载的特征更多的特征。 更确切地说, 如下面的权利要 求书所反映的那样, 发明方面在于少于前面公开的单个实施例的所有特征。 因此, 遵循具体实施方式的权利要求书由此明确地并入该具体实施方式, 其中每个权利要求本身都作为本发明的单独实施例。
本领域那些技术人员可以理解, 可以对实施例中的设备中的模块进行 自适应性地改变并且把它们设置在与该实施例不同的一个或多个设备中。 可以把实施例中的模块或单元或组件组合成一个模块或单元或组件, 以及 此外可以把它们分成多个子模块或子单元或子组件。 除了这样的特征和 /或 过程或者单元中的至少一些是相互排斥之外, 可以采用任何组合对本说明 书 (包括伴随的权利要求、 摘要和附图) 中公开的所有特征以及如此公开 的任何方法或者设备的所有过程或单元进行组合。 除非另外明确陈述, 本 说明书 (包括伴随的权利要求、 摘要和附图) 中公开的每个特征可以由提 供相同、 等同或相似目的的替代特征来代替。
此外, 本领域的技术人员能够理解, 尽管在此所述的一些实施例包括 其它实施例中所包括的某些特征而不是其它特征, 但是不同实施例的特征 的组合意味着处于本发明的范围之内并且形成不同的实施例。 例如, 在下 面的权利要求书中, 所要求保护的实施例的任意之一都可以以任意的组合 方式来使用。
本发明的各个部件实施例可以以硬件实现, 或者以在一个或者多个处 理器上运行的软件模块实现, 或者以它们的组合实现。 本领域的技术人员 应当理解, 可以在实践中使用微处理器或者数字信号处理器(DSP )来实现 根据本发明实施例的控制器中的一些或者全部部件的一些或者全部功能。 本发明还可以实现为用于执行这里所描述的方法的一部分或者全部的设备 或者装置程序(例如, 计算机程序和计算机程序产品)。 这样的实现本发明 的程序可以存储在计算机可读介质上, 或者可以具有一个或者多个信号的 形式。 这样的信号可以从因特网网站上下载得到, 或者在载体信号上提供, 或者以任何其他形式提供。
应该注意的是上述实施例对本发明进行说明而不是对本发明进行限 制, 并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出 替换实施例。 在权利要求中, 不应将位于括号之间的任何参考符号构造成 对权利要求的限制。 单词 "包含" 不排除存在未列在权利要求中的元件或 步骤。 位于元件之前的单词 "一" 或 "一个" 不排除存在多个这样的元件。 本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算 机来实现。 在列举了若干装置的单元权利要求中, 这些装置中的若干个可 以是通过同一个硬件项来具体体现。 单词第一、 第二、 以及第三等的使用 不表示任何顺序。 可将这些单词解释为名称。

Claims

权利要求书
1、 一种 USB低速设备数据传输控制方法, 包括:
在传输开始时, 检测 USB低速设备的 D+信号线和 D-信号线, 如果所 述 D+信号线和所述 D-信号线均处于空闲状态, 则拉高所述 D+信号线; 在主机侧将所述 D+信号线拉低后, 直接进入复位状态, 并拉高所述 D+信号线;
在所述主机侧复位完成后,控制数据传输通道 EP并与所述主机侧进行 数据传输,在传输结束后,将所述 D+信号线和所述 D-信号线均设置为空闲 状态。
2、 如权利要求 1所述的方法, 其中, 所述控制 EP包括:
步骤 1, 判断所述 EP是否准备好接收命令令牌包, 如果判断为是, 则 执行步骤 2, 如果判断为否, 则将所述 EP设置为空闲状态;
步骤 2, 更新所述 EP的先入先出队列 FIFO中存储的数据, 接收所述 命令令牌包, 并对所述命令令牌包进行译码解析;
步骤 3, 判断所述命令令牌包是否携带有数据包, 如果判断为是, 执行 步骤 4, 否则执行步骤 5;
步骤 4, 处理所述命令令牌包, 返回正确的响应, 并将所述 EP设置为 空闲状态;
步骤 5, 处理所述命令令牌包, 如果所述命令令牌包为 IN事务传输令 牌, 则将所述 EP设置为发送状态; 如果所述命令令牌包为 OUT事务传输 令牌, 则将所述 EP设置为接收状态。
3、 如权利要求 2所述的方法, 其中, 当所述 EP为发送状态时, 所述 与所述主机侧进行数据传输包括:
判断所述 EP是否准备好发送数据包, 如果判断为是, 则接收 OUT令 牌包, 并发送数据包, 同时产生发送数据中断给所述主机侧, 否则, 结束 发送, 并通知所述主机侧。
4、 如权利要求 2所述的方法, 其中, 当所述 EP为接收状态时, 所述 与所述主机侧进行数据传输包括:
判断所述 EP是否准备好接收数据包, 如果判断为是, 则接收 IN令牌 包, 并发送数据包, 同时产生发送数据中断给所述主机侧, 否则, 结束接 收, 并通知所述主机侧。
5、 如权利要求 1所述的方法, 其中, 所述方法还包括:
预先配置 EP的数目、 以及各 EP的 FIFO的大小; 和 /或,
自动探测数据传输过程中的错误,通知所述主机侧并产生中断; 和 /或, 在数据传输停止预定时间后, 产生暂停中断, 进入暂停模式, 并通过 暂停信号通知物理层进入暂停模式, 在检测到唤醒信号或复位信号后, 退 出所述暂停模式, 并通知所述物理层退出所述暂停模式。
6、 一种控制器, 用于控制 USB低速设备的数据传输, 所述控制器包 括:
检测模块, 配置为在传输开始时, 检测 USB低速设备的 D+信号线和 D-信号线,如果所述 D+信号线和所述 D-信号线均处于空闲状态,则拉高所 述 D+信号线;
复位模块, 配置为在主机侧将所述 D+信号线拉低后, 直接进入复位状 态, 并拉高所述 D+信号线;
传输模块, 配置为在所述主机侧复位完成后, 控制数据传输通道 EP并 与所述主机侧进行数据传输, 在传输结束后, 将所述 D+信号线和所述 D- 信号线均设置为空闲状态。
7、 如权利要求 6所述的控制器, 其中, 所述传输模块包括:
第一判断子模块, 配置为所述判断 EP是否准备好接收命令令牌包, 如 果判断为是, 则调用更新子模块, 如果判断为否, 则将所述 EP设置为空闲 状态;
更新子模块,配置为更新所述 EP的先入先出队列 FIFO中存储的数据; 接收子模块, 配置为接收所述命令令牌包;
第一处理子模块, 配置为对所述命令令牌包进行译码解析;
第二判断子模块, 配置为根据第一处理子模块的处理结果判断所述命 令令牌包是否携带有数据包, 如果判断为是, 调用第二处理子模块, 否贝 'J, 调用第三处理子模块;
第二处理子模块, 配置为处理所述命令令牌包, 返回正确的响应, 并 将所述 EP设置为空闲状态;
第三处理子模块, 配置为处理所述命令令牌包, 如果所述命令令牌包 为 IN事务传输令牌, 则将所述 EP设置为发送状态; 如果所述命令令牌包 为 OUT事务传输令牌, 则将所述 EP设置为接收状态。
8、 如权利要求 7所述的控制器, 其中, 所述传输模块还包括: 第三判断子模块, 配置为在所述 EP为发送状态时, 判断所述 EP是否 准备好发送数据包, 如果判断为是, 则调用第一发送子模块, 否则, 结束 发送, 并通知所述主机侧;
第一发送子模块, 配置为接收 OUT令牌包, 并发送数据包, 同时产生 发送数据中断给所述主机侧。
9、 如权利要求 7所述的控制器, 其中, 所述传输模块还包括: 第四判断子模块, 配置为在所述 EP为接收状态时, 判断所述 EP是否 准备好接收数据包, 如果判断为是, 则调用第二发送子模块, 否则, 结束 接收, 并通知所述主机侧;
第二发送子模块, 配置为接收 IN令牌包, 并发送数据包, 同时产生发 送数据中断给所述主机侧。
10、 如权利要求 6所述的控制器, 其中, 所述控制器还包括: 配置模块, 配置为配置 EP的数目、 以及各 EP的 FIFO的大小; 和 /或, 纠错模块, 配置为自动探测数据传输过程中的错误, 通知所述主机侧 并产生中断; 和 /或,
暂停模块, 配置为在数据传输停止预定时间后, 产生暂停中断, 进入 暂停模式, 并通过暂停信号通知物理层进入暂停模式, 在检测到唤醒信号 或复位信号后, 退出所述暂停模式, 并通知所述物理层退出所述暂停模式。
PCT/CN2013/085995 2012-11-13 2013-10-25 Usb低速设备数据传输控制方法及控制器 WO2014075545A1 (zh)

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