WO2014072410A1

WO2014072410A1 - Optoelectronic semiconductor chip and method for producing an optoelectronic semiconductor chip

Info

Publication number: WO2014072410A1
Application number: PCT/EP2013/073277
Authority: WO
Inventors: Alexander F. PFEUFFER; Lutz Höppel; Dominik Scholz
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2012-11-09
Filing date: 2013-11-07
Publication date: 2014-05-15
Also published as: TW201429000A; DE102012110775A1

Abstract

In at least one embodiment, the optoelectronic semiconductor chip (1) comprises a semiconductor layer sequence (3) having an n-conducting layer (31), a p-conducting layer (33) and an active zone (33) arranged therebetween. The semiconductor layer sequence (3) is arranged on a carrier (2). A first electrode (4) is designed for making contact with the n-conducting layer (31) and a second electrode (5) is designed for making contact with the p-conducting layer (33). An electrical contact location (6) for externally making electrical contact with the second electrode (5) is situated, as seen in plan view alongside the active zone (32) and on the same side of the carrier (2) as the semiconductor layer sequence (3). The first electrode (4) has a planar first region (41) and at least one island-shaped second region (42). The at least one island-shaped second region (42) extends right into the n-conducting layer (31). The second electrode (5) comprises as current-carrying layer a silver layer (51), which is situated between the planar first region (41) and the semiconductor layer sequence (3) and which is a mirror. A quotient of an average thickness of the silver layer (51) and an average edge length of the semiconductor layer sequence (3) is at least 2.5 x 10^-4 and the average thickness is at least 80 nm.

Description

description

Optoelectronic semiconductor chip and method for

Production of an optoelectronic semiconductor chip

An optoelectronic semiconductor chip is specified. In addition, a method for producing such a semiconductor chip is specified. The document WO 2011/120775 AI relates to a

optoelectronic semiconductor chip.

One problem to be solved is one

specify optoelectronic semiconductor chip with an efficiently producible StromaufWeitungsschicht.

This object is achieved inter alia by a semiconductor chip and by a method having the features of the independent patent claims. Preferred developments are the subject of the dependent claims.

According to at least one embodiment, the

Optoelectronic semiconductor chip configured to generate electromagnetic radiation during operation.

In particular, the semiconductor chip is a light-emitting diode. In operation of the semiconductor chip is

For example, generates near ultraviolet radiation, visible light or near-infrared radiation. According to at least one embodiment, the

Semiconductor chip on a semiconductor layer sequence. The

Semiconductor layer sequence includes an n-type layer and a p-type layer. Between the n-type Layer and the p-type layer is disposed an active zone. In the active zone, the radiation is generated during operation. The active zone includes at least one pn junction and / or at least one quantum well structure.

The semiconductor layer sequence is preferably based on a III-V compound semiconductor material. In the semiconductor material is, for example, a nitride compound semiconductor material such as Al _n _In] __ _n _ _m Ga _m N or a phosphide compound semiconductor material such as Al _n _In] __ _n _ _m Ga _m P or an arsenide compound semiconductor material such as Al _n In _] __ _n _ _m Ga _m As, where each 0 ^ n <1, 0 ^ m <1 and n + m -S 1. In this case, the semiconductor layer sequence may have dopants and additional constituents. For the sake of simplicity, however, only the essential constituents of the crystal lattice of the semiconductor layer sequence, ie Al, As, Ga, In, N or P, are given, even if these can be partially replaced and / or supplemented by small amounts of further substances. The semiconductor layer sequence is preferably based on AlInGaN.

According to at least one embodiment, the

Semiconductor chip a carrier. The semiconductor layer sequence is arranged indirectly or directly on the carrier, wherein the p-conducting layer is preferably closer to the carrier than the n-conducting layer. For example, the semiconductor layer sequence is soldered onto the carrier. The carrier may be different from a growth substrate of the preferably epitaxially grown semiconductor layer sequence.

According to at least one embodiment, the

Semiconductor chip on a first electrode. The first electrode is configured to contact the n-type layer. The first electrode is or is preferably based on one or more metals.

According to at least one embodiment, the

Semiconductor chip on a second electrode, the

Contacting the p-type layer is set up. Also, the second electrode is preferably based on one or more metals or consists of at least one metal. According to at least one embodiment, the

Semiconductor chip an electrical contact point, which is adapted for external electrical contacting of the second electrode. In other words, the semiconductor chip is externally electrically contacted via the second electrode and the electrical contact point.

According to at least one embodiment, the electrical contact point, in plan view of a

Radiation main side of the semiconductor layer sequence seen next to the active zone. The main radiation side is

For example, a carrier facing away from the main side of the semiconductor layer sequence.

In accordance with at least one embodiment, the electrical contact point is on the same side of the carrier as the

Semiconductor layer sequence arranged. In other words, then the carrier is not between the

Semiconductor layer sequence and the contact point. Alternatively, it is possible that the contact point is attached to one of the semiconductor layer sequence opposite bottom of the carrier and via an electrical

Through contact with the semiconductor layer sequence facing side of the carrier is electrically connected. According to at least one embodiment, the first

Electrode on a flat first area and at least one inseiform second area. Preferably, the first electrode has a plurality of soap-shaped first regions. The soap-shaped areas extend

For example, cylindrical, truncated pyramidal, prismatic and / or frusto-conical away from the flat, first area.

In accordance with at least one embodiment, the island-shaped region, starting from the planar first region, extends through the second electrode, the p-conducting layer and the active zone into the n-conducting layer. The p-type layer is in this case closer to the carrier and to the planar first region than the n-type layer.

Alternatively, it is also possible that the n-type and p-type layers are reversed in position. In this case, the first electrode is then preferably shaped like the second electrode and vice versa.

According to at least one embodiment, the second

Electrode as a current-carrying layer on a silver layer. The silver layer is set to the

To energize semiconductor layer sequence and a

Current injection into the semiconductor layer sequence in the lateral direction, in particular in the direction perpendicular to one

Growth direction of the semiconductor layer sequence to achieve.

In accordance with at least one embodiment, a portion of the silver layer is at a current distribution in the second

Electrode averaged in lateral direction over the Semiconductor layer sequence away at least 80% or

at least 90% or at least 95%. In other words, the silver layer is then not or only in a subordinate manner to the layer which is chiefly responsible for a lateral current distribution and further constituents of the second electrode contribute to a current distribution. For example, an average resistance along a lateral direction of the silver layer is at least a factor of 10 over all others

Layers of the second electrode reduced.

According to at least one embodiment, the

Silver layer partly or completely between the

flat area of the first electrode and the

Semiconductor layer sequence. Preferably, the silver layer is in direct contact with the semiconductor layer sequence. Alternatively, it is possible that between the

Silver layer and the semiconductor layer sequence, a layer for improving an electrical contact is attached, for example, a thin layer of a metal such as platinum or a thin layer of a transparent conductive oxide. In this case, a distance between the

Silver layer and the semiconductor layer sequence preferably at most 100 nm or 10 nm or 1 nm. According to at least one embodiment, the silver layer as a mirror for in the semiconductor layer sequence in

Operation generated radiation set up. By way of example, the silver layer has a reflectivity of at least 90% or at least 94% for the radiation generated in the semiconductor layer sequence. The silver layer preferably reflects specularly and not diffusely. According to at least one embodiment, the silver layer is formed comparatively thick. This may mean that a quotient of an average thickness of the silver layer and a mean edge length or an average diameter of the semiconductor layer sequence, seen in plan view,

at least 2.5 x 10 ^ or at least 5 x 10 ^ or

at least 8 x 10 ^ or at least 10 ^~ 3 or at least 2 x 10 ^~ 3. This means, for example, that with an average edge length of 500 μm, the silver layer has an average thickness of at least 250 nm, in the event that the quotient amounts to at least 5 × 10 -4. In addition, a thickness of the silver layer is preferably at least 80 nm or 150 nm or 200 nm. In at least one embodiment, FIG

optoelectronic semiconductor chip, preferably a

Light emitting diode is, a semiconductor layer sequence with an n-type layer, a p-type layer and an active zone arranged therebetween. The

Semiconductor layer sequence is arranged on a carrier. A first electrode is arranged for contacting the n-type layer and a second electrode for contacting the p-type layer. An electric

Contact point for the external electrical contacting of the second electrode is, seen in plan view, adjacent to the active zone and on the same side of the carrier as the semiconductor layer sequence. The first electrode has a flat first region and at least one second soap-shaped region. The at least one island-shaped second region extends through the second electrode, the p-conducting layer and the active zone into the n-conducting layer. The second electrode comprises as current-carrying

Layer a silver layer, at least in part is located between the planar first region of the first electrode and the semiconductor layer sequence and that is a mirror. A ratio of an average thickness of the silver layer and an average edge length of the semiconductor layer sequence is at least 80 nm is at least 2.5 x lO ^ _unc} b _e i.

Semiconductor chips, such as light-emitting diode chips, require a sufficiently conductive layer for the second electrode for uniform current injection, in particular if the second electrode lies between the first electrode and the second electrode

Semiconductor layer sequence is located. As material for the

Current spreading layer often finds gold use. Gold, however, is comparatively expensive. While maintaining a

A comparatively small, technically feasible layer thickness of the current spreading layer is one

Material selection limited. Copper is particularly suitable due to a possible cross-contamination only limited. In the case of silver, there is conventionally a risk of migration under the influence of moisture. Aluminum can also corrode under the influence of moisture. Especially for these reasons, often a gold layer for current spreading

used. This current spreading layer can also be called

Encapsulation of a silver mirror can be used. at

However, using a gold layer is between the

Silver mirror and the gold layer to provide a diffusion barrier, in order to mix the two layers

prevent. This represents a further limitation of the choice of materials and the sequence of the individual layers of the second electrode.

In the specified optoelectronic semiconductor chip, the silver mirror is manufactured with a significantly greater thickness than necessary for an optical effect and serves as current-carrying layer. This is, especially in comparison to a gold layer as a current-carrying layer, a

Cost savings achievable. In particular, by the position of the silver layer and by a shaping of the

Semiconductor layer sequence and the electrical contact point for contacting the second electrode, an encapsulation of the moisture-sensitive silver layer can be achieved.

According to at least one embodiment, the silver layer extends continuously and coherently to below the contact point. In other words, then overtops the

Silver layer, the active zone at least or only in the region of the contact point, seen in plan view of the main radiation side. The silver layer is then not restricted to the active zone, seen in plan view.

In accordance with at least one embodiment, the second one

Averaged across the semiconductor layer sequence, free of a layer having a weight fraction of gold of at least 10% or 1%. The second electrode may be free or substantially free of gold.

In accordance with at least one embodiment, the second electrode comprises a cover layer. The cover layer is preferably located directly at the contact point and / or at the

Silver layer. The silver layer is electrically connected by means of the cover layer to the contact point for contacting the second electrode. In accordance with at least one embodiment, the cover layer comprises or consists of one or more of the following materials: chromium, cobalt, platinum, ruthenium, tantalum, indium tin oxide, tantalum nitride, Titanium nitride, titanium tungsten nitride, zinc oxide, tin oxide, tungsten. By using such materials for the cover layer, efficient encapsulation of the silver layer can be achieved. It is possible that the cover layer is formed from exactly one layer of constant material composition or that the cover layer has a layer stack.

According to at least one embodiment, an average thickness of the cover layer is at most 100% or at most 50% or at most 25% or at most 10% or at most 5% of the mean thickness of the silver layer. It is then the cover layer, compared to the silver layer, thin.

In accordance with at least one embodiment, the silver layer extends as far as below the cover layer, viewed in plan view on the main radiation side. It is then the cover layer partially or completely between the

electrical contact point and the silver layer. According to at least one embodiment, the

Cover layer partially between the semiconductor layer sequence and the silver mirror. It is possible that the cover layer contacts the semiconductor layer sequence in places or has a distance to the semiconductor layer sequence of at most 10 nm or at most 1 nm.

In accordance with at least one embodiment, the cover layer is in an area adjacent to the active zone and / or adjacent to

Semiconductor layer sequence limited, seen in plan view of the main radiation side. It then overlap the

Semiconductor layer sequence and the cover layer not, in

Seen from above. In accordance with at least one embodiment, an area fraction of the semiconductor layer sequence which, when viewed in plan view, covers the cover layer is at most 5% or 2%, based on the area of the semiconductor layer sequence and / or the active zone.

According to at least one embodiment, the

Covering layer partly on a side facing away from the semiconductor layer sequence of the silver layer. It is then the

Silver layer in other words partly between the

Cover layer and the semiconductor layer sequence. The cover layer preferably covers only a small part of a side of the silver layer facing away from the semiconductor layer sequence, for example at most 10% or at most 2%.

According to at least one embodiment, the overlap

Cover layer and the silver layer, seen in plan view of the main radiation side, not. Then the cover layer and the silver layer only touch in one direction perpendicular to a direction of growth of the

Semiconductor layer sequence, ie in the lateral direction.

According to at least one embodiment, the p-type layer extends below the electrical contact point, seen in plan view. It is then the p-type

Layer in places between the electrical contact point and the second electrode. In particular, the p-type layer completely covers the silver layer, seen in plan view. It preferably has the p-type layer larger lateral dimensions than the active zone.

According to at least one embodiment, the p-type layer in the region of the electrical contact point a Protective layer for the silver layer. In other words, then a corrosion protection of the silver layer, in particular a protection against moisture, by the

Semiconductor layer sequence self-realized.

In accordance with at least one embodiment, the n-type layer and the active zone at the electrical contact point are completely removed, in plan view of FIG

Radiation main page seen. The p-type layer between the electrical pad and the silver layer is preferably completely or partially obtained.

In accordance with at least one embodiment, the p-type layer is re-doped at the electrical contact point. Due to the re-doping, the p-type layer has an n-type subregion. This portion is between the electrical contact point and the silver layer

and may be in direct physical contact with both the electrical pad and the silver layer. The subarea can be complete or

be partially covered by the electrical contact point.

According to at least one embodiment, there is an electrical connection between the planar first region of the first electrode and the silver layer of the second electrode

Insulating layer and / or an adhesion-promoting layer. The electrical insulating layer is, for example, a layer of a silicon oxide, a silicon nitride or an aluminum oxide. The primer layer comprises or consists of one or more of the following materials: chromium, indium tin oxide, titanium, zinc oxide. A thickness of the adhesion promoting layer is preferably at most 100 nm or at most 20 nm or at most 5 nm. The insulating layer has, for example, a thickness of at least 25 nm or at least 100 nm and / or at most 500 nm or at most 2000 nm. In accordance with at least one embodiment, the planar first region of the first electrode is formed by a solder layer or by a solderable layer.

According to at least one embodiment, the

Semiconductor layer sequence over the flat first region of the first electrode mechanically and / or thermally connected to the carrier. A thermal resistance of the layers between the flat first region and the

Semiconductor layer sequence is preferably only slightly pronounced. The carrier may be an electrically conductive carrier.

According to at least one embodiment, the

Silver layer and the electrical contact point in a common plane parallel to the active zone. It is possible that the pad does not protrude beyond the silver layer, away from the substrate. Alternatively or additionally, the cover layer is closer to the support than the electrical contact point and / or the silver layer.

In addition, a method for producing an optoelectronic semiconductor chip, as described in connection with one or more of the above embodiments, is given. Features of the method are therefore also disclosed for the semiconductor chip and vice versa.

In at least one embodiment, the method comprises at least the following steps: A) growing the semiconductor layer sequence onto a growth substrate,

B) applying the silver layer to the p-conducting layer facing away from the growth substrate,

C) generating the inseiform second regions of the second electrode, in particular comprising etching the

Semiconductor layer sequence,

D) attaching the carrier to the semiconductor layer sequence, for example by soldering or by bonding,

E) removing the growth substrate, for example by a laser lift-off method or by a mechanical or chemical process, and

F) at least partially removing the

Semiconductor layer sequence in one for the electrical

Contact point.

The individual process steps are preferably carried out in the order given. As far as technically possible, however, a different order may alternatively be used.

In accordance with at least one embodiment, in step F), the semiconductor layer sequence is removed as far as the p-conducting layer, from a side facing away from the carrier.

In particular, the p-type layer is completely retained, with a tolerance of, for example, at most 10% or at most 5% of the original thickness of the p-type layer. Partially removing the

Semiconductor layer sequence occurs approximately with an etching process, which is selective in terms of a conductivity type.

Hereinafter, an optoelectronic semiconductor chip described herein will be described with reference to the drawings Embodiments explained in more detail. The same reference numerals indicate the same elements in the individual figures. However, there are no scale relationships shown, but individual elements can be shown exaggerated for better understanding.

Show it:

Figures 1 to 9 and 11 are schematic sectional views of embodiments of optoelectronic semiconductor chips described herein, and

Figure 10 is a schematic sectional view of a

Modification of a semiconductor chip.

In Figure 1 is in a sectional view a

Embodiment of an optoelectronic semiconductor chip 1 shown. The semiconductor chip 1 has a

Semiconductor layer sequence 3 on. The semiconductor layer sequence 3 comprises an n-type layer 31, a p-type layer 33 and an intermediate active zone 32.

Immediately to the p-type layer 33 is a second electrode 5. The second electrode 5 includes a silver layer 51 which is adapted to a lateral current distribution and which has a comparatively large thickness. Furthermore, the second electrode 5 has a

Cover layer 52 on. Compared to the silver layer 51, the cover layer 52 is thin.

Between a carrier 2, which has a carrier top 20 and which mechanically stabilizes and carries the semiconductor chip 1, and the second electrode 5 is a first Electrode 4. The first electrode 4 has a flat first region 41 and an inner second region 42 in the form of a soap. Starting from the first region 41, the second region 42 extends through the silver layer 51, the p-type layer 33 and the active region 32 into the n-type layer 31. Deviating from the illustration, the semiconductor chip 1 preferably has a plurality of Islands 42 on. A current flow thus takes place via the first region 41, the second region 42 and through the

Semiconductor layer sequence 3 through to the second electrode. 5

On the cover layer 52 of the second electrode 5, an electrical contact point 6 is formed. The electrical contact point 6 is, for example, a bonding pad for the external electrical contacting of the semiconductor chip 1. A further electrical contact point for contacting the first electrode 4 is not shown in the figures in order to simplify the illustration. Such a further contact point is located, for example, at one of

Semiconductor layer sequence 3 on the opposite side of the support 3 or on the same side of the support 2 as the contact point 6. As preferred in all other embodiments, a roughening 8 is mounted on a remote from the carrier 2 main radiation side 80 of the semiconductor layer sequence 3 to improve light extraction. The radiation main side 80, unlike the one shown, may be arranged downstream of a conversion means for the at least partial conversion of radiation generated in the active zone 32 into radiation of other wavelengths or else at least one optical element. The first electrode 4 and the second electrode 5 are insulated from each other by an electrical insulating layer 71. At the main radiation side 80, on flanks of the

Semiconductor layer sequence 3 and optionally also at exposed areas of the electrical insulating layer 71, a further electrical insulating layer 72 is preferably attached. It is also optional, as in all others

Embodiments, between the silver layer 51 and the insulating layer 71 a not shown

Bonding layer.

In the exemplary embodiment according to FIG. 1, the second electrode 5 extends in an approximately equal thickness in the lateral direction over the semiconductor layer sequence 3 and the electrical contact point 6. The silver layer 51 is completely laterally and vertically surrounded by the insulating layer 71 and the cover layer 52 at the contact point 6. A thickness of the cover layer 52 is, for example, to

at least a factor of 0.2 or at least a factor of 0.5 or at least a factor of 10 or at least a factor of 100 smaller than an average thickness of

Silver layer 51.

The semiconductor chip 1 is produced in particular as follows: On a growth substrate, not shown

continuously grown the semiconductor layer sequence 3.

Subsequently, the cover layer 52 is preferably local

applied and subsequently the silver layer 51,

in particular over the entire surface over the semiconductor layer sequence 3 away. Subsequently, the silver layer 51 is patterned and recesses are produced in the semiconductor layer sequence 3 for the soap-like second regions 52. Subsequently, the insulating layer 71 is applied and the first electrode 4, 41, 42 are formed. Thereafter, the carrier 2 by means of the flat first portion 41 at the

Semiconductor layer sequence 3 are attached. Subsequently, the growth substrate is removed and the

Semiconductor layer sequence 3 is approximately by etching

structured, whereupon the further insulating layer 72 can be attached. Finally, the electrical contact point 6 is generated, which contains, for example, gold, nickel, palladium and / or tin.

In the exemplary embodiment according to FIG. 2, the cover layer 52, as in the exemplary embodiment according to FIG. 1, is located in places between the semiconductor layer sequence 3 and the silver layer 51a, 51b. A portion 51b of

Silver layer near the pad 6 extends further into the sheet-like first region 41 as remaining regions 51a of the silver layer. The silver layer 51a, 51b and the cover layer 52 have comparable thicknesses.

According to FIG. 3, the silver layer 51 is preferably applied in front of the cover layer 52a, 52b. As in the case of FIG. 2, the silver layer does not project beyond the semiconductor layer sequence 3 in a lateral direction. A partial region 52a of the cover layer extends further into the flat first region 41 as a partial region 52b of the cover layer directly at the contact point 6.

In the embodiment of Figure 4 overlap the

Cover layer 52 and the silver layer 51 in a lateral direction not. It is possible for the cover layer 52 and the silver layer 51 to be the same or approximately the same Have thickness. Other than illustrated, the cover layer 52 may also be formed thinner than the silver layer 51.

In the embodiment of Figure 5 is the

Semiconductor layer sequence 3 in the region of the contact point 6 is not completely removed, so that the p-type layer 33 is partially obtained. The p-type layer 33 preferably completely covers the silver layer 51, so that a

Corrosion protection of the silver layer 51 by the p-type layer 33 can be achieved. A thickness of the p-type layer 33 between the pad 6 and the silver layer 51 is, for example, at least 100 nm or at

at least 250 nm or at least 500 nm. The semiconductor layer sequence 3 is wet-chemically or dry-chemically etchable down to the p-type layer 33. An end point detection of an etching process is preferably carried out optically, in particular with photoluminescence on the basis of the active zone 32. In the case of a non-selective etching process, the photoluminescence of the active zone 32 then disappears

recognizable when the p-type layer 33 is exposed.

An etching of the semiconductor layer sequence 3 takes place for

Example, as in the publication Lei Ma in CS MANTECH

Conference, April 2006, "Comparison of different GaN Etching Techniques." The disclosure of this

Reference is included by reference.

In the embodiment according to FIG. 6, the n-conducting layer 31 and the active zone 32 are through

Conductivity-type selective etching in the range of

Contact point 6 completely removed. This results in a large thickness of the p-type layer 33 at the contact point 6 achievable and thus a better protection of the silver layer 51. Such etching is carried out, for example, as in the

References "Highly anisotropic photo-enhanced wet etching n-type GaN" in Applied Physics Letters 71, 1997, pages 2151 to 2153 or as in "Dopant-Selective Photoenhanced Wet

Etching of GaN "in Journal of Electronic Materials 27, 1998, pages 282 to 287, the disclosure content of which is incorporated by reference back In the embodiment, as illustrated in Figure 7, the p-type layer 33 is directly between the

Contact point 6 and the silver layer 51 in a portion 36 umdotiert. In the portion 36 is the p-type

Layer 33 therefore n-type. The partial region 36 is preferably limited to the contact point 6, for example with a tolerance of at most 25% or at most 50% of the surface of the contact point 6. The portion 36 may be surrounded all around by p-type regions of the p-type layer 33, in FIG

Seen from above. Between the p-type layer 33 and the partial region 36, preferably no or no occurs

significant current flow due, for example, to a lower contact resistance to the silver layer 51 or due to a lateral dopant profile. In the embodiment, as illustrated in FIG. 8, the p-type layer 33 is complete and the n-type layer 31 is at least partially obtained. The n-conducting

Layer 33 directly between the contact point 6 and the silver layer 51 is re-doped in the portion 36. In the partial region 36, the n-conducting layer 31 is therefore p-conducting. The n-type layer 31 in direct contact with the portion 36 is changed all around in a region 36a such that this region 36a acts as an electrical insulator. Of the Subarea 36 is preferably limited to the area of pad 6, for example with a tolerance of at most 25% or at most 50%. The silver layer 51 extends continuously below the contact point 6.

In a production of the semiconductor chip 1 according to FIG. 9, first of all the silver layer 51 is also produced at the electrical contact point 6. Then, in direct contact with the silver layer 51, in the direction of the support 2, the cover layer 52 is formed in a locally limited manner. The cover layer 52 is designed such that it at least the later

Contact point 6 complete and a partial area to

Semiconductor layer sequence 3 towards covered. After one

Structuring the semiconductor layer sequence 3, exposed areas of the silver layer 51 are selectively removed to a material of the cap layer 52, so that at the

Contact point 6, the cover layer 52 is exposed. Then, the silver layer 51 is sealed with the insulating layer 72. For an electrical contact between the silver layer 51 and the cover layer 52, a small lateral overlap is necessary. At the later contact point 6 is the

Insulating layer 72 then removed and the electrical

Contact point 6 is generated. The cover layer 52 and the silver layer 51 have approximately equal thicknesses.

FIG. 10 shows a modification of the semiconductor chip

illustrated. The silver layer 51 is only

comparatively thin. A current spreading in the lateral direction takes place via a current distribution layer 56 made of gold. Between the current distribution layer 56 and the silver layer 51 is not shown

Diffusion barrier. By using the thicker ones

Silver layer 51 according to the figures 1 to 7 and by the Cover layer 52 and / or the p-type layer 33 at the contact point 6, a structure of the second electrode 5 is simplified and a cost savings in terms of the material of the current distribution layer 51 can be achieved.

FIG. 11 shows a further exemplary embodiment of the invention

Semiconductor chips 1 shown in a schematic sectional view. The outer insulating layers 71a, 71b located furthest from the substrate 2 optionally have different thicknesses, as is possible in all other exemplary embodiments. This is enough

Insulating layer 71b, from the substrate 2, for example, only up to the semiconductor layer sequence 3 and thus laterally bounds the silver layer 51.

In the production of the semiconductor chip 1 according to FIG. 11, the silver layer 51 is first attached to the semiconductor layer sequence 3. Subsequently, the upper direction away from the substrate 2 away insulating layer 72a is applied and patterned. In this case, the upper insulating layer 72a has the same or a similar thickness as the cover layer 52, which overlaps with the silver layer 51 seen in plan view. Thereafter, the closer to the substrate 2 located, lower insulating layer 72b is applied. By this division into the upper one

Insulating layer 72a and into the lower insulating layer 72b is a planarization toward the substrate 2

reachable .

The semiconductor layer sequence 3 is subsequently fastened to the substrate 2 by means of the areal area 41, in particular formed by a solder. The invention described here is not by the

Description limited to the embodiments.

Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments. This patent application claims the priority of German Patent Application 10 2012 110 775.0, the disclosure of which is hereby incorporated by reference.

Claims

claims

1. Optoelectronic semiconductor chip (1) with

a semiconductor layer sequence (3) having an n-type layer (31), a p-type layer (33) and an active zone (32) arranged therebetween,

a support (2) on which the

Semiconductor layer sequence (3) is arranged,

a first electrode for contacting the n-conductive layer and a second electrode for contacting the p-conductive layer;

- An electrical contact point (6) for external electrical contacting of the second electrode (4), seen in plan view next to the active zone (32) and on the same side of the carrier (2) as the

Semiconductor layer sequence (3) is arranged,

in which

- The first electrode (4) has a flat first

Region (41) and at least one second soap-shaped region (42),

the at least one insular region (42) extends through the second electrode (5), the p-conducting layer (33) and the active zone (32) into the n-conducting layer (31),

- The second electrode (5) as a current-carrying layer comprises a silver layer (51) which is at least partially between the flat first region (41) of the first electrode (4) and the semiconductor layer sequence (3) and which is a mirror, and

a quotient of an average thickness of

Silver layer (51) and a mean edge length of the semiconductor layer sequence (3) at least 2.5 x 10- ^ and the average thickness is not less than 80 nm.

Optoelectronic semiconductor chip (1) after the

previous claim,

in which the silver layer (51) extends continuously and coherently as far as below the contact point (6), seen in plan view.

Optoelectronic semiconductor chip (1) after the

previous claim,

wherein the p-type layer (33) extends below the electrical contact point (6) and the

Silver layer (51) completely covered, seen in plan view,

so that the p-type layer (33) forms a protective layer for the silver layer (51) in the region of the electrical contact point (6).

Optoelectronic semiconductor chip (1) according to one of the preceding claims,

in which the second electrode (5) comprises a cover layer (52),

wherein the cover layer (52) is located directly at the electrical contact point (6) and the

Silver layer (51) electrically connected to the electrical contact point (6), and

wherein the cover layer (52) comprises or consists of at least one of the following materials: Co, Cr, Pt, Ru, Ta, InSnO, TaN, TiN, TiNW, ZnO, SnO 2, W. Optoelectronic semiconductor chip (1) after the

previous claim,

wherein the cover layer (52) and the silver layer (51) do not overlap, seen in plan view.

Optoelectronic semiconductor chip (1) according to one of the preceding claims,

in which the second electrode (5) averaged over the semiconductor layer sequence (3) is free of one

Layer containing a percentage by weight of gold

at least 10%,

the silver layer (51) being the layer of the second electrode (5) located between the support (2) and the semiconductor layer sequence (3) and having the lowest electrical resistance and the greatest thickness,

so that a portion of the silver layer (51) on a

Current distribution in the second electrode (5) across the semiconductor layer sequence (3) is at least 90%.

Optoelectronic semiconductor chip (1) after the

previous claim,

in which a mean thickness of the cover layer (52) is at most 50% of the average thickness of the silver layer (51),

wherein the silver layer (51) to below the

Cover layer (52) extends, seen in plan view.

Optoelectronic semiconductor chip (1) according to at least claim 4,

wherein the cover layer (52) partially between the semiconductor layer sequence (3) and the silver mirror (51) extends,

wherein a surface portion of the semiconductor layer sequence (3), which seen in plan view of the cover layer (52), at most 5%.

Optoelectronic semiconductor chip (1) according to at least claim 4,

in which the cover layer (52) is partly located on a side of the silver layer (51) facing away from the semiconductor layer sequence (3).

Optoelectronic semiconductor chip (1) after the

previous claim,

in which the n-type layer (31) and the active region (32) at the electrical contact point (6) are completely removed, seen in plan view, and the p-type layer (33) between the electrical

Contact point (6) and the silver layer (51)

completely or partially preserved.

Optoelectronic semiconductor chip (1) after the

previous claim,

wherein the p-type layer (33) at the electrical contact point (6) is re-doped, so that the p-type layer (33) at the electrical contact point (6) has an n-type portion (36) between the

electrical contact point (6) and the silver layer (51),

wherein the n-type portion (36) of a

electrically insulating region (36a) is surrounded all around. Optoelectronic semiconductor chip (1) according to one of the preceding claims,

in which between the planar first region (41) of the first electrode (4) and the silver layer (51) an electrical insulating layer (71) and a

Adhesion Layer are located,

wherein the planar first region (41) is a solder layer over which the semiconductor layer sequence (3)

mechanically and thermally connected to the carrier (2).

Optoelectronic semiconductor chip (1) according to one of the preceding claims,

in which the silver layer (51) and the electrical contact point (6) are located in a common plane parallel to the active zone (32),

wherein the cover layer (52) is closer to the support (2) than the electrical contact pad (6) and the silver layer (51).

Method for producing an optoelectronic semiconductor chip (1) according to one of the preceding

Claims with the steps:

A) growing the semiconductor layer sequence (3) on a growth substrate,

B) Applying the silver layer (51) on the

Growth substrate facing away p-type layer (33),

C) generating the inseptional second regions (42) of the second electrode (4),

D) attaching the carrier (2) to the

Semiconductor layer sequence (3),

E) removing the growth substrate, and

F) at least partially removing the Semiconductor layer sequence (3) in one for the

electrical contact point (6) provided area.

15. Method according to the preceding claim,

in which in step F) the semiconductor layer sequence (3) up to the p-type layer (33), of a

Carrier (2) facing away, with a

in terms of a conductivity type selective

Etching process is removed.