WO2014071458A1

WO2014071458A1 - Formation of metal contacts

Info

Publication number: WO2014071458A1
Application number: PCT/AU2013/001293
Authority: WO
Inventors: Yu Yao; Alison Joan Lennon; Xi LUO; Stuart Ross Wenham; Jie Cui
Original assignee: Newsouth Innovations Pty Ltd
Priority date: 2012-11-09
Filing date: 2013-11-08
Publication date: 2014-05-15

Abstract

A method of depositing metal on a surface of a silicon solar cell device is provided. The silicon solar cell has a dielectric surface layer located over the surface of the silicon solar cell device and localised openings in the dielectric layer exposing a silicon surface to be plated in a pattern corresponding to a desired metallisation pattern. The method comprises: (i) contacting the silicon surface to be plated with an electrolyte containing ions of the metal and depositing the metal onto the silicon surface exposed in the localised openings using an electrochemical reaction that includes the oxidation of silicon from the exposed silicon surface; (ii) controlling the concentrations of holes and electrons at the exposed silicon surface by using controlled illumination to control the rate and thickness of deposition on the exposed silicon surface. Oxidation of the silicon at the exposed silicon surface results in the exposed silicon surface being etched to thereby roughen the exposed silicon surface, and electrons freed by the etched silicon are incorporated into the reduction reaction which continues only until the exposed silicon surface is uniformly coated with a layer of the metal.

Description

Formation of metal contacts

Introduction

The present invention relates to the field of Photovoltaics and in particular the invention relates to the formation of metal contacts on doped surface regions of a semiconductor junction.

Background

For decades, screen printed silver contacts have been the dominant front-side (i.e. light receiving side) metallisation scheme for crystalline silicon solar cells in the photovoltaic industry. However, to reduce the cost per watt of silicon solar cells to meet grid parity, this technology is facing challenges that come from the increasingly high price of silver and the trend towards using thinner substrates. With current screen- printing technology, despite the improvements in screen designs and paste formulations, the printed lines are typically 110-150 micron wide requiring them to be spaced widely apart to reduce the shading loss. As a result, the emitter needs to be heavily-doped, such as with a phosphorus concentration of at least lxl O²⁰ cm^'3 at the surface, to reduce the resistive loss. However, this heavy doping can lower both the current and the voltage of the device because of the increased emitter recombination loss. It is therefore more desirable to develop an alternative front-side patterning and metal contacting technology that uses cheaper materials, such as copper to form good ohmic contacts on lightly-doped emitters, to overcome the technological and economical limitations of screen printing technology using silver. When copper is selected as the conducting material, a thin seed layer of a metal such as nickel is required that can reduce the contact resistance and prevent copper from diffusing into the silicon.

Alternative seed layers, such as titanium, titanium nitride or tantalum nitride have been investigated, however, for large scale production, their use is more complicated and expensive to deposit than nickel.

As front-side metallisation research progresses away from thick film printing technology, electrochemical methods of depositing metal conducting layers with high aspect ratio in a self-aligned manner are being increasingly investigated as viable metallisation strategies. However, for the thin seed layers, which employ metals such as nickel, the deposition methods can be diverse. It has been reported that a nickel seed layer can be formed on silicon solar cells by electroless plating, light-induced plating (LIP), field induced plating (FEP), and physical vapour deposition. Existing plating techniques (LIP, electroless plating, FIP etc.) are generally erratic in uniformity of coverage and thickness, possibly due to a tendency that they share where the plating rate accelerates in regions where the surface conductivity is greatest. This means that if plating nucleates in one location before another, then that region increases in conductivity and therefore becomes the favoured location for further plating, which may result in non-uniform thickness and/or poor coverage. Physical vapour deposition of metal can produce a blanket seed layer with controlled thickness and uniformity, however the use of this method to form metal contacts on silicon solar cells requires either mask alignment or silicidation treatment followed by removal of the deposited metal film from regions that do not need metal contacts.

The galvanic displacement process for depositing metal is not new and has been used in many industries to deposit metal onto various materials. It has been suggested in the past as a method for both texturing silicon surfaces and for forming conducting metallic regions for various silicon based semiconductor devices. However it has never been used commercially for metallising photovoltaic devices and it is far from obvious that this process would be either usable or useful for metallising emitters of solar cells.

It is well known in the field of solar cell manufacture that the emitter design in light receiving areas of a high efficiency solar cell is quite critical in terms of both doping profile and depth of the junction. Such light receiving emitter regions are typically very shallow (typically only 0.1-0.3 microns thick) with corresponding sheet resistivities needing to be at least 100 ohms per square and preferably higher. Contact to such emitters is generally made by creating significantly deeper, heavily-doped channels through the emitter, of the same dopant type as the emitter, and contacting to these deeper channels. Experts would agree that metallising directly onto such shallow emitter regions to form low resistance ohmic contacts would be near impossible and even if possible, would be extremely risky due to the proximity of the metal to the junction. Even more extraordinary would be the thought that a metallisation process would be used with such shallow emitter layers whereby the process would lead to etching/thinning of this emitter region in localised areas causing the metal to be located in even closer proximity to the junction.

Summary ,

According to a first aspect of the invention a method is provided for depositing metal on a surface of a silicon solar cell device having a dielectric surface layer located over the surface of the silicon solar cell device and localised openings in the dielectric layer exposing a silicon surface to be plated in a pattern corresponding to a desired metallisation pattern, the method comprising:

(i) contacting the silicon surface to be plated with an electrolyte containing ions of the metal and depositing the metal onto the silicon surface exposed in the localised openings using an electrochemical reaction that includes the oxidation of silicon from the exposed silicon surface;

(ii) controlling the concentrations of holes and electrons at the exposed silicon surface by using controlled illumination to control the rate and thickness of deposition on the exposed silicon surface;

whereby oxidation of the silicon at the exposed silicon surface results in the exposed silicon surface being etched to thereby roughen the exposed silicon surface, and electrons freed by the etched silicon are incorporated into the reduction reaction which continues only until the exposed silicon surface is uniformly coated with a layer of the metal.

Concentrations of holes and electrons at the exposed silicon surface may be controlled by using controlled illumination to control the rate and thickness of deposition on the exposed silicon surface.

The semiconductor junction may be located a distance of less than 1 μηι from a surface of the silicon solar cell device over which the dielectric layer is formed, but the method may also be used with deeper junctions.

According to a second aspect of the invention a method is provided for forming openings in a dielectric surface layer of a silicon solar cell device to expose a silicon surface and depositing metal on the exposed silicon surface, the method comprising: i. applying, over the dielectric layer, a layer of polymer;

ii. depositing onto the polymer surface a solution containing fluoride ions, the solution being deposited in a pattern corresponding to the desired metallisation pattern; and

iii. providing, in the solution containing fluoride ions and/or in the layer of polymer, ions of the metal to be deposited,

whereby the solution containing the fluoride ions acts with the polymer to etch the dielectric surface layer to form openings in the dielectric layer exposing the silicon surface of the silicon solar cell device in the pattern corresponding to the metallisation pattern, and the metal is deposited onto the exposed silicon surface in an electrochemical reaction that includes oxidation of silicon and reduction of metal ions.

It will be appreciated that methods of the first and second aspects are compatible and features of the two methods may also be used together in the formation of a device. The pH of the electrolyte is preferably >7.

The concentrations of electrons and holes may be controlled by illuminating the silicon solar cell device with an illumination source having a predetermined intensity and spectrum of the illumination reaching the silicon surface of the silicon solar cell. The intensity of the illumination reaching the surface of the silicon solar cell device from the source may be within the range of 0.001 -10 W/cm² The spectrum of the illumination reaching the surface of the silicon solar cell device from the source may be within the range of 350nm-1400nm.

The silicon of the exposed silicon surface may be doped to a predetermined level selected to affect the concentrations of electrons and holes at the exposed silicon surface, and in particular a p-n junction may be located within 300nm of the exposed silicon surface. The silicon solar cell device may have a shallow emitter of uniform depth in the range 100-300nm and the dielectric surface layer may be formed over the emitter.

The semiconductor junction may also be a high-low junction. The high-low junction may be located within 300nm of the exposed silicon surface.

The silicon solar cell device may also include areas of the exposed silicon surface that are not to be plated and which are passivated prior to being contacted with < the electrolyte to prevent plating of these areas.

The metal in the electrolyte may comprise ions of nickel, copper, silver or platinum. The electrolyte may comprise a solution in water of a salt of the metal to be deposited and a non-acidic fluoride.

The plating may be applied to a thickness which is less than or equal to 350nm.

Two opposite surfaces of the silicon solar cell device may also be plated simultaneously.

The temperature at which the plating is performed is above 30°C, or above 50°C or above 60°C depending upon other parameters of the process or of the solar cell.

The deposited metal may be sintered to form a silicide at the interface of the deposited metal and the exposed silicon surface. The silicide may have a thickness which is in the range of 50-90nm or 10-300nm or 10-250nm or 10-200nm or 10-150nm or 10-lOOnm or 10-80nm or I0-50nm or 10-40nm or 10-30nm or 10-20nm or 20-

300nm or 20-250nm or 20-200nm or 20-150nm or 20-100nm or 20-80nm or 20-50nm or 20-40nm or 20-30nm or 30-300nm or 30-250nm or 30-200nm or 30-150nm or 30- lOOnm or 30-80nm or 30-50nm or 30-40nm or 40-300nm or 40-250nm or 40-200nm or 40-150nm or 40-100nm or 40-80nm or 40-50nm or 50-300nm or 50-250nm or 50-

200nm or 50-150nm or 50-100nm or 50-80nm or 80-300nm or 80-250nm or 80-200nm or 80-150nm or 80-100nm or 100-300nm or 100-250nm or 100-200nm or 100-150nm or 150-300nm or 150-250nm or 150-200nm or 200-300nm or 200-250nm or 250- 300nm.

The metal ions may be provided as a water-soluble salt of the metal in the layer of polymer, or by incorporating the metal ions into the solution containing fluoride ions or both.

The solution containing the fluoride ions is preferably of neutral or alkaline pH. The polymer is preferably water-soluble. The water-soluble polymer may comprise water-soluble polymers or resins containing acidic groups (e.g., polyacrylic acid

(PAA), acidic polythiophene or polyaniline derivatives, polystyrene sulfonate, polyester or phenolic resins). It is also possible to use polymer mixtures or blends to form the acidic film. For example, PAA can be blended with other water soluble polymers such as polyvinyl alcohol (PVA) in PAA:PVA ratios ranging from 1 : 1 to 1:4 depending on the extent of etching required. Copolymers of the acidic polymer (e.g., PAA) can also be used to form the polymer film. The use of copolymers or polymer blends for forming the thin film is a way in which the acidity of the formed film can be controlled. Furthermore, polymer films can contain additives, such as nanoparticles, which can either directly provide further acidic groups or indirectly enhance the acidity of the film.

The silicon oxidation and/or metal deposition processes may cause the silicon surface to be roughened to thereby improve adhesion of the deposited metal to the silicon surface.

A p-n junction may be located within 10 micron of the exposed silicon surface or alternatively a high-low junction (i.e. a junction between a more heavily doped region and a less heavily doped region of the same dopant type) may be located within 20 micron of the exposed silicon surface.

The metal salt may be a water-soluble metal salt selected from nickel sulfate, nickel chloride, nickel sulfamate, copper sulfate, silver nitrate and the non-acidic fluoride may be selected from ammonium fluoride or sodium fluoride.

Brief Description of the Drawings

Embodiments of the invention will now be described, by way of example with reference to the accompanying drawings in which:

Figure 1 shows phosphorus dopant profiles for samples with:

(a) 10 Ω/square (A) emitter,

(b) 1 10 Ω/square (■) emitter and (c) 200 Ω/square (♦) emitter, measured by the electrochemical capacitance- voltage technique;

Figure 2 is a schematic drawing of an immersion plating arrangement;

Figure 3 is an Arrhenius plot showing the logarithm of reaction rate (In (k)) against inverse temperature (1/T) for the data presented in Table 2;

Figure 4 shows the measured thickness of a deposited nickel layer on 10 Ω/square silicon wafers, as a function of immersion plating duration (with a fitted curve). The process was undertaken at 50°C under illumination;

Figure 5 is a schematic of the operating principle for combined direct etching and nickel deposition processes in one step;

Figure 6 is a schematic drawing of the lab setup for nickel seed layer deposition on silicon solar cells. Illumination was provided from the sides of the beaker;

Figure 7 is a diagrammatic representation of the silicon solar cell of figure 7 after sintering and plating to thicken the contact;

Figure 8 shows an IV curve of the best solar cell made with a galvanic displaced nickel seed layer (Jsc: 38.34mA/cm², Voc: 628.6mV, FF: 77.01%, Efficiency: 18.6%);

Figure 9 schematically illustrates an apparatus for simultaneously etching a dielectric layer and plating the exposed silicon using the operating principal described with reference to Figure 6;

Figure 10 graphically shows a minority carrier concentration versus distance from the surface for a 0.5μπι junction depth under illumination of 0.1 W/cm² at various wavelengths (355nm, 532nm & 1064nm); and

Figure 11 graphically shows a minority carrier concentration versus distance from the surface for a 5μηι junction depth under illumination of 0.1 W/cm² at various wavelengths (355nm, 532nm & 1064nm).

Detailed description

A method has been developed for controlling the deposition of uniformly thin and continuous metal layer with good adhesion to form metal contacts on silicon solar cells. The process is described below with reference to nickel, however the process is equally applicable to the deposit of other metals, which may be desirable in certain circumstances, such as copper, silver or platinum, in which case an alternative metal compound will be substituted for each of the nickel compounds in the following description. With the thin metal layer, a very low resistance silicide can be achieved after sintering. This process provides a seed layer and would then normally be followed by a metal thickening process to enhance the conductivity of metal grids using electroplating, light-induced plating, or field-induced plating.

The control of seed layer deposition process to achieve this uniformly thin and continuous layer with good adhesion and low resistance to silicon solar cells is realized through the control of carrier (i.e. electrons and holes) concentrations at the silicon surface that is to be plated. Carrier concentrations during the metal deposition process are determined by both the plating conditions and the features of silicon solar cells.

In the galvanic displacement approach to plating nickel contacts using fluoride based chemistry without a reducing agent, the plating rate tends to diminish as the plated metal grows and covers the exposed silicon surface, eventually as the coverage of the metal saturates the plating process stops. Therefore the proposed process tends to be self-limiting. In fact, the process is such that the plating will continue until the entire silicon surface is plated, which enables both 100% coverage while

simultaneously achieving good and controllable uniformity in thickness, typically between 20nm and 300nm thick. The plating step is followed by a sintering step to convert the plated nickel near the silicon interface to nickel silicide, which improves the electrical contact of the nickel with the silicon.

The galvanic displacement process simultaneously textures (roughens) the silicon surface (which is important for improved adhesion and contact resistance) and uniformly plates the silicon with metal (further improving adhesion and contact resistance). This process is therefore not only very simple but potentially very important for various cell technologies that rely on plating as it ameliorates the < fundamental problems previously associated with plated contacts that have stopped them being widely used, namely:

1. poor adhesion

2. poor uniformity in coverage

3. poor uniformity in thickness

4. poor contact resistance to more lightly-doped regions. The proposed process works by progressively restricting the etching process as the plating becomes thicker such that it is the metal plating itself that eventually causes the process to cease before the etching of the silicon can reach down to the junction. Without the metal deposits, the etching would likely continue to penetrate through the junction and destroy the device. The etching of the silicon drives the reduction reaction that plates the metal, which then progressively restricts the chemicals from getting to the silicon surface thereby starving the reaction of the electrons that are needed to allow the metal to form on the silicon surface. The reduced etching of the silicon therefore slows the plating rate. Eventually, when 100% of the exposed silicon surface is covered by the metal, no more chemicals can etch the silicon surface and so both the plating and the etching cease in a VERY controllable and repeatable manner that can even be applied to lightly-doped emitters of solar cells.

Plating conditions that can be manipulated to control the carrier concentrations at the silicon surface include:

1. The temperature at which the plating occurs, as it affects the thermally generated carrier concentrations at the silicon surface.

2. The illumination condition (intensity and wavelength) at the silicon surface, as carriers can be generated under illumination.

The surface concentrations of light generated carriers are determined not just by the intensity of the light (i.e. photon flux), but also by the absorption depth in the silicon substrate that is a function of the wavelength of light. The wavelength and intensity of light reaching the silicon surface depend upon:

i) the spectrum and intensity of the illumination source; and ii) the medium through which the light needs to transmit before

reaching the silicon surface.

Features of silicon solar cells that affect localised carrier concentrations at the surface include:

1. The doping profile between a p-n j unction and the surface to be plated over;

2. The doping profile between a high-low junction and the surface to be plated over;

3. The carrier diffusion lengths in the silicon region below the silicon surface to be plated;

4. The surface passivation quality of surface areas adjacent to the silicon

surface to be plated;

5. Light receiving properties of the silicon surface and surface areas adjacent to the silicon surface to be plated.

When the metal deposition process is undertaken under circumstances where there are light generated carriers, the positioning and strength of an electric field induced by either a p-n junction or a high-low junction can cause the distribution of carrier concentrations to change from its distribution in the dark. By adjusting the intensity and/or wavelength of light reaching the silicon surface, the carrier concentrations may be tuned to serve for the desired plating result. Carrier generation by illumination is also affected by the light receiving property of the silicon surface, which depends on surface morphology and surface coatings.

To determine the localised carrier concentration, the recombination loss needs to be taken into account, in addition to carrier generation. The carrier concentrations and hence the seed layer deposition process are greatly affected by recombination sites at the silicon surface, such as grain boundaries and defects for multi -crystalline material, defects introduced during thermal diffusion or ion implantation or a laser doping process to generate the p-n junction or high-low junction, and metal deposits on the silicon surface during plating.

Surface passivation of the areas adjacent to the silicon surface to be metallised helps to maintain a high level of carrier concentrations. Those carriers can then diffuse to the exposed silicon region and affect the seed layer deposition process. Immersion nickel plating to thermally diffused n-type emitter

Experiments were performed to test immersion nickel deposition on

phosphorus-diffused emitters of silicon solar cells. The experiments were designed to study the effect of.

(i) the emitter profile;

(ii) the illumination conditions;

(iii) the electrolyte temperature; and

(iv) the plating duration on the nickel deposition rate, in order to better understand the control mechanisms and potential benefits of this seed layer deposition method when applied to solar cells with shallow emitters (i.e. less than 1 micron deep from the surface to be plated).

P-type 1 Q.cm Cz silicon wafers with a surface area of 16.3 cm² were alkaline- textured and diffused in a tube furnace using phosphorus solid sources to form different emitter profiles. The phosphosilicate glass (PSG) layer was removed after diffusion by immersion in 1% (w/v) HF for 1 min. Figure 1 illustrates the emitter doping profiles for wafers with 10 Ω square, 1 10 Ω square and 200 Ω/square emitter, as measured by the electrochemical capacitance-voltage (ECV) technique. Referring to Figure 2, which illustrates the immersion plating arrangement used for the experiments, the non- diffused surfaces of the wafers 201 were protected against anodic processes by spin- coating a layer of novolac resin 206 on the surface. The novolac resin 206 was used because it is resistant to the chemicals in the plating electrolytes studied. Four groups of wafers 201 were immersion plated in a bath of the plating solution 202 to investigate the effects of emitter profile, illumination, time and temperature on the rate of the galvanic displacement reaction.

For wafers 201 that were immersion plated under illumination 207, the illumination 207 was provided by a compact fluorescent light, which provided a broad illumination spectrum and an intensity of 30k lux at the air/electrolyte interface. The depth of the electrolyte above the surface of the wafers 201 was kept at 5 mm for all the immersion plated wafers. To correlate the deposition conditions with the rate of reaction, inductively-coupled plasma optical emission spectroscopy (ICP-OES) was employed to quantify the amount of nickel deposited on each of the silicon wafers 201. The aqueous samples for ICP-OES measurements were nickel loaded nitric acid solutions, which were prepared by immersing the wafers 201 that had nickel deposits into 35% (w/v) nitric acid to dissolve the nickel metal in the solution.

The immersion plating solution 202 used for the experiments comprised 10% (w/v) NH4F and 100 mM N1SO₄ with the pH adjusted to a value of 8. Three wafers 201 with three different emitter sheet resistances (10 Ω/square, 1 0 Ω square, and 200 Ω square) were used to investigate the effect of emitter profile on the galvanic displacement reaction rate. The wafers 201 were plated in the dark at 17 °C for 30 min. A further set of three wafers 201 for each of the different sheet resistances were plated under the compact fluorescent light at 17 °C for 30 min to compare the rate of nickel deposition under illumination 207 with the case where the silicon surface is in the dark. To investigate the effect of temperature, six wafers 201 with 10 Ω square emitters were plated for 5 min under illumination 207 at a range of temperatures between 20 °C and 60 °C. Finally, seven wafers 201 with 10 Ω square emitters were immersion-plated under illumination 207 at 50 °C to determine the correlation between immersion- plating duration and the thickness of deposited nickel layer.

Effect of Emitter Profile and Illumination Table 1 lists the mass of deposited nickel and the calculated average nickel deposition rate achieved in the above experiment for the different emitter profiles under illumination and in the dark. In general, wafers plated in the dark demonstrated slower nickel deposition rates than their counterparts plated under illumination. Also the lightly -doped wafers were plated faster than the more heavily-doped wafers, regardless of the illumination condition. However, the plating rate enhancement due to the illumination under conditions selected for this experiment varied from ~5 times for the 10 Ω/square emitter sample to less than 2 times for the 1 10 Ω/square and 200 Ω/square emitter samples. This is because for n-type silicon, the nickel deposition rate is limited by the availability of minority carrier holes at the surface to complete the silicon oxidation reaction. When the wafers were immersion plated in the dark, the supply of holes was primarily determined by the doping level of the silicon surface. In this case, the wafers with 10 Ω/square emitters had a much lower surface concentration of holes than the more lightly-doped wafers (as indicated in Figure 1), and therefore the rate of nickel deposition was limited by the rate of silicon oxidation, which is dependent upon hole injection. For samples plated under illumination, electron-hole pairs were generated to increase the surface concentration of carriers, resulting in faster nickel deposition in all cases. However, for the more heavily-doped, wafers which were characterised by deeper junctions (see Figure 1), the surface concentration of holes was less affected by the internal electric field, due to reduced collection probability of minority carriers (i.e. holes for n-type emitter) as the distance from the space-charge- region increases. This explains why the rate enhancement factor was higher for the more heavily-doped wafers when the plating occurred under illumination.

On the other hand, Figure 10 & 1 1 show that the effect of illuminating the silicon surface with selected monochromatic light can result in higher minority carrier concentrations at the surface of a device with deeper junction, indicating that a higher plating rate can be achieved. This highlights the importance of controlling the plating rate and metal thickness via matching the illumination condition with photovoltaic device designs.

Rate of Ni Deposition

Sample Sheet Mass of Deposited Ni (mg)

(nm s)

Resistivity

_ _^ , Under _{T Λ} , Under

(Ω/α) In Dark In Dark

Illumination Illumination

10 0.143 0.846 5.47E-3 3.24E-2

110 0.590 1.06 2.26E-2 4.04E-2

200 0.639 1.11 2.44E-2 4.26E-2 Table 1 Calculated mass of plated nickel and rate of nickel deposition on silicon with different emitter profiles, resulting from nickel immersion plating at 17 °C for 30 min in the dark or under illumination. The implications for solar cell metallisation from these experiments are twofold. First, nickel can be plated to lightly-doped n-type emitters, and in fact, the nickel immersion plating rate is faster for lightly-doped emitters than for heavily-doped emitters under the tested illumination conditions. Second, for all emitters the plating rate can be increased by illumination. The ability to plate to lightly-doped emitters and to thereby form good ohmic contact is potentially advantageous because it can eliminate the need to form selective emitters to improve short wavelength response.

In general, illuminating the silicon surface generates electron-hole pairs, which creates an increase in the surface concentrations of carriers compared to the case when the silicon surface is in the dark. Incorporation of dopant into the surface creates a p-n junction (if the doping is opposite to the substrate doping polarity, such as in the case of an emitter or a floating junction) or a high-low junction (that is a doping transition where the doping polarity remains the same as in the substrate, but at different dopant concentrations, such as in the case of a back surfa.ce field, a front surface field or a selective emitter) which generates an internal electric field within the semiconductor device that sweeps carriers across the junction, resulting in reduced minority carrier concentrations. The net minority carrier concentration, which results for devices with a semiconductor junction under illumination, depends on the illumination conditions and the characteristics of semiconductor junctions. Some examples will be provided below.

Because the galvanic displacement plating process is a redox reaction that requires both electrons and holes, the rate-limiting reaction is the one that involves minority carriers. Typically, when plating to p-type silicon, the metal deposition process is limited due to exhaustion of a supply of electrons at the surface; when plating to n-type silicon, the silicon etching process is limited due to exhaustion of a supply of holes at the surface.

The combined effect which illumination and the presence of a semiconductor junction have on the minority carrier concentrations at the silicon surface has been simulated and the results illustrated in Figures 10 & 1 1 by way of example. These results graphically show minority carrier concentration versus distance from the surface for a 0.5 m junction (Figure 10) and a 5μηη junction (Figure 11) under three monochromatic illumination conditions ((a) 355nm, (b) 532nm & (c) 1064nm) at intensities of 0.1W/cm². In these cases, the surface doping and surface recombination properties are kept the same when varying junction depths. Optical properties of the silicon solar cells such as the anti-reflection coating at the surface and surface texture were also consistent. Solar cell devices may have different surface doping levels, different dopant distribution profiles, and different junction depths. The techniques of forming semiconductor junctions include laser doping, thermal diffusion, solid phase epitaxial growth, liquid phase epitaxial growth and ion implantation. While forming

semiconductor junctions, each technique can introduce defects to the silicon surface and substrate, which also influence the carrier concentrations since defects contribute to recombination losses. The light trapping or light receiving properties of silicon solar cells may also vary according to optimal device design. When forming metal seed layers on silicon solar cells by galvanic displacement plating, the plating rate and thickness of metal deposits may be controlled by controlling the use of an illumination source in terms of its intensity and wavelength spectrum and taking into account the effect of transmitting the light through the plating solution. The features of the photovoltaic device should also be taken into account when designing the process. Effect of Electrolyte Temperature

As shown in Table 2, the plating rate increased for wafers having a 10 Ω/square emitter with electrolyte temperature in the range of 20 to 60 °C. The plating rate was increased by a factor of ~ 23 when plating was performed at 60 °C compared to when it was performed at 20 °C. However, the Arrhenius plot (Figure 3) indicates that there may be two rate limiting reactions occurring under different temperature regimes, with the transitioning point appearing at around 40 °C. This kinetic behaviour suggests that the reaction may transition from being oxidation limited to reduction limited at ~ 40 °C. From a practical perspective, these results indicate that faster nickel plating rates can be achieved with higher temperatures due to increased carrier concentrations generated by heat at the silicon surface and the increased diffusion rate of metal ions in the electrolyte.

Table 2 Calculated mass of plated nickel and rate of nickel deposition on silicon with ΙΟΩ/square emitters, nickel immersion plating at

various temperatures for 5min under illumination. Effect of Plating Time

Figure 4 illustrates the effect of time on the growth of the deposited nickel layer of wafers with a 10 Ω square emitter under illumination at 50 °C for 30 min. The growth of nickel was initially fast and then slowed as the thickness of the deposited layer approached a limiting value. This limited growth is consistent with the reaction slowing as metal covers more completely the silicon surface thus preventing the oxidation reaction. Eventually the redox reaction terminates once the nickel layer covers the entire silicon surface, resulting in a saturation condition.

For wafers with a 10 Ω square emitter used in this study, the saturated nickel layer had a thickness of ~260 nm when the immersion plating process was carried out at 50 °C under illumination for more than 30 min.

It has been observed that the sheet resistance of nickel silicide layer reaches an extremely low value when the initial thickness of the nickel layer is between 20 nm and 300 nm. The results above suggest that immersion nickel plating conditions are able to be optimised such that the saturating layer thickness is optimised for low contact resistance and 100% coverage.

Example I. Combined Dielectric Patterning and Metal Deposition The direct etching method can be used to pattern the dielectric layers on solar cells by printing or jetting a source of fluoride ions such as an H₄F solution onto a layer of water-soluble polymer such as a polyacrylic acid (PAA) layer that is formed on the dielectric's surface. The printing process results in small quantities of HF forming in-situ that etch the dielectric layer according to the printed pattern. The nickel seed layer deposition experiments described above used similar fluoride based chemistry and so the possibility of combining the dielectric patterning and nickel deposition processes was investigated. Figure 5 shows a graphical overview of the proposed combined process.

Referring to Figure 9, p-type 1 Ω cm alkaline-textured Cz silicon wafers 1201 with 100 Ω square phosphorus-diffused emitters 1200 forming a shallow junction 1204 (approx. 300nm deep) were used for the following experiments. An industrial plasma- enhanced chemical vapour deposition (PECVD) system was used to deposit a layer 1208 of 75nm SiNx with a refractive index of 2.0 on to the surface 1203 of the emitter

1200 for anti-reflection and passivation purposes. The rear surface of the samples was etched in HF HNO3 mixture to remove the diffused phosphorus emitter. Subsequently, aluminium (Al) paste was screen printed on the rear of the solar cells, followed by a fast firing process carried out in a belt furnace at a peak temperature of 850 °C for 1 s to form a full area back surface field (BSF) and p-type metal contact 1209.

A solution comprising 20% (w/v) polyacrylic acid (PAA) loaded with 50 mM N1SO4 was spin-coated on the SiNx surface of the wafers and dried to form a N1SO4 loaded PAA layer 1214. To evaluate the suitability of the proposed process for solar cell fabrication, an aerosol jet printer (OPTOMEC M³D^® system) 1215 was used to print a jet 1216 of 10% (w/v) NH4F with an adjusted pH of 8 on to the surface of the NiSC oaded PAA layer 1214. Note however that nickel ions might also be incorporated into the NH4F solution, instead of or as well as being incorporated in the polyacrylic acid. Printing parameters were selected to be the optimal for the direct etching process when using a tip of 100 μηι in diameter, as listed in Table 3. Wafers

1201 remained on the platen at a temperature of 60 °C for a total duration of 30 min. The reaction described above with reference to Figure 5 occurs in the zone 1217 where the jet 1216 impinges on the NiS0₄-loaded PAA layer 1214 to etch the SiNx and nickel plate the subsequently exposed silicon. Due to limitations of the aerosol jet printer used in in the experiment, only very weak light with a non -characterised spectrum could reach the silicon surface while processing.

Parameters Values

Printing speed (mm/s) 4

Platen temperature (°C) 60

Atomizer flow rate

(cmW¹)

Sheath flow rate (cm³min^"1) 10

No. of printed layers 8

Table 3 Aerosol jet printing conditions used for the

combined dielectric patterning and nickel deposition process.

After attempting to integrate the best-practice parameters for dielectric patterning and immersion plating into the design of this combined process, the resulting silicon surface was imaged under SEM. Nickel deposits can be seen on the surface of the etched areas, as they are more conductive and therefore appear brighter.

Clearly, benefits exist from combining into a single step the two processes of dielectric patterning and nickel seed layer deposition. Although complete etching is the aim, an effective metallisation will be possible even if small regions of dielectric layer remain on the silicon surface, provided the adhesion that is achieved with the plated regions is sufficient, and provided the conductive metal that is plated over the seed layer (e.g. copper) can effectively "grow" over the remaining dielectric regions and coalesce. Other dielectric layers such as silicon oxide, silicon oxynitride or aluminium oxide may also be used as an anti-reflection and passivation coating. The ability to pattern the dielectric layer and deposit metal on the etched region will not affected by changing the dielectric material to another suitable dielectric material. Depending on the passivation property of the dielectric layer and its interaction with different wavelengths of light, the desired plating rate and thickness of metal deposits, there will be differences in the process parameters selected. The light receiving properties of the silicon surface that is coated with polyacrylic acid also contributes to the variation of illumination required to control the process.

In the example described above, the water-soluble polymer is polyacrylic acid (PAA), however other polymers may also be used. For example the water-soluble polymer may comprise water-soluble polymers or resins containing acidic groups (e.g., acidic polythiophene or polyaniline derivatives, polystyrene sulfonate, polyester or phenolic resins). It is also possible to use polymer mixtures or blends to form the polymer film. For example, PAA can be blended with other water soluble polymers such as polyvinyl alcohol (PVA) in PAA:PVA ratios ranging from 1 : 1 to 1 :4 depending on the extent of etching required. Copolymers can also be used to form the polymer film. The use of copolymers or polymer blends for forming the thin film is a way in which the pH of the formed film can be controlled. Furthermore, polymer films can contain additives, such as nanoparticles, which can either directly provide further acidic groups or indirectly enhance the pH of the film.

In the above example the PAA is loaded with nickel sulphate however other water-soluble metal salts selected from nickel sulfate, nickel chloride, nickel sulfamate, copper sulfate, silver nitrate may be used Ammonium fluoride may also be replaced with other fluorides such as sodium fluoride. Example II. Metal deposition to silicon solar cells with semiconductor junction The results presented above suggest that the proposed galvanic nickel deposition can provide a useful way for forming seed (or barrier) nickel layers for plated metallisation of silicon solar cells.

Although the prior art method of light-induced plating (LIP) of nickel is conceptually simple, it can be difficult to obtain uniformly thin layers. In most cases, the aim is to achieve uniform layers of thickness < 1 μπι, however as stated above it has been shown that much thinner layers are desirable. In addition, it can be difficult to achieve layers of uniform thickness because in order to obtain uniform coverage of exposed silicon regions, much thicker layers typically result at least in some areas of the exposed region because the nickel will plate to regions where metal has already nucleated because those regions are more conductive. Furthermore, LIP is not self- limiting and can depend on properties of the individual cells resulting in further variation in plated nickel thickness between cells. This results in difficulties in process control.

An advantage that the proposed galvanic nickel deposition process may have over LIP nickel is the improved adhesion, in that silicon is being etched during the deposition process, the final metal silicon interface is rougher. The approach of roughening silicon before the plating of metal has been previously proposed, however most roughening processes require separate pre-processing steps. In the galvanic nickel deposition process the "roughening" occurs as part of the plating process which is clearly advantageous.

In a further experiment a batch of cells were fabricated with homogeneous emitters of sheet resistance 50 Ω/square, 85 Ω/square and 120 Ω/square using the proposed galvanic nickel deposition process for seed layer formation.

Referring to Figure 6, wafers 701 were prepared as described for the previous experiment. Three sets of cells were fabricated with homogeneous emitters doped to 50 Ω square, 85 Ω/square and 120 Ω/square respectively, forming a shallow junction 704. The front grid pattern was formed on the surfaces 703 of the emitters by direct etching to remove the SiNx layer 708, thus exposing the n-type silicon surface 703 of the emitter. The fingers of the front grid pattern (to be formed in the openings in the SiNx layer 708) were spaced 1.2 mm apart on a 6.5cm² cell. Nickel seed layer plating was performed using an electrolyte 702 comprising 10% (w v) NH₄F and 100 mM N1SO4 with the pH adjusted to a value of 8 at an elevated temperature of 50 °C for 5 min for all the cells, with the cells supported on Teflon spacers 705 such that only the front surface 703 of the solar cell contacting the plating solution 702 thereby avoiding the need to mask the rear surface. Due to the design constraints on the lab setup, only a very minimal level of illumination was able to reach the front surface of the solar cells during plating. The aluminium screen-printed contact 709 formed on the rear surface of the wafer 701 remained dry during the seed layer formation process thus eliminating any possible contribution of the cell's light-induced current to the plating process. Referring to Figure 7, after nickel plating, the nickel layer 712 is sintered using a typical nickel sintering process, such as heating the device to 350 °C for 1 min to form the silicides 71 1 at the interface between the nickel and the silicon. Presence of nickel silicides 71 1 not only reduces the contact resistance but also forms a barrier to copper diffusion. Finally, the copper 712 conducting layer was formed by plating for 10 mins on top of the silicide 71 1 via LIP from a Technisol copper plating solution (obtained from Technic, Inc.).

Electrical measurement data of the fabricated cells are listed in Table 4, as averages of three cells for each emitter sheet resistance. The average cell efficiencies of 15.1%, 18.4% and 18.1% were achieved from cells with 50 Ω square, 85 Ω/square and 120£i square emitters, respectively. The highest cell efficiency from all groups was 18.6%, obtained from a cell with an 85 Ω/square emitter (see the IV curve shown in Figure 8).

Table 4 - IV data of solar cells fabricated with plated thin nickel seed layer

Accordingly, a nickel seed layer deposition process is proposed that has the potential to be adapted for the fabrication of Si solar cells with lightly-doped emitters. The method has the advantage of being capable of plating a thin (<300 nm) and continuous layer without compromising the uniformity of the layer. Very low resistance nickel silicide can form after sintering, enabling cells with lightly-doped homogeneous emitter and Al-alloyed back surface contact to be fabricated with an efficiency exceeding 18.5%. The lower efficiencies achieved from devices with 50 Ω/square and 120 Ω square emitters were due to non-optimised front grid design, the plating and sintering conditions. W

19

The successful demonstration of homogeneous emitter silicon solar cells metallised using the plated nickel seed layer suggests that it is possible to produce high efficiency cells without the need of a selective emitter, thus minimising fabrication costs. The dielectric patterning can be achieved using wet chemical methods, or by 5 laser scribing.

This process can also be developed to plate to either p-type or n-type silicon surfaces that have different doping profiles and junction depths, as indicated by Figures 10 & 11. In general, short wavelength light is most effectively absorbed close to the silicon surface. The intensity of light reaching the surface depends on the medium that

10 light needs to transmit through. However, when a semiconductor junction (p-n junction or high-low junction) is incorporated into a device design and one of the surfaces needs to be plated, a desired plating rate and metal deposit thickness is achievable by using control measures which are selected according to the semiconductor junction characteristics. For example the minority carrier concentration will be reduced as a

15 result of minority carriers being swept across the junction and will be increased by the use of heat and illumination to generate additional minority carriers.

Example III. Metal deposition to pattered regions having a high aspect ratio

20 To plate metal onto high aspect ratio structures, it is advantageous to use

galvanic displacement plating to deposit a seed layer because the process is conformal and forms a continuous, thin layer. For example, a nickel seed layer can be deposited along the walls and in the bottom of laser grooves that may have a high-low junction or a p-n junction, depending on the device designs. The control of carrier concentrations

25 through the use of illumination may need to be varied by using diffused light to result in uniform generation of carriers at the wall and at the bottom of the patterned structure.

It is also possible to use galvanic displacement plating to metallise the pores of anodic aluminium oxide (AAO) structures.

30

Example IV. Metal deposition to advanced semiconductor finger solar cells

When plating metal to advanced semiconductor finger solar cells, it is extremely difficult to plate uniformly and continuously to regions that are close to the screen- 35 printed fingers and busbars. Firstly, because the silicon surface is not as conductive as the screen-printed metal lines, the electrons are easily transported to the screen-printed regions and are captured by the metal ions in the solution to form metal deposits on to the screen-printed lines. Secondly, because the surface overpotential required for the reduction reaction to occur at the silicon surface is higher than that at the screen-printed metal lines, it is more favourable thermodynamically for the metal to be deposited to the screen-printed lines.

The galvanic displacement plating process occurs by oxidising the silicon surface to provide the electrons for the reduction reaction to take place adjacent to the silicon surface. Because the regions the oxidation and reduction reactions take place are closely spaced, the competition for electrons between the cathodic silicon surface and screen-printed metal lines is greatly reduced. Initial experiments showed that the metal plating was continuous and thin, and formed very good connections between the semiconductor finger and the screen-printed metal lines.

With the control of carrier concentrations at the surface, this process can be far more controllable when compared to other plating techniques and therefore provide considerable advantage when used for this type of solar cell design.

For any solar cell design that requires plating to the silicon surface in proximity to a more conductive area, the galvanic displacement plating process can be used to form a uniform and thin metal layer that is continuous and covers the entire silicon surface.

Example V. Metal deposition to both polarities of silicon surfaces in one step

Because the limiting reaction of metal galvanic displacement plating process is different for p-type and n-type silicon surface, depending on the localised carrier concentrations, it is therefore possible to use different control measures to result in simultaneously metal deposition to surfaces comprising opposite polarity materials.

It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the above-described embodiments, without departing from the broad general scope of the present disclosure. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

Claims

CLAIMS:

1. A method of depositing metal on a surface of a silicon solar cell device having a dielectric surface layer located over the surface of the silicon solar cell device and localised openings in the dielectric layer exposing a silicon surface to be plated in a pattern corresponding to a desired metallisation pattern, the method comprising:

(i) contacting the silicon surface to be plated with an electrolyte containing ions of the metal and depositing the metal onto the silicon surface exposed in the localised openings using an electrochemical reaction that includes the oxidation of silicon from the exposed si li con surface;

2. The method of claim 1 wherein the silicon solar cell device has a semiconductor junction located a distance of less than Ιμηη from the dielectric surface layer.

3. The method as claimed in claim 1 or 2 wherein the pH of the electrolyte is >7.

4. The method as claimed in claim 1, 2 or 3 wherein the concentrations of electrons and holes is controlled by illuminating the silicon solar cell device with an illumination source having a predetermined intensity and spectrum of the illumination reaching the silicon surface of the silicon solar cell.

5. The method of claim 4 wherein the intensity of the illumination reaching the surface of the silicon solar cell device from the source is within the range of 0.001 -10 W/cm²

6. The method of claim 4 or 5 wherein the spectrum of the illumination reaching the surface of the silicon solar cell device from the source is within the range of

350nm-1400nm.

7. A method of forming openings in a dielectric surface layer of a silicon solar cell device to expose a silicon surface and depositing metal on the exposed silicon surface, the method comprising:

i. applying, over the dielectric layer, a layer of polymer; ii. depositing onto the polymer surface a solution containing fluoride ions, the solution being deposited in a pattern corresponding to the desired metallisation pattern; and

iii. providing, in the solution containing fluoride ions and /or in the layer of polymer, ions of the metal to be deposited,

8. The method of claim 7 wherein the metal ions are provided as a water-soluble salt of the metal in the layer of polymer.

9. The method of claim 7 wherein the metal ions are provided by incorporating the metal ions into the solution containing fluoride ions.

10. The method as claimed in claim 7, 8 or 9 wherein a p-n junction is located within 10 micron of the exposed silicon surface.

11. The method as claimed in claim 7, 8 or 9 wherein a high-low junction is located within 20 micron of the exposed silicon surface.

12. The method as claimed in any one of claims 1 to 11 wherein the opening of the dielectric layer to expose the silicon surface and the deposition of the metal onto the exposed silicon surface are performed by:

i. applying, over the dielectric layer, a layer of polymer;

iii. providing, in the solution containing fluoride ions and tor in the layer of polymer, ions of the metal to be deposited,

whereby the solution containing the fluoride ions act with the polymer to etch the dielectric surface layer to form openings in the dielectric layer exposing the silicon surface of the silicon solar cell device in the pattern corresponding to the metallisation pattern, and the metal is deposited onto the exposed silicon surface in an electrochemical reaction that includes oxidation of silicon and reduction of metal ions.

13. The method of claim 12 wherein the metal ions are provided as a water-soluble salt of the metal in the layer of polymer.

14. The method of claim 12 wherein the metal ions are provided by incorporating the metal ions into the solution containing fluoride ions.

15. The method as claimed in any one of claims 7 to 14 wherein concentrations of holes and electrons at the exposed silicon surface are controlled by using controlled illumination to control the rate and thickness of deposition on the exposed silicon surface.

16. The method as claimed in any one of claims 7 to 15 wherein the solution containing the fluoride ions is of neutral or alkaline pH.

17. The method as claimed in any one of claims 7 to 16 wherein the polymer is water-soluble.

18. The method as claimed in claim 17 wherein the water-soluble polymer comprises one of polyacrylic acid (PAA), acidic polythiophene or polyaniline derivatives, polystyrene sulfonate, polyester or phenolic resins,

19. The method as claimed in claim 17 wherein the water-soluble polymer comprises polymer mixtures or blends.

20. The method as claimed in claim 19 wherein the water-soluble polymer comprises a mixture of polyacrylic acid (PA) and polyvinyl alcohol (PV A) in

PAA:PVA ratios ranging from 1 : 1 to 1 :4 depending on the extent of etching required.

21. The method as claimed in claim 17 wherein the water-soluble polymer comprises copolymers of an acidic polymer.

22. The method as claimed in claim 17 wherein the water-soluble polymer comprises additives, which directly provide further acidic groups.

23. The method as claimed in claim 17 wherein the water-soluble polymer comprises additives, which indirectly enhance the acidity of the film.

24. The method as claimed in claim 22 or 23 wherein the additives comprise nanoparticles.

25. The method as claimed in any one of claims 7 to 24 wherein during the silicon oxidation and/or metal deposition processes cause the silicon surface to be roughened to thereby improve adhesion of the deposited metal to the silicon surface.

26. The method as claimed in any one of claims 7 to 25 wherein the metal salt is a water-soluble metal salt selected from nickel sulfate, nickel chloride, nickel sulfamate, copper sulfate, silver nitrate and the non-acidic fluoride is selected from ammonium fluoride or sodium fluoride.

27. The method as claimed in any one of claims 1 to 26 wherein a p-n junction is located within 300nm of the exposed silicon surface.

28. The method as claimed in any one of claims 1 to 27 wherein the silicon solar cell device has a shallow emitter of uniform depth in the range 100-300nm and the dielectric surface layer is formed over the emitter.

29. The method as claimed in any one of claims 1 to 26 wherein the semiconductor junction is a high-lowjunction.

30. The method as claimed in claim 29 wherein the high-low junction is located within 300nm of the exposed silicon surface.

31. The method as claimed in any one of claims 1 to 30 wherein areas of the exposed silicon surface that are not to be plated are passivated prior to being contacted with the electrolyte.

32. The method as claimed in any one of claims 1 to 31 wherein ions of the metal in the electrolyte comprise ions of nickel, copper, silver or platinum.

33. The method as claimed in any one of claims 1 to 32 wherein the electrolyte comprises a solution in water of a salt of the metal to be deposited and a non-acidic fluoride.

34. The method as claimed in any one of the preceding claims wherein the silicon of the exposed silicon surface is doped to a predetermined level selected to affect the concentrations of electrons and holes at the exposed silicon surface.

35. The method as claimed in any one of the preceding claims wherein the plating is applied to a thickness which is less than or equal to 350nm.

36. The method as claimed in any one of the preceding claims wherein the temperature at which the plating is performed is above 30°C.

37. The method as claimed in any one of the preceding claims wherein the temperature at which the plating is performed is above 50°C.

38. The method as claimed in any one of the preceding claims wherein the temperature at which the plating is performed is above 60°C.

39. The method as claimed in any one of the preceding claims wherein two opposite surfaces of the silicon solar cell device are simultaneously plated.

40. The method as claimed in any one of the preceding claims wherein the deposited metal is sintered to form a silicide at the interface of the deposited metal and the exposed silicon surface.

41. The method as claimed in claim 40 wherein the silicide has a thickness which is in the range of 50-90nm or 10-300nm or 10-250nm or 10-200nm or 10-150nm or 10- lOOnm or 10-80nm or 10-50nm or 10-40nm or 10-30nm or 10-20nm or 20-300nm or 20-250nm or 20-200nm or 20-150nm or 20-100nm or 20-80nm or 20-50nm or 20- 40nm or 20-30nm or 30-300nm or 30-250nm or 30-200nm or 30-150nm or 30-100nm or 30-80nm or 30-50nm or 30-40nm or 40-300nm or 40-250nm or 40-200nm or 40- 150nm or 40-1 OOnm or 40-80nm or 40-50nm or 50-300nm or 50-250nm or 50-200nm or 50-150nm or 50-1 OOnm or 50-80nm or 80-3 OOnm or 80-250nm or 80-200nm or 80- nm or 80-lOOnm or 100-300nm or 100-250nm or 100-200nm or 100-150nm ornm or 150-250nm or 5f 200nm or 200-300nm or 200-250nm or 250-300nm.