WO2014059620A1 - Circuit d'attaque isolé - Google Patents

Circuit d'attaque isolé Download PDF

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Publication number
WO2014059620A1
WO2014059620A1 PCT/CN2012/083076 CN2012083076W WO2014059620A1 WO 2014059620 A1 WO2014059620 A1 WO 2014059620A1 CN 2012083076 W CN2012083076 W CN 2012083076W WO 2014059620 A1 WO2014059620 A1 WO 2014059620A1
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WIPO (PCT)
Prior art keywords
circuit
signal
driving signal
pulse
isolated
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PCT/CN2012/083076
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English (en)
Chinese (zh)
Inventor
胡祖荣
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深圳市安能能源技术有限公司
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Priority to PCT/CN2012/083076 priority Critical patent/WO2014059620A1/fr
Publication of WO2014059620A1 publication Critical patent/WO2014059620A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
    • H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling

Definitions

  • the present invention relates to the field of drive circuits, and more particularly to an isolated drive circuit that avoids resonance due to a DC blocking capacitor and a drive transformer magnetizing inductance.
  • the pulse transformer isolation drive circuit is a common power switch tube drive circuit. It has the advantages of simple circuit structure, no need to provide isolated power supply, low cost and no transmission delay for pulse signals, and can meet the requirements of the power switch tube drive circuit. Electrical isolation, rapidity, and strong drive requirements.
  • FIG. 1 is a conventional pulse transformer isolation driving circuit.
  • the isolation driving circuit includes a resistor R1, a DC blocking capacitor C1, and an isolated driving transformer T1.
  • the isolation driving transformer T1 includes a primary winding and a secondary winding. Winding.
  • the driving pulse from the control circuit is at a high level and is added between the point A and the primary winding reference ground B, after the bootstrap by the isolation conversion and the negative voltage, the reference point D is output at the point C and the secondary winding.
  • the DC blocking capacitor C1 provides a negative voltage
  • the drive transformer T1 is isolated to perform a magnetic reset.
  • FIG. 2 is another conventional pulse transformer isolation driving circuit, which includes a resistor R1, a DC blocking capacitor C1, an isolation driving transformer T1, a bootstrap capacitor C2, and a bootstrap diode D1.
  • the drive transformer T1 includes a primary winding and a secondary winding.
  • the isolation driving circuit is provided with a bootstrap capacitor C2 and a bootstrap diode D1 in the secondary winding of the isolation driving transformer T1.
  • U0 is the conduction voltage drop of the bootstrap diode D1, and its value is small.
  • the primary side voltage of the isolated driving transformer T1 is Udrive-Uc1
  • the secondary side voltage of the isolated drive transformer T1 is also Udrive-Uc1
  • the voltage amplitude of the driving voltage is almost constant during the transmission.
  • the pulse transformer isolation driving circuit shown in FIG. 2 can ensure that the power switching tube is normally driven when the duty ratio of the driving pulse is large.
  • the pulse transformer isolation driving circuit shown in FIG. 1 and FIG. 2 has a disadvantage: the two pulse transformer isolation driving circuits all rely on the DC capacitor C1 to realize the magnetic reset of the isolated driving transformer T1. Due to the presence of the DC blocking capacitor C1, when the driving pulse of the control circuit is turned off, the DC-capacitor C1 and the magnetizing inductance of the isolated driving transformer T1 will resonate, so that the primary and secondary windings of the isolated driving transformer T1 are highly generated. Oscillation voltage may cause the power switch tube that is turned off to be mis-conducted.
  • the object of the present invention is to provide an isolated driving circuit capable of avoiding resonance due to a DC blocking capacitor and a driving transformer magnetizing inductance, and solving the problem that the existing isolated driving circuit resonates due to a DC blocking capacitor and a driving transformer magnetizing inductance, which may cause a shutdown.
  • the invention relates to an isolated drive circuit comprising:
  • Isolate the drive transformer including the primary winding and the secondary winding;
  • a double-ended excitation signal driving control circuit for generating a first pulse driving signal and a second pulse driving signal, wherein the first pulse driving signal and the second pulse driving signal are input by the primary winding;
  • At least one pulse drive signal conversion circuit for converting an output signal of the secondary winding into a drive signal for driving a corresponding power switch tube
  • the double-ended excitation signal driving control circuit is connected to a primary winding of the isolated driving transformer, and a secondary winding of the isolated driving transformer is connected to the pulse driving signal conversion circuit;
  • the isolated drive transformer includes a first primary winding, the first pulse driving signal is input by one end of the first primary winding, and the second pulse driving signal is input by the other end of the first primary winding ;
  • the isolation driving circuit further includes an anti-DC biasing circuit for preventing a DC bias phenomenon of the isolated driving transformer, the DC blocking biasing circuit and the double-ended excitation signal driving control circuit and the isolation driving respectively Transformer connection
  • the anti-DC bias circuit includes a first resistor and a first capacitor, and one end of the first resistor is respectively connected to one end of the first capacitor and the pulse driving signal conversion circuit, and the other end of the first resistor Connected to the other end of the first capacitor and the isolated drive transformer, respectively.
  • the invention also relates to an isolated drive circuit comprising:
  • Isolate the drive transformer including the primary winding and the secondary winding;
  • a double-ended excitation signal driving control circuit for generating a first pulse driving signal and a second pulse driving signal, wherein the first pulse driving signal and the second pulse driving signal are input by the primary winding;
  • At least one pulse drive signal conversion circuit for converting an output signal of the secondary winding into a drive signal for driving a corresponding power switch tube
  • the double-ended excitation signal driving control circuit is connected to a primary winding of the isolated driving transformer, and a secondary winding of the isolated driving transformer is connected to the pulse driving signal conversion circuit.
  • the isolated driving transformer includes a first primary winding, the first pulse driving signal is input by one end of the first primary winding, and the second pulse driving signal is The other end of the first primary winding is input.
  • the isolated driving transformer includes a first primary winding and a second primary winding, and the first pulse driving signal is input by the first primary winding, and the second pulse A drive signal is input by the second primary winding.
  • the frequency of the first pulse driving signal and the frequency of the second pulse driving signal are the same, the duty ratio of the first pulse driving signal and the second pulse driving signal The duty ratio is the same, the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are connected back and forth, or the high-level time of the second pulse driving signal and the The high-level time of the first pulse driving signal is connected back and forth.
  • the second pulse driving signal when the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are connected back and forth, the second pulse driving signal is low-powered a time point at which the flat start transitioning to a high level is earlier than a time point at which the first pulse drive signal is switched from a high level to a low level;
  • a time point at which the first pulse driving signal is switched from a low level to a high level A time point earlier than the second pulse drive signal transitioning from a high level to a low level.
  • the isolated driving transformer includes a first secondary winding and a second secondary winding
  • the pulse drive signal conversion circuit includes:
  • a first output circuit configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level;
  • a second output circuit configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level;
  • An OR circuit comprising: a first input terminal, a second input terminal, and an output terminal; configured to: when the first output circuit outputs the first low level signal, and the second output circuit outputs the second low When the level signal is output, the low level driving signal is output; otherwise, the high level driving signal is output;
  • One end of the first output circuit is connected to the first secondary winding, and the other end of the first output circuit is connected to a first input end of the OR circuit; one end of the second output circuit The second secondary winding is connected, and the other end of the second output circuit is connected to the second input of the OR circuit.
  • the first output circuit comprises:
  • a first charge and discharge circuit for shortening a time of a rising edge of the first high level signal and extending a time of a falling edge of the first high level signal
  • a first clamping circuit for clamping the first low level signal.
  • the first charging and discharging circuit includes a second resistor, a third resistor, a fourth resistor, a first diode, and a second capacitor
  • the first clamping circuit includes a second diode
  • One end of the second resistor is connected to one end of the first secondary winding, the other end of the second resistor is connected to the anode of the first diode, and the anode of the first diode is Connected to a first input end of the OR circuit, one end of the third resistor is connected to one end of the first secondary winding, and the other end of the third resistor is connected to a first input end of the OR gate circuit
  • One end of the second capacitor is connected to the first input end of the OR gate circuit, and the other end of the second capacitor is connected to the other end of the first secondary winding, and one end of the fourth resistor is a first input end of the OR circuit is connected, and another end of the fourth resistor is connected to another end of the first secondary winding, a positive pole of the second diode and the first secondary winding
  • the other end of the second diode is connected to the first input of the OR circuit.
  • the second output circuit comprises:
  • a second charge and discharge circuit for shortening a time of a rising edge of the second high level signal and extending a time of a falling edge of the second high level signal
  • a second clamping circuit for clamping the second low level signal.
  • the second charging and discharging circuit includes a fifth resistor, a sixth resistor, a seventh resistor, a third diode, and a third capacitor
  • the second clamping circuit includes a fourth diode
  • One end of the fifth resistor is connected to one end of the second secondary winding, the other end of the fifth resistor is connected to the anode of the third diode, and the cathode of the third diode is Connecting a second input end of the OR circuit, one end of the sixth resistor is connected to one end of the second secondary winding, and the other end of the sixth resistor is connected to the second input end of the OR circuit
  • One end of the third capacitor is connected to the second input end of the OR gate circuit, and the other end of the third capacitor is connected to the other end of the second secondary winding
  • one end of the seventh resistor is a second input end of the OR circuit is connected, and another end of the seventh resistor is connected to another end of the second secondary winding, and a positive pole of the fourth diode and the second secondary winding
  • the other end of the fourth diode is connected to the second input of the OR gate.
  • the isolated driving transformer further includes a first standby secondary winding and a second standby secondary winding;
  • the pulse drive signal conversion circuit further includes:
  • a first standby output circuit configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level;
  • a second standby output circuit configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level;
  • first standby output circuit One end of the first standby output circuit is connected to the first standby secondary winding, and the other end of the first standby output circuit is connected to a first input end of the OR gate circuit; the second standby output circuit One end is connected to the second standby secondary winding, and the other end of the second standby output circuit is connected to the second input of the OR circuit.
  • the isolated driving circuit includes an anti-DC biasing circuit for preventing a DC bias phenomenon of the isolated driving transformer, and the DC blocking bias circuit and the double-ended excitation respectively a signal driving control circuit and the isolated driving transformer are connected;
  • the DC-blocking bias circuit includes a first resistor and a first capacitor, and one end of the first resistor is respectively connected to one end of the first capacitor and the pulse driving signal conversion circuit Connected, the other end of the first resistor is respectively connected to the other end of the first capacitor and the isolated driving transformer.
  • the isolated driving circuit further includes:
  • a power amplifying circuit for amplifying the driving signal output by the pulse driving signal conversion circuit
  • the power amplifying circuit is connected to the pulse driving signal conversion circuit.
  • the isolated driving circuit of the invention can avoid resonance due to the DC blocking capacitor and the excitation inductance of the driving transformer, and solves the resonance of the existing isolated driving circuit due to the DC blocking capacitance and the driving transformer excitation inductance.
  • 1 is a conventional pulse transformer isolation driving circuit
  • FIG. 3 is a schematic block diagram of a first preferred embodiment of an isolated driving circuit of the present invention.
  • FIG. 4 is a schematic diagram of a specific module of a first preferred embodiment of the isolated driving circuit of the present invention.
  • Figure 5 is a specific circuit diagram of a first preferred embodiment of the isolated drive circuit of the present invention.
  • Figure 6 is a voltage waveform diagram of each point in Figure 5;
  • FIG. 7 is a schematic diagram of signal synthesis of a driving signal through an OR gate circuit of a preferred embodiment of the isolated driving circuit of the present invention.
  • Figure 8 is a specific circuit diagram of a second preferred embodiment of the isolated drive circuit of the present invention.
  • Figure 9 is a specific circuit diagram of a third preferred embodiment of the isolated drive circuit of the present invention.
  • Figure 10 is a specific circuit diagram of a fourth preferred embodiment of the isolated drive circuit of the present invention.
  • Figure 11 is a specific circuit diagram of a fifth preferred embodiment of the isolated drive circuit of the present invention.
  • FIG. 12 is a specific circuit diagram of a sixth preferred embodiment of the isolated driving circuit of the present invention.
  • FIG. 3 is a schematic block diagram of a first preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated drive circuit includes an isolated drive transformer 32, a double-ended excitation signal drive control circuit 31, and a pulse drive signal conversion circuit 33.
  • the isolated driving transformer 32 includes a first primary winding and a secondary winding;
  • the double-ended excitation signal driving control circuit 31 is configured to generate a first pulse driving signal and a second pulse driving signal, the first pulse driving signal being the first primary winding One end of the input, the second pulse driving signal is input from the other end of the first primary winding;
  • the pulse driving signal conversion circuit 33 is for converting the output signal of the secondary winding of the isolated driving transformer 32 into a driving signal, and then using the driving signal Drive the corresponding power switch tube.
  • the double-ended excitation signal drive control circuit 31 is connected to the first primary winding of the isolated drive transformer 32, and the secondary winding of the isolated drive transformer 32 is connected to the input of the pulse drive signal conversion circuit 33, and the output of the pulse drive signal conversion circuit 33 is The power switch tube to be driven is connected.
  • FIG. 4 is a schematic diagram of a specific module of a first preferred embodiment of the isolated driving circuit of the present invention
  • FIG. 5 is a specific circuit diagram of a first preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated drive transformer 32 includes a first primary winding 321 , a first secondary winding 322 , and a second secondary winding 323 .
  • the pulse driving signal conversion circuit 33 includes a first output circuit 331, a second output circuit 332, and an OR gate circuit 333, wherein the first output circuit 331 is configured to output a first high level signal when the second pulse signal is at a high level, When the second pulse driving signal is low level, the first low level signal is output; the second output circuit 332 is configured to output the second high level signal when the first pulse driving signal is high level, when the first pulse is driven When the signal is low, the second low level signal is output; or the gate circuit 333 includes a first input end, a second input end, and an output end, when the first output circuit 331 outputs the first low level signal to the first At the input end, when the second output circuit 332 outputs the second low level signal to the second input end, the output end outputs a low level driving signal, otherwise the output end outputs a high level driving signal.
  • One end of the first output circuit 331 is connected to the first secondary winding 322, the other end of the first output circuit 331 is connected to the first input terminal of the OR gate circuit 333, and one end of the second output circuit 332 and the second secondary winding 323 Connected, the other end of the second output circuit 332 is coupled to the second input of the OR gate circuit 333.
  • the same name end of the first primary winding 321 , the first secondary winding 322 and the second secondary winding 323 are arranged as shown in FIG. 5 .
  • the OR gate circuit 333 herein may be an integrated logic gate circuit or an OR gate circuit composed of discrete components.
  • the first output circuit 331 includes a first charge and discharge circuit and a first clamp circuit
  • the second output circuit 332 includes a second charge and discharge circuit and a second clamp circuit
  • the first charging and discharging circuit is configured to shorten the time of the rising edge of the first high level signal and extend the time of the falling edge of the first high level signal; the first clamping circuit is configured to perform the first low level signal Clamp.
  • the first charging and discharging circuit includes a second resistor R2', a third resistor R3', a fourth resistor R4', a first diode D1', and a second capacitor C2'; the first clamping circuit includes a second diode D2 '.
  • One end of the second resistor R2' is connected to one end of the first secondary winding 322, the other end of the second resistor R2' is connected to the anode of the first diode D1', and the negative terminal and OR gate of the first diode D1'
  • the first input end of the circuit 333 is connected, one end of the third resistor R3' is connected to one end of the first secondary winding 322, and the other end of the third resistor R3' is connected to the first input end of the OR circuit 333, and the second capacitor One end of C2' is connected to the first input end of the OR circuit 333, the other end of the second capacitor C2' is connected to the other end of the first sub-side winding 322, and one end of the fourth resistor R4' is opposite to the OR gate 333.
  • One input terminal is connected, the other end of the fourth resistor R4' is connected to the other end of the first secondary winding 322, and the anode of the second diode D2' is connected to the other end of the first secondary winding 322, and the second diode
  • the cathode of the tube D2' is connected to the first input of the OR circuit 333.
  • the second charging and discharging circuit is configured to shorten the rising edge of the second high level signal and extend the interval between the falling edges of the second high level signal; the second clamping circuit is configured to perform the second low level signal Clamp.
  • the second charging and discharging circuit includes a fifth resistor R5', a sixth resistor R6', a seventh resistor R7', a third diode D3', and a third capacitor C3', and the second clamping circuit includes a fourth diode D4 '.
  • One end of the fifth resistor R5' is connected to one end of the second secondary winding 323, the other end of the fifth resistor R5' is connected to the anode of the third diode D3', and the anode of the third diode D3' is OR gate.
  • the second input end of the circuit 333 is connected, one end of the sixth resistor R6' is connected to one end of the second secondary winding 323, and the other end of the sixth resistor R6' is connected to the second input end of the OR circuit 333, the third capacitor One end of C3' is connected to the second input end of the OR circuit 333, the other end of the third capacitor C3' is connected to the other end of the second sub-side winding 323, and one end of the seventh resistor R7' is opposite to the OR gate circuit 333.
  • the two input terminals are connected, the other end of the seventh resistor R7' is connected to the other end of the second secondary winding 323, and the anode of the fourth diode D4' is connected to the other end of the second secondary winding 323, and the fourth pole
  • the cathode of the tube D4' is connected to the second input of the OR circuit 333.
  • FIG. 6 is a voltage waveform diagram of each point in FIG.
  • the double-ended excitation signal driving control circuit 31 generates a first pulse driving signal and a second pulse driving signal, and the first pulse driving signal is input from one end of the first primary winding 321 of the isolation driving transformer 32.
  • the second pulse driving signal is input from the other end of the first primary winding 321 of the isolation driving transformer 32.
  • the frequency of the first pulse driving signal is the same as the frequency of the second pulse driving signal, the duty ratio of the first pulse driving signal and the duty ratio of the second pulse driving signal are the same, and the high time of the first pulse driving signal is The high-level time of the second pulse driving signal is engaged back and forth, and then the first pulse driving signal and the second pulse driving signal are both low.
  • the high level time of the second pulse driving signal and the high level time of the first pulse driving signal are connected before and after.
  • the input first pulse driving signal is outputted by the isolating driving transformer 32.
  • the first output circuit 331 and the second output circuit 332 Up to the first output circuit 331 and the second output circuit 332, at which time C' of the first output circuit 331 is low, and E' of the first output circuit 331 is discharged through the third resistor R3', so the first output circuit 331 E' is also low, that is, the first low level signal is input to the first input of the OR circuit 333.
  • D' of the second output circuit 332 is at a high potential, and F' of the second output circuit 332 is charged through the fifth resistor R5' and the third diode D3', so the F' of the second output circuit 332 is also high.
  • the potential, i.e., the second input of the OR gate 333 inputs a second high level signal.
  • the output G' of the OR gate 333 is a high level drive signal.
  • the input second pulse driving signal is outputted by the isolating driving transformer 32.
  • the first output circuit 331 and the second output circuit 332 Up to the first output circuit 331 and the second output circuit 332, at which time C' of the first output circuit 331 is high, and the E of the first output circuit 331 is passed through the second resistor R2' and the first diode D1' 'Charging, so E' of the first output circuit 331 is also high, that is, the first high level signal is input to the first input terminal of the OR circuit 333.
  • D' of the second output circuit 332 is low, and F' of the second output circuit 332 is discharged through the sixth resistor R6', so F' of the second output circuit 332 is also low, that is, the second of the OR circuit 333
  • the input terminal inputs a second low level signal.
  • the output G' of the OR gate 333 is still a high level drive signal.
  • the frequency and the duty ratio of the first pulse driving signal and the second pulse driving signal are the same, both are half of the duty ratio of the driving signal output from the OR circuit 333, and then the first pulse driving signal and the second pulse driving signal are from Isolating the different terminal inputs of the first primary winding 321 of the drive transformer 32 ensures isolation of the magnetic reset of the drive transformer 32 without the need for a DC-blocking magnetic reset.
  • the isolated driving circuit of the present invention synthesizes the first pulse driving signal and the second pulse driving signal into a continuous driving signal for output by the pulse driving signal conversion circuit 33, and realizes on the basis of ensuring the magnetic reset of the isolated driving transformer 32.
  • the specific flow of the synthesis of the first pulse drive signal and the second pulse drive signal will be described below.
  • FIG. 7 is a schematic diagram of the synthesis of a driving signal through an OR gate circuit of a preferred embodiment of the isolated driving circuit of the present invention.
  • E' of the first output circuit 331 is at a low potential
  • F' of the second output circuit 332 is at a high potential
  • the gate circuit 333 is The output G' is a high level driving signal; when the first pulse driving signal is low level and the second pulse driving signal is low level, E' of the first output circuit 331 is high potential, and F of the second output circuit 332 'It is low, or the output G' of the gate circuit 333 is a high level drive signal.
  • the E' of the first output circuit 331 may still be low, and F' of the second output circuit 332 is also switched to a low potential, at which time the output G' of the OR circuit 333 outputs a short low-level drive while the first pulse drive signal and the second pulse drive signal are switched between high and low levels.
  • the signal may cause the power switch tube to be turned off by mistake.
  • the first output circuit 331 is provided with a first charging and discharging circuit and a first clamping circuit
  • the second output circuit 332 is provided with a second charging and discharging circuit and a second clamping circuit.
  • the discharge speed of F' of circuit 332 makes it possible to extend the high potential time of F' of second output circuit 332.
  • the fourth diode D4' of the second clamp circuit further clamps the potential of the second output circuit 332 at the low potential of F', so that the low potential of F' is not damaged or the gate circuit 333 or the OR gate Circuit 333 produces a false positive. This ensures that the high-low level switching of the first pulse driving signal and the second pulse driving signal, the output G' of the OR circuit 333 outputs a high-level driving signal.
  • the above is an example in which the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are connected back and forth, and how the first pulse driving signal and the second pulse driving signal are combined.
  • the high-level time of the second pulse driving signal and the high-level time of the first pulse driving signal can also be connected before and after.
  • the D' of the second output circuit 332 is at a high level, and can pass the fifth resistor R5' and The third diode D3' quickly charges F' of the second output circuit 332 such that F' of the second output circuit 332 can quickly reach a high potential.
  • the C' of the first output circuit 331 is low, and the E' of the first output circuit 331 is discharged through the third resistor R3'. Under the action of the third resistor R3' and the second capacitor C2', the first output can be slowed down.
  • the throwing speed of E' of the circuit 331 makes it possible to extend the high potential time of E' of the first output circuit 331.
  • the second diode D2' of the first clamp circuit further clamps the potential of the E' low potential of the first output circuit 331 so that the low potential of E' is not damaged or the gate 333 or the OR gate Circuit 333 produces a false positive. This ensures that the high-low level switching of the first pulse driving signal and the second pulse driving signal, the output G' of the OR circuit 333 outputs a high-level driving signal.
  • the isolated drive circuit of the present invention further includes an anti-DC bias circuit for preventing DC biasing of the isolated drive transformer 32.
  • the anti-DC bias circuit is connected to the double-ended excitation signal drive control circuit 31 and the isolated drive transformer 32, respectively.
  • the DC-blocking bias circuit includes a first resistor R1' and a first capacitor C1'. One end of the first resistor R1' is connected to one end of the first capacitor C1' and the pulse driving signal conversion circuit 33, respectively. The other end of the first resistor R1' is connected to the other end of the first capacitor C1' and the isolated drive transformer 32, respectively.
  • the isolated driving transformer 32 When the duty ratio of the first pulse driving signal and the duty ratio of the second pulse driving signal are different, the isolated driving transformer 32 generates a DC bias phenomenon, so that the isolated driving transformer 32 cannot be completely magnetically reset.
  • the magnetic bias reset of the isolated drive transformer 32 in the above case can be ensured by the anti-DC bias circuit.
  • the isolated drive circuit of the present invention further includes a power amplifying circuit for amplifying the drive signal output from the pulse drive signal conversion circuit 33.
  • the power amplifying circuit is connected to the output of the pulse drive signal conversion circuit 33. This further ensures the power of the drive signal driving the power switch.
  • FIG. 8 is a specific circuit diagram showing a second preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated driving transformer includes a first primary winding 321 and a second primary winding 324, and the first pulse driving signal is input by the A1' end of the first primary winding 321 .
  • the second pulse drive signal is input from the B2' terminal of the second primary winding 324, so that the same advantageous effects as the first preferred embodiment can be achieved.
  • the same name end of the first primary winding 321 and the second primary winding 324 is set as shown in FIG.
  • FIG. 9 is a specific circuit diagram showing a third preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated drive transformer further includes a first backup secondary winding 325
  • the pulse drive signal conversion circuit further includes a first standby output circuit 334
  • the first standby output circuit 334 When the second pulse driving signal is at a high level, the first high level signal is output, and when the second pulse driving signal is at a low level, the first low level signal is output.
  • One end of the first standby output circuit 334 is connected to the first standby secondary winding 325, and the other end of the first standby output circuit 334 is connected to the first input of the OR gate circuit 333.
  • the same name end of the first standby secondary winding 325 is set as shown in FIG.
  • the isolated driving circuit of the present invention can also operate normally.
  • FIG. 10 is a detailed circuit diagram showing a fourth preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated drive transformer further includes a second backup secondary winding 326
  • the pulse drive signal conversion circuit further includes a second standby output circuit 335
  • the second standby output circuit 335 When the first pulse driving signal is at a high level, the second high level signal is output, and when the first pulse driving signal is at a low level, the second low level signal is output.
  • One end of the second standby output circuit 335 is connected to the second standby secondary winding 326, and the other end of the second standby output circuit 335 is connected to the second input of the OR circuit 333.
  • the same name end of the second standby secondary winding 326 is set as shown in FIG.
  • the isolated driving circuit of the present invention can also operate normally.
  • FIG. 11 is a specific circuit diagram of a fifth preferred embodiment of the isolated driving circuit of the present invention.
  • the present embodiment differs from the first preferred embodiment in that the isolated drive transformer includes both a first backup secondary winding 325 and a second backup secondary winding 326.
  • the pulse drive signal conversion circuit further includes a first standby output circuit 334 and a second standby output circuit 335.
  • the first standby output circuit 334 is configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level; the second standby output The circuit 335 is configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level.
  • first standby output circuit 334 is connected to the first standby secondary winding 325, the other end of the first standby output circuit 334 is connected to the first input terminal of the OR gate circuit 333, and one end of the second standby output circuit 335 is connected to the second
  • the alternate secondary winding 326 is coupled and the other end of the second alternate output circuit 335 is coupled to the second input of the OR gate 333.
  • the same name end of the first standby secondary winding 325 and the second standby secondary winding 326 are arranged as shown in FIG.
  • the design of the dual standby secondary winding and the alternate output circuit described above makes the isolated drive circuit of the present invention more stable.
  • the isolated drive circuit of the present invention may further include a plurality of pulse drive signal conversion circuits.
  • FIG. 12 is a specific circuit diagram of a sixth preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated driving circuit includes two pulse driving signal conversion circuits, and each pulse driving signal conversion circuit output signal can drive a power switch tube.
  • the specific working principle of each pulse driving signal conversion circuit is the same as that of the pulse driving signal conversion circuit in the first preferred embodiment of the above isolated driving circuit. Please refer to the first preferred embodiment of the above isolated driving circuit. Therefore, the present invention uses a double-ended excitation signal drive control circuit to simultaneously drive a plurality of pulse drive signal conversion circuits, and the change in the number of drive pulse drive signal conversion circuits does not limit the scope of protection of the present invention.
  • the isolated driving circuit of the invention effectively avoids the reduction of the driving voltage amplitude of the secondary winding of the isolated driving transformer 32 during the isolated driving and the wide duty ratio transmission of the conventional isolated driving transformer 32, and avoids the isolation driving transformer During the magnetic reset process of 32, the resonance of the DC blocking capacitor and the excitation inductance of the driving transformer causes the power switch tube that is turned off to be mis-conducted.

Abstract

La présente invention concerne un circuit d'attaque isolé comprenant un transformateur d'attaque isolé, un circuit d'attaque et de commande de signal d'excitation à double extrémité et un circuit de conversion de signal d'attaque par impulsion, le circuit d'attaque et de commande de signal d'excitation à double extrémité étant destiné à produire un premier signal d'attaque par impulsion et un second signal d'attaque par impulsion ; et le circuit de conversion de signal d'attaque par impulsion étant destiné à convertir un signal de sortie d'un enroulement secondaire en un signal d'attaque destiné à attaquer un tube de commutation d'énergie correspondant. Le circuit d'attaque isolé selon la présente invention peut éviter les oscillations de résonance causées par les inductances magnétiques d'un condensateur de blocage et d'un transformateur d'attaque.
PCT/CN2012/083076 2012-10-17 2012-10-17 Circuit d'attaque isolé WO2014059620A1 (fr)

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PCT/CN2012/083076 WO2014059620A1 (fr) 2012-10-17 2012-10-17 Circuit d'attaque isolé

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CN110425174A (zh) * 2019-07-24 2019-11-08 许继电源有限公司 风机调速电路、多路并联风机调速电路
CN111082799A (zh) * 2019-12-25 2020-04-28 广州金升阳科技有限公司 信号隔离传输电路
CN112313862A (zh) * 2018-06-22 2021-02-02 华为技术有限公司 隔离驱动器
CN114244078A (zh) * 2021-11-30 2022-03-25 广州金升阳科技有限公司 一种驱动控制方法、边沿调制电路及驱动控制电路
CN116073809A (zh) * 2023-03-23 2023-05-05 杭州飞仕得科技股份有限公司 一种脉冲变压器信号双向传输装置及其保护方法

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CN102916570A (zh) * 2012-09-27 2013-02-06 深圳市安能能源技术有限公司 隔离驱动电路
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CN112313862A (zh) * 2018-06-22 2021-02-02 华为技术有限公司 隔离驱动器
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CN111082799A (zh) * 2019-12-25 2020-04-28 广州金升阳科技有限公司 信号隔离传输电路
CN111082799B (zh) * 2019-12-25 2023-06-06 广州金升阳科技有限公司 信号隔离传输电路
CN114244078A (zh) * 2021-11-30 2022-03-25 广州金升阳科技有限公司 一种驱动控制方法、边沿调制电路及驱动控制电路
CN114244078B (zh) * 2021-11-30 2024-02-13 广州金升阳科技有限公司 一种驱动控制方法、边沿调制电路及驱动控制电路
CN116073809A (zh) * 2023-03-23 2023-05-05 杭州飞仕得科技股份有限公司 一种脉冲变压器信号双向传输装置及其保护方法
CN116073809B (zh) * 2023-03-23 2023-06-16 杭州飞仕得科技股份有限公司 一种脉冲变压器信号双向传输装置及其保护方法

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