WO2014059620A1 - Isolated driving circuit - Google Patents

Isolated driving circuit Download PDF

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Publication number
WO2014059620A1
WO2014059620A1 PCT/CN2012/083076 CN2012083076W WO2014059620A1 WO 2014059620 A1 WO2014059620 A1 WO 2014059620A1 CN 2012083076 W CN2012083076 W CN 2012083076W WO 2014059620 A1 WO2014059620 A1 WO 2014059620A1
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WO
WIPO (PCT)
Prior art keywords
circuit
signal
driving signal
pulse
isolated
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PCT/CN2012/083076
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French (fr)
Chinese (zh)
Inventor
胡祖荣
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深圳市安能能源技术有限公司
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Priority to PCT/CN2012/083076 priority Critical patent/WO2014059620A1/en
Publication of WO2014059620A1 publication Critical patent/WO2014059620A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
    • H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling

Definitions

  • the present invention relates to the field of drive circuits, and more particularly to an isolated drive circuit that avoids resonance due to a DC blocking capacitor and a drive transformer magnetizing inductance.
  • the pulse transformer isolation drive circuit is a common power switch tube drive circuit. It has the advantages of simple circuit structure, no need to provide isolated power supply, low cost and no transmission delay for pulse signals, and can meet the requirements of the power switch tube drive circuit. Electrical isolation, rapidity, and strong drive requirements.
  • FIG. 1 is a conventional pulse transformer isolation driving circuit.
  • the isolation driving circuit includes a resistor R1, a DC blocking capacitor C1, and an isolated driving transformer T1.
  • the isolation driving transformer T1 includes a primary winding and a secondary winding. Winding.
  • the driving pulse from the control circuit is at a high level and is added between the point A and the primary winding reference ground B, after the bootstrap by the isolation conversion and the negative voltage, the reference point D is output at the point C and the secondary winding.
  • the DC blocking capacitor C1 provides a negative voltage
  • the drive transformer T1 is isolated to perform a magnetic reset.
  • FIG. 2 is another conventional pulse transformer isolation driving circuit, which includes a resistor R1, a DC blocking capacitor C1, an isolation driving transformer T1, a bootstrap capacitor C2, and a bootstrap diode D1.
  • the drive transformer T1 includes a primary winding and a secondary winding.
  • the isolation driving circuit is provided with a bootstrap capacitor C2 and a bootstrap diode D1 in the secondary winding of the isolation driving transformer T1.
  • U0 is the conduction voltage drop of the bootstrap diode D1, and its value is small.
  • the primary side voltage of the isolated driving transformer T1 is Udrive-Uc1
  • the secondary side voltage of the isolated drive transformer T1 is also Udrive-Uc1
  • the voltage amplitude of the driving voltage is almost constant during the transmission.
  • the pulse transformer isolation driving circuit shown in FIG. 2 can ensure that the power switching tube is normally driven when the duty ratio of the driving pulse is large.
  • the pulse transformer isolation driving circuit shown in FIG. 1 and FIG. 2 has a disadvantage: the two pulse transformer isolation driving circuits all rely on the DC capacitor C1 to realize the magnetic reset of the isolated driving transformer T1. Due to the presence of the DC blocking capacitor C1, when the driving pulse of the control circuit is turned off, the DC-capacitor C1 and the magnetizing inductance of the isolated driving transformer T1 will resonate, so that the primary and secondary windings of the isolated driving transformer T1 are highly generated. Oscillation voltage may cause the power switch tube that is turned off to be mis-conducted.
  • the object of the present invention is to provide an isolated driving circuit capable of avoiding resonance due to a DC blocking capacitor and a driving transformer magnetizing inductance, and solving the problem that the existing isolated driving circuit resonates due to a DC blocking capacitor and a driving transformer magnetizing inductance, which may cause a shutdown.
  • the invention relates to an isolated drive circuit comprising:
  • Isolate the drive transformer including the primary winding and the secondary winding;
  • a double-ended excitation signal driving control circuit for generating a first pulse driving signal and a second pulse driving signal, wherein the first pulse driving signal and the second pulse driving signal are input by the primary winding;
  • At least one pulse drive signal conversion circuit for converting an output signal of the secondary winding into a drive signal for driving a corresponding power switch tube
  • the double-ended excitation signal driving control circuit is connected to a primary winding of the isolated driving transformer, and a secondary winding of the isolated driving transformer is connected to the pulse driving signal conversion circuit;
  • the isolated drive transformer includes a first primary winding, the first pulse driving signal is input by one end of the first primary winding, and the second pulse driving signal is input by the other end of the first primary winding ;
  • the isolation driving circuit further includes an anti-DC biasing circuit for preventing a DC bias phenomenon of the isolated driving transformer, the DC blocking biasing circuit and the double-ended excitation signal driving control circuit and the isolation driving respectively Transformer connection
  • the anti-DC bias circuit includes a first resistor and a first capacitor, and one end of the first resistor is respectively connected to one end of the first capacitor and the pulse driving signal conversion circuit, and the other end of the first resistor Connected to the other end of the first capacitor and the isolated drive transformer, respectively.
  • the invention also relates to an isolated drive circuit comprising:
  • Isolate the drive transformer including the primary winding and the secondary winding;
  • a double-ended excitation signal driving control circuit for generating a first pulse driving signal and a second pulse driving signal, wherein the first pulse driving signal and the second pulse driving signal are input by the primary winding;
  • At least one pulse drive signal conversion circuit for converting an output signal of the secondary winding into a drive signal for driving a corresponding power switch tube
  • the double-ended excitation signal driving control circuit is connected to a primary winding of the isolated driving transformer, and a secondary winding of the isolated driving transformer is connected to the pulse driving signal conversion circuit.
  • the isolated driving transformer includes a first primary winding, the first pulse driving signal is input by one end of the first primary winding, and the second pulse driving signal is The other end of the first primary winding is input.
  • the isolated driving transformer includes a first primary winding and a second primary winding, and the first pulse driving signal is input by the first primary winding, and the second pulse A drive signal is input by the second primary winding.
  • the frequency of the first pulse driving signal and the frequency of the second pulse driving signal are the same, the duty ratio of the first pulse driving signal and the second pulse driving signal The duty ratio is the same, the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are connected back and forth, or the high-level time of the second pulse driving signal and the The high-level time of the first pulse driving signal is connected back and forth.
  • the second pulse driving signal when the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are connected back and forth, the second pulse driving signal is low-powered a time point at which the flat start transitioning to a high level is earlier than a time point at which the first pulse drive signal is switched from a high level to a low level;
  • a time point at which the first pulse driving signal is switched from a low level to a high level A time point earlier than the second pulse drive signal transitioning from a high level to a low level.
  • the isolated driving transformer includes a first secondary winding and a second secondary winding
  • the pulse drive signal conversion circuit includes:
  • a first output circuit configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level;
  • a second output circuit configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level;
  • An OR circuit comprising: a first input terminal, a second input terminal, and an output terminal; configured to: when the first output circuit outputs the first low level signal, and the second output circuit outputs the second low When the level signal is output, the low level driving signal is output; otherwise, the high level driving signal is output;
  • One end of the first output circuit is connected to the first secondary winding, and the other end of the first output circuit is connected to a first input end of the OR circuit; one end of the second output circuit The second secondary winding is connected, and the other end of the second output circuit is connected to the second input of the OR circuit.
  • the first output circuit comprises:
  • a first charge and discharge circuit for shortening a time of a rising edge of the first high level signal and extending a time of a falling edge of the first high level signal
  • a first clamping circuit for clamping the first low level signal.
  • the first charging and discharging circuit includes a second resistor, a third resistor, a fourth resistor, a first diode, and a second capacitor
  • the first clamping circuit includes a second diode
  • One end of the second resistor is connected to one end of the first secondary winding, the other end of the second resistor is connected to the anode of the first diode, and the anode of the first diode is Connected to a first input end of the OR circuit, one end of the third resistor is connected to one end of the first secondary winding, and the other end of the third resistor is connected to a first input end of the OR gate circuit
  • One end of the second capacitor is connected to the first input end of the OR gate circuit, and the other end of the second capacitor is connected to the other end of the first secondary winding, and one end of the fourth resistor is a first input end of the OR circuit is connected, and another end of the fourth resistor is connected to another end of the first secondary winding, a positive pole of the second diode and the first secondary winding
  • the other end of the second diode is connected to the first input of the OR circuit.
  • the second output circuit comprises:
  • a second charge and discharge circuit for shortening a time of a rising edge of the second high level signal and extending a time of a falling edge of the second high level signal
  • a second clamping circuit for clamping the second low level signal.
  • the second charging and discharging circuit includes a fifth resistor, a sixth resistor, a seventh resistor, a third diode, and a third capacitor
  • the second clamping circuit includes a fourth diode
  • One end of the fifth resistor is connected to one end of the second secondary winding, the other end of the fifth resistor is connected to the anode of the third diode, and the cathode of the third diode is Connecting a second input end of the OR circuit, one end of the sixth resistor is connected to one end of the second secondary winding, and the other end of the sixth resistor is connected to the second input end of the OR circuit
  • One end of the third capacitor is connected to the second input end of the OR gate circuit, and the other end of the third capacitor is connected to the other end of the second secondary winding
  • one end of the seventh resistor is a second input end of the OR circuit is connected, and another end of the seventh resistor is connected to another end of the second secondary winding, and a positive pole of the fourth diode and the second secondary winding
  • the other end of the fourth diode is connected to the second input of the OR gate.
  • the isolated driving transformer further includes a first standby secondary winding and a second standby secondary winding;
  • the pulse drive signal conversion circuit further includes:
  • a first standby output circuit configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level;
  • a second standby output circuit configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level;
  • first standby output circuit One end of the first standby output circuit is connected to the first standby secondary winding, and the other end of the first standby output circuit is connected to a first input end of the OR gate circuit; the second standby output circuit One end is connected to the second standby secondary winding, and the other end of the second standby output circuit is connected to the second input of the OR circuit.
  • the isolated driving circuit includes an anti-DC biasing circuit for preventing a DC bias phenomenon of the isolated driving transformer, and the DC blocking bias circuit and the double-ended excitation respectively a signal driving control circuit and the isolated driving transformer are connected;
  • the DC-blocking bias circuit includes a first resistor and a first capacitor, and one end of the first resistor is respectively connected to one end of the first capacitor and the pulse driving signal conversion circuit Connected, the other end of the first resistor is respectively connected to the other end of the first capacitor and the isolated driving transformer.
  • the isolated driving circuit further includes:
  • a power amplifying circuit for amplifying the driving signal output by the pulse driving signal conversion circuit
  • the power amplifying circuit is connected to the pulse driving signal conversion circuit.
  • the isolated driving circuit of the invention can avoid resonance due to the DC blocking capacitor and the excitation inductance of the driving transformer, and solves the resonance of the existing isolated driving circuit due to the DC blocking capacitance and the driving transformer excitation inductance.
  • 1 is a conventional pulse transformer isolation driving circuit
  • FIG. 3 is a schematic block diagram of a first preferred embodiment of an isolated driving circuit of the present invention.
  • FIG. 4 is a schematic diagram of a specific module of a first preferred embodiment of the isolated driving circuit of the present invention.
  • Figure 5 is a specific circuit diagram of a first preferred embodiment of the isolated drive circuit of the present invention.
  • Figure 6 is a voltage waveform diagram of each point in Figure 5;
  • FIG. 7 is a schematic diagram of signal synthesis of a driving signal through an OR gate circuit of a preferred embodiment of the isolated driving circuit of the present invention.
  • Figure 8 is a specific circuit diagram of a second preferred embodiment of the isolated drive circuit of the present invention.
  • Figure 9 is a specific circuit diagram of a third preferred embodiment of the isolated drive circuit of the present invention.
  • Figure 10 is a specific circuit diagram of a fourth preferred embodiment of the isolated drive circuit of the present invention.
  • Figure 11 is a specific circuit diagram of a fifth preferred embodiment of the isolated drive circuit of the present invention.
  • FIG. 12 is a specific circuit diagram of a sixth preferred embodiment of the isolated driving circuit of the present invention.
  • FIG. 3 is a schematic block diagram of a first preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated drive circuit includes an isolated drive transformer 32, a double-ended excitation signal drive control circuit 31, and a pulse drive signal conversion circuit 33.
  • the isolated driving transformer 32 includes a first primary winding and a secondary winding;
  • the double-ended excitation signal driving control circuit 31 is configured to generate a first pulse driving signal and a second pulse driving signal, the first pulse driving signal being the first primary winding One end of the input, the second pulse driving signal is input from the other end of the first primary winding;
  • the pulse driving signal conversion circuit 33 is for converting the output signal of the secondary winding of the isolated driving transformer 32 into a driving signal, and then using the driving signal Drive the corresponding power switch tube.
  • the double-ended excitation signal drive control circuit 31 is connected to the first primary winding of the isolated drive transformer 32, and the secondary winding of the isolated drive transformer 32 is connected to the input of the pulse drive signal conversion circuit 33, and the output of the pulse drive signal conversion circuit 33 is The power switch tube to be driven is connected.
  • FIG. 4 is a schematic diagram of a specific module of a first preferred embodiment of the isolated driving circuit of the present invention
  • FIG. 5 is a specific circuit diagram of a first preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated drive transformer 32 includes a first primary winding 321 , a first secondary winding 322 , and a second secondary winding 323 .
  • the pulse driving signal conversion circuit 33 includes a first output circuit 331, a second output circuit 332, and an OR gate circuit 333, wherein the first output circuit 331 is configured to output a first high level signal when the second pulse signal is at a high level, When the second pulse driving signal is low level, the first low level signal is output; the second output circuit 332 is configured to output the second high level signal when the first pulse driving signal is high level, when the first pulse is driven When the signal is low, the second low level signal is output; or the gate circuit 333 includes a first input end, a second input end, and an output end, when the first output circuit 331 outputs the first low level signal to the first At the input end, when the second output circuit 332 outputs the second low level signal to the second input end, the output end outputs a low level driving signal, otherwise the output end outputs a high level driving signal.
  • One end of the first output circuit 331 is connected to the first secondary winding 322, the other end of the first output circuit 331 is connected to the first input terminal of the OR gate circuit 333, and one end of the second output circuit 332 and the second secondary winding 323 Connected, the other end of the second output circuit 332 is coupled to the second input of the OR gate circuit 333.
  • the same name end of the first primary winding 321 , the first secondary winding 322 and the second secondary winding 323 are arranged as shown in FIG. 5 .
  • the OR gate circuit 333 herein may be an integrated logic gate circuit or an OR gate circuit composed of discrete components.
  • the first output circuit 331 includes a first charge and discharge circuit and a first clamp circuit
  • the second output circuit 332 includes a second charge and discharge circuit and a second clamp circuit
  • the first charging and discharging circuit is configured to shorten the time of the rising edge of the first high level signal and extend the time of the falling edge of the first high level signal; the first clamping circuit is configured to perform the first low level signal Clamp.
  • the first charging and discharging circuit includes a second resistor R2', a third resistor R3', a fourth resistor R4', a first diode D1', and a second capacitor C2'; the first clamping circuit includes a second diode D2 '.
  • One end of the second resistor R2' is connected to one end of the first secondary winding 322, the other end of the second resistor R2' is connected to the anode of the first diode D1', and the negative terminal and OR gate of the first diode D1'
  • the first input end of the circuit 333 is connected, one end of the third resistor R3' is connected to one end of the first secondary winding 322, and the other end of the third resistor R3' is connected to the first input end of the OR circuit 333, and the second capacitor One end of C2' is connected to the first input end of the OR circuit 333, the other end of the second capacitor C2' is connected to the other end of the first sub-side winding 322, and one end of the fourth resistor R4' is opposite to the OR gate 333.
  • One input terminal is connected, the other end of the fourth resistor R4' is connected to the other end of the first secondary winding 322, and the anode of the second diode D2' is connected to the other end of the first secondary winding 322, and the second diode
  • the cathode of the tube D2' is connected to the first input of the OR circuit 333.
  • the second charging and discharging circuit is configured to shorten the rising edge of the second high level signal and extend the interval between the falling edges of the second high level signal; the second clamping circuit is configured to perform the second low level signal Clamp.
  • the second charging and discharging circuit includes a fifth resistor R5', a sixth resistor R6', a seventh resistor R7', a third diode D3', and a third capacitor C3', and the second clamping circuit includes a fourth diode D4 '.
  • One end of the fifth resistor R5' is connected to one end of the second secondary winding 323, the other end of the fifth resistor R5' is connected to the anode of the third diode D3', and the anode of the third diode D3' is OR gate.
  • the second input end of the circuit 333 is connected, one end of the sixth resistor R6' is connected to one end of the second secondary winding 323, and the other end of the sixth resistor R6' is connected to the second input end of the OR circuit 333, the third capacitor One end of C3' is connected to the second input end of the OR circuit 333, the other end of the third capacitor C3' is connected to the other end of the second sub-side winding 323, and one end of the seventh resistor R7' is opposite to the OR gate circuit 333.
  • the two input terminals are connected, the other end of the seventh resistor R7' is connected to the other end of the second secondary winding 323, and the anode of the fourth diode D4' is connected to the other end of the second secondary winding 323, and the fourth pole
  • the cathode of the tube D4' is connected to the second input of the OR circuit 333.
  • FIG. 6 is a voltage waveform diagram of each point in FIG.
  • the double-ended excitation signal driving control circuit 31 generates a first pulse driving signal and a second pulse driving signal, and the first pulse driving signal is input from one end of the first primary winding 321 of the isolation driving transformer 32.
  • the second pulse driving signal is input from the other end of the first primary winding 321 of the isolation driving transformer 32.
  • the frequency of the first pulse driving signal is the same as the frequency of the second pulse driving signal, the duty ratio of the first pulse driving signal and the duty ratio of the second pulse driving signal are the same, and the high time of the first pulse driving signal is The high-level time of the second pulse driving signal is engaged back and forth, and then the first pulse driving signal and the second pulse driving signal are both low.
  • the high level time of the second pulse driving signal and the high level time of the first pulse driving signal are connected before and after.
  • the input first pulse driving signal is outputted by the isolating driving transformer 32.
  • the first output circuit 331 and the second output circuit 332 Up to the first output circuit 331 and the second output circuit 332, at which time C' of the first output circuit 331 is low, and E' of the first output circuit 331 is discharged through the third resistor R3', so the first output circuit 331 E' is also low, that is, the first low level signal is input to the first input of the OR circuit 333.
  • D' of the second output circuit 332 is at a high potential, and F' of the second output circuit 332 is charged through the fifth resistor R5' and the third diode D3', so the F' of the second output circuit 332 is also high.
  • the potential, i.e., the second input of the OR gate 333 inputs a second high level signal.
  • the output G' of the OR gate 333 is a high level drive signal.
  • the input second pulse driving signal is outputted by the isolating driving transformer 32.
  • the first output circuit 331 and the second output circuit 332 Up to the first output circuit 331 and the second output circuit 332, at which time C' of the first output circuit 331 is high, and the E of the first output circuit 331 is passed through the second resistor R2' and the first diode D1' 'Charging, so E' of the first output circuit 331 is also high, that is, the first high level signal is input to the first input terminal of the OR circuit 333.
  • D' of the second output circuit 332 is low, and F' of the second output circuit 332 is discharged through the sixth resistor R6', so F' of the second output circuit 332 is also low, that is, the second of the OR circuit 333
  • the input terminal inputs a second low level signal.
  • the output G' of the OR gate 333 is still a high level drive signal.
  • the frequency and the duty ratio of the first pulse driving signal and the second pulse driving signal are the same, both are half of the duty ratio of the driving signal output from the OR circuit 333, and then the first pulse driving signal and the second pulse driving signal are from Isolating the different terminal inputs of the first primary winding 321 of the drive transformer 32 ensures isolation of the magnetic reset of the drive transformer 32 without the need for a DC-blocking magnetic reset.
  • the isolated driving circuit of the present invention synthesizes the first pulse driving signal and the second pulse driving signal into a continuous driving signal for output by the pulse driving signal conversion circuit 33, and realizes on the basis of ensuring the magnetic reset of the isolated driving transformer 32.
  • the specific flow of the synthesis of the first pulse drive signal and the second pulse drive signal will be described below.
  • FIG. 7 is a schematic diagram of the synthesis of a driving signal through an OR gate circuit of a preferred embodiment of the isolated driving circuit of the present invention.
  • E' of the first output circuit 331 is at a low potential
  • F' of the second output circuit 332 is at a high potential
  • the gate circuit 333 is The output G' is a high level driving signal; when the first pulse driving signal is low level and the second pulse driving signal is low level, E' of the first output circuit 331 is high potential, and F of the second output circuit 332 'It is low, or the output G' of the gate circuit 333 is a high level drive signal.
  • the E' of the first output circuit 331 may still be low, and F' of the second output circuit 332 is also switched to a low potential, at which time the output G' of the OR circuit 333 outputs a short low-level drive while the first pulse drive signal and the second pulse drive signal are switched between high and low levels.
  • the signal may cause the power switch tube to be turned off by mistake.
  • the first output circuit 331 is provided with a first charging and discharging circuit and a first clamping circuit
  • the second output circuit 332 is provided with a second charging and discharging circuit and a second clamping circuit.
  • the discharge speed of F' of circuit 332 makes it possible to extend the high potential time of F' of second output circuit 332.
  • the fourth diode D4' of the second clamp circuit further clamps the potential of the second output circuit 332 at the low potential of F', so that the low potential of F' is not damaged or the gate circuit 333 or the OR gate Circuit 333 produces a false positive. This ensures that the high-low level switching of the first pulse driving signal and the second pulse driving signal, the output G' of the OR circuit 333 outputs a high-level driving signal.
  • the above is an example in which the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are connected back and forth, and how the first pulse driving signal and the second pulse driving signal are combined.
  • the high-level time of the second pulse driving signal and the high-level time of the first pulse driving signal can also be connected before and after.
  • the D' of the second output circuit 332 is at a high level, and can pass the fifth resistor R5' and The third diode D3' quickly charges F' of the second output circuit 332 such that F' of the second output circuit 332 can quickly reach a high potential.
  • the C' of the first output circuit 331 is low, and the E' of the first output circuit 331 is discharged through the third resistor R3'. Under the action of the third resistor R3' and the second capacitor C2', the first output can be slowed down.
  • the throwing speed of E' of the circuit 331 makes it possible to extend the high potential time of E' of the first output circuit 331.
  • the second diode D2' of the first clamp circuit further clamps the potential of the E' low potential of the first output circuit 331 so that the low potential of E' is not damaged or the gate 333 or the OR gate Circuit 333 produces a false positive. This ensures that the high-low level switching of the first pulse driving signal and the second pulse driving signal, the output G' of the OR circuit 333 outputs a high-level driving signal.
  • the isolated drive circuit of the present invention further includes an anti-DC bias circuit for preventing DC biasing of the isolated drive transformer 32.
  • the anti-DC bias circuit is connected to the double-ended excitation signal drive control circuit 31 and the isolated drive transformer 32, respectively.
  • the DC-blocking bias circuit includes a first resistor R1' and a first capacitor C1'. One end of the first resistor R1' is connected to one end of the first capacitor C1' and the pulse driving signal conversion circuit 33, respectively. The other end of the first resistor R1' is connected to the other end of the first capacitor C1' and the isolated drive transformer 32, respectively.
  • the isolated driving transformer 32 When the duty ratio of the first pulse driving signal and the duty ratio of the second pulse driving signal are different, the isolated driving transformer 32 generates a DC bias phenomenon, so that the isolated driving transformer 32 cannot be completely magnetically reset.
  • the magnetic bias reset of the isolated drive transformer 32 in the above case can be ensured by the anti-DC bias circuit.
  • the isolated drive circuit of the present invention further includes a power amplifying circuit for amplifying the drive signal output from the pulse drive signal conversion circuit 33.
  • the power amplifying circuit is connected to the output of the pulse drive signal conversion circuit 33. This further ensures the power of the drive signal driving the power switch.
  • FIG. 8 is a specific circuit diagram showing a second preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated driving transformer includes a first primary winding 321 and a second primary winding 324, and the first pulse driving signal is input by the A1' end of the first primary winding 321 .
  • the second pulse drive signal is input from the B2' terminal of the second primary winding 324, so that the same advantageous effects as the first preferred embodiment can be achieved.
  • the same name end of the first primary winding 321 and the second primary winding 324 is set as shown in FIG.
  • FIG. 9 is a specific circuit diagram showing a third preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated drive transformer further includes a first backup secondary winding 325
  • the pulse drive signal conversion circuit further includes a first standby output circuit 334
  • the first standby output circuit 334 When the second pulse driving signal is at a high level, the first high level signal is output, and when the second pulse driving signal is at a low level, the first low level signal is output.
  • One end of the first standby output circuit 334 is connected to the first standby secondary winding 325, and the other end of the first standby output circuit 334 is connected to the first input of the OR gate circuit 333.
  • the same name end of the first standby secondary winding 325 is set as shown in FIG.
  • the isolated driving circuit of the present invention can also operate normally.
  • FIG. 10 is a detailed circuit diagram showing a fourth preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated drive transformer further includes a second backup secondary winding 326
  • the pulse drive signal conversion circuit further includes a second standby output circuit 335
  • the second standby output circuit 335 When the first pulse driving signal is at a high level, the second high level signal is output, and when the first pulse driving signal is at a low level, the second low level signal is output.
  • One end of the second standby output circuit 335 is connected to the second standby secondary winding 326, and the other end of the second standby output circuit 335 is connected to the second input of the OR circuit 333.
  • the same name end of the second standby secondary winding 326 is set as shown in FIG.
  • the isolated driving circuit of the present invention can also operate normally.
  • FIG. 11 is a specific circuit diagram of a fifth preferred embodiment of the isolated driving circuit of the present invention.
  • the present embodiment differs from the first preferred embodiment in that the isolated drive transformer includes both a first backup secondary winding 325 and a second backup secondary winding 326.
  • the pulse drive signal conversion circuit further includes a first standby output circuit 334 and a second standby output circuit 335.
  • the first standby output circuit 334 is configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level; the second standby output The circuit 335 is configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level.
  • first standby output circuit 334 is connected to the first standby secondary winding 325, the other end of the first standby output circuit 334 is connected to the first input terminal of the OR gate circuit 333, and one end of the second standby output circuit 335 is connected to the second
  • the alternate secondary winding 326 is coupled and the other end of the second alternate output circuit 335 is coupled to the second input of the OR gate 333.
  • the same name end of the first standby secondary winding 325 and the second standby secondary winding 326 are arranged as shown in FIG.
  • the design of the dual standby secondary winding and the alternate output circuit described above makes the isolated drive circuit of the present invention more stable.
  • the isolated drive circuit of the present invention may further include a plurality of pulse drive signal conversion circuits.
  • FIG. 12 is a specific circuit diagram of a sixth preferred embodiment of the isolated driving circuit of the present invention.
  • the isolated driving circuit includes two pulse driving signal conversion circuits, and each pulse driving signal conversion circuit output signal can drive a power switch tube.
  • the specific working principle of each pulse driving signal conversion circuit is the same as that of the pulse driving signal conversion circuit in the first preferred embodiment of the above isolated driving circuit. Please refer to the first preferred embodiment of the above isolated driving circuit. Therefore, the present invention uses a double-ended excitation signal drive control circuit to simultaneously drive a plurality of pulse drive signal conversion circuits, and the change in the number of drive pulse drive signal conversion circuits does not limit the scope of protection of the present invention.
  • the isolated driving circuit of the invention effectively avoids the reduction of the driving voltage amplitude of the secondary winding of the isolated driving transformer 32 during the isolated driving and the wide duty ratio transmission of the conventional isolated driving transformer 32, and avoids the isolation driving transformer During the magnetic reset process of 32, the resonance of the DC blocking capacitor and the excitation inductance of the driving transformer causes the power switch tube that is turned off to be mis-conducted.

Abstract

The present invention relates to an isolated driving circuit comprising an isolated driving transformer, a double-end excitation signal driving and controlling circuit and a pulse-driving signal conversion circuit, wherein the double-end excitation signal driving and controlling circuit is used for generating a first pulse driving signal and a second pulse driving signal; and the pulse-driving signal conversion circuit is used for converting an output signal of a secondary winding into a driving signal which is used for driving a corresponding power switching tube. The isolated driving circuit provided by the present invention can avoid resonance oscillation caused by the magnetic inductances of a blocking capacitor and a driver transformer.

Description

隔离驱动电路  Isolated drive circuit 技术领域Technical field
本发明涉及驱动电路领域，特别是涉及一种可避免由于隔直电容和驱动变压器励磁电感产生谐振的隔离驱动电路。The present invention relates to the field of drive circuits, and more particularly to an isolated drive circuit that avoids resonance due to a DC blocking capacitor and a drive transformer magnetizing inductance.
背景技术Background technique
脉冲变压器隔离驱动电路是一种常见的功率开关管驱动电路，由于其具有电路结构简单、不需要提供隔离电源、成本较低以及对脉冲信号无传输延迟等优点，能够满足功率开关管驱动电路的电气隔离、快速性以及强驱动力的要求。The pulse transformer isolation drive circuit is a common power switch tube drive circuit. It has the advantages of simple circuit structure, no need to provide isolated power supply, low cost and no transmission delay for pulse signals, and can meet the requirements of the power switch tube drive circuit. Electrical isolation, rapidity, and strong drive requirements.
如图1所示，图1为一种现有的脉冲变压器隔离驱动电路，该隔离驱动电路包括电阻R1、隔直电容C1以及隔离驱动变压器T1，该隔离驱动变压器T1包括原边绕组以及副边绕组。当来自控制电路的驱动脉冲为高电平，并加在A点和原边绕组参考地B之间，通过隔离变换、负压自举后，在C点和副边绕组参考地D输出，用来驱动相应的功率开关管。当来自控制电路的驱动脉冲跳变为低电平时，隔直电容C1提供负压，隔离驱动变压器T1进行磁复位。隔直电容C1的电压稳态值为Uc1=EUdrive，其中驱动脉冲的占空比为E（0<E<1），传到隔离驱动变压器T1的副边绕组的驱动脉冲的电压幅值为Us=（1-E）Udrive，该电压幅值随着占空比E的变换而变化，这样当占空比较大时，很难保证有足够幅值的电压来驱动相应的功率开关管。As shown in FIG. 1 , FIG. 1 is a conventional pulse transformer isolation driving circuit. The isolation driving circuit includes a resistor R1, a DC blocking capacitor C1, and an isolated driving transformer T1. The isolation driving transformer T1 includes a primary winding and a secondary winding. Winding. When the driving pulse from the control circuit is at a high level and is added between the point A and the primary winding reference ground B, after the bootstrap by the isolation conversion and the negative voltage, the reference point D is output at the point C and the secondary winding. To drive the corresponding power switch tube. When the drive pulse from the control circuit jumps to a low level, the DC blocking capacitor C1 provides a negative voltage, and the drive transformer T1 is isolated to perform a magnetic reset. The voltage steady state value of the DC blocking capacitor C1 is Uc1=EUdrive, wherein the duty ratio of the driving pulse is E (0<E<1), and the voltage amplitude of the driving pulse transmitted to the secondary winding of the isolated driving transformer T1 is Us = (1-E) Udrive, the voltage amplitude changes with the change of the duty cycle E, so when the duty cycle is large, it is difficult to ensure that there is a voltage of sufficient amplitude to drive the corresponding power switch.
如图2所示，图2为另一种现有的脉冲变压器隔离驱动电路，该隔离驱动电路包括电阻R1、隔直电容C1、隔离驱动变压器T1、自举电容C2以及自举二极管D1，隔离驱动变压器T1包括原边绕组以及副边绕组。该隔离驱动电路在隔离驱动变压器T1的副边绕组设置有自举电容C2以及自举二极管D1。隔直电容C1的电压稳态值依然为Uc1=DUdrive，自举电容C2的电压稳态值为Uc2=Uc1-U0，U0为自举二极管D1的导通压降，其值较小。当来自控制电路的驱动脉冲为高电平，并加在A点和原边绕组参考地B之间时，隔离驱动变压器T1的原边电压为Udrive-Uc1，若隔离驱动变压器T1的匝比为1:1，隔离驱动变压器T1的副边电压也为Udrive-Uc1，这样施加在相应的功率开关管上的电压为Us= Uc1-U0+ Udrive-Uc1= Udrive- U0，驱动电压在传递过程中电压幅值几乎不变。当来自控制电路的驱动脉冲跳变为低电平时，隔直电容C1提供负压，隔离驱动变压器T1进行磁复位。 As shown in FIG. 2, FIG. 2 is another conventional pulse transformer isolation driving circuit, which includes a resistor R1, a DC blocking capacitor C1, an isolation driving transformer T1, a bootstrap capacitor C2, and a bootstrap diode D1. The drive transformer T1 includes a primary winding and a secondary winding. The isolation driving circuit is provided with a bootstrap capacitor C2 and a bootstrap diode D1 in the secondary winding of the isolation driving transformer T1. The voltage steady state value of the DC blocking capacitor C1 is still Uc1=DUdrive, and the voltage steady state value of the bootstrap capacitor C2 is Uc2=Uc1-U0, and U0 is the conduction voltage drop of the bootstrap diode D1, and its value is small. When the driving pulse from the control circuit is at a high level and is applied between the point A and the primary winding reference ground B, the primary side voltage of the isolated driving transformer T1 is Udrive-Uc1, and if the driving ratio of the isolated driving transformer T1 is 1:1, the secondary side voltage of the isolated drive transformer T1 is also Udrive-Uc1, so the voltage applied to the corresponding power switch tube is Us= Uc1-U0+ Udrive-Uc1= Udrive- U0, the voltage amplitude of the driving voltage is almost constant during the transmission. When the drive pulse from the control circuit jumps to a low level, the DC blocking capacitor C1 provides a negative voltage, and the drive transformer T1 is isolated to perform a magnetic reset.
虽然图2所示的脉冲变压器隔离驱动电路可以保证在驱动脉冲的占空比较大时，正常驱动功率开关管。但是图1和图2所示的脉冲变压器隔离驱动电路均具有一缺点：两种脉冲变压器隔离驱动电路均靠隔直电容C1实现隔离驱动变压器T1的磁复位。由于隔直电容C1的存在，当控制电路的驱动脉冲关断时，隔直电容C1和隔离驱动变压器T1的励磁电感会产生谐振，使得在隔离驱动变压器T1的原副边绕组均产生很高的振荡电压，可能会导致关断的功率开关管误导通。Although the pulse transformer isolation driving circuit shown in FIG. 2 can ensure that the power switching tube is normally driven when the duty ratio of the driving pulse is large. However, the pulse transformer isolation driving circuit shown in FIG. 1 and FIG. 2 has a disadvantage: the two pulse transformer isolation driving circuits all rely on the DC capacitor C1 to realize the magnetic reset of the isolated driving transformer T1. Due to the presence of the DC blocking capacitor C1, when the driving pulse of the control circuit is turned off, the DC-capacitor C1 and the magnetizing inductance of the isolated driving transformer T1 will resonate, so that the primary and secondary windings of the isolated driving transformer T1 are highly generated. Oscillation voltage may cause the power switch tube that is turned off to be mis-conducted.
故，有必要提供一种隔离驱动电路，以解决现有技术所存在的问题。Therefore, it is necessary to provide an isolated driving circuit to solve the problems of the prior art.
技术问题technical problem
本发明的目的在于提供一种可避免由于隔直电容和驱动变压器励磁电感产生谐振的隔离驱动电路，解决了现有的隔离驱动电路由于隔直电容和驱动变压器励磁电感产生谐振，可能导致关断的功率开关管误导通的技术问题。The object of the present invention is to provide an isolated driving circuit capable of avoiding resonance due to a DC blocking capacitor and a driving transformer magnetizing inductance, and solving the problem that the existing isolated driving circuit resonates due to a DC blocking capacitor and a driving transformer magnetizing inductance, which may cause a shutdown. The technical problem of the power switch tube mis-conducting.
技术解决方案Technical solution
本发明涉及一种隔离驱动电路，其包括：The invention relates to an isolated drive circuit comprising:
隔离驱动变压器，包括原边绕组以及副边绕组；Isolate the drive transformer, including the primary winding and the secondary winding;
双端激励信号驱动控制电路，用于产生第一脉冲驱动信号和第二脉冲驱动信号，所述第一脉冲驱动信号和所述第二脉冲驱动信号由所述原边绕组输入；以及a double-ended excitation signal driving control circuit for generating a first pulse driving signal and a second pulse driving signal, wherein the first pulse driving signal and the second pulse driving signal are input by the primary winding;
至少一个脉冲驱动信号转换电路，用于将所述副边绕组的输出信号转换为驱动信号，该驱动信号用于驱动相应的功率开关管，At least one pulse drive signal conversion circuit for converting an output signal of the secondary winding into a drive signal for driving a corresponding power switch tube,
所述双端激励信号驱动控制电路与所述隔离驱动变压器的原边绕组连接，所述隔离驱动变压器的副边绕组与所述脉冲驱动信号转换电路连接；The double-ended excitation signal driving control circuit is connected to a primary winding of the isolated driving transformer, and a secondary winding of the isolated driving transformer is connected to the pulse driving signal conversion circuit;
所述隔离驱动变压器包括第一原边绕组，所述第一脉冲驱动信号由所述第一原边绕组的一端输入，所述第二脉冲驱动信号由所述第一原边绕组的另一端输入；The isolated drive transformer includes a first primary winding, the first pulse driving signal is input by one end of the first primary winding, and the second pulse driving signal is input by the other end of the first primary winding ;
所述隔离驱动电路还包括用于防止所述隔离驱动变压器的直流偏磁现象的防直流偏磁电路，所述防直流偏磁电路分别与所述双端激励信号驱动控制电路和所述隔离驱动变压器连接；The isolation driving circuit further includes an anti-DC biasing circuit for preventing a DC bias phenomenon of the isolated driving transformer, the DC blocking biasing circuit and the double-ended excitation signal driving control circuit and the isolation driving respectively Transformer connection
所述防直流偏磁电路包括第一电阻和第一电容，所述第一电阻的一端分别与所述第一电容的一端和所述脉冲驱动信号转换电路连接，所述第一电阻的另一端分别与所述第一电容的另一端和所述隔离驱动变压器连接。The anti-DC bias circuit includes a first resistor and a first capacitor, and one end of the first resistor is respectively connected to one end of the first capacitor and the pulse driving signal conversion circuit, and the other end of the first resistor Connected to the other end of the first capacitor and the isolated drive transformer, respectively.
本发明还涉及一种隔离驱动电路，其包括：The invention also relates to an isolated drive circuit comprising:
隔离驱动变压器，包括原边绕组以及副边绕组；Isolate the drive transformer, including the primary winding and the secondary winding;
双端激励信号驱动控制电路，用于产生第一脉冲驱动信号和第二脉冲驱动信号，所述第一脉冲驱动信号和所述第二脉冲驱动信号由所述原边绕组输入；以及a double-ended excitation signal driving control circuit for generating a first pulse driving signal and a second pulse driving signal, wherein the first pulse driving signal and the second pulse driving signal are input by the primary winding;
至少一个脉冲驱动信号转换电路，用于将所述副边绕组的输出信号转换为驱动信号，该驱动信号用于驱动相应的功率开关管，At least one pulse drive signal conversion circuit for converting an output signal of the secondary winding into a drive signal for driving a corresponding power switch tube,
所述双端激励信号驱动控制电路与所述隔离驱动变压器的原边绕组连接，所述隔离驱动变压器的副边绕组与所述脉冲驱动信号转换电路连接。The double-ended excitation signal driving control circuit is connected to a primary winding of the isolated driving transformer, and a secondary winding of the isolated driving transformer is connected to the pulse driving signal conversion circuit.
在本发明所述隔离驱动电路中，所述隔离驱动变压器包括第一原边绕组，所述第一脉冲驱动信号由所述第一原边绕组的一端输入，所述第二脉冲驱动信号由所述第一原边绕组的另一端输入。In the isolated driving circuit of the present invention, the isolated driving transformer includes a first primary winding, the first pulse driving signal is input by one end of the first primary winding, and the second pulse driving signal is The other end of the first primary winding is input.
在本发明所述隔离驱动电路中，所述隔离驱动变压器包括第一原边绕组以及第二原边绕组，所述第一脉冲驱动信号由所述第一原边绕组输入，所述第二脉冲驱动信号由所述第二原边绕组输入。In the isolated driving circuit of the present invention, the isolated driving transformer includes a first primary winding and a second primary winding, and the first pulse driving signal is input by the first primary winding, and the second pulse A drive signal is input by the second primary winding.
在本发明所述隔离驱动电路中，所述第一脉冲驱动信号的频率和所述第二脉冲驱动信号的频率相同，所述第一脉冲驱动信号的占空比和所述第二脉冲驱动信号的占空比相同，所述第一脉冲驱动信号的高电平时间和所述第二脉冲驱动信号的高电平时间前后衔接，或所述第二脉冲驱动信号的高电平时间和所述第一脉冲驱动信号的高电平时间前后衔接。In the isolated driving circuit of the present invention, the frequency of the first pulse driving signal and the frequency of the second pulse driving signal are the same, the duty ratio of the first pulse driving signal and the second pulse driving signal The duty ratio is the same, the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are connected back and forth, or the high-level time of the second pulse driving signal and the The high-level time of the first pulse driving signal is connected back and forth.
在本发明所述隔离驱动电路中，当所述第一脉冲驱动信号的高电平时间和所述第二脉冲驱动信号的高电平时间前后衔接时，所述第二脉冲驱动信号由低电平开始转换为高电平的时间点早于等于所述第一脉冲驱动信号由高电平开始转换为低电平的时间点；In the isolated driving circuit of the present invention, when the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are connected back and forth, the second pulse driving signal is low-powered a time point at which the flat start transitioning to a high level is earlier than a time point at which the first pulse drive signal is switched from a high level to a low level;
当所述第二脉冲驱动信号的高电平时间和所述第一脉冲驱动信号的高电平时间前后衔接时，所述第一脉冲驱动信号由低电平开始转换为高电平的时间点早于等于所述第二脉冲驱动信号由高电平开始转换为低电平的时间点。When the high-level time of the second pulse driving signal and the high-level time of the first pulse driving signal are connected back and forth, a time point at which the first pulse driving signal is switched from a low level to a high level A time point earlier than the second pulse drive signal transitioning from a high level to a low level.
在本发明所述隔离驱动电路中，所述隔离驱动变压器包括第一副边绕组以及第二副边绕组；In the isolated driving circuit of the present invention, the isolated driving transformer includes a first secondary winding and a second secondary winding;
所述脉冲驱动信号转换电路包括：The pulse drive signal conversion circuit includes:
第一输出电路，用于当所述第二脉冲驱动信号为高电平时，输出第一高电平信号，当所述第二脉冲驱动信号为低电平时，输出第一低电平信号；a first output circuit, configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level;
第二输出电路，用于当所述第一脉冲驱动信号为高电平时，输出第二高电平信号，当所述第一脉冲驱动信号为低电平时，输出第二低电平信号；以及a second output circuit, configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level;
或门电路，包括第一输入端、第二输入端以及输出端；用于当所述第一输出电路输出所述第一低电平信号，同时所述第二输出电路输出所述第二低电平信号时，输出低电平驱动信号；否则输出高电平驱动信号；An OR circuit comprising: a first input terminal, a second input terminal, and an output terminal; configured to: when the first output circuit outputs the first low level signal, and the second output circuit outputs the second low When the level signal is output, the low level driving signal is output; otherwise, the high level driving signal is output;
所述第一输出电路的一端和所述第一副边绕组连接，所述第一输出电路的另一端与所述或门电路的第一输入端连接；所述第二输出电路的一端和所述第二副边绕组连接，所述第二输出电路的另一端与所述或门电路的第二输入端连接。One end of the first output circuit is connected to the first secondary winding, and the other end of the first output circuit is connected to a first input end of the OR circuit; one end of the second output circuit The second secondary winding is connected, and the other end of the second output circuit is connected to the second input of the OR circuit.
在本发明所述隔离驱动电路中，所述第一输出电路包括：In the isolated driving circuit of the present invention, the first output circuit comprises:
第一充放电电路，用于缩短所述第一高电平信号的上升沿的时间，延长所述第一高电平信号的下降沿的时间；以及a first charge and discharge circuit for shortening a time of a rising edge of the first high level signal and extending a time of a falling edge of the first high level signal;
第一箝位电路，用于对所述第一低电平信号进行箝位。a first clamping circuit for clamping the first low level signal.
在本发明所述隔离驱动电路中，所述第一充放电电路包括第二电阻、第三电阻、第四电阻、第一二极管以及第二电容，所述第一箝位电路包括第二二极管，In the isolated driving circuit of the present invention, the first charging and discharging circuit includes a second resistor, a third resistor, a fourth resistor, a first diode, and a second capacitor, and the first clamping circuit includes a second diode,
所述第二电阻的一端与所述第一副边绕组的一端连接，所述第二电阻的另一端与所述第一二极管的正极连接，所述第一二极管的负极与所述或门电路的第一输入端连接，所述第三电阻的一端与所述第一副边绕组的一端连接，所述第三电阻的另一端与所述或门电路的第一输入端连接，所述第二电容的一端与所述或门电路的第一输入端连接，所述第二电容的另一端与所述第一副边绕组的另一端连接，所述第四电阻的一端与所述或门电路的第一输入端连接，所述第四电阻的另一端与所述第一副边绕组的另一端连接，所述第二二极管的正极与所述第一副边绕组的另一端连接，所述第二二极管的负极与所述或门电路的第一输入端连接。One end of the second resistor is connected to one end of the first secondary winding, the other end of the second resistor is connected to the anode of the first diode, and the anode of the first diode is Connected to a first input end of the OR circuit, one end of the third resistor is connected to one end of the first secondary winding, and the other end of the third resistor is connected to a first input end of the OR gate circuit One end of the second capacitor is connected to the first input end of the OR gate circuit, and the other end of the second capacitor is connected to the other end of the first secondary winding, and one end of the fourth resistor is a first input end of the OR circuit is connected, and another end of the fourth resistor is connected to another end of the first secondary winding, a positive pole of the second diode and the first secondary winding The other end of the second diode is connected to the first input of the OR circuit.
在本发明所述隔离驱动电路中，所述第二输出电路包括：In the isolated driving circuit of the present invention, the second output circuit comprises:
第二充放电电路，用于缩短所述第二高电平信号的上升沿的时间，延长所述第二高电平信号的下降沿的时间；以及a second charge and discharge circuit for shortening a time of a rising edge of the second high level signal and extending a time of a falling edge of the second high level signal;
第二箝位电路，用于对所述第二低电平信号进行箝位。a second clamping circuit for clamping the second low level signal.
在本发明所述隔离驱动电路中，所述第二充放电电路包括第五电阻、第六电阻、第七电阻、第三二极管以及第三电容，所述第二箝位电路包括第四二极管，In the isolated driving circuit of the present invention, the second charging and discharging circuit includes a fifth resistor, a sixth resistor, a seventh resistor, a third diode, and a third capacitor, and the second clamping circuit includes a fourth diode,
所述第五电阻的一端与所述第二副边绕组的一端连接，所述第五电阻的另一端与所述第三二极管的正极连接，所述第三二极管的负极与所述或门电路的第二输入端连接，所述第六电阻的一端与所述第二副边绕组的一端连接，所述第六电阻的另一端与所述或门电路的第二输入端连接，所述第三电容的一端与所述或门电路的第二输入端连接，所述第三电容的另一端与所述第二副边绕组的另一端连接，所述第七电阻的一端与所述或门电路的第二输入端连接，所述第七电阻的另一端与所述第二副边绕组的另一端连接，所述第四二极管的正极与所述第二副边绕组的另一端连接，所述第四二极管的负极与所述或门电路的第二输入端连接。One end of the fifth resistor is connected to one end of the second secondary winding, the other end of the fifth resistor is connected to the anode of the third diode, and the cathode of the third diode is Connecting a second input end of the OR circuit, one end of the sixth resistor is connected to one end of the second secondary winding, and the other end of the sixth resistor is connected to the second input end of the OR circuit One end of the third capacitor is connected to the second input end of the OR gate circuit, and the other end of the third capacitor is connected to the other end of the second secondary winding, and one end of the seventh resistor is a second input end of the OR circuit is connected, and another end of the seventh resistor is connected to another end of the second secondary winding, and a positive pole of the fourth diode and the second secondary winding The other end of the fourth diode is connected to the second input of the OR gate.
在本发明所述隔离驱动电路中，所述隔离驱动变压器还包括第一备用副边绕组以及第二备用副边绕组；In the isolated driving circuit of the present invention, the isolated driving transformer further includes a first standby secondary winding and a second standby secondary winding;
所述脉冲驱动信号转换电路还包括：The pulse drive signal conversion circuit further includes:
第一备用输出电路，用于当所述第二脉冲驱动信号为高电平时，输出第一高电平信号，当所述第二脉冲驱动信号为低电平时，输出第一低电平信号；以及a first standby output circuit, configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level; as well as
第二备用输出电路，用于当所述第一脉冲驱动信号为高电平时，输出第二高电平信号，当所述第一脉冲驱动信号为低电平时，输出第二低电平信号；a second standby output circuit, configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level;
所述第一备用输出电路的一端与所述第一备用副边绕组连接，所述第一备用输出电路的另一端与所述或门电路的第一输入端连接；所述第二备用输出电路的一端和所述第二备用副边绕组连接，所述第二备用输出电路的另一端与所述或门电路的第二输入端连接。One end of the first standby output circuit is connected to the first standby secondary winding, and the other end of the first standby output circuit is connected to a first input end of the OR gate circuit; the second standby output circuit One end is connected to the second standby secondary winding, and the other end of the second standby output circuit is connected to the second input of the OR circuit.
在本发明所述隔离驱动电路中，所述隔离驱动电路包括用于防止所述隔离驱动变压器的直流偏磁现象的防直流偏磁电路，所述防直流偏磁电路分别与所述双端激励信号驱动控制电路和所述隔离驱动变压器连接；In the isolated driving circuit of the present invention, the isolated driving circuit includes an anti-DC biasing circuit for preventing a DC bias phenomenon of the isolated driving transformer, and the DC blocking bias circuit and the double-ended excitation respectively a signal driving control circuit and the isolated driving transformer are connected;
在本发明所述隔离驱动电路中，所述防直流偏磁电路包括第一电阻和第一电容，所述第一电阻的一端分别与所述第一电容的一端和所述脉冲驱动信号转换电路连接，所述第一电阻的另一端分别与所述第一电容的另一端和所述隔离驱动变压器连接。In the isolated driving circuit of the present invention, the DC-blocking bias circuit includes a first resistor and a first capacitor, and one end of the first resistor is respectively connected to one end of the first capacitor and the pulse driving signal conversion circuit Connected, the other end of the first resistor is respectively connected to the other end of the first capacitor and the isolated driving transformer.
在本发明所述隔离驱动电路中，所述隔离驱动电路还包括：In the isolated driving circuit of the present invention, the isolated driving circuit further includes:
功率放大电路，用于对所述脉冲驱动信号转换电路输出的驱动信号进行放大处理，a power amplifying circuit for amplifying the driving signal output by the pulse driving signal conversion circuit,
所述功率放大电路与所述脉冲驱动信号转换电路连接。The power amplifying circuit is connected to the pulse driving signal conversion circuit.
有益效果 Beneficial effect
相较于现有的隔离驱动电路，本发明的隔离驱动电路可避免由于隔直电容和驱动变压器励磁电感产生谐振，解决了现有的隔离驱动电路由于隔直电容和驱动变压器励磁电感产生谐振，可能导致关断的功率开关管误导通的技术问题。Compared with the existing isolated driving circuit, the isolated driving circuit of the invention can avoid resonance due to the DC blocking capacitor and the excitation inductance of the driving transformer, and solves the resonance of the existing isolated driving circuit due to the DC blocking capacitance and the driving transformer excitation inductance. A technical problem that may cause the power switch tube to be turned off to be mis-conducted.
附图说明DRAWINGS
图1为一种现有的脉冲变压器隔离驱动电路；1 is a conventional pulse transformer isolation driving circuit;
图2为另一种现有的脉冲变压器隔离驱动电路；2 is another conventional pulse transformer isolation driving circuit;
图3为本发明的隔离驱动电路的第一优选实施例的模块示意图；3 is a schematic block diagram of a first preferred embodiment of an isolated driving circuit of the present invention;
图4为本发明的隔离驱动电路的第一优选实施例的具体模块示意图；4 is a schematic diagram of a specific module of a first preferred embodiment of the isolated driving circuit of the present invention;
图5为本发明的隔离驱动电路的第一优选实施例的具体电路图；Figure 5 is a specific circuit diagram of a first preferred embodiment of the isolated drive circuit of the present invention;
图6为图5中各点的电压波形图；Figure 6 is a voltage waveform diagram of each point in Figure 5;
图7为本发明的隔离驱动电路的优选实施例的通过或门电路的驱动信号的信号合成示意图；7 is a schematic diagram of signal synthesis of a driving signal through an OR gate circuit of a preferred embodiment of the isolated driving circuit of the present invention;
图8为本发明的隔离驱动电路的第二优选实施例的具体电路图；Figure 8 is a specific circuit diagram of a second preferred embodiment of the isolated drive circuit of the present invention;
图9为本发明的隔离驱动电路的第三优选实施例的具体电路图；Figure 9 is a specific circuit diagram of a third preferred embodiment of the isolated drive circuit of the present invention;
图10为本发明的隔离驱动电路的第四优选实施例的具体电路图；Figure 10 is a specific circuit diagram of a fourth preferred embodiment of the isolated drive circuit of the present invention;
图11为本发明的隔离驱动电路的第五优选实施例的具体电路图；Figure 11 is a specific circuit diagram of a fifth preferred embodiment of the isolated drive circuit of the present invention;
图12为本发明的隔离驱动电路的第六优选实施例的具体电路图；12 is a specific circuit diagram of a sixth preferred embodiment of the isolated driving circuit of the present invention;
其中，附图标记说明如下：Among them, the reference numerals are as follows:
31、双端激励信号驱动控制电路；31. A double-ended excitation signal driving control circuit;
32、隔离驱动变压器；32. Isolated drive transformer;
321、第一原边绕组；321 , a first primary winding;
322、第一副边绕组；322, a first secondary winding;
323、第二副边绕组；323, a second secondary winding;
324、第二原边绕组；324, the second primary winding;
325、第一备用副边绕组；325, a first alternate secondary winding;
326、第二备用副边绕组；326, a second alternate secondary winding;
33、脉冲驱动信号转换电路； 33. A pulse driving signal conversion circuit;
331、第一输出电路；331, a first output circuit;
332、第二输出电路；332, a second output circuit;
333、或门电路；333, OR gate circuit;
334、第一备用输出电路；334, a first standby output circuit;
335、第二备用输出电路。335. A second standby output circuit.
本发明的最佳实施方式BEST MODE FOR CARRYING OUT THE INVENTION
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。The following description of the various embodiments is provided to illustrate the specific embodiments of the invention. The directional terms mentioned in the present invention, such as "upper", "lower", "before", "after", "left", "right", "inside", "outside", "side", etc., are merely references. Attach the direction of the drawing. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention.
在图中，结构相似的单元是以相同标号表示。In the figures, structurally similar elements are denoted by the same reference numerals.
请参照图3，图3为本发明的隔离驱动电路的第一优选实施例的模块示意图。该隔离驱动电路包括隔离驱动变压器32、双端激励信号驱动控制电路31以及脉冲驱动信号转换电路33。其中隔离驱动变压器32包括第一原边绕组以及副边绕组；双端激励信号驱动控制电路31用于产生第一脉冲驱动信号以及第二脉冲驱动信号，第一脉冲驱动信号由第一原边绕组的一端输入，第二脉冲驱动信号由第一原边绕组的另一端输入；脉冲驱动信号转换电路33用于将隔离驱动变压器32的副边绕组的输出信号转换为驱动信号，然后使用该驱动信号驱动相应的功率开关管。Please refer to FIG. 3. FIG. 3 is a schematic block diagram of a first preferred embodiment of the isolated driving circuit of the present invention. The isolated drive circuit includes an isolated drive transformer 32, a double-ended excitation signal drive control circuit 31, and a pulse drive signal conversion circuit 33. The isolated driving transformer 32 includes a first primary winding and a secondary winding; the double-ended excitation signal driving control circuit 31 is configured to generate a first pulse driving signal and a second pulse driving signal, the first pulse driving signal being the first primary winding One end of the input, the second pulse driving signal is input from the other end of the first primary winding; the pulse driving signal conversion circuit 33 is for converting the output signal of the secondary winding of the isolated driving transformer 32 into a driving signal, and then using the driving signal Drive the corresponding power switch tube.
其中双端激励信号驱动控制电路31与隔离驱动变压器32的第一原边绕组连接，隔离驱动变压器32的副边绕组与脉冲驱动信号转换电路33的输入连接，脉冲驱动信号转换电路33的输出与待驱动的功率开关管连接。The double-ended excitation signal drive control circuit 31 is connected to the first primary winding of the isolated drive transformer 32, and the secondary winding of the isolated drive transformer 32 is connected to the input of the pulse drive signal conversion circuit 33, and the output of the pulse drive signal conversion circuit 33 is The power switch tube to be driven is connected.
下面通过图4和图5进一步说明本发明的隔离驱动电路中的各模块的具体结构。图4为本发明的隔离驱动电路的第一优选实施例的具体模块示意图，图5为本发明的隔离驱动电路的第一优选实施例的具体电路图。其中隔离驱动变压器32包括第一原边绕组321、第一副边绕组322以及第二副边绕组323。脉冲驱动信号转换电路33包括第一输出电路331、第二输出电路332以及或门电路333，其中第一输出电路331用于当第二脉冲信号为高电平时，输出第一高电平信号，当第二脉冲驱动信号为低电平时，输出第一低电平信号；第二输出电路332用于当第一脉冲驱动信号为高电平时，输出第二高电平信号，当第一脉冲驱动信号为低电平时，输出第二低电平信号；或门电路333包括第一输入端、第二输入端以及输出端，用于当第一输出电路331输出第一低电平信号至第一输入端，同时第二输出电路332输出第二低电平信号至第二输入端时，输出端输出低电平驱动信号，否则输出端输出高电平驱动信号。The specific structure of each module in the isolated drive circuit of the present invention will be further described below with reference to FIGS. 4 and 5. 4 is a schematic diagram of a specific module of a first preferred embodiment of the isolated driving circuit of the present invention, and FIG. 5 is a specific circuit diagram of a first preferred embodiment of the isolated driving circuit of the present invention. The isolated drive transformer 32 includes a first primary winding 321 , a first secondary winding 322 , and a second secondary winding 323 . The pulse driving signal conversion circuit 33 includes a first output circuit 331, a second output circuit 332, and an OR gate circuit 333, wherein the first output circuit 331 is configured to output a first high level signal when the second pulse signal is at a high level, When the second pulse driving signal is low level, the first low level signal is output; the second output circuit 332 is configured to output the second high level signal when the first pulse driving signal is high level, when the first pulse is driven When the signal is low, the second low level signal is output; or the gate circuit 333 includes a first input end, a second input end, and an output end, when the first output circuit 331 outputs the first low level signal to the first At the input end, when the second output circuit 332 outputs the second low level signal to the second input end, the output end outputs a low level driving signal, otherwise the output end outputs a high level driving signal.
第一输出电路331的一端和第一副边绕组322连接，第一输出电路331的另一端与或门电路333的第一输入端连接，第二输出电路332的一端和第二副边绕组323连接，第二输出电路332的另一端与或门电路333的第二输入端连接。此处第一原边绕组321、第一副边绕组322以及第二副边绕组323的同名端设置如图5所示。One end of the first output circuit 331 is connected to the first secondary winding 322, the other end of the first output circuit 331 is connected to the first input terminal of the OR gate circuit 333, and one end of the second output circuit 332 and the second secondary winding 323 Connected, the other end of the second output circuit 332 is coupled to the second input of the OR gate circuit 333. Here, the same name end of the first primary winding 321 , the first secondary winding 322 and the second secondary winding 323 are arranged as shown in FIG. 5 .
这里的或门电路333可以采用集成的逻辑门电路，也可以采用由分立元件组成的或门电路。The OR gate circuit 333 herein may be an integrated logic gate circuit or an OR gate circuit composed of discrete components.
从图5中可见，第一输出电路331包括第一充放电电路以及第一箝位电路，第二输出电路332包括第二充放电电路以及第二箝位电路。As can be seen from FIG. 5, the first output circuit 331 includes a first charge and discharge circuit and a first clamp circuit, and the second output circuit 332 includes a second charge and discharge circuit and a second clamp circuit.
其中第一充放电电路用于缩短第一高电平信号的上升沿的时间，并延长第一高电平信号的下降沿的时间；第一箝位电路用于对第一低电平信号进行箝位。第一充放电电路包括第二电阻R2’、第三电阻R3’、第四电阻R4’、第一二极管D1’以及第二电容C2’；第一箝位电路包括第二二极管D2’。The first charging and discharging circuit is configured to shorten the time of the rising edge of the first high level signal and extend the time of the falling edge of the first high level signal; the first clamping circuit is configured to perform the first low level signal Clamp. The first charging and discharging circuit includes a second resistor R2', a third resistor R3', a fourth resistor R4', a first diode D1', and a second capacitor C2'; the first clamping circuit includes a second diode D2 '.
第二电阻R2’的一端与第一副边绕组322的一端连接，第二电阻R2’的另一端与第一二极管D1’的正极连接，第一二极管D1’的负极与或门电路333的第一输入端连接，第三电阻R3’的一端与第一副边绕组322的一端连接，第三电阻R3’的另一端与或门电路333的第一输入端连接，第二电容C2’的一端与或门电路333的第一输入端连接，第二电容C2’的另一端与第一副边绕组322的另一端连接，第四电阻R4’的一端与或门电路333的第一输入端连接，第四电阻R4’的另一端与第一副边绕组322的另一端连接，第二二极管D2’的正极与第一副边绕组322的另一端连接，第二二极管D2’的负极与或门电路333的第一输入端连接。One end of the second resistor R2' is connected to one end of the first secondary winding 322, the other end of the second resistor R2' is connected to the anode of the first diode D1', and the negative terminal and OR gate of the first diode D1' The first input end of the circuit 333 is connected, one end of the third resistor R3' is connected to one end of the first secondary winding 322, and the other end of the third resistor R3' is connected to the first input end of the OR circuit 333, and the second capacitor One end of C2' is connected to the first input end of the OR circuit 333, the other end of the second capacitor C2' is connected to the other end of the first sub-side winding 322, and one end of the fourth resistor R4' is opposite to the OR gate 333. One input terminal is connected, the other end of the fourth resistor R4' is connected to the other end of the first secondary winding 322, and the anode of the second diode D2' is connected to the other end of the first secondary winding 322, and the second diode The cathode of the tube D2' is connected to the first input of the OR circuit 333.
其中第二充放电电路用于缩短第二高电平信号的上升沿的间，并延长第二高电平信号的下降沿的间；第二箝位电路用于对第二低电平信号进行箝位。第二充放电电路包括第五电阻R5’、第六电阻R6’、第七电阻R7’、第三二极管D3’以及第三电容C3’，第二箝位电路包括第四二极管D4’。The second charging and discharging circuit is configured to shorten the rising edge of the second high level signal and extend the interval between the falling edges of the second high level signal; the second clamping circuit is configured to perform the second low level signal Clamp. The second charging and discharging circuit includes a fifth resistor R5', a sixth resistor R6', a seventh resistor R7', a third diode D3', and a third capacitor C3', and the second clamping circuit includes a fourth diode D4 '.
第五电阻R5’的一端与第二副边绕组323的一端连接，第五电阻R5’的另一端与第三二极管D3’的正极连接，第三二极管D3’的负极与或门电路333的第二输入端连接，第六电阻R6’的一端与第二副边绕组323的一端连接，第六电阻R6’的另一端与或门电路333的第二输入端连接，第三电容C3’的一端与或门电路333的第二输入端连接，第三电容C3’的另一端与第二副边绕组323的另一端连接，第七电阻R7’的一端与或门电路333的第二输入端连接，第七电阻R7’的另一端与第二副边绕组323的另一端连接，第四二极管D4’的正极与第二副边绕组323的另一端连接，第四二极管D4’的负极与或门电路333的第二输入端连接。One end of the fifth resistor R5' is connected to one end of the second secondary winding 323, the other end of the fifth resistor R5' is connected to the anode of the third diode D3', and the anode of the third diode D3' is OR gate. The second input end of the circuit 333 is connected, one end of the sixth resistor R6' is connected to one end of the second secondary winding 323, and the other end of the sixth resistor R6' is connected to the second input end of the OR circuit 333, the third capacitor One end of C3' is connected to the second input end of the OR circuit 333, the other end of the third capacitor C3' is connected to the other end of the second sub-side winding 323, and one end of the seventh resistor R7' is opposite to the OR gate circuit 333. The two input terminals are connected, the other end of the seventh resistor R7' is connected to the other end of the second secondary winding 323, and the anode of the fourth diode D4' is connected to the other end of the second secondary winding 323, and the fourth pole The cathode of the tube D4' is connected to the second input of the OR circuit 333.
请参照图6，图6为图5中各点的电压波形图。本发明的隔离驱动电路使用时，双端激励信号驱动控制电路31产生第一脉冲驱动信号和第二脉冲驱动信号，第一脉冲驱动信号由隔离驱动变压器32的第一原边绕组321的一端输入，第二脉冲驱动信号由隔离驱动变压器32的第一原边绕组321的另一端输入。第一脉冲驱动信号的频率和第二脉冲驱动信号的频率相同，第一脉冲驱动信号的占空比和第二脉冲驱动信号的占空比相同，同时第一脉冲驱动信号的高电平时间和第二脉冲驱动信号的高电平时间前后衔接，随后第一脉冲驱动信号和第二脉冲驱动信号均为低电平。当然这里也可以是第二脉冲驱动信号的高电平时间和第一脉冲驱动信号的高电平时间前后衔接。Please refer to FIG. 6. FIG. 6 is a voltage waveform diagram of each point in FIG. When the isolated driving circuit of the present invention is used, the double-ended excitation signal driving control circuit 31 generates a first pulse driving signal and a second pulse driving signal, and the first pulse driving signal is input from one end of the first primary winding 321 of the isolation driving transformer 32. The second pulse driving signal is input from the other end of the first primary winding 321 of the isolation driving transformer 32. The frequency of the first pulse driving signal is the same as the frequency of the second pulse driving signal, the duty ratio of the first pulse driving signal and the duty ratio of the second pulse driving signal are the same, and the high time of the first pulse driving signal is The high-level time of the second pulse driving signal is engaged back and forth, and then the first pulse driving signal and the second pulse driving signal are both low. Of course, it may also be that the high level time of the second pulse driving signal and the high level time of the first pulse driving signal are connected before and after.
当第一脉冲驱动信号为高电平、第二脉冲驱动信号为低电平时，即图5的A’为高电位，B’为低电位，输入的第一脉冲驱动信号经隔离驱动变压器32输出至第一输出电路331和第二输出电路332，这时第一输出电路331的C’为低电位，第一输出电路331的E’通过第三电阻R3’放电，因此第一输出电路331的E’也为低电位，即或门电路333的第一输入端输入第一低电平信号。第二输出电路332的D’为高电位，并且通过第五电阻R5’以及第三二极管D3’给第二输出电路332的F’充电，因此第二输出电路332的F’也为高电位，即或门电路333的第二输入端输入第二高电平信号。这样或门电路333的输出G’为高电平驱动信号。When the first pulse driving signal is high level and the second pulse driving signal is low level, that is, A' of FIG. 5 is high potential, B' is low potential, and the input first pulse driving signal is outputted by the isolating driving transformer 32. Up to the first output circuit 331 and the second output circuit 332, at which time C' of the first output circuit 331 is low, and E' of the first output circuit 331 is discharged through the third resistor R3', so the first output circuit 331 E' is also low, that is, the first low level signal is input to the first input of the OR circuit 333. D' of the second output circuit 332 is at a high potential, and F' of the second output circuit 332 is charged through the fifth resistor R5' and the third diode D3', so the F' of the second output circuit 332 is also high. The potential, i.e., the second input of the OR gate 333, inputs a second high level signal. The output G' of the OR gate 333 is a high level drive signal.
当第一脉冲驱动信号为低电平、第二脉冲驱动信号为高电平时，即图5的A’为低电位，B’为高电位，输入的第二脉冲驱动信号经隔离驱动变压器32输出至第一输出电路331和第二输出电路332，这时第一输出电路331的C’为高电位，并且通过第二电阻R2’以及第一二极管D1’给第一输出电路331的E’充电，因此第一输出电路331的E’也为高电位，即或门电路333的第一输入端输入第一高电平信号。第二输出电路332的D’为低电位，第二输出电路332的F’通过第六电阻R6’放电，因此第二输出电路332的F’也为低电位，即或门电路333的第二输入端输入第二低电平信号。这样或门电路333的输出G’依然为高电平驱动信号。When the first pulse driving signal is low level and the second pulse driving signal is high level, that is, A' of FIG. 5 is low potential, B' is high potential, and the input second pulse driving signal is outputted by the isolating driving transformer 32. Up to the first output circuit 331 and the second output circuit 332, at which time C' of the first output circuit 331 is high, and the E of the first output circuit 331 is passed through the second resistor R2' and the first diode D1' 'Charging, so E' of the first output circuit 331 is also high, that is, the first high level signal is input to the first input terminal of the OR circuit 333. D' of the second output circuit 332 is low, and F' of the second output circuit 332 is discharged through the sixth resistor R6', so F' of the second output circuit 332 is also low, that is, the second of the OR circuit 333 The input terminal inputs a second low level signal. The output G' of the OR gate 333 is still a high level drive signal.
当第一脉冲驱动信号为低电平、第二脉冲驱动信号为低电平时，即图5的A’为低电位，B’也为低电位，这时第一输出电路331的C’为低电位，第一输出电路331的E’通过第三电阻R3’放电，因此第一输出电路331的E’也为低电位，即或门电路333的第一输入端输入第一低电平信号。第二输出电路332的D’为低电位，第二输出电路332的F’通过第六电阻R6’放电，因此第二输出电路332的F’也为低电位，即或门电路333的第一输入端输入第二低电平信号。这样或门电路333的输出G’为低电平驱动信号。When the first pulse driving signal is low level and the second pulse driving signal is low level, that is, A' of FIG. 5 is low potential, and B' is also low potential, when C' of the first output circuit 331 is low. At the potential, E' of the first output circuit 331 is discharged through the third resistor R3', so E' of the first output circuit 331 is also low, that is, the first input terminal of the OR circuit 333 inputs the first low level signal. D' of the second output circuit 332 is low, and F' of the second output circuit 332 is discharged through the sixth resistor R6', so F' of the second output circuit 332 is also low, that is, the first of the OR circuit 333 The input terminal inputs a second low level signal. The output G' of the OR gate 333 is a low level drive signal.
由于第一脉冲驱动信号和第二脉冲驱动信号的频率和占空比相同，均为或门电路333输出的驱动信号的占空比的一半，然后第一脉冲驱动信号和第二脉冲驱动信号从隔离驱动变压器32的第一原边绕组321的不同端输入，保证隔离驱动变压器32的磁复位，而不需要再采用隔直电容进行磁复位。Since the frequency and the duty ratio of the first pulse driving signal and the second pulse driving signal are the same, both are half of the duty ratio of the driving signal output from the OR circuit 333, and then the first pulse driving signal and the second pulse driving signal are from Isolating the different terminal inputs of the first primary winding 321 of the drive transformer 32 ensures isolation of the magnetic reset of the drive transformer 32 without the need for a DC-blocking magnetic reset.
同时本发明的隔离驱动电路通过脉冲驱动信号转换电路33，将第一脉冲驱动信号和第二脉冲驱动信号合成为连续的驱动信号进行输出，在保证隔离驱动变压器32的磁复位的基础上，实现了对功率开关管的完美驱动，下面对第一脉冲驱动信号和第二脉冲驱动信号合成的具体流程进行说明。At the same time, the isolated driving circuit of the present invention synthesizes the first pulse driving signal and the second pulse driving signal into a continuous driving signal for output by the pulse driving signal conversion circuit 33, and realizes on the basis of ensuring the magnetic reset of the isolated driving transformer 32. For the perfect driving of the power switch tube, the specific flow of the synthesis of the first pulse drive signal and the second pulse drive signal will be described below.
如图7所示，图7为本发明的隔离驱动电路的优选实施例的通过或门电路的驱动信号的合成示意图。当第一脉冲驱动信号为高电平、第二脉冲驱动信号为低电平时，第一输出电路331的E’为低电位，第二输出电路332的F’为高电位，或门电路333的输出G’为高电平驱动信号；当第一脉冲驱动信号为低电平、第二脉冲驱动信号为低电平时，第一输出电路331的E’为高电位，第二输出电路332的F’为低电位，或门电路333的输出G’为高电平驱动信号。由于当第一脉冲驱动信号由高电平转换为低电平，同时第二脉冲驱动信号由低电平转换为高电平时，可能会导致第一输出电路331的E’仍为低电位，而第二输出电路332的F’也转换到了低电位，这时或门电路333的输出G’在第一脉冲驱动信号和第二脉冲驱动信号高低电平转换的同时输出一短暂的低电平驱动信号，可能导致功率开关管的误关闭。As shown in FIG. 7, FIG. 7 is a schematic diagram of the synthesis of a driving signal through an OR gate circuit of a preferred embodiment of the isolated driving circuit of the present invention. When the first pulse driving signal is at a high level and the second pulse driving signal is at a low level, E' of the first output circuit 331 is at a low potential, F' of the second output circuit 332 is at a high potential, or the gate circuit 333 is The output G' is a high level driving signal; when the first pulse driving signal is low level and the second pulse driving signal is low level, E' of the first output circuit 331 is high potential, and F of the second output circuit 332 'It is low, or the output G' of the gate circuit 333 is a high level drive signal. Since the first pulse driving signal is converted from a high level to a low level, and the second pulse driving signal is converted from a low level to a high level, the E' of the first output circuit 331 may still be low, and F' of the second output circuit 332 is also switched to a low potential, at which time the output G' of the OR circuit 333 outputs a short low-level drive while the first pulse drive signal and the second pulse drive signal are switched between high and low levels. The signal may cause the power switch tube to be turned off by mistake.
因此第一输出电路331设置有第一充放电电路以及第一箝位电路，第二输出电路332设置有第二充放电电路以及第二箝位电路。当第一脉冲驱动信号由高电平转换为低电平，同时第二脉冲驱动信号由低电平转换为高电平（这里第二脉冲驱动信号由低电平开始转换为高电平的时间点早于等于第一脉冲驱动信号由高电平开始转换为低电平的时间点）时，这时第一输出电路331的C’为高电位，并可通过第二电阻R2’以及第一二极管D1’给第一输出电路331的E’快速充电，使得第一输出电路331的E’可以快速达到高电位。而第二输出电路332的D’为低电位，第二输出电路332的F’通过第六电阻R6’放电，在第六电阻R6’和第三电容C3’的作用下，可以减缓第二输出电路332的F’的放电速度，使得可以延长第二输出电路332的F’的高电位时间。同时第二箝位电路的第四二极管D4’进一步对第二输出电路332的F’低电位时的电位进行箝位，使得F’的低电位不会损坏或门电路333或使或门电路333产生误判。这样保证了第一脉冲驱动信号和第二脉冲驱动信号的高低电平切换时，或门电路333的输出G’输出高电平驱动信号。Therefore, the first output circuit 331 is provided with a first charging and discharging circuit and a first clamping circuit, and the second output circuit 332 is provided with a second charging and discharging circuit and a second clamping circuit. When the first pulse driving signal is converted from a high level to a low level, and the second pulse driving signal is converted from a low level to a high level (where the second pulse driving signal is converted from a low level to a high level) When the point is earlier than the time point when the first pulse driving signal is switched from the high level to the low level, the C' of the first output circuit 331 is at a high level, and the second resistor R2' and the first The diode D1' quickly charges E' of the first output circuit 331 so that E' of the first output circuit 331 can quickly reach a high potential. While D' of the second output circuit 332 is low, F' of the second output circuit 332 is discharged through the sixth resistor R6', and the second output can be slowed down by the sixth resistor R6' and the third capacitor C3'. The discharge speed of F' of circuit 332 makes it possible to extend the high potential time of F' of second output circuit 332. At the same time, the fourth diode D4' of the second clamp circuit further clamps the potential of the second output circuit 332 at the low potential of F', so that the low potential of F' is not damaged or the gate circuit 333 or the OR gate Circuit 333 produces a false positive. This ensures that the high-low level switching of the first pulse driving signal and the second pulse driving signal, the output G' of the OR circuit 333 outputs a high-level driving signal.
以上是第一脉冲驱动信号的高电平时间和第二脉冲驱动信号的高电平时间前后衔接为例，说明了如何对第一脉冲驱动信号和第二脉冲驱动信号进行合成。当然这里也可第二脉冲驱动信号的高电平时间和第一脉冲驱动信号的高电平时间前后衔接。这时当第二脉冲驱动信号由高电平转换为低电平，同时第一脉冲驱动信号由低电平转换为高电平（这里第一脉冲驱动信号由低电平开始转换为高电平的时间点早于等于第二脉冲驱动信号由高电平开始转换为低电平的时间点）时，这时第二输出电路332的D’为高电位，并可通过第五电阻R5’以及第三二极管D3’给第二输出电路332的F’快速充电，使得第二输出电路332的F’可以快速达到高电位。而第一输出电路331的C’为低电位，第一输出电路331的E’通过第三电阻R3’放电，在第三电阻R3’和第二电容C2’的作用下，可以减缓第一输出电路331的E’的放点速度，使得可以延长第一输出电路331的E’的高电位时间。同时第一箝位电路的第二二极管D2’进一步对第一输出电路331的E’低电位时的电位进行箝位，使得E’的低电位不会损坏或门电路333或使或门电路333产生误判。这样保证了第一脉冲驱动信号和第二脉冲驱动信号的高低电平切换时，或门电路333的输出G’输出高电平驱动信号。The above is an example in which the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are connected back and forth, and how the first pulse driving signal and the second pulse driving signal are combined. Of course, the high-level time of the second pulse driving signal and the high-level time of the first pulse driving signal can also be connected before and after. At this time, when the second pulse driving signal is converted from a high level to a low level, and the first pulse driving signal is converted from a low level to a high level (where the first pulse driving signal is converted from a low level to a high level) When the time point is earlier than or equal to the time point when the second pulse driving signal is switched from the high level to the low level, the D' of the second output circuit 332 is at a high level, and can pass the fifth resistor R5' and The third diode D3' quickly charges F' of the second output circuit 332 such that F' of the second output circuit 332 can quickly reach a high potential. The C' of the first output circuit 331 is low, and the E' of the first output circuit 331 is discharged through the third resistor R3'. Under the action of the third resistor R3' and the second capacitor C2', the first output can be slowed down. The throwing speed of E' of the circuit 331 makes it possible to extend the high potential time of E' of the first output circuit 331. At the same time, the second diode D2' of the first clamp circuit further clamps the potential of the E' low potential of the first output circuit 331 so that the low potential of E' is not damaged or the gate 333 or the OR gate Circuit 333 produces a false positive. This ensures that the high-low level switching of the first pulse driving signal and the second pulse driving signal, the output G' of the OR circuit 333 outputs a high-level driving signal.
本发明的隔离驱动电路还包括防直流偏磁电路，该防直流偏磁电路用于防止隔离驱动变压器32的直流偏磁现象。该防直流偏磁电路分别与双端激励信号驱动控制电路31和隔离驱动变压器32连接。如图5所示，该防直流偏磁电路包括第一电阻R1’和第一电容C1’，第一电阻R1’的一端分别与第一电容C1’的一端和脉冲驱动信号转换电路33连接，第一电阻R1’的另一端分别与第一电容C1’的另一端和隔离驱动变压器32连接。当第一脉冲驱动信号的占空比和第二脉冲驱动信号的占空比出现差异时，隔离驱动变压器32会产生直流偏磁现象，使得隔离驱动变压器32不能完全磁复位。而通过该防直流偏磁电路可以保证隔离驱动变压器32在上述情况下的磁复位。The isolated drive circuit of the present invention further includes an anti-DC bias circuit for preventing DC biasing of the isolated drive transformer 32. The anti-DC bias circuit is connected to the double-ended excitation signal drive control circuit 31 and the isolated drive transformer 32, respectively. As shown in FIG. 5, the DC-blocking bias circuit includes a first resistor R1' and a first capacitor C1'. One end of the first resistor R1' is connected to one end of the first capacitor C1' and the pulse driving signal conversion circuit 33, respectively. The other end of the first resistor R1' is connected to the other end of the first capacitor C1' and the isolated drive transformer 32, respectively. When the duty ratio of the first pulse driving signal and the duty ratio of the second pulse driving signal are different, the isolated driving transformer 32 generates a DC bias phenomenon, so that the isolated driving transformer 32 cannot be completely magnetically reset. The magnetic bias reset of the isolated drive transformer 32 in the above case can be ensured by the anti-DC bias circuit.
本发明的隔离驱动电路还包括功率放大电路，该功率放大电路用于对脉冲驱动信号转换电路33输出的驱动信号进行放大处理。该功率放大电路与脉冲驱动信号转换电路33的输出连接。这样可以进一步保证驱动功率开关管的驱动信号的功率。The isolated drive circuit of the present invention further includes a power amplifying circuit for amplifying the drive signal output from the pulse drive signal conversion circuit 33. The power amplifying circuit is connected to the output of the pulse drive signal conversion circuit 33. This further ensures the power of the drive signal driving the power switch.
请参照图8，图8为图本发明的隔离驱动电路的第二优选实施例的具体电路图。本实施例和第一优选实施例的区别在于，该隔离驱动变压器包括第一原边绕组321和第二原边绕组324，第一脉冲驱动信号由第一原边绕组321的A1’端输入，第二脉冲驱动信号由第二原边绕组324的B2’端输入，这样可以达到与第一优选实施例相同的有益效果。此处第一原边绕组321和第二原边绕组324的同名端设置如图8所示。本优选实施例除了第一脉冲驱动信号和第二脉冲驱动信号的信号输入端不同，其他工作原理和有益效果与第一优选实施例中的隔离驱动电路相同或相似，具体请参见上述隔离驱动电路的第一优选实施例。Please refer to FIG. 8. FIG. 8 is a specific circuit diagram showing a second preferred embodiment of the isolated driving circuit of the present invention. The difference between this embodiment and the first preferred embodiment is that the isolated driving transformer includes a first primary winding 321 and a second primary winding 324, and the first pulse driving signal is input by the A1' end of the first primary winding 321 . The second pulse drive signal is input from the B2' terminal of the second primary winding 324, so that the same advantageous effects as the first preferred embodiment can be achieved. Here, the same name end of the first primary winding 321 and the second primary winding 324 is set as shown in FIG. In the preferred embodiment, except for the signal input terminals of the first pulse driving signal and the second pulse driving signal, other working principles and beneficial effects are the same as or similar to the isolated driving circuit in the first preferred embodiment. For details, please refer to the above isolated driving circuit. A first preferred embodiment of the invention.
请参照图9，图9为图本发明的隔离驱动电路的第三优选实施例的具体电路图。本实施例与第一优选实施例的区别在于，该隔离驱动变压器还包括第一备用副边绕组325，该脉冲驱动信号转换电路还包括第一备用输出电路334，该第一备用输出电路334用于当第二脉冲驱动信号为高电平时，输出第一高电平信号，当第二脉冲驱动信号为低电平时，输出第一低电平信号。第一备用输出电路334的一端与第一备用副边绕组325连接，第一备用输出电路334的另一端与或门电路333的第一输入端连接。此处第一备用副边绕组325的同名端设置如图9所示。第一备用副边绕组325和第一备用输出电路334的设置使得第一原边绕组321或第一输出电路331出现问题时，本发明的隔离驱动电路也能够正常工作。Please refer to FIG. 9. FIG. 9 is a specific circuit diagram showing a third preferred embodiment of the isolated driving circuit of the present invention. The difference between the embodiment and the first preferred embodiment is that the isolated drive transformer further includes a first backup secondary winding 325, the pulse drive signal conversion circuit further includes a first standby output circuit 334, and the first standby output circuit 334 When the second pulse driving signal is at a high level, the first high level signal is output, and when the second pulse driving signal is at a low level, the first low level signal is output. One end of the first standby output circuit 334 is connected to the first standby secondary winding 325, and the other end of the first standby output circuit 334 is connected to the first input of the OR gate circuit 333. Here, the same name end of the first standby secondary winding 325 is set as shown in FIG. When the first standby secondary winding 325 and the first standby output circuit 334 are disposed such that the first primary winding 321 or the first output circuit 331 has a problem, the isolated driving circuit of the present invention can also operate normally.
请参照图10，图10为图本发明的隔离驱动电路的第四优选实施例的具体电路图。本实施例与第一优选实施例的区别在于，该隔离驱动变压器还包括第二备用副边绕组326，该脉冲驱动信号转换电路还包括第二备用输出电路335，该第二备用输出电路335用于当第一脉冲驱动信号为高电平时，输出第二高电平信号，当第一脉冲驱动信号为低电平时，输出第二低电平信号。第二备用输出电路335的一端与第二备用副边绕组326连接，第二备用输出电路335的另一端与或门电路333的第二输入端连接。此处第二备用副边绕组326的同名端设置如图10所示。第二备用副边绕组326和第二备用输出电路335的设置使得第二原边绕组322或第二输出电路332出现问题时，本发明的隔离驱动电路也能够正常工作。Please refer to FIG. 10. FIG. 10 is a detailed circuit diagram showing a fourth preferred embodiment of the isolated driving circuit of the present invention. The difference between the embodiment and the first preferred embodiment is that the isolated drive transformer further includes a second backup secondary winding 326, the pulse drive signal conversion circuit further includes a second standby output circuit 335, and the second standby output circuit 335 When the first pulse driving signal is at a high level, the second high level signal is output, and when the first pulse driving signal is at a low level, the second low level signal is output. One end of the second standby output circuit 335 is connected to the second standby secondary winding 326, and the other end of the second standby output circuit 335 is connected to the second input of the OR circuit 333. Here, the same name end of the second standby secondary winding 326 is set as shown in FIG. When the second standby secondary winding 326 and the second standby output circuit 335 are disposed such that the second primary winding 322 or the second output circuit 332 has a problem, the isolated driving circuit of the present invention can also operate normally.
请参照图11，图11为本发明的隔离驱动电路的第五优选实施例的具体电路图。本实施例与第一优选实施例的区别在于，该隔离驱动变压器同时包括第一备用副边绕组325和第二备用副边绕组326。该脉冲驱动信号转换电路还包括第一备用输出电路334和第二备用输出电路335。第一备用输出电路334用于当第二脉冲驱动信号为高电平时，输出第一高电平信号，当第二脉冲驱动信号为低电平时，输出第一低电平信号；第二备用输出电路335用于当第一脉冲驱动信号为高电平时，输出第二高电平信号，当第一脉冲驱动信号为低电平时，输出第二低电平信号。第一备用输出电路334的一端与第一备用副边绕组325连接，第一备用输出电路334的另一端与或门电路333的第一输入端连接；第二备用输出电路335的一端与第二备用副边绕组326连接，第二备用输出电路335的另一端与或门电路333的第二输入端连接。此处第一备用副边绕组325和第二备用副边绕组326的同名端设置如图11所示。上述双备用副边绕组和备用输出电路的设计使得本发明的隔离驱动电路工作更加稳定。Please refer to FIG. 11. FIG. 11 is a specific circuit diagram of a fifth preferred embodiment of the isolated driving circuit of the present invention. The present embodiment differs from the first preferred embodiment in that the isolated drive transformer includes both a first backup secondary winding 325 and a second backup secondary winding 326. The pulse drive signal conversion circuit further includes a first standby output circuit 334 and a second standby output circuit 335. The first standby output circuit 334 is configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level; the second standby output The circuit 335 is configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level. One end of the first standby output circuit 334 is connected to the first standby secondary winding 325, the other end of the first standby output circuit 334 is connected to the first input terminal of the OR gate circuit 333, and one end of the second standby output circuit 335 is connected to the second The alternate secondary winding 326 is coupled and the other end of the second alternate output circuit 335 is coupled to the second input of the OR gate 333. Here, the same name end of the first standby secondary winding 325 and the second standby secondary winding 326 are arranged as shown in FIG. The design of the dual standby secondary winding and the alternate output circuit described above makes the isolated drive circuit of the present invention more stable.
本发明的隔离驱动电路还可以包括多个脉冲驱动信号转换电路。请参照图12，图12为本发明的隔离驱动电路的第六优选实施例的具体电路图。该隔离驱动电路包括有两个脉冲驱动信号转换电路，每个脉冲驱动信号转换电路的输出信号均可以驱动一功率开关管。每个脉冲驱动信号转换电路的具体工作原理与上述隔离驱动电路的第一优选实施例中的脉冲驱动信号转换电路的具体工作原理相同，请参见上述隔离驱动电路的第一优选实施例。因此本发明使用双端激励信号驱动控制电路可同时驱动多个脉冲驱动信号转换电路，驱动脉冲驱动信号转换电路的数量的改变并不限制本发明的保护范围。The isolated drive circuit of the present invention may further include a plurality of pulse drive signal conversion circuits. Please refer to FIG. 12. FIG. 12 is a specific circuit diagram of a sixth preferred embodiment of the isolated driving circuit of the present invention. The isolated driving circuit includes two pulse driving signal conversion circuits, and each pulse driving signal conversion circuit output signal can drive a power switch tube. The specific working principle of each pulse driving signal conversion circuit is the same as that of the pulse driving signal conversion circuit in the first preferred embodiment of the above isolated driving circuit. Please refer to the first preferred embodiment of the above isolated driving circuit. Therefore, the present invention uses a double-ended excitation signal drive control circuit to simultaneously drive a plurality of pulse drive signal conversion circuits, and the change in the number of drive pulse drive signal conversion circuits does not limit the scope of protection of the present invention.
本发明的隔离驱动电路有效的避免了传统隔离驱动变压器32隔离驱动、宽占空比传递过程中，传导到隔离驱动变压器32的副边绕组的驱动电压幅值减小，以及避免了隔离驱动变压器32的磁复位过程中隔直电容和驱动变压器励磁电感的谐振导致关断的功率开关管误导通。The isolated driving circuit of the invention effectively avoids the reduction of the driving voltage amplitude of the secondary winding of the isolated driving transformer 32 during the isolated driving and the wide duty ratio transmission of the conventional isolated driving transformer 32, and avoids the isolation driving transformer During the magnetic reset process of 32, the resonance of the DC blocking capacitor and the excitation inductance of the driving transformer causes the power switch tube that is turned off to be mis-conducted.
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。In the above, the present invention has been disclosed in the above preferred embodiments, but the preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various modifications without departing from the spirit and scope of the invention. The invention is modified and retouched, and the scope of the invention is defined by the scope defined by the claims.
本发明的实施方式Embodiments of the invention
工业实用性Industrial applicability
序列表自由内容Sequence table free content

Claims (17)

  1. 一种隔离驱动电路，其包括：An isolated driving circuit comprising:
    隔离驱动变压器，包括原边绕组以及副边绕组；Isolate the drive transformer, including the primary winding and the secondary winding;
    双端激励信号驱动控制电路，用于产生第一脉冲驱动信号和第二脉冲驱动信号，所述第一脉冲驱动信号和所述第二脉冲驱动信号由所述原边绕组输入；以及a double-ended excitation signal driving control circuit for generating a first pulse driving signal and a second pulse driving signal, wherein the first pulse driving signal and the second pulse driving signal are input by the primary winding;
    至少一个脉冲驱动信号转换电路，用于将所述副边绕组的输出信号转换为驱动信号，该驱动信号用于驱动相应的功率开关管，At least one pulse drive signal conversion circuit for converting an output signal of the secondary winding into a drive signal for driving a corresponding power switch tube,
    所述双端激励信号驱动控制电路与所述隔离驱动变压器的原边绕组连接，所述隔离驱动变压器的副边绕组与所述脉冲驱动信号转换电路连接；The double-ended excitation signal driving control circuit is connected to a primary winding of the isolated driving transformer, and a secondary winding of the isolated driving transformer is connected to the pulse driving signal conversion circuit;
    所述隔离驱动变压器包括第一原边绕组，所述第一脉冲驱动信号由所述第一原边绕组的一端输入，所述第二脉冲驱动信号由所述第一原边绕组的另一端输入；The isolated drive transformer includes a first primary winding, the first pulse driving signal is input by one end of the first primary winding, and the second pulse driving signal is input by the other end of the first primary winding ;
    所述隔离驱动电路还包括用于防止所述隔离驱动变压器的直流偏磁现象的防直流偏磁电路，所述防直流偏磁电路分别与所述双端激励信号驱动控制电路和所述隔离驱动变压器连接；The isolation driving circuit further includes an anti-DC biasing circuit for preventing a DC bias phenomenon of the isolated driving transformer, the DC blocking biasing circuit and the double-ended excitation signal driving control circuit and the isolation driving respectively Transformer connection
    所述防直流偏磁电路包括第一电阻和第一电容，所述第一电阻的一端分别与所述第一电容的一端和所述脉冲驱动信号转换电路连接，所述第一电阻的另一端分别与所述第一电容的另一端和所述隔离驱动变压器连接。The anti-DC bias circuit includes a first resistor and a first capacitor, and one end of the first resistor is respectively connected to one end of the first capacitor and the pulse driving signal conversion circuit, and the other end of the first resistor Connected to the other end of the first capacitor and the isolated drive transformer, respectively.
  2. 一种隔离驱动电路，其包括：An isolated driving circuit comprising:
    隔离驱动变压器，包括原边绕组以及副边绕组；Isolate the drive transformer, including the primary winding and the secondary winding;
    双端激励信号驱动控制电路，用于产生第一脉冲驱动信号和第二脉冲驱动信号，所述第一脉冲驱动信号和所述第二脉冲驱动信号由所述原边绕组输入；以及a double-ended excitation signal driving control circuit for generating a first pulse driving signal and a second pulse driving signal, wherein the first pulse driving signal and the second pulse driving signal are input by the primary winding;
    至少一个脉冲驱动信号转换电路，用于将所述副边绕组的输出信号转换为驱动信号，该驱动信号用于驱动相应的功率开关管，At least one pulse drive signal conversion circuit for converting an output signal of the secondary winding into a drive signal for driving a corresponding power switch tube,
    所述双端激励信号驱动控制电路与所述隔离驱动变压器的原边绕组连接，所述隔离驱动变压器的副边绕组与所述脉冲驱动信号转换电路连接。The double-ended excitation signal driving control circuit is connected to a primary winding of the isolated driving transformer, and a secondary winding of the isolated driving transformer is connected to the pulse driving signal conversion circuit.
  3. 根据权利要求2所述的隔离驱动电路，其中所述隔离驱动变压器包括第一原边绕组，所述第一脉冲驱动信号由所述第一原边绕组的一端输入，所述第二脉冲驱动信号由所述第一原边绕组的另一端输入。The isolated drive circuit of claim 2, wherein said isolated drive transformer comprises a first primary winding, said first pulse drive signal being input by one end of said first primary winding, said second pulse drive signal Input from the other end of the first primary winding.
  4. 根据权利要求3所述的隔离驱动电路，其中所述第一脉冲驱动信号的频率和所述第二脉冲驱动信号的频率相同，所述第一脉冲驱动信号的占空比和所述第二脉冲驱动信号的占空比相同，所述第一脉冲驱动信号的高电平时间和所述第二脉冲驱动信号的高电平时间前后衔接，或所述第二脉冲驱动信号的高电平时间和所述第一脉冲驱动信号的高电平时间前后衔接。The isolated driving circuit according to claim 3, wherein a frequency of said first pulse driving signal and a frequency of said second pulse driving signal are the same, a duty ratio of said first pulse driving signal and said second pulse The duty ratio of the driving signal is the same, the high level time of the first pulse driving signal and the high level time of the second pulse driving signal are connected back and forth, or the high level time of the second pulse driving signal The high level time of the first pulse driving signal is connected back and forth.
  5. 根据权利要求4所述的隔离驱动电路，其中当所述第一脉冲驱动信号的高电平时间和所述第二脉冲驱动信号的高电平时间前后衔接时，所述第二脉冲驱动信号由低电平开始转换为高电平的时间点早于等于所述第一脉冲驱动信号由高电平开始转换为低电平的时间点；The isolated driving circuit according to claim 4, wherein when the high-level time of the first pulse driving signal and the high-level time of the second pulse driving signal are engaged back and forth, the second pulse driving signal is a time point at which the low level starts to be converted to a high level is earlier than a time point at which the first pulse driving signal is switched from a high level to a low level;
    当所述第二脉冲驱动信号的高电平时间和所述第一脉冲驱动信号的高电平时间前后衔接时，所述第一脉冲驱动信号由低电平开始转换为高电平的时间点早于等于所述第二脉冲驱动信号由高电平开始转换为低电平的时间点。When the high-level time of the second pulse driving signal and the high-level time of the first pulse driving signal are connected back and forth, a time point at which the first pulse driving signal is switched from a low level to a high level A time point earlier than the second pulse drive signal transitioning from a high level to a low level.
  6. 根据权利要求2所述的隔离驱动电路，其中所述隔离驱动变压器包括第一原边绕组以及第二原边绕组，所述第一脉冲驱动信号由所述第一原边绕组输入，所述第二脉冲驱动信号由所述第二原边绕组输入。The isolated drive circuit of claim 2, wherein said isolated drive transformer comprises a first primary winding and a second primary winding, said first pulse drive signal being input by said first primary winding, said A two-pulse drive signal is input by the second primary winding.
  7. 根据权利要求6所述的隔离驱动电路，其中所述第一脉冲驱动信号的频率和所述第二脉冲驱动信号的频率相同，所述第一脉冲驱动信号的占空比和所述第二脉冲驱动信号的占空比相同，所述第一脉冲驱动信号的高电平时间和所述第二脉冲驱动信号的高电平时间前后衔接，或所述第二脉冲驱动信号的高电平时间和所述第一脉冲驱动信号的高电平时间前后衔接。The isolated driving circuit according to claim 6, wherein a frequency of said first pulse driving signal and a frequency of said second pulse driving signal are the same, a duty ratio of said first pulse driving signal and said second pulse The duty ratio of the driving signal is the same, the high level time of the first pulse driving signal and the high level time of the second pulse driving signal are connected back and forth, or the high level time of the second pulse driving signal The high level time of the first pulse driving signal is connected back and forth.
  8. 根据权利要求8所述的隔离驱动电路，其中当所述第一脉冲驱动信号的高电平时间和所述第二脉冲驱动信号的高电平时间前后衔接时，所述第二脉冲驱动信号由低电平开始转换为高电平的时间点早于等于所述第一脉冲驱动信号由高电平开始转换为低电平的时间点；The isolated driving circuit of claim 8, wherein when the high level time of the first pulse driving signal and the high level time of the second pulse driving signal are engaged back and forth, the second pulse driving signal is a time point at which the low level starts to be converted to a high level is earlier than a time point at which the first pulse driving signal is switched from a high level to a low level;
    当所述第二脉冲驱动信号的高电平时间和所述第一脉冲驱动信号的高电平时间前后衔接时，所述第一脉冲驱动信号由低电平开始转换为高电平的时间点早于等于所述第二脉冲驱动信号由高电平开始转换为低电平的时间点。When the high-level time of the second pulse driving signal and the high-level time of the first pulse driving signal are connected back and forth, a time point at which the first pulse driving signal is switched from a low level to a high level A time point earlier than the second pulse drive signal transitioning from a high level to a low level.
  9. 根据权利要求2所述的隔离驱动电路，其中所述隔离驱动变压器包括第一副边绕组以及第二副边绕组；The isolated drive circuit of claim 2 wherein said isolated drive transformer comprises a first secondary winding and a second secondary winding;
    所述脉冲驱动信号转换电路包括：The pulse drive signal conversion circuit includes:
    第一输出电路，用于当所述第二脉冲驱动信号为高电平时，输出第一高电平信号，当所述第二脉冲驱动信号为低电平时，输出第一低电平信号；a first output circuit, configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level;
    第二输出电路，用于当所述第一脉冲驱动信号为高电平时，输出第二高电平信号，当所述第一脉冲驱动信号为低电平时，输出第二低电平信号；以及a second output circuit, configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level;
    或门电路，包括第一输入端、第二输入端以及输出端；用于当所述第一输出电路输出所述第一低电平信号，同时所述第二输出电路输出所述第二低电平信号时，输出低电平驱动信号；否则输出高电平驱动信号；An OR circuit comprising: a first input terminal, a second input terminal, and an output terminal; configured to: when the first output circuit outputs the first low level signal, and the second output circuit outputs the second low When the level signal is output, the low level driving signal is output; otherwise, the high level driving signal is output;
    所述第一输出电路的一端和所述第一副边绕组连接，所述第一输出电路的另一端与所述或门电路的第一输入端连接；所述第二输出电路的一端和所述第二副边绕组连接，所述第二输出电路的另一端与所述或门电路的第二输入端连接。One end of the first output circuit is connected to the first secondary winding, and the other end of the first output circuit is connected to a first input end of the OR circuit; one end of the second output circuit The second secondary winding is connected, and the other end of the second output circuit is connected to the second input of the OR circuit.
  10. 根据权利要求9所述的隔离驱动电路，其中所述第一输出电路包括：The isolated drive circuit of claim 9 wherein said first output circuit comprises:
    第一充放电电路，用于缩短所述第一高电平信号的上升沿的时间，延长所述第一高电平信号的下降沿的时间；以及a first charge and discharge circuit for shortening a time of a rising edge of the first high level signal and extending a time of a falling edge of the first high level signal;
    第一箝位电路，用于对所述第一低电平信号进行箝位。a first clamping circuit for clamping the first low level signal.
  11. 根据权利要求10所述的隔离驱动电路，其中所述第一充放电电路包括第二电阻、第三电阻、第四电阻、第一二极管以及第二电容，所述第一箝位电路包括第二二极管，The isolated driving circuit of claim 10, wherein the first charging and discharging circuit comprises a second resistor, a third resistor, a fourth resistor, a first diode, and a second capacitor, the first clamping circuit comprising Second diode,
    所述第二电阻的一端与所述第一副边绕组的一端连接，所述第二电阻的另一端与所述第一二极管的正极连接，所述第一二极管的负极与所述或门电路的第一输入端连接，所述第三电阻的一端与所述第一副边绕组的一端连接，所述第三电阻的另一端与所述或门电路的第一输入端连接，所述第二电容的一端与所述或门电路的第一输入端连接，所述第二电容的另一端与所述第一副边绕组的另一端连接，所述第四电阻的一端与所述或门电路的第一输入端连接，所述第四电阻的另一端与所述第一副边绕组的另一端连接，所述第二二极管的正极与所述第一副边绕组的另一端连接，所述第二二极管的负极与所述或门电路的第一输入端连接。One end of the second resistor is connected to one end of the first secondary winding, the other end of the second resistor is connected to the anode of the first diode, and the anode of the first diode is Connected to a first input end of the OR circuit, one end of the third resistor is connected to one end of the first secondary winding, and the other end of the third resistor is connected to a first input end of the OR gate circuit One end of the second capacitor is connected to the first input end of the OR gate circuit, and the other end of the second capacitor is connected to the other end of the first secondary winding, and one end of the fourth resistor is a first input end of the OR circuit is connected, and another end of the fourth resistor is connected to another end of the first secondary winding, a positive pole of the second diode and the first secondary winding The other end of the second diode is connected to the first input of the OR circuit.
  12. 根据权利要求9所述的隔离驱动电路，其中所述第二输出电路包括：The isolated drive circuit of claim 9 wherein said second output circuit comprises:
    第二充放电电路，用于缩短所述第二高电平信号的上升沿的时间，延长所述第二高电平信号的下降沿的时间；以及a second charge and discharge circuit for shortening a time of a rising edge of the second high level signal and extending a time of a falling edge of the second high level signal;
    第二箝位电路，用于对所述第二低电平信号进行箝位。a second clamping circuit for clamping the second low level signal.
  13. 根据权利要求12所述的隔离驱动电路，其中所述第二充放电电路包括第五电阻、第六电阻、第七电阻、第三二极管以及第三电容，所述第二箝位电路包括第四二极管，The isolated driving circuit according to claim 12, wherein said second charging and discharging circuit comprises a fifth resistor, a sixth resistor, a seventh resistor, a third diode, and a third capacitor, and said second clamping circuit comprises Fourth diode,
    所述第五电阻的一端与所述第二副边绕组的一端连接，所述第五电阻的另一端与所述第三二极管的正极连接，所述第三二极管的负极与所述或门电路的第二输入端连接，所述第六电阻的一端与所述第二副边绕组的一端连接，所述第六电阻的另一端与所述或门电路的第二输入端连接，所述第三电容的一端与所述或门电路的第二输入端连接，所述第三电容的另一端与所述第二副边绕组的另一端连接，所述第七电阻的一端与所述或门电路的第二输入端连接，所述第七电阻的另一端与所述第二副边绕组的另一端连接，所述第四二极管的正极与所述第二副边绕组的另一端连接，所述第四二极管的负极与所述或门电路的第二输入端连接。One end of the fifth resistor is connected to one end of the second secondary winding, the other end of the fifth resistor is connected to the anode of the third diode, and the cathode of the third diode is Connecting a second input end of the OR circuit, one end of the sixth resistor is connected to one end of the second secondary winding, and the other end of the sixth resistor is connected to the second input end of the OR circuit One end of the third capacitor is connected to the second input end of the OR gate circuit, and the other end of the third capacitor is connected to the other end of the second secondary winding, and one end of the seventh resistor is a second input end of the OR circuit is connected, and another end of the seventh resistor is connected to another end of the second secondary winding, and a positive pole of the fourth diode and the second secondary winding The other end of the fourth diode is connected to the second input of the OR gate.
  14. 根据权利要求9所述的隔离驱动电路，其中所述隔离驱动变压器还包括第一备用副边绕组以及第二备用副边绕组；The isolated drive circuit of claim 9 wherein said isolated drive transformer further comprises a first standby secondary winding and a second standby secondary winding;
    所述脉冲驱动信号转换电路还包括：The pulse drive signal conversion circuit further includes:
    第一备用输出电路，用于当所述第二脉冲驱动信号为高电平时，输出第一高电平信号，当所述第二脉冲驱动信号为低电平时，输出第一低电平信号；以及a first standby output circuit, configured to output a first high level signal when the second pulse driving signal is at a high level, and output a first low level signal when the second pulse driving signal is at a low level; as well as
    第二备用输出电路，用于当所述第一脉冲驱动信号为高电平时，输出第二高电平信号，当所述第一脉冲驱动信号为低电平时，输出第二低电平信号；a second standby output circuit, configured to output a second high level signal when the first pulse driving signal is at a high level, and output a second low level signal when the first pulse driving signal is at a low level;
    所述第一备用输出电路的一端与所述第一备用副边绕组连接，所述第一备用输出电路的另一端与所述或门电路的第一输入端连接；所述第二备用输出电路的一端和所述第二备用副边绕组连接，所述第二备用输出电路的另一端与所述或门电路的第二输入端连接。One end of the first standby output circuit is connected to the first standby secondary winding, and the other end of the first standby output circuit is connected to a first input end of the OR gate circuit; the second standby output circuit One end is connected to the second standby secondary winding, and the other end of the second standby output circuit is connected to the second input of the OR circuit.
  15. 根据权利要求2所述的隔离驱动电路，其中所述隔离驱动电路还包括用于防止所述隔离驱动变压器的直流偏磁现象的防直流偏磁电路，所述防直流偏磁电路分别与所述双端激励信号驱动控制电路和所述隔离驱动变压器连接。The isolated driving circuit according to claim 2, wherein said isolated driving circuit further comprises an anti-DC biasing circuit for preventing a DC bias phenomenon of said isolated driving transformer, said DC blocking biasing circuit respectively A double-ended excitation signal drive control circuit is coupled to the isolated drive transformer.
  16. 根据权利要求15所述的隔离驱动电路，其中所述防直流偏磁电路包括第一电阻和第一电容，所述第一电阻的一端分别与所述第一电容的一端和所述脉冲驱动信号转换电路连接，所述第一电阻的另一端分别与所述第一电容的另一端和所述隔离驱动变压器连接。The isolated driving circuit according to claim 15, wherein said DC blocking bias circuit comprises a first resistor and a first capacitor, one end of said first resistor and an end of said first capacitor and said pulse driving signal, respectively The switching circuit is connected, and the other end of the first resistor is respectively connected to the other end of the first capacitor and the isolated driving transformer.
  17. 根据权利要求2所述的隔离驱动电路，其中所述隔离驱动电路还包括：The isolated drive circuit of claim 2, wherein the isolated drive circuit further comprises:
    功率放大电路，用于对所述脉冲驱动信号转换电路输出的驱动信号进行放大处理，a power amplifying circuit for amplifying the driving signal output by the pulse driving signal conversion circuit,
    所述功率放大电路与所述脉冲驱动信号转换电路连接。The power amplifying circuit is connected to the pulse driving signal conversion circuit.
PCT/CN2012/083076 2012-10-17 2012-10-17 Isolated driving circuit WO2014059620A1 (en)

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