WO2014059423A1 - Génération de signaux basée sur une suite périodique de segments temporels - Google Patents

Génération de signaux basée sur une suite périodique de segments temporels Download PDF

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Publication number
WO2014059423A1
WO2014059423A1 PCT/US2013/064867 US2013064867W WO2014059423A1 WO 2014059423 A1 WO2014059423 A1 WO 2014059423A1 US 2013064867 W US2013064867 W US 2013064867W WO 2014059423 A1 WO2014059423 A1 WO 2014059423A1
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Prior art keywords
signal
time segment
values
output signal
sequence
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PCT/US2013/064867
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English (en)
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David K. NIENABER
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Nienaber David K
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Priority claimed from US13/651,259 external-priority patent/US9490944B2/en
Application filed by Nienaber David K filed Critical Nienaber David K
Priority to EP13845880.7A priority Critical patent/EP2909942A4/fr
Priority claimed from US14/053,360 external-priority patent/US9225368B2/en
Publication of WO2014059423A1 publication Critical patent/WO2014059423A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0491—Circuits with frequency synthesizers, frequency converters or modulators

Definitions

  • Cognitive Radio Systems as currently envisioned within the R&D community, include plans for flexible transceiver's, which can adjust to band utilization variations as needed, changing frequency bands, modulation techniques, and transmission bandwidths as required to make best use of the current RF environment. This discussion continues, yet currently there is not even a cost effective or efficient method to implement a fully flexible SDR.
  • SDR Scalable Radio Systems
  • each of the many differing modulation techniques and wireless standards have historically required different customized analog front-end receiver blocks and customized back-end analog transmitter blocks for each bandwidth, modulation technique, or wireless standard accommodated.
  • the concept of SDR has often been put forth with the promise of a single circuit block that could, under software control, be able to operate and provide competitive performance, while working with any of the current wireless transmission schemes. Yet this promise remains unfulfilled.
  • Figure 1 is a system block diagram showing one embodiment of the present invention implemented in a time segment based software defined radio.
  • Figure 2 is a timing signals chart for quadrature and time segment processing.
  • Figure 3a is a diagram illustrating one embodiment of a time segment distributed integrator of the present invention.
  • Figure 3b is a timing diagram for the diagram of Figure 3a.
  • Figure 4 is a diagram illustrating one embodiment of alternating blocks as time segment distributed integrators with a charge responding A to D.
  • Figure 5 is a diagram illustrating one embodiment of alternating blocks as time segment correlated decimation filters, or alternately each could also be considered a signal value combining system, combining sampled values by accumulation, and passing accumulated values to a charge responding A to D.
  • Figures 6 is a flow chart showing one embodiment of the present invention method for extracting filtered signal values from an input signal.
  • Figure 7 is a flow chart showing one embodiment of the method of the present invention including a transmit mode.
  • Selectivity the technique of selecting which relatively narrow band of frequencies to respond to, has always been key to the signal reception process.
  • Narrow band filtering is fundamental to this process, and the performance of the specific narrow band filters utilized has always been critical in determining the signal to noise ratio of received signals.
  • Periodic Time Segment Sequence Based Decimation is, most fundamentally, a filtering technique, a discrete time decimation filter that achieves a narrow band or band pass response.
  • the challenge of a fully flexible SDR system is to accomplish effective narrow band filtering, using fully flexible reconfigurable techniques that can be used throughout any band. Essentially, achieving fully flexible narrow band response, using broadband techniques.
  • Periodic Time Segment Sequence Based Decimation achieves much of this goal.
  • a modulated signal is one such term, carrier signal is another, and modulation signal is another.
  • a modulated signal is a signal which includes information representative of a modulation signal, which is superimposed, encoded, or modulated onto a carrier signal to become the modulated signal, and from which the original modulation signal can be recovered by some means.
  • Radio Frequency (RF) signals are modulated signals, as are all Intermediate Frequency (IF) signals.
  • IF Intermediate Frequency
  • the carrier signal is a single frequency sinusoidal waveform, generally higher in frequency than any of the spectral content of the modulation signal.
  • the modulation signal is a signal superimposed on a carrier using any of a wide variety of modulation techniques common in the art.
  • FIG. 1 shows a top level block diagram of a Time Segment Based Software Defined Radio (TSB-SDR) system 2, based on these developments.
  • the RF2D block 4 a novel development, is an input block that receives a wide-band modulated signal from a wide-band amplifier 8, or perhaps directly from an antenna, and outputs to a digital signal processor (DSP) block 10 a wide-band stream of data where each piece of data is representative of a modulation component and where the data is time segment correlated.
  • DSP digital signal processor
  • a modulation signal component here is any quantity, value, or signal, which when combined with other modulation signal components, can form a representation of a modulation signal.
  • a representation of a modulation signal thus formed is then referred to as a reconstructed modulation signal.
  • time segment represents a span of the phase of a sequence clock signal, which remains essentially constant from one sequence clock cycle to the next in the phase angle of the sequence clock at which it begins and in the phase angle of the sequence clock at which it ends.
  • Each cycle of the sequence clock spans multiple time segments, equal in number to the number of time segments in a time segment sequence.
  • the number of time segments in a time segment sequence is an adjustable or programmable number, but regardless of how many time segments are selected to be within a time segment sequence, the entire sequence is repeated once per cycle of the sequence clock.
  • time segments While it is not necessary that time segments be contiguous, where every possible phase angle of the sequence clock is thereby included in one or another time segment; it is desirable that time segments remain non-overlapping so that no two time segments both include any one phase angle of the sequence clock. Generally, it is intended that time segments be nearly contiguous, so that every phase be included in one or another time segment, except for transition phases at the beginning or end of a time segment. However, it is possible to have time segments which have significant gaps between them, yet they should not overlap.
  • the sequence clock signal is an approximately constant frequency signal, generated by a local oscillator block 12, or timing system.
  • the sequence clock becomes synonymous with the common usage of the term local clock, where local means within the context of the receiver system.
  • Typical radio systems anticipate that, during the normal operation of receiving a signal, a hardware local clock will be at the same frequency, and in a constant phase relative to a carrier signal used to construct the modulated signal input to the radio system.
  • the actual carrier is generated at the transmitter, and the pure carrier signal itself is therefore not generally available at the receiver.
  • the carrier signal is not necessarily even present within the modulated signal, depending on modulation and transmission scheme.
  • phase lock is generally achieved by first defining some window of time, established by timing format, during which the modulated signal can be relied upon to be representative of the carrier frequency, and to be at some known reference phase. However, precisely how this works can vary substantially from one system to another.
  • the term local clock has been used to refer to a hardware clock, generated locally within a receiver, which is made to be synchronous with some target modulated signal.
  • the only local clock which synchronizes to an input signal may exist only in the software space.
  • the term software defined local clock or the term soft local clock will be used.
  • the term local clock will continue to be used here forward, nondescript in its type of "ware", representing either a hardware or software clock, yet always understood to be synchronous with a target modulated signal.
  • sampling clock will be used in reference to what is normally the fastest clock in the system, which controls the rate at which the fully analog input signal is sampled in time to become a discrete time signal.
  • sequence clock will be used in reference to a clock slower than the sample clock, which is the rate at which a complete sequence of time segments repeats. For hardware synchronous applications of PTSSBD, the sequence clock becomes synonymous with local clock.
  • the option to synchronize the sequence clock or the sampling clock in hardware to the carrier frequency of the target modulated signal always carries with it some additional overhead.
  • This overhead comes in the form of additional complexity, and can also require some compromises in performance.
  • implementing a voltage controlled oscillator will often result in more jitter than a fixed frequency oscillator.
  • synchronizing the sequence or sampling clock to the input signal usually leads to a performance enhancement, but not always.
  • There are target modulated signal cases where it is better to use a hardware asynchronous local clock. Depending upon the carrier frequency and bandwidth of the target modulated signal, particularly where the carrier frequency is low enough to allow a higher number of time segments per carrier cycle, the benefits of synchronizing the local clock in a hardware manner can be less significant, and be mitigated by other factors.
  • Some systems necessitate the demodulation of multiple modulated signals having different carrier rates, all in the same channel. For example, Doppler effects on GPS signals from different satellites can make it impossible to be synchronous with all of the satellites in a constellation at the same time. This would mean hardware synchronicity with one satellite signal assures that other satellite signals will be hardware asynchronous.
  • the system herein described is an SDR system intended to be capable of receiving essentially any transmitted signal. It is therefore desirable for the system to be capable of all methods of frequency or phase lock, including where signal synchronicity is achieved only in software, perhaps with a phase locked loop or frequency locked loop implemented entirely in software. Such an approach requires that the hardware remain asynchronous.
  • the local clock when in proper frequency and phase relationship relative to the carrier of the target modulated signal, can generally be said to be correlated in time to the modulated signal. It is important to note however, that this is not always a strong mathematical correlation in the strictest sense. Where the carrier is suppressed (not transmitted) and if the modulation factor is high (a statistically high percentage of the modulation range is utilized) this means there may not be very much of the carrier frequency contained in the modulated signal, such that the mathematical correlation may not be very high at all.
  • the local clock can still be considered as correlated in time with the modulated signal.
  • time segment correlation is intended to indicate a very high level of mathematical correlation, virtually 100%.
  • Each time segment amounts to a window of time during which the modulated signal gets acquired or captured, with the value captured becoming associated only with the time segment active during the time of capture.
  • time segments are non-overlapping ensures that any instantaneous time value of the input signal gets included in only one time segment. This maintains the independence of the modulated signal values so captured and the significance of the time segments as separate from one another. Signal transmitted or received within a time segments span remains isolated and separated from signal transmitted or received during other time segments.
  • Time segment correlation can now be understood, and signal or data can be understood to be time segment correlated whenever all data or signal captured during any one time segment of a time segment sequence is collected or captured and kept separate from data or signal captured or collected during any other time segment of the sequence. Wherever this separation is maintained, the data or signal can be said to be time segment correlated. Again, this correlation is a type of correlation where a high mathematical correlation is important in order for it to be time segment correlated. In fact, time segment correlation indicates a case where full correlation is virtually assured by design or by definition.
  • the data stream output of the RF2D converter block 4, RF2Dout has an adjustable data rate, f_RF2Dout, adjustable under the control of the DSP 10 and generally chosen to be fast enough to at least provide Nyquist rate data relative to the widest band information present in the incoming signal. In this way, no loss of bandwidth in the data or signal received occurs within the RF2D block 10. It is important to note however, that it would be possible to allow a reduction in bandwidth, if so desired, within the RF2D block merely by selecting an RF2Dout speed slower than the Nyquist rate relative to the widest band information present in the incoming signal.
  • the first processing block within the RF2D block 4 is a discrete time processing block called Time Segment Correlated Capturing (TSCC) 14, or for applications where the sampling rate is synchronous, usually at some integer multiple frequency, with the target modulated signal (Synchronous Acquisition), this block is called Phase Sector Correlated Capturing.
  • TSCC Time Segment Correlated Capturing
  • this capturing block is where the modulated signal input to the RF2D block 4 is broken up into discrete time segments and thereby sampled or acquired according to time segment, and then processed without yet being converted to a digital or binary representation of the signal.
  • the signal in this first stage still has full analog signal resolution, where the effective resolution is limited only by a noise floor present. This noise floor is formed as a combination of local circuit processing noise and noise present in the incoming signal.
  • this discrete time block also includes multiple channels of low-pass filters, which act like discrete time decimation filters on the input data. There is one filter for each time segment. Each of these time segment correlated decimation filters has a decimation rate that is variable depending on the number of sequence clock cycles, or the number of time segment sequences over which the sampled values are acquired and combined to obtain filtered signal values.
  • the simplest discrete time filter for this application is implemented by simply adding up (or “accumulating") the captured signal values (or “sampled values”), separately by time segment, from one sequence clock cycle to the next. In this way, each value captured during any one time segment of one cycle of the sequence clock is simply added together with signal values captured during the same time segment of subsequent sequence clock cycles.
  • Another option, rather than down-conversion, is to pass the signal captured for each time segment to the A to D 16 at full speed, one value per time segment per sequence clock cycle. This amounts to f_RF2Dout Fsclk, where Fsclk is the frequency of the sequence clock, which for hardware synchronous systems, becomes the same as the local clock, equal in frequency to the carrier frequency of the modulated signal. This would require that the DSP 10 process values coming in from the A to D 16 at a rate equal to the number of time segments per sequence clock cycle times the Fsclk rate. For processing a quadrature signal, that rate would be at least four times the Fsclk rate.
  • the RF2D block 4 in one embodiment, includes two identical discrete time processing input blocks, one receiving input values, while the other is dumping its values to a subsequent block, usually the A to D block 16.
  • Figure 4 illustrates one embodiment of these two blocks 18, 20 (accumulation blocks) for a time segment integration capturing system, described below.
  • Each of these two blocks also has their value reinitialized during its dumping period, reinitialized to a level which the A to D 16 would receive and interpret as a zero value. This occurs after it has dumped its value to the A to D 16 but before it is reconnected to new input for its subsequent acquisition phase.
  • these two blocks are included within in the Time Segment Correlated Capturing block 14 of Figure 1 .
  • Fsclk/RF2Dout down-conversion factor the number of time segments per clock cycle, and the selection of sequence clock frequency; such that the resulting digitized time segment correlated values can be passed to the DSP block 10, containing the information necessary to fully decode, demodulate, filter, and present data in whatever form most desirable, for any RF signal which can be transmitted, and to do so in a way which provides the best signal to noise ratio possible. Because of this, this system is capable of the full flexibility envisioned in the original concept of SDR, as no conventional or prior art circuits or systems have been.
  • Quadrature modulation is used for many different systems, 8QAM, 16QAM, and 32QAM to name a specific few, and countless others. Quadrature modulation is also key to consider because the quadrature relationship of the I and Q signals adds the significance of phase variation, as well as generally adding complexity to the demodulation process.
  • a quadrature modulated signal is most simply processed using TSCC, with four time segments per sequence clock cycle. For the highest frequency RF signals that a given semiconductor implementation of the block can handle, this would almost certainly be the number of time segments chosen. However it is also important to note that for lower frequency RF signals, a higher number of time segments per cycle of the carrier or or the sequence clock can provide various advantages.
  • Figure 2 includes waveforms, which show the timing relationships for each of four equally sized time segments shown as (a), (b), (c), and (d).
  • (e) shows a cosine wave, in the ideal phase relationship with the timing signals of (a), (b), (c), and (d).
  • Figure 2 shows a synchronous case, such that a phase lock condition between the carrier that formed the modulated signal and the sequence clock exists. The effects of an asynchronicity will be considered below.
  • Simple impulse sampling may not provide the best signal to noise ratio, but is the most common method of acquiring a discrete time representation of a signal, and therefore an interesting case to consider.
  • Applying TSCC to simple impulse sampling results in a technique described below as Time Segment Impulse
  • TSIS can be used for both hardware synchronous cases, and for asynchronous, but in both cases impulse sampling must be done at regular intervals.
  • This synchronicity, in combination with time segment correlation, requires that each time segment include an equal number of evenly time-spaced samples. For a four time segment or quadrature case, this necessitates an integer multiple of four samples per Fsclk cycle.
  • the simplest case is again the best to consider, which is just the single sample per time segment case. The only remaining choice then is where to phase the impulse sample within the time segment.
  • Figure 5 is a diagram illustrating one embodiment of alternating blocks as time segment correlated decimation filters, or alternately each could also be considered a signal value combining system, combining sampled values by accumulation to obtain filtered signal values, and passing accumulated values (or filtered signal values) to a charge responding A to D.
  • TSIS operates by first acquiring a sampled value using an impulse sampling method, within an impulse sampling block. This is done for the TSIS system shown in Figure 5 for each of four time segments, during the time when each of the sampling switches, SWa, SWb, SWc,
  • SWa_BAR is designated by the letters SWa with a line above it to designate the BAR notation, indicating that the timing for SWa_BAR is the inverse of the timing for SWa.
  • each of the complement switches is non-overlapping with that of the sampling switches, as is typical for most switched capacitor circuits, so that no sampling switch and its respective complement switch are ever on at the same time.
  • the timing of the sampling switches relative to each other can be seen in Figure 3b.
  • the timing of signals a b c and d of Figure 2 are arranged to show the intervals of each time segment, but these are NOT phased the same as the switch control signals for the TSIS system.
  • the effective moment of impulse sampling occurs at the end of the sampling interval. This should occur at the moments of impulse sampling shown in Figure 2 at (e), which as previously described, should occur at the center of a time segment, as shown in Figure 2, for the case where only one sample is captured per time segment.
  • Each accumulation type decimation filter of Figure 5 then continues to accumulate sample values by time segment during one entire cycle of the f_RF2Dout clock, At the end of that clock period the decimation filter which had been capturing, switches to transfer mode, and begins passing the accumulated values for each time segment to the A to D, one value at a time. While the other decimation filter block is then put into capture mode, and begins accumulating sampled values.
  • capacitors made throughout the circuits, systems, and blocks of the TSB-SDR 2. Each capacitor as described here and throughout this writing could be replaced with a capacitive device.
  • a capacitive device being any device or plurality of devices generally having two or more terminals, which has capacitance between two terminals such that it behaves like a conventional capacitor, in a manner sufficient so as to allow the circuit or system to behave approximately as it would if a capacitor were in its place, generally having an amount of charge stored on the device equal to the voltage across the device multiplied by its capacitance.
  • the term capacitor will be generally used, with the understanding that it could be replaced by any capacitive device.
  • the impulse samples are also shown in Figure 2 at (e), where there are four impulse samples per cycle of the modulated signal. From left to right, these impulse samples shown in Figure 2 at (e) are for time segments A, B, C, D, A, B, C, D, A, B, C, D.
  • the time segments A, B, C, D comprise a periodic time segment sequence having a plurality of ordered time segments. The sequence is periodic because it repeats the time segments. The tie segments are ordered because they repeat in the same order.
  • TSIS allows for multiple impulse samples to be accumulated over multiple Fsclk cycles, as long as the accumulation is done separately for each time segment, yielding a separate accumulated value for each time segment, and so that any values accumulated together are captured within the same time segment, although probably over multiple cycles.
  • This accumulation for the TSIS case, can be accomplished with the addition of a switched-capacitor circuit designed for this purpose, Figure 5 shows two such blocks.
  • each switched capacitor filter provides an analog decimation filter, separately for each time segment, accumulating the sum of the values captured on a capacitor, for later transfer to the A to D block 16.
  • the down-conversion ratio of Fsclk/RF2Dout would normally be chosen so that the bandwidth of the resulting RF2D output data would not be significantly reduced, which means generally, that there would not be much variation in the values of all of the A time segment values over the time of their accumulation. Whatever variation there is gets averaged over the accumulation. Naturally, this also applies to the B, C, and D values respectively.
  • the effective bandwidth, resulting from the down-conversion factor selected becomes a significant factor in determining how much error is too much error.
  • the decimation ratio it is not the goal of the decimation ratio to narrow the band of the target modulated signal, but only to reduce the data rate out of the A to D and into the DSP down to a manageable rate. So, for the asynchronous case, If the entire band of the target modulated signal is within the pass-band of the decimation filter, this by itself ensures that the effects on the signal due to the error in frequency between the sequence rate and the target modulated signal carrier rate is going to be minimal in most cases. Furthermore, the frequency offset by itself will only cause a slow and constant rate of shifting phase between the signals, a rate of phase shift that will be averaged by the accumulation process. The soft local clock in the DSP will phase lock to the data acquired after the affects of this averaging of the phase shift are factored in, which means this will not even generate any static phase error.
  • Each of the values for time segments A, B, C, and D gets transferred and converted to a digital value by the same A to D converter 16, with resulting digital values then made available to the DSP 10, while their time segment correlation also is provided to the DSP 10, so that each value is still identified by the A to D as data resulting from time segment A, B, C or D. In this way the DSP can continue filtering or processing the data in any desired programmable manner, while maintaining its time segment correlation.
  • the input signal is an RF or IF or any modulated signal
  • mixing of these time segment correlated values can also then be easily performed by the DSP, or by any digital signal value combining system.
  • the values thus acquired for I and Q are no different if the values for A,B,C,and D are first low pass filtered by time segment, and then combined to develop I and Q as shown here, or whether they are first combined or mixed by traditional means, and then low pass filtered.
  • One advantage is that for lower frequency target modulated signals, using a higher number of time segments or time segments per cycle of the target modulated signal helps avoid aliasing and eliminates the need for tunable anti-aliasing filter blocks out in front of the decimation filter block. Otherwise, signal bands that are at harmonics of the target modulated signal can be aliased into the base-band data wherever only the minimum number of time segments are utilized (two for non-phase significant forms of modulation, or four for I and Q and other phase significant forms of modulation).
  • each time segment must then get weighted by either +1 or -1 in the DSP where the mixing is done, making the effective soft clock local oscillator injection into mixing essentially a square wave, such that any harmonics of the target modulated signal present at the input will get demodulated down to base-band along with the intended target modulated signal.
  • increasing the number of time segments per cycle of the target from four to eight has a dramatic effect on the ability to filter out those undesired harmonics of the target. This is because with eight values, the weighting values applied to the time segment accumulated values while mixing in the DSP block are far more gradually varying and can more closely approach the ideal sinusoidal mixing, compared to the binary mixing which results from 4 values per cycle of the target.
  • a larger number of time segments per sequence, or per local clock cycle, is desirable is its effect on the noise level in the signal detected.
  • a larger number of time segments for a given target frequency essentially provides more data points to be combined into a final value. This has the similar effect as increasing an oversampling factor, on reducing the error or noise in the signal so obtained.
  • a third value to having a higher number of time segments per sequence is that it increases the time resolution of the data acquired. This in effect means that when processing data in the DSP, there is a higher density of time samples to process with, meaning a higher effective time based resolution on the data, resulting in higher resolution control and measurement of frequency and time.
  • the sample clock is synchronous or asynchronous with any input target modulated signal.
  • the frequency of the sequence clock must be chosen to be near enough to that of a target modulated signal, so that the target modulated signal is still in the pass band of the resulting decimation bandpass filter.
  • a software defined clock also referred to herein as a soft clock. Is likely to work nearly as well as a hardware synchronous case.
  • phase comparator that compares the phase of a received modulated signal to that of the local clock, usually during a predefined reference period discerned from receiving a signal with the proper timing format.
  • the phase comparator most conventionally uses a four quadrant multiplier or an exclusive-OR block that essentially implements a binary type multiplication on the two input signals, where one is the local clock and the other is the received modulated signal, where the multiplier is only on during a predefined phase reference period.
  • the output of this phase comparator is disabled and a low pass filter, most often just a single capacitor, holds its voltage unaltered until the next predefined reference period occurs.
  • phase comparator tends to cause a phase lock loop to lock with the two inputs to the phase comparator in quadrature with one another, that is 90 degrees out of phase, which results in an equal period of charging the hold capacitor as discharging it per local clock cycle, during the predefined reference period.
  • the output of this phase comparator is often that of a charge- pump, charging or discharging the hold capacitor in response to the relative phase of the local clock and reference period signal.
  • the voltage on the capacitor then typically becomes the control voltage input for a voltage controlled oscillator.
  • This same functionality can be achieved, using time segment correlated capturing as applied to a quadrature modulation case, by employing a digital low pass filter technique on the post conversion mixed Q signal, developed within the DSP, or, alternately, by acting on a separately developed control signal having control signal values developed within the DSP from accumulated values previously discussed.
  • This low pass filtering would then be done to obtain a control value or voltage to be applied as a control input to the local oscillator, thereby controlling its frequency, as with a convention Voltage Controlled Oscillator, (VCO), and thereby forming a PLL 10.
  • VCO Voltage Controlled Oscillator
  • some of the low pass function could be reserved for an analog final stage, which could be a charge pump type design, either charging or discharging a hold capacitor, similar to that of a conventional PLL phase comparator output and VCO control input, but with the signal driving it being a digitally low pass filtered version of the Q signal.
  • This digital low pass and/or charge pump could then be programmed, under the control of the DSP 10, to be enabled only during the correct reference period, thereby again creating an effective sample hold on the phase comparator output.
  • the voltage on the hold capacitor is then applied to a VCO, and so controls the oscillator frequency used to develop the local clock, and the timing of the four time segments. This now essentially forms a fully programmable PLL. The programming for this could be changed.
  • the precise filter response of the low-pass could be changed as with the rest of the features of this SDR system 2, to accommodate any signal/modulation format, now including the timing details of the desired phase reference period.
  • the programming could also be changed in response to signal conditions, by having a control signal evaluator, probably formed merely by program steps operating within the DSP, which can evaluate the control signal described above, before it is low pass filtered, or any of the other signals otherwise developed within the DSP, comparing the signals to any number of characterization metrics, many determined by mere mathematical processing of the control signal, to determine what the low pass filter characteristics should be, or to determine how the control signal is processed in developing the control value or voltage used to control the VCO.
  • This Post Conversion Mixing is advantageous in every way, as it provides for virtually no mismatch between either the I and Q channels, nor between either of those and the phase detection mixing traditionally used to provide the control voltage to control the voltage controlled local oscillator of the PLL. All of this mixing is now done post down-conversion and post analog to digital conversion, and is therefore acting on data which has been processed through a single analog block and a single analog to digital conversion process. I and Q are now formed by mathematically mixing identical data. This leaves essentially no place for l/Q mismatch to occur within the receiver. This is a major advancement over conventional techniques.
  • the RF2D converter block can be considered merely an RF to base-band translation and down conversion block.
  • a very unique block however, in that it converts to base-band, a signal which still contains both I and Q in a single signal.
  • the output of this block is a number of separate outputs equal in number to the number of time segments in a sequence. Each output is a base-band output, with a band limit determined by the down conversion factor. This is much like a direct conversion receiver except that multiple different time segments of the RF signal has been direct converted down to baseband, a number equal to the number of time segments in the sequence. Since no real mixing has occurred yet, this signal processing method has applications much broader than merely RF signal processing.
  • This is a novel technique broadly applicable and valuable to many different signal processing applications, not just for a modulated signal input. This most directly applies to applications where the signal of interest is a band pass signal. Furthermore, all the advantages of using this technique, including the signal to noise performance enhancement, apply to this wider scope of signal processing applications as well.
  • TSIS Time Segment Integration Capturing
  • this block 22 and its signal timing is arranged to show a specific case of Time Segment Integration Capturing, and a special case of Time Segment
  • this arrangement also includes a specific selection where there are four time segments per sequence clock cycle, and where the phase relationship between the sequence clock and the incoming modulated signal appears phase locked, just as in the impulse sampling case, in a manner suggesting that the frequency of the sequence clock and that of the incoming modulated signal are very close.
  • the input signal a target modulated signal, which might be received directly from an antenna, or from a very wide-band amplified version of signal present at the antenna, or perhaps an attenuated transmit output, is applied to one side of a resistor Rin, where the other side of the resistor is connected to the inverting input of an ideal op-amp 24.
  • the positive input 26 to the op-amp is connected to a DC voltage reference level, which might be ground, and is certainly an effective AC ground.
  • the output 28 of the op-amp is connected to four switches,
  • SWa, SWb, SWc, SWd (for the quadrature case), where only one of the switches is closed or on at any one time.
  • the other side of each switch is connected to one side of a capacitor, Ca, Cb, Cc, Cd, with the other side of the capacitor Ca, Cb, Cc, Cd connected back to the inverting input 30.
  • Each switch SWa, SWb, SWc, SWd is connected to its own capacitor Ca, Cb, Cc, Cd. In this way, because of the switches SWa, SWb, SWc, SWd, only one of the capacitors Ca, Cb, Cc, Cd is connected at any one time.
  • the op- amp 24 acts on the capacitor Ca, Cb, Cc, Cd through the switch SWa, SWb, SWc, SWd, providing whatever voltage is required to keep the inverting input of the op- amp 24 essentially and approximately equal to the positive input 26 of the op-amp 24. Since the inverting input node is then maintained at a constant voltage, in this case at ground, any signal present at the input side of the resistor Rin, is converted into a current through the resistor Rin. This current has no where to go except through the capacitor Ca, Cb, Cc, Cd having its related switch SWa, SWb, SWc, SWd on.
  • each capacitor Ca, Cb, Cc, Cd is charged with a current that is a replica of the input signal, and thereby the charge on the capacitor Ca, Cb, Cc, Cd becomes proportional to, and a replica of, the integral of the input signal during the period when its associated switch SWa, SWb, SWc, SWd is on.
  • this block 22 becomes essentially a time segment accumulator, accumulating a value, in this case charge, over each non-overlapping, timing system developed time segment.
  • Each of the four switches SWa, SWb, SWc, SWd is then sequentially turned on, after the other switches SWa, SWb, SWc, SWd are all off, so that there is no overlapping time period where more than one switch is on. This prevents charge representing signal, which has correctly been acquired onto one capacitor Ca, Cb, Cc, Cd, from being altered by signal during a different phase of clock, or by charge on an alternate capacitor Ca, Cb, Cc, Cd.
  • the timing of the turning on of each of the switches SWa, SWb, SWc, SWd is sequentially arranged, so that any one switches SWa, SWb, SWc, SWd period of on time, always follows the on period of the same other switch SWa, SWb, SWc, SWd.
  • each switch and capacitor combination A, B, C, and D is named so that the time when switch SWa is on always follows when switch SWd is on, SWb always follows SWa, SWc always follows SWb, and SWd always follows SWc, these four periods together complete one full cycle of the sequence clock.
  • the circuit from Figure 3a operates so as to integrate the input signal current, and thereby store a charge on each of the capacitors, which is proportional to the integral of the input signal over the period where the switch associated with that capacitor is on. This then results in charges, referred to as Qa, Qb, Qc, and Qd, which are the charges representative of accumulated values, specifically analog accumulated values, on each of the four capacitors Ca, Cb, Cc, Cd of Figure 3a, during periods A, B, C, and D, respectively.
  • Figure 3b shows the timing of SWa, SWb, SWc, and SWd.
  • each of the capacitors Ca, Cb, Cc, Cd which have now accumulated a signal related charge as an accumulated value, are then dumped into a charge responding A to D converter
  • a to D output value is acquired for each time segment value, one for the charge accumulated during each of quadrature time segments A, B, C, and D.
  • the A to D 16 does not have to execute an A to D nearly as quickly. Furthermore, as before with the impulse sampled case, the data is averaged, so any random noise is reduced, while the signal in effect, gets larger because of the ongoing integration. None of the desired pass band data is lost unless the down- conversion factor becomes large enough to result in a restriction of the bandwidth to a value that is narrower than that of the data contained in the modulation of the modulated signal. Ideally, the down-conversion factor is chosen so as to make the bandwidth just large enough to avoid significantly limiting the bandwidth of the data. The exact bandwidth chosen would likely be chosen to provide the best signal to noise ratio of the resulting data.
  • Time Segment Integration Capturing can be used in this way, to achieve modulation signal values, using analog discrete time methods.
  • This combining can be accomplished using any accumulated value combining system. Where the processing block is analog, the values are usually charges, and the combining is most commonly implemented using switched-capacitor techniques. Where the combining is accomplished using digital values, the accumulated values are just digital values in active memory, and the accumulated value combining system generally becomes a mathematical step executed by a program running on or within a DSP block.
  • selective combining of accumulated values can be performed on digital accumulated values, after digitizing the analog accumulated values.
  • the option of reconstructing the modulation signal value before digitization, by selectively combining the analog accumulated values, has already been described.
  • some portions of this selective combining might be performed before the A to D, with others left until after the conversion to digital. In some cases, this can be done by merely reconnecting using switched-capacitor techniques, the capacitors of Figure 4, during different time segments of the four time segment clock. This combines multiple time segment accumulated values before the A to D conversion.
  • This option reduces the A to D conversion rate to two values per cycle, while also maintaining the benefits of post conversion mixing for the I and Q reconstructed modulation signals.
  • This alternate combining system is one of several ways the RF2D 4 can be setup to accumulate and operate on the modulated signal, the accumulated values, and the modulation signal values.
  • Different setups are likely to yield better signal to noise ratio than others, depending on signal conditions. These signal conditions can include a large set a variables, strong or weak signal, whether or not there is a strong interfering signal nearby in frequency or physically near the receiver so that it is overwhelming the desired signal, or whether or not there is rapidly changing fading conditions, just to name a few.
  • the program running in the DSP 10 can adjust the selection of setups, to get the best signal to noise ratio, under current signal conditions.
  • Continuous Signal Capturing is an advantage referred to as Continuous Signal Capturing.
  • Continuous Signal Capturing is achieved by performing continuous accumulation on the input signal. Whenever the input signal is no longer accumulated on the most recently charging integration capacitor Ca, Cb, Cc, Cd , it is now effectively becomes accumulated on the subsequent time segment's capacitor Ca, Cb, Cc, Cd.
  • time segment Distributed Integrator block can accumulate time segment correlated values for time segments, A, B, C, and D, which represent low pass filtered, or decimation filtered accumulated values.
  • the charge stored on capacitor Ca gets added to, by additional charge during a second phase A of a subsequent full cycle, and by each phase A of multiple subsequent full cycles.
  • the charge already on capacitor Cb gets added to by a second and multiple subsequent phase B portions of second or multiple full cycles of the set of four switches.
  • Capacitors Cc and Cd also, can thereby integrate charge over multiple full cycles of the set of four switches SWa, SWb, SWc, SWd. Charges accumulated in this way are still time segment correlated, with each capacitor Ca, Cb, Cc, Cd accumulating charge only during its active time segment of each sequence clock cycle. This is similar to the low pass filter used in conjunction with the impulse sampling method previously described, the simplest of which just adds up the input samples. However, with this integrating block, there is no additional circuitry required, and no additional components being clocked at the fastest clock rate, effectively 4 times the sequence clock rate. The same integrating capacitors Ca, Cb, Cc, Cd just continue to add up the charge over multiple sequence clock cycles.
  • the signal adds up over multiple sequence clock cycles, and the resulting integrated charge can be made available to a subsequent A to D converter 16 at a much slower, down-converted rate.
  • signal to noise ratio resulting from the averaging of the time segment correlated charge components over time, as they are integrated onto each of their respective capacitors Ca, Cb, Cc, Cd, linearly compounding the amount of charge that is in response to the signal, while adding only stochastically, the amount of charge that is present on the each capacitor Ca, Cb, Cc, Cd due to noise.
  • this band narrowing is a function of the down-conversion factor, which is just Fsclk/f_RF2Dout, and which is under the control of the DSP 10.
  • this down-conversion factor can be chosen so as to not narrow the band of the information contained in the modulated signal, or it can be chosen to narrow the band, if so desired.
  • both I and Q are first formed after digitization has occurred using a single A to D block 16.
  • I and Q are formed in the DSP 10 by combining, in the right polarity, the values collected during each of the quadrature time segments. This again constitutes Post Conversion Mixing with all of the same advantages as previously described, all profound in several ways.
  • the mixing and filtering to provide the control voltage for the voltage controlled oscillator portion of the PLL is also the same as previously described.
  • this modulation signal evaluator can evaluate the reconstructed modulation signal relative to any number of characterization metrics, many determined by mere mathematical processing of the reconstructed modulation signal, which could be done by any processing system, but generally for this TSB-SDR system, the processing system is the DSP block.
  • this TSB-SDR system 2 As applied to achieve a receiver, receiving a modulated signal.
  • the transmitter portion of a radio system can also be greatly enhanced by all of the previously described techniques.
  • a number of conventional transmitter methods and techniques can be applied to this system, merely by adding programming code within the DSP block 10 of this TSB-SDR 2.
  • this system provides for a relatively wide-band, and thereby a relatively fast, acquisition of reconstructed I and Q modulation signal values from a modulated signal. This enables the novel use of a closed loop feedback system, which is amply stable, incorporating the transmitter block in the loop.
  • a transmit/receive mode control For transmit mode, a transmit/receive mode control, generally a control signal or control bit from the DSP block 10, switches the modulated signal input to the TSCC block 14 from a received signal over to an attenuated version of the transmit output.
  • the TSCC block 14 then provides reasonably quick feedback to the DSP block 10, so that it can compare the actual transmit signal to a desired transmit signal and make calculated adjustments to the real time transmit data signals and thereby to the Transmit Driver Output, (TDO), signal driving the transmit output stage 32, as necessary to achieve the desired transmit signal at the output of the transmit output stage 32.
  • TDO Transmit Driver Output
  • the output of the transmit output stage 32 is in effect regulated to match the desired signal, so that the desired transmit signal is more closely achieved at the output of the transmit output stage 32, greatly mitigating non-linearities, and thermal non-idealities, of the transmit output stage 32.
  • Conventional systems have not been able to take this approach, because conventional systems have much too much delay in any signal path which reconstructs a modulation signal or component from a modulated signal by conventional means.
  • the digital transmission values that are output from the DSP 10 are converted to quantized analog values by the RF digital to analog converter (RF
  • This RF DAC 34 provides quantized analog values serially, one for each time segment of the periodic time segment sequence. These values are then stored using a sample and hold amplifier with a hold capacitor, within the Periodic Time Segment Sequence Based Signal Generation block (PTSSBSG) 36.
  • the PTSSBSG 36 or some other value generator, provides time segment correlated signal values, providing each value in the form of either a current or a voltage or some combination thereof, in an amount proportional to this time segment correlated signal value, providing these values at an RF carrier rate, to the transmitter output stage 32 for transmission.
  • the values correlated to each time segment are contributory values, in that these values contribute to the TDO signal.
  • the DSP 10 typically provides serially, one contributory value for each ordered time segment, once for each RF DAC update cycle.
  • the frequency of the RF DAC update cycle is equal to the Generator Time Segment Sequence (GTSS) rate, (freqGTSS), divided by a Band Narrowing Factor, (BNF).
  • GTSS Generator Time Segment Sequence
  • BNF Band Narrowing Factor
  • the quantized analog value at the output of the RF DAC 34 is stored on one hold capacitor or capacitive device for each time segment, within the PTSSBSG block 36. In this way, a single RF DAC 34 is used, avoiding any value mismatch issues, and this also makes it much easier to support the use of many time segments per time segment sequence. Because of this arrangement, the data update rate out of the DSP 10 does not have a full RF carrier rate, but can have an update rate more on the order of the bandwidth of the resulting RF transmission, rather than on the order of its carrier frequency.
  • this PTSSBSG block 36 is a functional inverse of PTSSBD, in that rather than functioning as part of a receiver type block, down- converting digitizing, and mixing a signal as the receiver of a TSB-SDR does, the PTSSBSG 36 functions as a signal generator part of a TSB-SDR transmitter, obtaining quantized analog values from the RF DAC 34, providing these values or interpolated versions of these values as modulation, providing an up-conversion mixing function, ultimately forming a modulated signal as a transmit signal.
  • the time segment sequence rate of the PTSSBSG 36 can be at the same speed, and fully synchronous with the time segment sequence rate of the PTSSBD, or they can be fully independent.
  • the PTSSBSG 36 does not need to have its freqGTSS synchronous with the carrier or center frequency of its output, the Generated Modulated Signal (GMS).
  • GMS Generated Modulated Signal
  • the output signal from the PTSSBSG is adjustable in bandwidth, which is determined by the BNF.
  • the PTSSBSG 36 has applications other than radio or RF systems.
  • This block 36 can be used to create any comb signal, for example generating a voice signal, or perhaps many voice signals using a DSP 10.
  • a comb signal is a signal having one or more bands, each band centered at a fundamental frequency or at an integer multiple of the fundamental frequency, and each band having spectral content substantially narrower in frequency span than the center frequency of the band containing the signal.
  • Such a DSP 10 would be more efficiently utilized, since its processing data rate for any given channel could be much slower than if the data were processed at the effective carrier rate.
  • the PTSSBSG 36 would be a good choice for generating any signal having a comb type spectral content, or characteristic. It is a reasonably efficient encoding method as well for any such signals.
  • the PTSSBSG 36 is best utilized by allowing the
  • DSP 10 to output data for transmission at a rate that is a function of the bandwidth of the desired resultant transmitted modulated signal, rather than its center or carrier frequency.
  • This transmission data once converted by an RF DAC becomes a quantized analog signal present at the output of the sample and hold amplifier within the PTSSBSG block 36, having a step in its value whenever the transmit data is updated. Rather than generating abrupt steps in the output signal in response to these steps, it would often, and even generally, be preferable to smooth the steps, with the update values treated as target values, and utilizing an interpolator and any of a number of interpolation methods known in the art, within the PTSSBSG block 36, to interpolate between adjacent target values.
  • interpolators examples include linear interpolators and cubic spline interpolators. Simple linear interpolation is easily implemented using a capacitor charged and discharged with a current source. This interpolation is in effect inserted into the signal path immediately following the sample and hold amplifier within the PTSSBSG block 36, and dubbed Quantized Analog Signal Interpolation (QASI) to differentiate it from TDO interpolation described below.
  • QISI Quantized Analog Signal Interpolation
  • the GMS of the PTSSBSG 36 since the output signal, the GMS of the PTSSBSG 36, typically drives a transmitter output stage, it is necessary to limit unintended non-linearities or harmonic content in this signal, since such content tends to generate interference with other out of band communications if emitted by the antenna. Limiting such harmonic content is the main value of QASI. Similarly, with a linear harmonic free transmission as the goal, it is also very convenient, and a major advantage of PTSSBSG, that its output signal to the transmitter can be pre-distorted to compensate for any non-linearities of the transmitter output stage.
  • the PTSSBSG block 36 subsequently includes this pre-distortion into its Transmit Driver Output (TDO) signal.
  • TDO Transmit Driver Output
  • This pre-distortion then makes the TDO a modulated signal with a non-sinusoidal, complex waveform carrier.
  • this complex waveform carrier causes what otherwise might be a bandpass signal content to be spread more broadly across the spectrum, with multiple copies of the bandpass signal centered at each of the harmonic frequencies of the carrier fundamental frequency, thereby forming a comb signal, that is a signal having a spectral content similar to that of a full band signal filtered by a comb filter.
  • This TDO signal is formed by providing each time segment correlated value to the output of the PTSSBSG 36. This process also tends to yield analog value output levels with steps between them as the PTSSBSG 36 steps between time segments of the GTSS.
  • a second interpolator can also provide an advantage, to eliminate any steps in the TDO signal, by interpolating between time segment correlated output values from the PTSSBSG 36. This interpolation also can be linear, cubic spline, or utilize any of a number of known interpolation methods.
  • This TSB-SDR system 2 provides for a zero IF, direct RF down-conversion technique, which converts as directly as possible, an RF band-constrained signal located at a center frequency, to a clocked parallel data stream.
  • the center frequency at which RF information is down-converted from is determined by the frequency of the sequence clock, Fsclk.
  • This sequence clock is developed by the sequence clock generation block 12, under the control of the DSP 10.
  • a down- conversion factor is given by the ratio of the sequence clock to the frequency of the complete cycle output rate of the A to D conversion block 16, or Fsclk/f_RF2Dout. This ratio is an integer ratio, also controlled by the DSP block 10.
  • the output of this block 4 is a stream of multiple bit wide data, provided to the DSP block 10.
  • the TSB-SDR 2 incorporates a transmitter 32, also controlled by the DSP 10, with a reconstructed modulation signal generated by the RF2D block 4 from the output of the transmitter fed back to the DSP 10, allowing the DSP 10 to maintain closed loop control of the transmitted output signal.
  • This system is capable of receiving and transmitting in accordance with any transmission or wireless standard, requiring only programming to do so, and is limited in RF application only by the operational bandwidth limitations imposed by the semiconductor process into which it is fabricated.
  • Figures 6 and 7 are flow charts representing steps of various embodiments of aspects of the present invention. Although the steps represented in these Figures are presented in a specific order, the technology presented herein can be performed in any variation of this order. Furthermore, additional steps may be executed between the steps illustrated in these Figures.
  • FIG. 6 is a flow chart representing steps of one embodiment method for developing an output signal.
  • a periodic time segment sequence having a plurality of ordered time segments is defined 50 by a timing system. Defining 50 the periodic time segment sequence includes selecting the number and sequence of the ordered time segments. The periodic time segment sequence is repeated 52. The repetition rate of the periodic time segment sequence is adjustable to generate the output signal at the desired frequency.
  • a plurality of sets of signal values are provided 58 to an output.
  • a digital value is converted 54 to analog to obtain the signal value.
  • the signal values of each set of signal values are generated by interpolating 56 between target values.
  • each signal value is represented by a charge on a capacitive device and the capacitive device interpolates 56 between the target values.
  • the signal values sequentially form a representation of a bandpass signal.
  • the bandpass signal is a modulated signal.
  • the modulated signal has a standard sinusoidal carrier.
  • the modulated signal includes a complex waveform carrier.
  • Each set of signal values is provided 58 to the output during a different ordered time segment than each other set.
  • Each signal value of a set is provided 58 to the output during a different repetition of the periodic time segment sequence.
  • the output signal is smoothed 60 by interpolating between steps in the output signal.
  • the output signal is provided 62 to a transmitter output stage for transmitting 64 the output signal. If the transmitter output stage has a non-linear performance, the complex waveform carrier advantageously contains pre-distortion to compensate for the non-linear performance.
  • Figure 7 illustrates one embodiment for the method of the present invention including a transmit mode.
  • the present invention is useful in both a receive mode and a transmit mode and may be selectively switched 66 between the modes.
  • a single digital signal processing system selectively switches 66 between the transmit and receive modes, supplying data to a transmitter to transmit, and obtaining data from a receiver.
  • a target modulated signal is received 68 and demodulated 70.
  • the output signal is fed back 72 for reference.
  • the fed back output signal is attenuated 74.
  • a desired output signal is compared 76 to the fed back, or attenuated, output signal.
  • the development of the output signal is regulated 78 with the comparison between the desired output signal and the fed back, or attenuated, output signal.
  • the present invention does not require any synchronous relationship between any of four potentially different clocking domains.
  • One domain is the input signal domain
  • the second domain is a sampling or signal acquisition domain
  • the third domain is a decimation domain
  • the fourth domain is a signal processing or DSP domain.
  • the first domain is the input signal domain and includes the circuits or signals, if any, that are synchronous, or are intended to become or remain synchronous with a target modulated signal.
  • the sampling or signal acquisition domain is a clock or timing domain where regular samples or value acquisitions occur, at a rate and for intervals controlled by a sampling or value acquisition clock or timing signal.
  • the decimation domain is characterized by circuits driven and responsive to a sequence clock timing circuit, wherein are defined two or more separately identified time segments, each being approximately constant in period or duration, and a regular sequence of these time segments, which counts sequentially through each of the time segments in a consistent order, and then repeats the sequence in order, with the first time segment immediately following the last time segment of the sequence.
  • a sequence clock timing circuit wherein are defined two or more separately identified time segments, each being approximately constant in period or duration, and a regular sequence of these time segments, which counts sequentially through each of the time segments in a consistent order, and then repeats the sequence in order, with the first time segment immediately following the last time segment of the sequence.
  • Any input signal sample or acquisition value acquired during any ordered time segment of the sequence is combined with any other signal sample or acquisition value acquired during the same ordered time segment. Whenever such values acquired and so combined are from separate repetitions of the same time segment, decimation thereby occurs. This combination and decimation happens throughout the duration of any one RF2Dout cycle, for however many repetitions of the time segment sequence occur during each RF2Dout cycle. Since these clocks are not necessarily synchronous, this can result in variable counts of time segment sequences for any given RF2Dout cycle. This tends to result in a time based quantization error. However, this error becomes less significant, as the average number of time segment sequence repetitions per RF2Dout cycle increases.
  • the fourth domain is the processing domain, and includes the circuits of a Digital Signal Processing block, (DSP block), wherein programmable sequential steps are executed, and where thereby data delivered to the DSP from the A to D block, can be operated upon mathematically, in any means desirable and programmable, to filter or extract various signal values and signal streams from the stream of signal data delivered to the DSP from the A to D.
  • DSP block Digital Signal Processing block
  • Asynchronicity between the first and second clock domains has been elaborately discussed, asynchronicity between the third and fourth domains is assumed, as this is typical for most DSP systems, as long as the DSP processes data fast enough, synchronicity is not usually a factor.
  • Asynchronicity between the second and third domains is potentially problematic, but as long as there are more than the minimum of four time segments in the periodic time segment sequence, the higher the number of time segments in the periodic time segment sequence, the less significant an error in values accumulated during any one periodic decimation time segment would be.
  • An asynchronicity between the sampling and decimation clock domains could only generate an error between the two domains which is less than or equal to twice the largest value accumulated during a single time segment. If there are many time segments, this will become increasingly small.

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Abstract

L'invention a pour objet de développer un signal de sortie. Une suite périodique de segments temporels comprenant des segments temporels multiples ordonnés est définie. La suite périodique de segments temporels est répétée. Une pluralité d'ensembles de valeurs de signal est transmise à une sortie, générant ainsi le signal de sortie. Chaque ensemble de valeurs de signal est transmis pendant un segment temporel ordonné différent de ceux de chacun des autres ensembles. Chaque valeur de signal d'un ensemble est transmise pendant une répétition différente de la suite périodique de segments temporels. Chaque ensemble de valeurs de signal, dans l'ordre, présente une dépendance statistique vis-à-vis d'au moins un autre ensemble de valeurs de signal, dans l'ordre.
PCT/US2013/064867 2012-10-12 2013-10-14 Génération de signaux basée sur une suite périodique de segments temporels WO2014059423A1 (fr)

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US13/651,259 US9490944B2 (en) 2012-10-12 2012-10-12 Phase sector based RF signal acquisition
US13/651,259 2012-10-12
US14/053,360 US9225368B2 (en) 2012-10-12 2013-10-14 Periodic time segment sequence based signal generation
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EP0208817B1 (fr) * 1985-07-17 1990-12-19 Pilkington A.E.P. Limited Système de communication
EP0757446A2 (fr) * 1995-08-04 1997-02-05 Nokia Mobile Phones Ltd. Convertisseur analogiques-numériques et numériques-analogiques
US6341216B1 (en) * 1995-12-18 2002-01-22 Matsushita Electric Industrial Co., Ltd. Transmitter-receiver circuit for radio communication and semiconductor integrated circuit device
US6397048B1 (en) * 1998-07-21 2002-05-28 Sharp Kabushiki Kaisha Signal processing apparatus and communication apparatus
US20030093278A1 (en) * 2001-10-04 2003-05-15 David Malah Method of bandwidth extension for narrow-band speech
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EP0208817B1 (fr) * 1985-07-17 1990-12-19 Pilkington A.E.P. Limited Système de communication
EP0757446A2 (fr) * 1995-08-04 1997-02-05 Nokia Mobile Phones Ltd. Convertisseur analogiques-numériques et numériques-analogiques
US6341216B1 (en) * 1995-12-18 2002-01-22 Matsushita Electric Industrial Co., Ltd. Transmitter-receiver circuit for radio communication and semiconductor integrated circuit device
US6397048B1 (en) * 1998-07-21 2002-05-28 Sharp Kabushiki Kaisha Signal processing apparatus and communication apparatus
US20030093278A1 (en) * 2001-10-04 2003-05-15 David Malah Method of bandwidth extension for narrow-band speech
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