WO2014057546A1 - Circuit de détection à impacts multiples, dispositif de traitement et procédé de détection à impacts multiples - Google Patents

Circuit de détection à impacts multiples, dispositif de traitement et procédé de détection à impacts multiples Download PDF

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Publication number
WO2014057546A1
WO2014057546A1 PCT/JP2012/076240 JP2012076240W WO2014057546A1 WO 2014057546 A1 WO2014057546 A1 WO 2014057546A1 JP 2012076240 W JP2012076240 W JP 2012076240W WO 2014057546 A1 WO2014057546 A1 WO 2014057546A1
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Prior art keywords
circuit
common node
hit detection
hit
detection circuit
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PCT/JP2012/076240
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English (en)
Japanese (ja)
Inventor
任 佐野
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富士通株式会社
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Priority to PCT/JP2012/076240 priority Critical patent/WO2014057546A1/fr
Publication of WO2014057546A1 publication Critical patent/WO2014057546A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Definitions

  • the present invention relates to a multi-hit detection circuit, a processing device, and a multi-hit detection method.
  • the computer has a storage device such as a processor (processing unit), a memory (main memory), and a disk device.
  • the processor generally accesses the storage device based on the virtual address
  • the address conversion unit generally accesses the storage device by converting the virtual address into a physical address.
  • the performance of the storage device is lower (slower) than the performance of the processing unit, and the performance difference between the processing unit and the storage device has become a bottleneck with respect to the overall performance.
  • a cache memory hereinafter simply referred to as a cache
  • the processor accesses the cache based on the virtual address, and the address conversion unit provided in the cache converts the virtual address into the physical address of the cache.
  • the cache and the main memory determine whether or not the data corresponding to the virtual address accessed by the processor is held, and if it is held, the data of the accessed address is searched and the access operation from the processor Execute.
  • the corresponding data is transferred from the lower storage device to the inside and held in blocks.
  • the case where the data of the address accessed by the processor is held is called “hit”, and the case where the data is not held is called “miss hit”.
  • the storage area is divided into a plurality of entries, and the upper bits (frame address) of the address are associated with each entry, and the frame address is searched first.
  • the frame address storage buffer is a tag.
  • association level a data storage structure having a plurality of tags
  • set associative method a data storage structure having a plurality of tags
  • CAM has a circuit that functions as a cache in a memory management unit, usually called a translation lookaside buffer (TLB).
  • TLB translation lookaside buffer
  • the TLB uses the virtual address as a search key. If there is an entry corresponding to the address on the TLB, the TLB returns a corresponding physical address as a search result. This is a TLB hit. If there is no entry corresponding to the address, it is a TLB miss.
  • the TLB has a plurality of address comparison circuits that respectively detect a match between an access address and a plurality of tags (entries). Since the plurality of tags correspond to different frame addresses, in the case of a TLB hit, one output of the plurality of address comparison circuits is matched (hit), and the other outputs are mismatched (miss). In the case of a TLB miss, all the outputs of the plurality of address comparison circuits do not match.
  • the output of two or more address comparison circuits is a hit, that is, a hit occurs in a plurality of entries, due to something such as a failure. This is called multi-hit.
  • the multi-hit detection circuit is a circuit in which the output becomes true when two or more bits out of all input bits are hit, that is, one of the logical values (eg, “1”). Used for places.
  • FIG. 1 is a diagram showing an example of a 4-bit multi-hit detection circuit formed by logic gates and realized in the form of a static circuit.
  • FIG. 2 is a truth table of the output X for the input signals A0, A1, A2 and A3 of the multi-hit detection circuit of FIG.
  • the multi-hit detection circuit in FIG. 1 implements a gate circuit that executes this logical expression with three AND gates and four OR gates.
  • FIG. 3 is a diagram showing an example of a 4-bit multi-hit detection circuit realized in the form of a dynamic circuit that operates in synchronization with the clock CLK.
  • the truth table of the operation is as shown in FIG.
  • the multi-hit detection circuit in FIG. 3 is a dynamic circuit to which a clock-synchronized input signal CLK is added, and realizes a circuit that executes this logical expression.
  • the digital multi-hit detection circuit shown in FIG. 1 and FIG. 3 is a relatively small circuit as shown if the input signal is about 4 bits. However, as the number of bits of the input signal increases, the circuit naturally becomes more complex, and the number of logic gate stages that pass through until reaching the output increases.
  • FIG. 4 is a diagram showing an example of an 8-bit multi-hit detection circuit, which is a circuit realized in the form of a static circuit by a logic gate as in FIG.
  • FIG. 5 is a diagram showing an example of an 8-bit multi-hit detection circuit, which is a circuit realized in the form of a dynamic circuit as in FIG.
  • the number of bits of the input signal is changed from 4 bits to 8 bits, so that the number of logic gate stages is not changed.
  • the number of F / Os (fanouts) you see increases.
  • the maximum number of F / Os increases from 3 to 7.
  • the number of transistors used is about 2.8 times.
  • the potential level of the detection line is changed in accordance with the number of inputs “1” among a plurality of input signals, and is compared with the reference potential to detect whether the number of input signals “1” is 2 or more.
  • An analog type multi-hit detection circuit has been proposed.
  • the multi-hit detection circuit includes a first voltage generation circuit, a second voltage generation circuit, and a comparison circuit.
  • the first voltage generation circuit generates a detection voltage by changing the level of the potential of the detection line in accordance with the number of inputs “1” among the plurality of input signals.
  • the comparison circuit compares the detection voltage with the reference voltage, and outputs a multi-hit signal when the number of inputs “1” is K or more.
  • the delay time also increases due to the increase in the number of logic gate stages in the static circuit and the increase in the F / O number in the dynamic circuit.
  • the multi-hit detection circuit is mainly used in the TLB to detect that a tag and a virtual address simultaneously match in a plurality of entries. That is, the number of TLB entries is the number of input bits of the multi-hit detection circuit. Since the TLB greatly affects the performance of the processor, it is desirable that the TLB has a high speed and a large capacity (a large number of entries). However, in the above-described multi-hit detection circuit, as the number of input bits increases as described above, the area and delay time also increase significantly. For this reason, it has been difficult to increase the capacity of the TLB.
  • the analog multi-hit detection circuit includes a second voltage generation circuit that generates a reference voltage and a comparison circuit that includes a sense amplifier circuit that amplifies the comparison result. Since the second voltage generation circuit has exactly the same configuration as the first voltage generation circuit, the scale of the second voltage generation circuit increases with the increase in the number of bits targeted for multi-hit detection, and the scale of the entire circuit. Becomes larger. Furthermore, when manufacturing variation is taken into account, the second voltage generation circuit and the first voltage generation circuit may have different variations. Further, since a slight potential difference is detected and amplified by the sense amplifier circuit, even if the voltage fluctuates slightly due to manufacturing variations, there is a possibility that it may lead to operation failure.
  • a multi-bit multi-hit detection circuit that operates at a higher speed and is formed with a smaller number of transistors is realized.
  • the multi-hit detection circuit includes a plurality of first polarity transistors, an inverter circuit, and an adjustment circuit.
  • the plurality of first polarity transistors have a source connected to the first potential source, a drain connected to the common node, and a plurality of input signals applied to the gates.
  • the inverter circuit has a common node as an input.
  • the adjustment circuit is connected to a common node, and the output of the inverter circuit is different when one of the plurality of first polarity transistors is on and when two or more of the plurality of first polarity transistors are on. Thus, the potential of the common node is set.
  • the processing device includes an address conversion unit that converts a virtual address into a physical address, and accesses the memory using the virtual address.
  • the address conversion unit includes a plurality of address comparison circuits that output a plurality of determination signals indicating a determination result indicating whether the virtual address corresponds to a plurality of tags included in the table, and two or more of the plurality of determination signals.
  • a multi-hit circuit that determines whether the determination signal indicates that it corresponds.
  • the multi-hit detection circuit includes a plurality of first polarity transistors, an inverter circuit, and an adjustment circuit.
  • the plurality of first polarity transistors have a source connected to the first potential source, a drain connected to the common node, and a plurality of input signals applied to the gates.
  • the inverter circuit has a common node as an input.
  • the adjustment circuit is connected to a common node, and the output of the inverter circuit is different when one of the plurality of first polarity transistors is on and when two or more of the plurality of first polarity transistors are on. Thus, the potential of the common node is set.
  • the multi-hit determination method determines whether two or more signals have one logical value among a plurality of signals.
  • a plurality of first polarity transistors are connected in parallel between the first potential source and the common node, an adjustment circuit is connected to the common node, and an inverter circuit is connected using the common node as an input.
  • the adjustment circuit is adjusted so that the output of the inverter circuit is different when one of the plurality of first polarity transistors is on and when two or more of the plurality of first polarity transistors are on.
  • the potential of the common node is set.
  • a plurality of signals are applied to the gates of the plurality of first polarity transistors, and it is detected from the output of the inverter circuit whether or not two or more signals among the plurality of signals have one logical value.
  • FIG. 1 is a diagram showing an example of a 4-bit multi-hit detection circuit formed by logic gates and realized in the form of a static circuit.
  • FIG. 2 is a truth table of the output X for the input signals A0, A1, A2, and A3 of the multi-hit detection circuit of FIG.
  • FIG. 3 is a diagram showing an example of a 4-bit multi-hit detection circuit realized in the form of a dynamic circuit that operates in synchronization with the clock CLK.
  • FIG. 4 is a diagram showing an example of an 8-bit multi-hit detection circuit, which is a circuit realized by a logic gate in the form of a static circuit.
  • FIG. 5 is a diagram showing an example of an 8-bit multi-hit detection circuit, which is a circuit realized in the form of a dynamic circuit.
  • FIG. 6A and 6B are diagrams showing the configuration of the multi-hit detection circuit according to the first embodiment.
  • FIG. 6A shows a circuit with a 4-bit input signal number
  • FIG. 6B shows a circuit with an 8-bit input signal number.
  • . 7 shows the relationship between the number of bits of the input signal and the number of transistors in the multi-hit detection circuit of the first embodiment shown in FIG. 6, the static circuit shown in FIGS. 1 and 4, and FIGS. It is the figure shown about the shown dynamic type circuit.
  • FIG. 8 shows the relationship between the number of bits of the input signal and the number of logic gate passage stages, the multi-hit detection circuit of the first embodiment shown in FIG. 6, the static circuit shown in FIGS. 1 and 4, and FIGS.
  • FIG. 8 shows the relationship between the number of bits of the input signal and the number of logic gate passage stages, the multi-hit detection circuit of the first embodiment shown in FIG. 6, the static circuit shown in FIGS. 1 and 4, and FIGS.
  • FIG. 8 shows the relationship between the number of bits
  • FIG. 6 is a diagram showing a dynamic circuit shown in FIG. 9 shows the relationship between the number of bits of the input signal and the maximum number of F / Os, the multi-hit detection circuit of the first embodiment shown in FIG. 6, the static circuit shown in FIGS.
  • FIG. 6 is a diagram showing the dynamic circuit shown in FIG. 5.
  • FIG. 10 is a diagram illustrating a configuration of a 4-bit multi-hit detection circuit according to the second embodiment.
  • FIG. 11 is a diagram showing a truth table showing the relationship of the output signal X of the 4-bit multi-hit detection circuit with respect to the input signals A0-A3.
  • 12A and 12B are diagrams showing a modification of the adjustment circuit.
  • FIG. 12A shows an example when the enable signal EN is not applied, and FIG.
  • FIG. 12B shows an example when the enable signal EN is applied.
  • FIG. 13 is a diagram illustrating a configuration of a 4-bit multi-hit detection circuit according to the third embodiment.
  • FIG. 14 is a flowchart showing the setting operation of the fuse ROM in the 4-bit multi-hit detection circuit of the third embodiment.
  • FIG. 15 is a diagram illustrating a configuration of an 8-bit multi-hit detection circuit according to the fourth embodiment.
  • FIG. 16 is a diagram showing a truth table showing the relationship of the output signal X of the 8-bit multi-hit detection circuit with respect to the input signals A0-A7.
  • FIG. 17 is a diagram illustrating a configuration of an 8-bit multi-hit detection circuit according to the fifth embodiment.
  • FIG. 18 is a flowchart showing the setting operation of the fuse circuit of the 8-bit multi-hit detection circuit of the fifth embodiment.
  • FIG. 19 is a diagram illustrating a configuration example of a processing device.
  • FIG. 20 is a diagram for explaining the conversion of a virtual address into a physical address by the address conversion unit.
  • FIG. 21 is a diagram for explaining processing in TLB.
  • FIG. 22 is a diagram showing an address comparison circuit and a multi-hit detection circuit in the TLB, where (A) shows an address comparison circuit and (B) shows a multi-hit detection circuit.
  • FIG. 6A and 6B are diagrams showing the configuration of the multi-hit detection circuit according to the first embodiment.
  • FIG. 6A shows a circuit with a 4-bit input signal number
  • FIG. 6B shows a circuit with an 8-bit input signal number.
  • the output signal X 0 (low) when the number of signals that are 1 (high (H)) among the input signals A0 to A3 is zero or 1 (L))
  • the 4-bit multi-hit detection circuit includes four Nch transistors N0 to N3 connected in parallel between the common node 11 and the first potential source (VSS), and an adjustment connected to the common node 11.
  • a circuit 10 and an inverter circuit having the common node 11 as an input are included.
  • Input signals A0-A3 are applied to the gates of Nch transistors N0-N3.
  • the Nch transistors N0 to N3 are manufactured so that the on-resistance when the input signal is turned on at 1 is substantially equal. This is realized by arranging Nch transistors N0 to N3 adjacent to each other and manufacturing them by the same process.
  • the inverter circuit has an Nch transistor N4 and a Pch transistor P4 connected in series between VSS and the second potential source (VDD), and the gates of N4 and P4 are connected to the common node 11.
  • the inverter circuit outputs the output signal X of the multi-hit detection circuit from the connection node of N4 and P4.
  • the adjustment circuit 10 When the number of signals that are 1 among the input signals A0-A3 is zero or 1, the adjustment circuit 10 outputs 0 when the number of signals that are 1 among A0-A3 is 2 or more.
  • the potential of the common node 11 is set so that the output of the inverter circuit becomes 1. Specifically, in the case where the number of signals that are 1 among A0-A3 is one and two, the potential of the common node 11 is positioned above and below the threshold Vth of the inverter circuit, that is, Vth is set to Set to straddle. More specifically, when the number of signals that are 1 among A0 to A3 is 1, the potential of the common node 11 is higher than the threshold Vth of P4 and the number of signals that is 1 is 2 when the potential of the common node 11 is 2.
  • the potential is set to be lower than the threshold value Vth of P4.
  • an 8-bit multi-hit detection circuit according to the first embodiment shown in FIG. 6B will be described.
  • the multi-hit detection circuit of the first embodiment includes four Nch transistors N10-N17 connected in parallel between the common node 11 and the first potential source (VSS), and an adjustment circuit 10 connected to the common node 11. And an inverter circuit having the common node 11 as an input. Input signals A0-A7 are applied to the gates of Nch transistors N10-N17.
  • the Nch transistors N10 to N17 are manufactured so that the on-resistance when the input signal is turned on at 1 is substantially equal.
  • the inverter circuit has an Nch transistor N4 and a Pch transistor P4 connected in series between VSS and the second potential source (VDD), and the gates of N4 and P4 are connected to the common node 11.
  • the inverter circuit outputs the output signal X of the multi-hit detection circuit from the connection node of N4 and P4.
  • the adjustment circuit 10 When the number of signals that are 1 among the input signals A0 to A7 is zero or 1, the adjustment circuit 10 outputs 0 when the output of the inverter circuit is 0 and the number of signals that is 1 among A0 to A7 is 2 or more.
  • the potential of the common node 11 is set so that the output of the inverter circuit becomes 1.
  • the voltage of the common node 11 is positioned above and below the threshold value Vth of the inverter circuit, in other words, Vth, when the number of signals that are one of A0 to A7 is one and two. Set to cross.
  • the output of the inverter circuit becomes 0, and when the number of signals that are 1 among the input signals A0 to A7 is 2 or more.
  • the output of the inverter circuit becomes 1, and functions as a multi-hit detection circuit.
  • the adjustment circuit 10 sets the potential of the common node 11. Therefore, even if there is a manufacturing variation, the output signal X becomes “0” when the number of signals that are 1 among the input signals is 1 or less, and becomes “1” when the number of signals that are 1 is 2 or more. Therefore, it operates as a multi-hit detection circuit.
  • the 8-bit multi-hit detection circuit of the first embodiment shown in FIG. 6B uses fewer transistors and the number of pass gate stages. Remains two stages. It can also be seen that the maximum number of F / Os of the input signals A0-A7 remains 1 and does not change. For this reason, the 8-bit multi-hit detection circuit of the first embodiment is a smaller and faster circuit than the circuits of FIGS.
  • FIG. 7 shows the relationship between the number of bits of the input signal and the number of transistors in the multi-hit detection circuit of the first embodiment shown in FIG. 6, the static circuit shown in FIGS. 1 and 4, and FIGS. It is the figure shown about the shown dynamic type circuit.
  • A is the case of the multi-hit detection circuit of the first embodiment
  • B is the case of the static type circuit shown in FIGS. 1 and 4
  • C is the case of the dynamic type circuit shown in FIGS. Show the case.
  • FIG. 8 shows the relationship between the number of bits of the input signal and the number of logic gate passage stages, the multi-hit detection circuit of the first embodiment shown in FIG. 6, the static circuit shown in FIGS. 1 and 4, and FIGS.
  • FIG. 6 is a diagram showing a dynamic circuit shown in FIG. 8, A is the case of the multi-hit detection circuit of the first embodiment, B is the case of the static type circuit shown in FIGS. 1 and 4, and C is the case of the dynamic type circuit shown in FIGS. Show the case.
  • FIG. 9 shows the relationship between the number of bits of the input signal and the maximum number of F / Os, the multi-hit detection circuit of the first embodiment shown in FIG. 6, the static circuit shown in FIGS.
  • FIG. 6 is a diagram showing the dynamic circuit shown in FIG. 5.
  • A is the case of the multi-hit detection circuit of the first embodiment
  • B is the case of the static type circuit shown in FIGS. 1 and 4
  • C is the case of the dynamic type circuit shown in FIGS. Show the case.
  • the increase in circuit scale is relatively small even when the number of bits of the input signal increases, and the number of passing gate stages and the maximum number of F / Os Does not increase.
  • FIG. 10 is a diagram illustrating a configuration of a 4-bit multi-hit detection circuit according to the second embodiment.
  • the 4-bit multi-hit detection circuit of the second embodiment is connected between the second potential source (VDD) and the common node 11 in the 4-bit multi-hit detection circuit of the first embodiment shown in FIG.
  • the adjustment circuit 10 is realized by the Pch transistor P0.
  • the enable signal EN is applied to the gate of P0, and the adjustment circuit 10 and the 4-bit multi-hit detection circuit are activated only when EN is “0” (L). In the non-operating state, by setting EN to “1” (H), a through current can be prevented.
  • the gate of P0 may be connected to VSS or the like so that a signal of “0” (L) is always applied to enter an operating state.
  • the potential of the common node 11 is always set to VDD during operation. When any of the input signals A0-A3 becomes 1, the potential of the common node 11 is higher than Vth of P4 of the inverter circuit at the next stage, and any two or more of A0-A3 become 1.
  • the ON resistance of P0 is set so as to be lower than Vth of P1 at the time.
  • the four Nch transistors N0 to N3 all have the same on-resistance.
  • Vth of P4 of the inverter circuit is VDD / 2
  • the on-resistance of P0 of the adjustment circuit 10 is 1
  • each of the on-resistances of N0-N3 is The ratio is larger than 1 and smaller than 2.
  • the ratio of the on-resistance of the adjusting circuit 10 and the Nch transistors N0 to N3 is specifically preferably about 1 to 1.5. If the ratio is 1: 1, the potential of the common node 11 is sufficiently lower than Vth when two or more of N0-N3 are on, but when only one of N0-N3 is on, Since the potential of the common node 11 is almost equal to Vth, X becomes indefinite. On the other hand, at the ratio of 1 to 2, the potential of the common node 11 is sufficiently higher than Vth when one of N0-N3 is on, but is common when two of N0-N3 are on. Since the potential of the node 11 is substantially equal to Vth, X also becomes unstable. From the above, it is desirable that the ratio of 1: 1.5, which is intermediate between 1: 1 and 1: 2, is such that X does not become indefinite and a function operation as expected can be expected.
  • FIG. 11 is a diagram showing a truth table showing the relationship of the output signal X of the 4-bit multi-hit detection circuit with respect to the input signals A0-A3.
  • the on-resistance ratio has the most influence when the output signal X is 0 when any one of the input signals A0-A3 that is the input of the hit signal is 1, and when any two of the A0-A3 are 1.
  • the output signal X is 1 condition.
  • the truth table in FIG. 11 shows this condition. Therefore, it can be said that the operation can be performed without any problem if the truth table of FIG. 11 can be satisfied.
  • the only requirement for the normal operation of the circuit is the Vth of the transistor. This can be determined by the ON resistance of P 0 included in the adjustment circuit 10.
  • the on-resistance of the Pch transistor P0 of the adjusting circuit 10 need not be adjusted when the above condition is satisfied by the control of the manufacturing process.
  • the driving capability that is, the on-resistance of P0 using a trimming circuit or the like.
  • the on-resistance of the Pch transistor P0 of the adjustment circuit 10 may be adjusted by a method other than trimming.
  • FIG. 12A and 12B are diagrams showing a modification of the adjustment circuit 10, where FIG. 12A shows an example when the enable signal EN is not applied, and FIG. 12B shows an example when the enable signal EN is applied.
  • the adjustment circuit 10 includes the N + 1 Pch transistors P10-P1N connected in parallel between the second potential source (VDD) and the common node 11, and in parallel between VDD and VSS.
  • N + 1 setting units connected to each other.
  • Each of the N + 1 setting units includes a set of resistors R10-R1N and fuses F10-F1N connected in series between VDD and VSS. The connection node between the resistor and the fuse of each setting unit is connected to the gate of the corresponding Pch transistor P10-P1N.
  • the fuse F10-F1N When the fuse F10-F1N is not cut, “0” (L: VSS) is applied to the gates of the Pch transistors P10-P1N. Therefore, all the Pch transistors P10-P1N are in the on state, and the on resistance of the adjustment circuit 10 is a composite value of the on resistances of the Pch transistors P10-P1N connected in parallel.
  • “1” L: VDD
  • the on-resistance of the adjustment circuit 10 is a composite value of the on-resistance of the Pch transistor connected to the uncut fuse. In other words, it is possible to select the Pch transistor to be turned on depending on whether the fuse is cut or not, and to adjust the on-resistance of the adjustment circuit 10.
  • the on-resistances of the Pch transistors P10-P1N may be all the same or different.
  • the on-resistances of the Pch transistors P10 to P1N may be set so as to differ by a power of 2 such as 1: 2: 4.
  • the modification of FIG. 12B is provided with a plurality of OR gates OR10-OR1N that receive the signal of the connection node of the resistor and the fuse and the enable signal EN, and the modification of FIG. Different.
  • the output of OR10-OR1N is applied to the gate of the corresponding Pch transistor P10-P1N.
  • the on-resistance of the adjustment circuit 10 can be adjusted in the same way as the modification of FIG. 12A, and the Pch transistors P10 to P1N are turned off by the enable signal EN. Can be.
  • FIG. 13 is a diagram illustrating a configuration of a 4-bit multi-hit detection circuit according to the third embodiment.
  • the ratio of the resistance between VDD and the common node formed by the adjustment circuit 10 and the ON resistance of the Nch transistors N0 to N3 is within a predetermined range. Is required. However, this ratio may fluctuate due to manufacturing variations and may not fit within a predetermined range, resulting in malfunctions.
  • the on-resistance exhibited by the adjustment circuit 10 is set by a method different from that of the second embodiment and the modification shown in FIG.
  • the 4-bit multi-hit detection circuit of the third embodiment is the same as that of the 4-bit multi-hit detection circuit of the first embodiment shown in FIG. 6A, with three Pch transistors P20 to P21 and one Nch transistor N20. Thus, the adjustment circuit 10 is realized.
  • the control terminal SL0 of the adjustment circuit 10 is connected to the output of the fuse ROM 20.
  • the adjustment circuit 10 includes two Pch transistors P20 and P21 connected between the second potential source (VDD) and the common node 11. Further, the adjustment circuit 10 includes a Pch transistor P22 and an Nch transistor N22 connected in series between the second potential source (VDD) and the first potential source (VSS).
  • the output of the fuse ROM 20 is applied to the gates of P20, P22 and N22.
  • the signal at the connection node of P22 and N22 is applied to the gate of P21. Since P22 and N22 operate as an inverter, a signal obtained by inverting the output of the fuse ROM 20 is applied to the gate of P21.
  • P20 and P21 are connected in parallel between VDD and the common node 11, and when one is on, the other is off according to the output of the fuse ROM 20. Specifically, if the output of the fuse ROM 20 is “0” (L), P20 is turned on, P21 is turned off, and if the output of the fuse ROM 20 is “1” (H), P21 is turned on. And P20 is turned off.
  • P20 is turned on (P21 is turned off), and the circuit operates normally under the condition that the manufacturing process variation is slow (SLOW). Design to do.
  • P21 is turned on (P20 is turned off), and the circuit is designed so that the circuit operates normally under the condition that the manufacturing process variation is fast.
  • transistors other than P20 and P21 are designed without changing the transistor parameters between the SLOW condition and the Fast condition. Note that the on-resistance of the transistor differs between the SLOW condition and the Fast condition.
  • FIG. 14 is a flowchart showing the setting operation of the fuse ROM 20 in the 4-bit multi-hit detection circuit of the third embodiment.
  • the flowchart of FIG. 14 also shows the setting operation of the 4-bit multi-hit detection circuit of the fourth embodiment to be described later in addition to the third embodiment, and some steps are deleted in the third embodiment.
  • the setting (adjustment) on the actual machine is performed by inputting a specific circuit verification pattern and checking whether the result matches the expected value.
  • the on-resistance ratio has the greatest influence when the output signal X is 0 when any one of the input signals A0 to A3 that are the inputs of the hit signal is 1, and any two of A0 to A3.
  • the output signal X is 1 when one is 1. Therefore, it can be said that the operation can be performed without any problem if the truth table of FIG. 11 can be satisfied.
  • step S10 the 4-bit multi-hit detection circuit of the third embodiment to be processed with the fuse ROM 20 set to the initial value is set. If the initial value of the fuse ROM 20 is 0, P20 is on and P21 is off.
  • step S11 all the verification patterns in the truth table of FIG. 11 are input, and the result is read out by a scan circuit or the like.
  • step S12 the read result is compared with the expected value. If it matches the expected value, the process proceeds to step S17 and ends. If not, the process proceeds to step S13.
  • step S13 the fuse ROM 20 is blown and the output of the fuse ROM 20 is changed.
  • step S14 all verification patterns in the truth table of FIG. 11 are input, and the results are read out by a scan circuit or the like.
  • step S15 the read result is compared with the expected value. If it matches the expected value, the process proceeds to step S17 and ends. If not, the process proceeds to step S18, and the 4-bit multi-hit detection circuit to be processed operates normally. It is determined that the defective chip cannot be adjusted. Thus, step S16 is omitted in the setting operation of the 4-bit multi-hit detection circuit of the third embodiment.
  • the above setting process optimizes the actual machine and realizes tolerance against manufacturing variations.
  • FIG. 15 is a diagram illustrating a configuration of an 8-bit multi-hit detection circuit according to the fourth embodiment.
  • the above-described conditions are required.
  • the adjustment range of the on-resistance exhibited by the adjustment circuit 10 is expanded, and an adjustment circuit different from the adjustment circuit described so far is used.
  • the 8-bit multi-hit detection circuit according to the fourth embodiment is similar to the 8-bit multi-hit detection circuit according to the first embodiment shown in FIG. 6B, with six Pch transistors P30 to P35 and three inverters Inv30- An adjustment circuit is realized by Inv32.
  • Control terminals SL0-SL2 of the adjusting circuit 10 are connected from the F0 fuse ROM 30 to the output of the F2 fuse ROM 32.
  • the output of the F0 fuse ROM 30 is represented by F0
  • the output of the F1 fuse ROM 31 is represented by F1
  • the output of the F2 fuse ROM 32 is represented by F2.
  • the drains of P30 and P31 are connected to the common node 11, and P34 is connected between the sources of P30 and P31 and VDD.
  • the drains of P32 and P33 are connected to the common node 11, and P35 is connected between the sources of P32 and P33 and VDD.
  • F2 is connected to the gate of P30 and the inverter Inv30. Since the output of Inv30 is connected to the gate of P31, the inverted signal of F2 is applied to the gate of P31.
  • F1 is connected to the gate of P34 and the inverter Inv31. Since the Inv301 output is connected to the gate of P35, the inverted signal of F1 is applied to the gate of P35.
  • F0 is connected to the gate of P32 and the inverter Inv32. Since the output of Inv32 is connected to the gate of P33, the inverted signal of F0 is applied to the gate of P33.
  • the four Pch transistors from P30 to P33 are designed to have different on-resistances and vary in the same direction after manufacture, so that P30 to P33 have different on-resistances.
  • P34 and P35 are designed and manufactured to have the same on-resistance. Therefore, as described above, by setting the values of F0 to F3, the resistance value between the common node 11 and VDD is set to one of four types of values. As a result, the ratio between the resistance value between the common node 11 and VDD and the on-resistance of N10 to N17 connected between the common node 11 and VSS can be set to any of four values, resulting in manufacturing variations. It can correspond to.
  • FIG. 16 is a diagram showing a truth table showing the relationship of the output signal X of the 8-bit multi-hit detection circuit with respect to the input signals A0-A7.
  • the ratio of the on-resistance has the greatest effect when the output signal X is 0 when any of the input signals A0 to A7 that are hit signal inputs is 1, and any two of A0 to A7.
  • the output signal X is 1 when one is 1.
  • the truth table in FIG. 16 shows this condition. Therefore, if the truth table of FIG. 16 can be satisfied, it can be said that the 8-bit multi-hit detection circuit operates without any problem.
  • the setting operation of the three fuse ROMs 30-32 is performed according to the flowchart shown in FIG.
  • the number of fuse ROMs is three, and the setting of the three fuse ROMs 30-32 is different from the case of the third embodiment.
  • steps S10 to S12 all the verification patterns in the truth table of FIG. 16 are input with the initial values of the three fuse ROMs, and the result is read by a scan circuit or the like to determine whether or not the expected values match. finish. If they do not match, the F2 fuse ROM 32 is cut in step S13, and steps S14 and S15 are performed. If they do not match, the process ends. Thereafter, by repeating S13 to S16, it is determined whether or not the four types of ratios match the expected values. If they match, the process ends.
  • the above processing is the same even if the number of bits of the input bedding and the number of fuse ROMs are increased, and the adjustment range of the adjustment circuit 10 is expanded to optimize the actual machine.
  • FIG. 17 is a diagram illustrating a configuration of an 8-bit multi-hit detection circuit according to the fifth embodiment.
  • the 8-bit multi-hit detection circuit of the fifth embodiment is a circuit in which the adjustment width of the adjustment circuit 10 is further expanded from that of the fourth embodiment.
  • the 8-bit multi-hit detection circuit according to the fifth embodiment is the same as the 8-bit multi-hit detection circuit shown in FIG. 6B, in which the adjustment circuit 10 can be arbitrarily set to an on state. This is formed by transistors P40 to P43.
  • the 8-bit multi-hit detection circuit of the fifth embodiment includes a fuse circuit 40 for arbitrarily setting P40 to P43 of the adjustment circuit 10 to an on state.
  • the fuse circuit 40 is controlled by a scan latch circuit 50 provided inside or outside the multi-hit detection circuit.
  • the four Pch transistors P40 to P43 of the adjustment circuit 10 are connected in parallel between the four terminals of the fuse circuit 40 that outputs the signals SL0 to SL3 and the common node 11, and have different on-resistances.
  • the on-resistance of P40 to P43 is set to, for example, 1: 2: 4: 8.
  • the fuse circuit 40 outputs “0” or “1” to the four terminals according to the signal from the scan latch circuit 50 and sets “0” or “1” to the four terminals by setting internal fuses. 1 "is output. After the internal fuse is set, the terminal output is not changed. Therefore, until the internal fuse is set, the outputs from the four terminals can be arbitrarily set by the signal from the scan latch circuit 50.
  • P40-P43 there are 16 combinations of outputs from the four terminals, and if the on-resistance of P40-P43 is 1: 2: 4: 8 as described above, it can be set to 15 on-resistances. This is to exclude this case because all of P40 to P43 are not operated as a multi-hit detection circuit when they are in the OFF state.
  • FIG. 18 is a flowchart showing the setting operation of the fuse circuit 40 of the 8-bit multi-hit detection circuit of the fifth embodiment.
  • step S20 the output of the fuse circuit 40 is set to an initial value from the scan latch circuit 50. For example, when “0000” is set from the scan latch circuit 50 to the fuse circuit 40, the outputs SL0 to SL3 of the fuse circuit 40 are all “0” and all of P0 to P3 are turned on.
  • step S21 all verification patterns in the truth table of FIG. 16 are input, and the results are read out by a scan circuit or the like.
  • step S22 the read result is compared with the expected value. If the result matches the expected value, the process proceeds to step S27, and if not, the process proceeds to step S23.
  • step S23 the output of the fuse circuit 40 is incremented by 1 (+1) by the signal from the scan latch circuit 50 and set to “0001”. As a result, P0 is turned off and P1-P3 are turned on.
  • step S24 all the verification patterns in the truth table of FIG. 16 are input, and the result is read by a scan circuit or the like.
  • step S25 the read result is compared with the expected value, and if it matches the expected value, the process proceeds to step S27, and if not, the process proceeds to step S26.
  • step S26 it is determined whether all combinations of the outputs SL0 to SL3 of the fuse circuit 40 have been determined (trials have been performed). If there are remaining combinations, the process returns to step S23, and the trials have been completed for all combinations. If so, the process proceeds to step S28.
  • step S27 the number of P40 to P43 that are turned on is changed, and the on-resistance between the common node 11 and VDD changes accordingly.
  • step S27 the fuse of the fuse circuit 40 is set so that the outputs SL0-SL3 of the fuse circuit 40 at that time are obtained, and the process proceeds to step S29 and ends.
  • step S28 If even if steps S23 to S26 are repeated and all the verification patterns in the truth table of FIG. 16 do not match the expected values, the process proceeds to step S28, and the 8-bit multi-hit detection circuit to be processed operates normally. It is determined that the defective chip cannot be adjusted.
  • step S27 when all the verification patterns in the truth table of FIG. 16 match the expected values, and all combinations of the outputs SL0 to SL3 of the fuse circuit 40 are performed. You may make it determine about. Then, the fuse of the fuse circuit 40 may be set so as to obtain an on-resistance corresponding to the center of the range that matches the expected value for all verification patterns in the truth table of FIG.
  • the adjustment range of the adjustment circuit 10 is further expanded, the tolerance to manufacturing variations is further improved.
  • the multi-hit detection circuits of the first to fifth embodiments have the following advantages. (1) A dramatic increase in circuit scale due to an increase in the number of bits of the input signal can be prevented. (2) The number of logic input stages and the number of fan-outs (FANOUT) of input pins can be suppressed, which is suitable for speeding up. (3) Occurrence of malfunction due to manufacturing variations can be suppressed. With these effects, it is easy to increase the capacity of the TLB mechanism, which has been difficult until now, and the CPU performance is improved.
  • FIG. 19 is a diagram illustrating a configuration example of a processing apparatus.
  • 19 includes a processor (processing unit) 51, a cache 52, a main memory (memory) 53, I / O ports 54 and 55, disk devices 56A and 56B, and a bus 57.
  • the processor 51 accesses programs and data stored in the cache 52.
  • the cache 52 inputs / outputs programs and data accessed by the processor 51 to / from the main storage 53 via the bus 57 and to / from the disk devices 56A and 56B via the bus 57 and the I / O port 54.
  • the cache 52 inputs and outputs data between communication paths and the like via the I / O port 55 as necessary.
  • the processor 51 may input / output data to / from the main memory 53, the disk devices 56A and 56B, and the communication path without going through the cache 52. Further, the main memory 53 may input / output data to / from the disk devices 56A and 56B and the communication path by the DMA mechanism.
  • the processor 51 accesses a storage device based on a virtual address
  • the address conversion unit generally converts the virtual address into a physical address and accesses the storage device.
  • the performance of the storage devices such as the main storage 53 and the disk devices 56A and 56B is lower (slower) than the performance of the processor 51, and the performance difference between the processor 51 and the storage device has become a bottleneck with respect to the overall performance.
  • the cache 52 is used to alleviate this bottleneck. Even when the cache 52 is used, the processor 51 accesses the cache 52 based on the virtual address, and an address conversion unit provided in the cache 52 converts the virtual address into a physical address of the cache.
  • FIG. 20 is a diagram for explaining the conversion of a virtual address into a physical address by the address conversion unit.
  • the virtual address includes a virtual page number on the upper bit side and an in-page offset on the lower bit side.
  • the physical address includes a physical page number on the upper bit side and an in-page offset on the lower bit side.
  • the intra-page offset of the virtual address corresponds to the intra-page offset of the physical address. Therefore, it is necessary to associate the virtual page number of the virtual address with the physical page number of the physical address.
  • the page table 60 performs this association.
  • the page table 60 is indexed by virtual page numbers, and corresponding physical page numbers are registered.
  • the start address of the page table is given by the page table register 61.
  • the valid bit of each entry in the page table indicates whether or not the contents are valid. When this bit is off (“0”), it indicates that the corresponding page does not exist in the memory.
  • the cache 52 and the main memory 53 determine whether or not the data corresponding to the virtual address accessed by the processor 51 is held by the address conversion unit, and search for the data of the accessed address if held. To do. Then, the access operation from the processor 51 is executed based on the search result. When the data corresponding to the virtual address to be accessed is not held, the corresponding data is transferred from the lower storage device to the inside and held in blocks. A hit is when the data of the address accessed by the processor 51 is held, and a miss is when the data is not held. In order to improve the search speed, the storage area is divided into a plurality of entries, and the upper bits (frame address) of the address are associated with each entry, and the frame address is searched first.
  • the frame address storage buffer is a tag.
  • association level a data storage structure having a plurality of tags
  • set associative method a data storage structure having a plurality of tags
  • CAM has a circuit that functions as a cache in a memory management unit, usually called a translation lookaside buffer (TLB).
  • TLB translation lookaside buffer
  • the TLB uses the virtual address as a search key. If there is an entry corresponding to the address on the TLB, the TLB returns a corresponding physical address as a search result. This is a TLB hit. If there is no entry corresponding to the address, it is a TLB miss.
  • FIG. 21 is a diagram for explaining processing in TLB.
  • the TLB stores a part of entries to which physical pages in the page table are allocated.
  • the physical address of the TLB and the physical memory address correspond to each other as shown by a broken line. Since TLB is a cache, it has a tag field. If the required page is not registered in the TLB, the page table is referred to. If the physical page number of the page required in the page table is registered, information is registered in the TLB using that page. A page fault occurs when the required page disk address is registered in the page table.
  • the TLB has a plurality of address comparison circuits that respectively detect a match between an access address and a plurality of tags (entries). Since the plurality of tags correspond to different frame addresses, in the case of a TLB hit, one output of the plurality of address comparison circuits is matched (hit), and the other outputs are mismatched (miss). In the case of a TLB miss, all the outputs of the plurality of address comparison circuits do not match.
  • the output of two or more address comparison circuits is a hit, that is, a hit occurs in a plurality of entries, due to something such as a failure. This is called multi-hit.
  • the multi-hit detection circuit is a circuit in which the output becomes true when two or more bits out of all input bits are hit, that is, one of the logical values (eg, “1”). Used for places.
  • FIG. 22 is a diagram showing an address comparison circuit and a multi-hit detection circuit in TLB, where (A) shows an address comparison circuit and (B) shows a multi-hit detection circuit.
  • FIG. 22 shows an example of 32 entries with 64-bit addresses.
  • the address comparison circuit 71 has 32 address comparison circuits 700-731 corresponding to 32 entries.
  • the address comparison circuit 700-731 compares 32 tags (addresses) corresponding to 32 entries with the access address (Access address), and outputs comparison results HIT0-HIT31.
  • HIT0 to HIT31 indicate “1” when the corresponding tag (address) and the access address match, and indicate “0” when they do not match.
  • data corresponding to the entries of HIT0 to HIT31 indicating “1” is read.
  • two or more of HIT0 to HIT31 indicate “1”, the superimposed data is read out, leading to a serious malfunction.
  • the multi-hit detection circuit of the first to fifth embodiments is used as the multi-hit detection circuit shown in FIG. However, other than the example described, it is used in the same manner for the part that detects multi-hits in the processing apparatus.
  • the input signal is input to the Nch transistor and the Pch transistor is used as the adjustment circuit.
  • the input signal is input to the Pch transistor and the Nch transistor is used as the adjustment circuit. Good.
  • Adjustment circuit 20 Fuse ROM N0-N3, N4, N10-N17 Nch transistors P0, P4, P10-P1N, P20-P22 Pch transistors

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Abstract

L'invention concerne un circuit de détection à impacts multiples comprenant: une pluralité de transistors de première polarité dont chacun est doté d'une source reliée à une source d'un premier niveau de tension, un drain relié à un nœud commun et une grille à laquelle est appliquée une pluralité de signaux d'entrée; un circuit inverseur dont l'entrée est le nœud commun; et un circuit de réglage relié au nœud commun et réglant le niveau de tension du nœud commun de telle façon que la sortie du circuit inverseur diffère entre le cas où un des transistors de première polarité est à l'état passant et le cas où au moins deux des transistors de première polarité sont à l'état passant. Le circuit de détection à impacts multiples détecte le fait qu'au moins deux signaux d'une pluralité de signaux d'entrée indiquent un impact.
PCT/JP2012/076240 2012-10-10 2012-10-10 Circuit de détection à impacts multiples, dispositif de traitement et procédé de détection à impacts multiples WO2014057546A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07153279A (ja) * 1993-12-01 1995-06-16 Mitsubishi Electric Corp 多重一致検出装置
JPH11512550A (ja) * 1995-09-13 1999-10-26 エルエスアイ ロジック コーポレーション 多重信号有効化検出方法および装置
US6622267B1 (en) * 1999-12-08 2003-09-16 Intel Corporation Method and apparatus for detecting multi-hit errors in cache
WO2006038258A1 (fr) * 2004-09-30 2006-04-13 Renesas Technology Corp. Processeur de donnees
JP2011101266A (ja) * 2009-11-06 2011-05-19 Elpida Memory Inc 半導体装置及び情報処理システム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07153279A (ja) * 1993-12-01 1995-06-16 Mitsubishi Electric Corp 多重一致検出装置
JPH11512550A (ja) * 1995-09-13 1999-10-26 エルエスアイ ロジック コーポレーション 多重信号有効化検出方法および装置
US6622267B1 (en) * 1999-12-08 2003-09-16 Intel Corporation Method and apparatus for detecting multi-hit errors in cache
WO2006038258A1 (fr) * 2004-09-30 2006-04-13 Renesas Technology Corp. Processeur de donnees
JP2011101266A (ja) * 2009-11-06 2011-05-19 Elpida Memory Inc 半導体装置及び情報処理システム

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