WO2014049806A1 - Silicon carbide semiconductor device and method for manufacturing same - Google Patents

Silicon carbide semiconductor device and method for manufacturing same Download PDF

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WO2014049806A1
WO2014049806A1 PCT/JP2012/075004 JP2012075004W WO2014049806A1 WO 2014049806 A1 WO2014049806 A1 WO 2014049806A1 JP 2012075004 W JP2012075004 W JP 2012075004W WO 2014049806 A1 WO2014049806 A1 WO 2014049806A1
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ring
silicon carbide
region
semiconductor device
carbide semiconductor
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PCT/JP2012/075004
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French (fr)
Japanese (ja)
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宏行 松島
直樹 手賀
龍太 土屋
久本　大
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株式会社日立製作所
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Priority to PCT/JP2012/075004 priority Critical patent/WO2014049806A1/en
Priority to JP2014537975A priority patent/JP5799176B2/en
Publication of WO2014049806A1 publication Critical patent/WO2014049806A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Definitions

  • the present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same, and more particularly to a termination structure of a high voltage semiconductor device.
  • the power semiconductor device using SiC can reduce the on-resistance at the same breakdown voltage as compared with the power semiconductor device using Si. This is due to the fact that the dielectric breakdown strength of SiC is about 10 times that of Si, so that the depletion layer width is about one-tenth and the epitaxial layer serving as the drift layer can be made thinner.
  • the breakdown voltage of the power semiconductor device is determined by the thickness and impurity concentration of the epitaxial layer constituting the drift layer. However, since electric field concentration occurs in the termination region around the active region, if a structure for relaxing the electric field is not provided, breakdown occurs at a value smaller than the designed breakdown voltage.
  • JTE Joint Termination Extension
  • FLR Field Limiting Ring
  • the FLR structure is a floating region in which conductive impurities opposite to the conductivity of the substrate are implanted in a ring shape having a plan view.
  • the breakdown voltage of the FLR structure can be adjusted by adjusting the number of p-type ring rings, the interval between p-type rings, the depth for forming the p-type ring, or the impurity concentration.
  • the degree of electric field concentration is different between the corner portion and the line portion in a plan view shape, the electric field is more likely to be concentrated at the corner portion than at the line portion. For this reason, breakage easily occurs at the corner.
  • the extension of the depletion layer in the corner portion is smaller than the extension of the depletion layer in the line portion, the optimum distance between the p-type rings and the impurity concentration constituting the p-type ring in the line portion and the corner portion. Will be different.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2004-158817 (Patent Document 1), by selectively adding impurities only to the outside of the corner portion of the p-type ring, the electric field concentrated on the corner portion is dispersed to the outside of the corner portion. , Making it difficult to break down.
  • Patent Document 2 the width of the p-type ring corner portion is wider than that of the line portion. As a result, the distance between the p-type rings at the corner portion is reduced, and the corner portion The electric field concentration is reduced.
  • An object of the present invention is to provide a high voltage silicon carbide semiconductor device with high reproducibility.
  • the epitaxial layer includes, as a planar view region, an active region and an end region surrounding the active region.
  • Impurities of a second conductivity type having a plan view shape surrounding the active region in a ring shape are implanted, and a plurality of rings that are not in direct contact with the first electrode are provided, and the ring is a straight line in a plan view shape And a corner portion connecting the line portions, the distance between the rings gradually increases from the connecting portion between the line portion and the corner portion toward the middle of the corner.
  • the ring has a structure in which the high-concentration region is sandwiched between the low-concentration regions in a plan view shape, and the ring of the low-concentration regions as it goes from the connection part of the line part and the corner part to the middle of the corner. Reduce impurity concentration.
  • a high breakdown voltage silicon carbide semiconductor device having high reproducibility can be provided.
  • FIG. 1 is a top view of a principal part of a silicon carbide semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view of a termination region of a silicon carbide semiconductor device of Example 1.
  • FIG. 5 is a cross-sectional view of a termination region in another structure of the silicon carbide semiconductor device of Example 1.
  • FIG. 1 is a detailed cross-sectional view of a termination region of a silicon carbide semiconductor device of Example 1.
  • FIG. It is the figure shown about the impurity concentration of the ring 3 in FIG. 2 is a cross-sectional view of a corner portion and a line portion in a termination region of the silicon carbide semiconductor device of Example 1.
  • FIG. 3 is a schematic cross-sectional view showing an enlarged part of a termination region of the silicon carbide semiconductor device of Example 1.
  • FIG. 6 is a cross-sectional view of the termination region of the silicon carbide semiconductor device for explaining the manufacturing process of Example 1;
  • FIG. 9 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 8.
  • FIG. 10 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 9.
  • FIG. 13 is a cross-sectional view corresponding to a cross section taken along line II in FIG. 12 and a cross-sectional view corresponding to II-II. 3 is a top view of a principal part of the silicon carbide semiconductor according to Example 1.
  • FIG. 5 is a cross-sectional view of a termination region in the manufacturing process of the silicon carbide semiconductor according to Example 1.
  • FIG. 5 is a cross-sectional view of a termination region in the manufacturing process of the silicon carbide semiconductor according to Example 1.
  • FIG. 5 is a cross-sectional view of a termination region in the manufacturing process of the silicon carbide semiconductor according to Example 1.
  • FIG. 3 is a cross-sectional view of a termination region for explaining a manufacturing process of a silicon carbide semiconductor of Example 1.
  • FIG. FIG. 17 is a cross-sectional view of a termination region illustrating a manufacturing process following FIG. 16.
  • FIG. 18 is a sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 17;
  • FIG. 18 is a sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 17;
  • FIG. 10 is a termination region cross-sectional view illustrating a manufacturing process of a silicon carbide semiconductor device of Example 2.
  • FIG. 21 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 20.
  • FIG. 6 is an enlarged view of a ring 205 of the silicon carbide semiconductor device of Example 2.
  • FIG. 12 is a cross-sectional view of a termination region of the silicon carbide semiconductor device of Example 3.
  • FIG. 12 is a cross-sectional view of a termination region in the manufacturing process of the silicon carbide semiconductor device of Example 3.
  • FIG. 12 is a cross-sectional view of a termination region of the silicon carbide semiconductor device of Example 4.
  • FIG. FIG. 12 is a cross-sectional view of a termination region in the process for manufacturing a silicon carbide semiconductor device according to Example 4;
  • FIG. 27 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 26.
  • FIG. 28 is a sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 27.
  • 10 is a sectional view of a termination region of a silicon carbide semiconductor device of Example 5.
  • FIG. 10 is a cross-sectional view of a termination region illustrating a manufacturing process for a silicon carbide semiconductor device of Example 5.
  • FIG. FIG. FIG. 12 is a cross-sectional view of a termination region in the process for manufacturing a silicon carbide semiconductor device according to Example 4;
  • FIG. 27 is a cross-sectional view of a termination region of the
  • FIG. 31 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 30.
  • FIG. 32 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 31.
  • 12 is a sectional view of a termination region of a silicon carbide semiconductor device of Example 6.
  • FIG. 10 is a sectional view of a termination region, illustrating a manufacturing process according to Example 6.
  • FIG. 32 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 31.
  • FIG. 32 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a
  • FIG. 12 is a sectional view of a termination region in the manufacturing process of Example 7.
  • FIG. FIG. 38 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 37.
  • FIG. 39 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 38.
  • FIG. 40 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 39;
  • FIGS. 1 is a top view of a principal part of a silicon carbide semiconductor device
  • FIG. 2 is a sectional view of a termination region of the silicon carbide semiconductor device of Example 1
  • FIG. 3 is a sectional view of a termination region in another structure of the silicon carbide semiconductor device of Example 1.
  • 4 is a detailed view of a cross section of the termination region of the silicon carbide semiconductor device of Example 1
  • FIG. 5 is a diagram showing the impurity concentration of the ring in FIG. 4
  • FIG. 6 is a corner in the termination region of the silicon carbide semiconductor device of Example 1.
  • FIG. 7 is a schematic cross-sectional view showing a part of the termination region of the silicon carbide semiconductor device of Example 1 in an enlarged manner.
  • silicon carbide semiconductor device 1 includes a p-type well region in an active region 2 at the center of a silicon carbide semiconductor device in which a diode and a transistor are arranged, and a terminal region surrounding active region 2 in plan view.
  • 106 a plurality of p-type floating field limiting rings (hereinafter, referred to as rings) 105 that are arranged in multiple concentric positions, and an n + -type ring region that surrounds the ring 105 in plan view
  • a channel stopper 107 is a plurality of p-type floating field limiting rings 105 that are arranged in multiple concentric positions, and an n + -type ring region that surrounds the ring 105 in plan view.
  • the maximum electric field portion sequentially moves to the outer p-type ring 105 and yields at the outermost ring 105, so that the silicon carbide semiconductor device can have a high breakdown voltage.
  • the example in which the triple ring 105 is formed is illustrated using FIG. 1, the present invention is not limited to this.
  • An electrode 104 is formed on the back surface (second main surface) of the SiC substrate 101.
  • n ⁇ type epitaxial layer 102 made of SiC having an impurity concentration lower than that of the SiC substrate 101 is formed on the surface (first main surface) of the n + type SiC substrate 101 made of SiC.
  • the thicknesses of the n + type SiC substrate 101 and the n ⁇ type epitaxial layer 102 are set in the range of 5 to 20 ⁇ m.
  • a p-type ring 105 is formed in the n ⁇ -type epitaxial layer 102.
  • the depth of the ring 105 from the surface of the epitaxial layer 102 is set within a range of 0.5 to 2.0 ⁇ m, and the distance between the rings 105 is set within a range of 0.5 to 2.5 ⁇ m.
  • the distances between the rings 105 do not necessarily have to be constant.
  • FIG. 3 shows a structure in which the distance between the rings 105 is changed while maintaining the distance between the well region 106 and the channel stopper 107 in FIG. Specifically, the pressure resistance is further improved by narrowing the distance between the inner rings 105 and widening the distance between the outer rings 105.
  • the distance between the channel stopper and the outermost ring 105 is outside.
  • the distance between the rings 105 is the largest.
  • a p-type well region 106 is formed inside the ring 105 of the n ⁇ -type epitaxial layer 102.
  • the depth of the p-type well region 106 from the surface of the epitaxial layer 102 is set within a range of 0.5 to 2.0 ⁇ m.
  • the depth of the ring 105 and the well region 106 can be set individually, but it goes without saying that when the same depth is set, they can be formed simultaneously in the same process.
  • a channel stopper 107 having an n + type planar view shape in a ring shape is formed in the n ⁇ type epitaxial layer 102.
  • the depth of the channel stopper 107 from the surface of the epitaxial layer 102 is set within a range of 0.5 to 2 ⁇ m.
  • ⁇ ” and “ + ” used in the description so far are symbols representing the relative impurity concentration of n-type or p-type conductivity.
  • the impurity concentration of the n-type impurity increases in the order of “n ⁇ ”, “n”, and “n + ”.
  • the preferable range of the impurity concentration of the n + -type SiC substrate 101 is 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3
  • the preferable range of the impurity concentration of the n ⁇ -type epitaxial layer 102 is 1 ⁇ 10 14 to 1 ⁇ .
  • the ring 105 and the p-type well region are 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3
  • the n + -type channel stopper 107 is 1 ⁇ 10 19 to 1 ⁇ 10 21 cm ⁇ 3. Is set within the range.
  • the ring 105 includes a high concentration region 105a having a high impurity concentration and a low concentration region 105b having a low impurity concentration sandwiching the high concentration region 105a.
  • a more detailed structure is shown in FIG.
  • the position of the surface of the high concentration region 105a of the ring 105 is 0.05 ⁇ m lower than the position of the surface of the low concentration region of the ring 105 and the n ⁇ type epitaxial layer where the ring 105 is not formed. This is formed by scraping the surface in the etching step when forming the high concentration region 105a of the ring 105.
  • the vertical axis represents the impurity concentration of the ring 105
  • the horizontal axis represents the width of the ring 105.
  • the concentration distribution becomes the darkest at the center of the ring (high concentration region 105a), and gradually decreases toward the periphery of the ring 105 (low concentration region 105b).
  • the impurity concentration of the high concentration region 105a at the center of the ring is 1 ⁇ 10 17 to 1 ⁇ 10 18 cm ⁇ 3
  • the impurity concentration of the low concentration region 105b at the periphery of the ring is 1 ⁇ 10 15 to 2 ⁇ 10 17 cm -3
  • the width of the low concentration region 105b in the corner portion of the ring 105 is larger.
  • the ring width of the line portion is substantially constant, but the width of the ring 105 gradually increases from the connecting portion between the line portion and the corner portion to the middle of the corner portion. It is widest in the middle of the corner.
  • the corner ring has a ring width 1.3 to 1.6 times the ring width of the line portion.
  • the density of the peripheral part is different between the corner part and the line part. Specifically, although the impurity concentration in the low concentration region 105b in the line portion is substantially constant, the impurity concentration in the low concentration region 105b increases from the connection portion between the line portion and the corner portion to the middle of the corner portion. Is gradually thinner, and is the thinnest in the middle of the corner portion of the ring 105. The density at the midpoint of the corner portion of the ring 105 is approximately half that of the line portion.
  • the electric field concentration applied to the p-type well region 106 is easily dispersed to the outer ring 105, and the silicon carbide semiconductor device can have a high breakdown voltage.
  • FIG. 12 is a top view of the silicon carbide semiconductor device of Example 1, and is a diagram in which the ring 105 of FIG. 1 is extracted.
  • a silicon carbide according to the present embodiment will be described with reference to a cross-sectional view corresponding to a cross section taken along line II of the corner portion of the ring 105 and a cross-sectional view corresponding to a cross section taken along line II-II of the stripe portion of the ring 105.
  • a method for manufacturing a semiconductor device will be described.
  • a 4H—SiC (silicon carbide) substrate 101 is prepared, and the Si surface is the upper surface.
  • SiC substrate 101 a substrate into which nitrogen which is an n-type impurity is introduced is used.
  • an SiC n ⁇ type epitaxial layer 102 is formed on the surface (first main surface) of the SiC substrate 101 by an epitaxial growth method.
  • N-type impurities are introduced into epitaxial layer 102 so as to have a concentration lower than that of SiC substrate 101.
  • the impurity concentration of epitaxial layer 102 depends on the element rating of the silicon carbide semiconductor device, but is set in the range of 1 ⁇ 10 14 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the thickness of the epitaxial layer 102 is set in the range of 5 to 20 ⁇ m.
  • an insulating film is deposited on the surface of the epitaxial layer 102 by a plasma CVD (Chemical Vapor Deposition) method.
  • a SiO 2 film 109 is deposited.
  • the thickness of the SiO 2 film 109 is set in the range of 1 to 3 ⁇ m.
  • the hard mask pattern 109 a is formed on the surface of the epitaxial layer 102 by processing the SiO 2 film 109 by a dry etching method using the resist pattern as a mask.
  • the width of the hard mask pattern 109a corresponding to the ring 105 is set in the range of 1 to 2.5 ⁇ m.
  • the surface of the epitaxial layer 102 is shaved by several nm (5 nm or less), and a first step is formed in the epitaxial layer 102 below the side surface of the hard mask pattern 109a (see FIG. (Not shown in FIG. 10).
  • p-type impurities are ion-implanted into the epitaxial layer 102.
  • Al was used as the p-type impurity.
  • the ring 105 of the epitaxial layer 102 is formed.
  • FIG. 11 is a cross-sectional view corresponding to the cross section taken along line II of FIG. 12 and a cross-sectional view corresponding to II-II.
  • the oblique impurity implantation is performed four times in total from the directions of N1, N2, N3, and N4 shown in FIG. 12 and at an angle from the normal line of the substrate.
  • N1, N2, N3, and N4 are inclined 45 degrees from the line portion of the ring 105.
  • the angle (elevation angle) at the time of oblique impurity implantation is 10 to 45 degrees (elevation angle 45 to 80 degrees) from the normal direction of SiC epitaxial substrate 103.
  • the depth of the ring 105 from the surface of the epitaxial layer 102 is set in the range of 0.5 to 2 ⁇ m.
  • FIG. 13 shows a p-type impurity distribution when impurities are implanted from the N1 direction of FIG. If only the ring by this injection process is shown, it will be the ring 105c. Since the N1 direction is a direction toward the upper right in the figure inclined 45 degrees to the right from the vertical line of the ring 105 when viewed in plan, impurities are implanted into a region where the hard mask pattern 109a is shifted in the upper right direction. In addition, the lateral spread of impurities in the II section, which is the corner portion of the ring 105, and the lateral spread of impurities in the II-II section, which is the line portion of the ring 105, are different. Will spread greatly.
  • FIG. 14 shows a p-type impurity distribution when impurities are implanted from the N2 direction of FIG. If only the ring by this injection process is shown, it will be the ring 105d.
  • the N2 direction is a direction from the vertical line of the ring 105 toward the lower left in the figure tilted 135 degrees to the left when viewed in plan, so that the impurity is implanted into a region where the hard mask pattern 109a is shifted to the lower left.
  • the lateral spread of impurities in the II section which is the corner portion of the ring 105
  • the lateral spread of impurities in the II-II section which is the line portion of the ring 105, are different. Will spread greatly.
  • FIG. 15 is a p-type impurity distribution when impurities are implanted from the N3 direction of FIG. If only the ring by this injection process is shown, it will be the ring 105e.
  • the N3 direction is a direction from the vertical line of the ring 105 toward the lower right in the drawing inclined 135 degrees to the right in the plan view, so that impurities are implanted into a region where the hard mask pattern 109a is shifted to the lower right.
  • the lateral spread of impurities in the II section which is the corner portion of the ring 105
  • the lateral spread of impurities in the II-II section which is the line portion of the ring 105, are different. Will spread greatly.
  • FIG. 16 shows a p-type impurity distribution when impurities are implanted from the N4 direction of FIG. If only the ring by this injection process is shown, it will be the ring 105f. Since the N3 direction is a direction from the vertical line of the ring 105 toward the upper left in the drawing when viewed in plan, an impurity is implanted into a region where the hard mask pattern 109a is shifted in the upper left direction. In addition, the lateral spread of impurities in the II section, which is the corner portion of the ring 105, and the lateral spread of impurities in the II-II section, which is the line portion of the ring 105, are different. Will spread greatly.
  • the rings 105c to 105f are overlapped, so that the ring 105 having the high concentration region 105a and the low concentration region 105b shown in FIG. 11 is formed.
  • the impurity concentration in the low concentration region 105b arranged inside and outside the ring so as to sandwich the high concentration region 105a in the corner portion (II cross section) of the ring 105 is one impurity implantation, whereas the line of the ring 105
  • the impurity concentration of the low concentration region 105b in the portion (II-II cross section) is equivalent to two impurity implantations.
  • the low concentration region 105 b at the corner portion of the ring 105 has half the concentration of the low concentration region 105 b at the line portion of the ring 105.
  • the spread of the low concentration region 105b at the corner portion of the ring 105 is 1 / ⁇ 2 at the maximum of the spread of the low concentration region 105b at the line portion of the ring 105 because the implantation angle is 45 degrees.
  • vertical implantation is combined in addition to oblique implantation.
  • the impurity concentration of the high concentration region 105a of the ring 105 is set to 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3
  • the impurity concentration of the low concentration region 105b is set to 1 ⁇ 10 15 to 1 ⁇ 10 18 cm ⁇ 3.
  • the low concentration region 106b is formed outside the high concentration region 106a.
  • the low concentration region 106b is wider than the low concentration region 105b of the ring 105 because the opening of the hard mask pattern 109a in the well region 106 is large.
  • vertical implantation is combined.
  • the impurity concentration of the well region 106 is set in the range of 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 .
  • impurities are vertically implanted using the hard mask pattern 109b as a mask.
  • nitrogen is ion-implanted as an n-type impurity into the epitaxial layer 102 to form an n + -type channel stopper 107.
  • the impurity concentration of the channel stopper 107 is set in the range of 1 ⁇ 10 19 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the manufacturing method of the first embodiment as a result of forming the ring 105 by oblique implantation of impurities, the spread of the impurities at the corners of the ring 105 becomes larger, so that the electric field is more easily relaxed than the vertical implantation of impurities. . Furthermore, since it can be realized with a single hard mask, the reproducibility is high with no mask displacement.
  • the ring 205 is not formed by oblique impurity implantation but is formed by two or more impurity implantation steps.
  • a method for manufacturing a silicon carbide semiconductor device according to Example 2 will be described in the order of steps with reference to FIGS.
  • an n ⁇ type epitaxial layer 102 is formed on the surface (first main surface) of the n + type SiC substrate 101, and an SiC epitaxial layer comprising the SiC substrate 101 and the epitaxial layer 102 is formed.
  • a substrate 103 is formed.
  • the impurity concentration of the SiC substrate 101 is set in the range of 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3
  • the impurity concentration of the epitaxial layer 102 is in the range of 1 ⁇ 10 14 to 1 ⁇ 10 17 cm ⁇ 3 . Is set in
  • the low concentration region 205b is formed.
  • the distance (opening width) between the adjacent hard mask patterns 209a is wider in the corner portion than in the line portion, and the opening width that is constant in the line portion is intermediate between the connecting portion between the line portion and the corner portion. Widening towards the point.
  • the impurity concentration of the low concentration region 205b is in the range of 1 ⁇ 10 15 to 2 ⁇ 10 17 cm ⁇ 3 .
  • the surface of the epitaxial layer 102 is shaved by 1 to 5 nm as in the first embodiment, and the epitaxial layer below the side surface of the hard mask is formed.
  • a first step is formed at 102.
  • Al which is a p-type impurity
  • a hard mask pattern 209b made of a SiO 2 film whose width between the hard masks is narrower than that of the hard mask pattern 209a.
  • the impurity concentration of the high concentration region 205a is set within the range of 1 ⁇ 10 17 to 1 ⁇ 10 18 cm ⁇ 3 .
  • the high concentration region 205a is formed inside the low concentration region 205b.
  • the low concentration region 205b is arranged so as to sandwich the high concentration region 205a.
  • the surface of the epitaxial layer 102 is shaved by 1 to 5 nm as in the first step, and the epitaxial layer below the side surface of the hard mask is formed.
  • a second step is formed at 102 (see FIG. 22).
  • a well region 206 is formed by ion-implanting p-type impurities and Al into the epitaxial layer 203 using the hard mask pattern 209c as a mask (not shown).
  • the impurity concentration of the well region 206 is in the range of 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the well region 206 may be formed simultaneously with the ring 205. Further, the well region 206 may be formed in two or more exposure steps simultaneously with the ring 205.
  • n-type impurities and nitrogen are ion-implanted into the epitaxial layer 102 to form an n + -type ring (not shown).
  • the impurity concentration of the n-type ring is set in the range of 1 ⁇ 10 19 to 1 ⁇ 10 21 cm ⁇ 3 .
  • a ring may be formed with two or more exposures by increasing the number of hard mask patterns during ring formation.
  • the final width and impurity concentration of the low concentration region 205b can be arbitrarily set. Can be set.
  • a p + -type auxiliary ring 310 is formed in the well region 306.
  • a p + -type auxiliary ring 310 is formed in the well region.
  • the depth of the p + -type auxiliary ring 310 from the surface of the epitaxial layer 102 is set in the range of 0.1 to 0.5 ⁇ m.
  • the impurity concentration of the p + -type auxiliary ring 310 is set in the range of 1 ⁇ 10 19 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the p + type auxiliary ring 310 is formed by the process shown in FIG. A p-type impurity, Al, is implanted into the epitaxial layer 102 using the hard mask 309a made of the SiO 2 film as a pattern.
  • the formation of the ring 105 and the channel stopper 107 are the same as in the first embodiment.
  • the well region is formed by the p + -type auxiliary ring 310 having a high impurity concentration.
  • the elongation of the depletion layer in 306 stops. That is, the breakdown in the well region 306 is less likely to occur, so that it is robust against the termination structure of the active region.
  • Example 4 The difference between Example 4 and Example 1 described above is that the depth of the p-type ring differs depending on the ring.
  • the ring close to the active region is formed shallow and formed deeper as the distance from the active region increases.
  • FIG. 25 shows a sectional view of the termination region of the silicon carbide semiconductor device.
  • the formation depth of the ring 405 increases as the distance from the active region increases.
  • the depth of each ring 405 is set to 0.5 to 4.0 ⁇ m.
  • the ring on the outer side of the ring on the active region side is larger than the ring on the active region side so that the depth of the ring 405h adjacent to the outside of the ring 405g is not less than the first ring and the depth of the ring 405i on the outside of the ring 405h is not less than the ring 405h It is formed to be deep. Therefore, a more robust termination can be formed.
  • a method for manufacturing a silicon carbide semiconductor device in Example 4 will be described with reference to FIGS. Since the manufacturing method other than the p-type ring is the same as that of the first embodiment, it will not be described.
  • the epitaxial layer 102 is ion-implanted with a p-type impurity, Al. This forms the innermost ring 405g.
  • a p-type ring 405h that is deeper from the surface than the ring 405g is adjacent to the outside of the ring 405g.
  • p-type impurities and Al are obliquely ion-implanted into the epitaxial layer 102 to form a p-type ring 405i that is deeper from the surface than the ring 405g adjacent to the outside of the ring 405g. Form.
  • Each ring is formed by oblique ion implantation as in the first embodiment.
  • the difference between the fifth embodiment and the first embodiment described above is that the ring epitaxial layer is dug to a predetermined depth by the p-type well region 506, and the p-type ring 505 is formed below the step.
  • FIG. 29 shows a sectional view of the termination region of the silicon carbide semiconductor device.
  • the region for forming the ring 505 b is dug to a predetermined depth from the surface of the epitaxial layer 102.
  • the predetermined depth is 0.5 to 1.5 ⁇ m.
  • the depth of the p-type well region 506 is 0.5 to 2.0 ⁇ m from the dug surface, and the impurity concentration is in the range of 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 .
  • Example 5 A method for manufacturing a silicon carbide semiconductor device in Example 5 will be described with reference to FIGS.
  • An insulating film and a SiO 2 film are deposited on the surface of the epitaxial layer 102 by plasma CVD (Chemical Vapor Deposition).
  • the thickness of the SiO 2 film is 1 to 3 ⁇ m.
  • the hard mask pattern 509a made of the SiO 2 film is formed on the surface of the epitaxial layer 102 by processing the SiO 2 film by a dry etching method using the resist pattern as a mask.
  • a ring region without a hard mask is processed by a dry etching method.
  • the depth of the processed region from the surface of the epitaxial layer 102 is 0.5 to 1.5 ⁇ m.
  • a p-type ring 505 is formed in the lower stage of the step formed by digging in the same manner as in the first embodiment.
  • a p-type well region 506 is also formed at the same time.
  • the p-type well region 506 straddles the stepped portion. Since the p-type well region 506 is formed by oblique impurity implantation similarly to the ring, a region 506b that is not formed by normal impurity implantation is formed. As a result, the distance from the side wall of the stepped portion at the bottom of the p-type well region to the stepped portion on the surface becomes longer, and the destruction in the p-type well region does not occur.
  • the ring can be formed at a position deeper than the active region from the epitaxial layer 102, so that a higher breakdown voltage can be obtained.
  • This is a silicon carbide semiconductor device.
  • the difference between the sixth embodiment and the first embodiment described above is that the widths of the p-type rings 605g, 605h, and 605i are not constant, the ring width close to the active region is formed wider, and narrower as the distance from the active region increases. It is a point to be done.
  • FIG. 34 shows a cross-sectional view of the termination region of the silicon carbide semiconductor device.
  • the width of the ring decreases as the distance from the active region increases.
  • the width of the first ring that is closest to the active is 4.0 to 5.0 ⁇ m.
  • the outer ring is wider than the inner ring width so that the width of the second ring outside the first ring is equal to or smaller than the first ring, and the width of the third ring outside the second ring is equal to or smaller than the second ring.
  • the width is formed to be smaller.
  • a method for manufacturing the silicon carbide semiconductor device according to the sixth embodiment will be described with reference to FIGS. Since the manufacturing method other than the p-type ring 605 is the same as that of the first embodiment, it is omitted.
  • the hard mask pattern 609a made of the SiO 2 film is formed on the surface of the epitaxial layer 102 by processing the SiO 2 film by the dry etching method using the resist pattern as a mask.
  • the innermost pattern width L1 is 4.0 to 5.0 ⁇ m.
  • the outermost pattern width L2 from the innermost side is narrower than the pattern width L1.
  • the pattern width L3 that is one outside of the pattern width L2 is narrower than the pattern width L2.
  • the pattern width Ln is formed narrower than the pattern width Ln-1.
  • a ring 605 is formed by implanting oblique ions of p-type impurities and Al into the epitaxial layer 102. At this time, since the width of the ring 605 depends on the pattern width of FIG.
  • Example 6 the total impurity concentration of the ring in the region near the active is large, and the total impurity concentration is decreased as the distance is increased. Therefore, a more robust termination can be formed.
  • the difference between the seventh embodiment and the first embodiment described above is that the total impurity concentration constituting the p-type ring 705 is larger in the inner ring, and the total impurity concentration is smaller toward the outer side. Is a point.
  • FIG. 37 shows a cross-sectional view of the termination region of the silicon carbide semiconductor device.
  • 38 to 40 are diagrams showing a method of manufacturing the silicon carbide semiconductor device in the seventh embodiment. Since the manufacturing method other than the p-type ring is the same as that of the first embodiment, it is omitted.
  • the total impurity concentration of the ring 705 in the region close to the active region is large, and the total impurity concentration decreases as the distance from the active region increases.
  • a p-type first ring 705a is formed in the epitaxial layer 102 by ion-implanting p-type impurities and Al into the epitaxial layer 102.
  • the ring 705g is formed by oblique ion implantation as in the first embodiment.
  • p-type impurities and Al are obliquely ion-implanted into the epitaxial layer 102, whereby p having a total impurity concentration lower than the total impurity concentration of the first ring outside the first ring.
  • a second ring 705h of the mold is formed.
  • a p-type impurity, Al is obliquely ion-implanted into the epitaxial layer 102, so that p having a total impurity concentration lower than the total impurity concentration of the second ring outside the second ring.
  • a third ring 705i of the mold is formed.
  • the total impurity concentration of the ring in the region close to the active region is large, and the total impurity concentration decreases as the distance from the active region increases, so that a more robust termination can be formed.
  • SYMBOLS 1 Silicon carbide semiconductor device, 2 ... Active region, 3 ... Ring, 4 ... Channel stopper, 5 ... P-type well region, 101 ... SiC substrate, 102 ... Epitaxial layer, 103 ... SiC epitaxial substrate, 104 ... Electrode, 105 ... p-type ring, 105a ... high concentration region of ring 105, 105b ... low concentration region of ring 105, 106 ... p-type well region, 106a ... high concentration region of p-type well region, 106b ... high concentration region of p-type well region , 107 ... channel stopper, 108 ... SiO film, 109 ... hard mask, 109a, 109b, 109c ... hard mask pattern, N1 ... impurity injection direction, N2 ... impurity injection direction, N3 ... impurity injection direction, N4 ... impurity injection direction,

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Abstract

The purpose of the present invention is to provide a silicon carbide semiconductor device having high repeatability and a high withstand voltage. In order to achieve the purpose, in multi-formed field limiting rings, the distance between the rings is gradually reduced toward a corner portion from a line portion, and the impurity concentration of a low-concentration region that sandwiches a high-concentration region at the center of a line is reduced toward the corner portion from the line portion.

Description

炭化珪素半導体装置およびその製造方法Silicon carbide semiconductor device and manufacturing method thereof
　本発明は、炭化珪素半導体装置及びその製造方法に関し、特に高耐圧半導体装置のターミネーション構造に関する。 The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same, and more particularly to a termination structure of a high voltage semiconductor device.
　ＳｉＣを用いたパワー半導体装置は、Ｓｉを用いたパワー半導体装置と比較して、同耐圧ではオン抵抗の低抵抗化が可能である。これは、ＳｉＣの絶縁破壊強度がＳｉの約１０倍であるため、空乏層幅が約１０分の１となり、ドリフト層となるエピタキシャル層を薄くできることに起因している。 The power semiconductor device using SiC can reduce the on-resistance at the same breakdown voltage as compared with the power semiconductor device using Si. This is due to the fact that the dielectric breakdown strength of SiC is about 10 times that of Si, so that the depletion layer width is about one-tenth and the epitaxial layer serving as the drift layer can be made thinner.
　しかしながら、オフ状態において、ＳｉＣを用いたパワー半導体装置の最大電界はＳｉを用いたパワー半導体の１０倍であるため、電界を緩和するために用いるターミネーション構造が重要となる。 However, since the maximum electric field of a power semiconductor device using SiC is 10 times that of a power semiconductor using Si in the off state, the termination structure used for relaxing the electric field is important.
　パワー半導体装置の耐圧はドリフト層を構成するエピタキシャル層の厚さと不純物濃度によって決まる。しかしながら、アクティブ領域の周囲にある終端領域では電界集中が生じるため、電界緩和のための構造を設けなければ、設計上の耐圧よりも小さな値で破壊がおきてしまう。 The breakdown voltage of the power semiconductor device is determined by the thickness and impurity concentration of the epitaxial layer constituting the drift layer. However, since electric field concentration occurs in the termination region around the active region, if a structure for relaxing the electric field is not provided, breakdown occurs at a value smaller than the designed breakdown voltage.
　そのような電界緩和構造として、一般に、ＪＴＥ（Ｊｕｎｃｔｉｏｎ　Ｔｅｒｍｉｎａｔｉｏｎ　Ｅｘｔｅｎｔｉｏｎ）構造、ＦＬＲ（Ｆｉｅｌｄ　Ｌｉｍｉｔｔｉｎｇ　Ｒｉｎｇ）構造が知られている。 As such an electric field relaxation structure, a JTE (Junction Termination Extension) structure and an FLR (Field Limiting Ring) structure are generally known.
　上記構造のうち、ＦＬＲ構造は、基板の導電性と反対の導電性不純物が平面視形状が多重のリング状に注入されたフローティング領域のことである。一般に、ＦＬＲ構造は、ｐ型リング環数、ｐ型リング間の間隔、ｐ型リングを形成する深さあるいは不純物濃度を調整することで、耐圧が調整できることが知られている。 Among the above structures, the FLR structure is a floating region in which conductive impurities opposite to the conductivity of the substrate are implanted in a ring shape having a plan view. In general, it is known that the breakdown voltage of the FLR structure can be adjusted by adjusting the number of p-type ring rings, the interval between p-type rings, the depth for forming the p-type ring, or the impurity concentration.
　しかしながら、ＦＬＲ構造において、平面視形状のコーナー部とライン部では、電界集中の度合いが異なるため、コーナー部ではライン部に比べ電界が集中しやすい。そのため、コーナー部で破壊が起きやすい。このとき、コーナー部での空乏層の伸びは、ライン部の空乏層の伸びに比べて小さくなるため、ライン部とコーナー部とでは最適なｐ型リング間距離やｐ型リングを構成する不純物濃度が異なってくる。 However, in the FLR structure, since the degree of electric field concentration is different between the corner portion and the line portion in a plan view shape, the electric field is more likely to be concentrated at the corner portion than at the line portion. For this reason, breakage easily occurs at the corner. At this time, since the extension of the depletion layer in the corner portion is smaller than the extension of the depletion layer in the line portion, the optimum distance between the p-type rings and the impurity concentration constituting the p-type ring in the line portion and the corner portion. Will be different.
　特開２００４－１５８８１７号公報（特許文献１）では、ｐ型リングのコーナー部の外側にのみ選択的に不純物を添加することで、コーナー部へ集中していた電界をコーナー部の外側へ分散させ、破壊を生じにくくしている。 In Japanese Patent Application Laid-Open No. 2004-158817 (Patent Document 1), by selectively adding impurities only to the outside of the corner portion of the p-type ring, the electric field concentrated on the corner portion is dispersed to the outside of the corner portion. , Making it difficult to break down.
　特開２０１１－１７１５５２号公報（特許文献２）では、ｐ型リングコーナー部の幅をライン部よりも広くしているため、結果としてコーナー部でのｐ型リング間距離が小さくなり、コーナー部での電界集中が緩和される構造となっている。 In Japanese Patent Application Laid-Open No. 2011-171552 (Patent Document 2), the width of the p-type ring corner portion is wider than that of the line portion. As a result, the distance between the p-type rings at the corner portion is reduced, and the corner portion The electric field concentration is reduced.
特開２００４－１５８８１７号公報JP 2004-158817 A 特開２０１１－１７１５５２号公報JP 2011-171552 A
　特許文献１の各コーナーの外側にのみ選択的に不純物を添加する構造は、ｐ型リングの不純物インプラント用マスクとは別のマスクで不純物をインプラントせざるをえない。しかし、インプラントする領域がｐ型リングの外側に限定されているので、マスクの位置ズレにより耐圧が変動しやすい。また、深い位置だけのインプラントは不純物濃度の制御が難しい。従って、この構造では高い再現性で高耐圧の炭化珪素半導体装置が得られない。 In the structure in which impurities are selectively added only outside the corners of Patent Document 1, impurities must be implanted using a mask different from the p-type ring impurity implantation mask. However, since the region to be implanted is limited to the outside of the p-type ring, the breakdown voltage tends to fluctuate due to the displacement of the mask. Moreover, it is difficult to control the impurity concentration of an implant only at a deep position. Therefore, with this structure, a silicon carbide semiconductor device with high reproducibility and high breakdown voltage cannot be obtained.
　特許文献２の不純物濃度を一様に小さくしてリング内への空乏層の伸びを大きくする方法では、リング内に空乏層が伸びきってしまい、破壊が生じてしまう。 In the method of uniformly reducing the impurity concentration in Patent Document 2 to increase the extension of the depletion layer into the ring, the depletion layer extends completely into the ring, resulting in destruction.
　本発明の目的は、高い再現性のある高耐圧炭化珪素半導体装置を提供することにある。 An object of the present invention is to provide a high voltage silicon carbide semiconductor device with high reproducibility.
　本願において開示される発明のうち、上記目的を解決する代表的な手段簡単に説明すれば、次のとおりである。 Of the inventions disclosed in the present application, representative means for solving the above-described object will be briefly described as follows.
　第１導電型の炭化珪素基板と、前記炭化珪素基板の表面上に形成された第１導電型の炭化珪素エピタキシャル層と、前記エピタキシャル層上に配置された第１電極と、前記炭化珪素基板の裏面に配置された第２電極とを備えた炭化珪素半導体装置において、前記エピタキシャル層は平面視領域として、アクティブ領域と、前記アクティブ領域を囲む端部領域とを備え、前記端部領域は、前記アクティブ領域を前記リング状に囲む平面視形状となる第２導電型の不純物が注入され、前記第１電極に直接接していないリングを多重に備え、前記リングは、平面視形状で直線状のライン部と、前記ライン部を繋ぐコーナー部とを備え、前記ライン部と前記コーナー部の接続部から前記コーナーの中間に向かうにしたがって前記リング間距離が徐々に狭くし、さらに、前記リングは、平面視形状で高濃度領域を低濃度領域で挟み込む構造を備え、前記ライン部と前記コーナー部の接続部から前記コーナーの中間に向かうにしたがって前記低濃度領域の不純物濃度を薄くする。 A first conductivity type silicon carbide substrate; a first conductivity type silicon carbide epitaxial layer formed on a surface of the silicon carbide substrate; a first electrode disposed on the epitaxial layer; and the silicon carbide substrate. In the silicon carbide semiconductor device including the second electrode disposed on the back surface, the epitaxial layer includes, as a planar view region, an active region and an end region surrounding the active region. Impurities of a second conductivity type having a plan view shape surrounding the active region in a ring shape are implanted, and a plurality of rings that are not in direct contact with the first electrode are provided, and the ring is a straight line in a plan view shape And a corner portion connecting the line portions, the distance between the rings gradually increases from the connecting portion between the line portion and the corner portion toward the middle of the corner. Further, the ring has a structure in which the high-concentration region is sandwiched between the low-concentration regions in a plan view shape, and the ring of the low-concentration regions as it goes from the connection part of the line part and the corner part to the middle of the corner. Reduce impurity concentration.
　本発明によれば、高い再現性を備えた高耐圧な炭化珪素半導体装置を提供することができる。 According to the present invention, a high breakdown voltage silicon carbide semiconductor device having high reproducibility can be provided.
実施例１の炭化珪素半導体装置の要部上面図である。1 is a top view of a principal part of a silicon carbide semiconductor device of Example 1. FIG. 実施例１の炭化珪素半導体装置の終端領域断面図である。1 is a cross-sectional view of a termination region of a silicon carbide semiconductor device of Example 1. FIG. 実施例１の炭化珪素半導体装置の別構造における終端領域断面図である。5 is a cross-sectional view of a termination region in another structure of the silicon carbide semiconductor device of Example 1. FIG. 実施例１の炭化珪素半導体装置を終端領域の断面詳細図である。1 is a detailed cross-sectional view of a termination region of a silicon carbide semiconductor device of Example 1. FIG. 図４におけるリング３の不純物濃度について示した図である。It is the figure shown about the impurity concentration of the ring 3 in FIG. 実施例１の炭化珪素半導体装置の終端領域におけるコーナー部とライン部の断面図である。2 is a cross-sectional view of a corner portion and a line portion in a termination region of the silicon carbide semiconductor device of Example 1. FIG. 実施例１の炭化珪素半導体装置の終端領域の一部を拡大して示す模式断面図である。FIG. 3 is a schematic cross-sectional view showing an enlarged part of a termination region of the silicon carbide semiconductor device of Example 1. 実施例１の製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 6 is a cross-sectional view of the termination region of the silicon carbide semiconductor device for explaining the manufacturing process of Example 1; 図８に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 9 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 8. 図９に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 10 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 9. 図１２のI―I線の断面に相当する断面図とII―IIに相当する断面図である。FIG. 13 is a cross-sectional view corresponding to a cross section taken along line II in FIG. 12 and a cross-sectional view corresponding to II-II. 実施例１による炭化珪素半導体の要部上面図である。3 is a top view of a principal part of the silicon carbide semiconductor according to Example 1. FIG. 実施例１による炭化珪素半導体の製造工程における終端領域断面図である。5 is a cross-sectional view of a termination region in the manufacturing process of the silicon carbide semiconductor according to Example 1. FIG. 実施例１による炭化珪素半導体の製造工程における終端領域断面図である。5 is a cross-sectional view of a termination region in the manufacturing process of the silicon carbide semiconductor according to Example 1. FIG. 実施例１による炭化珪素半導体の製造工程における終端領域断面図である。5 is a cross-sectional view of a termination region in the manufacturing process of the silicon carbide semiconductor according to Example 1. FIG. 実施例１の炭化珪素半導体の製造工程を説明する終端領域断面図である。3 is a cross-sectional view of a termination region for explaining a manufacturing process of a silicon carbide semiconductor of Example 1. FIG. 図１６に続く製造工程を説明する終端領域断面図である。FIG. 17 is a cross-sectional view of a termination region illustrating a manufacturing process following FIG. 16. 図１７に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 18 is a sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 17; 図１７に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 18 is a sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 17; 実施例２の炭化珪素半導体装置の製造工程を説明する終端領域断面図である。FIG. 10 is a termination region cross-sectional view illustrating a manufacturing process of a silicon carbide semiconductor device of Example 2. 図２０に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 21 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 20. 実施例２の炭化珪素半導体装置のリング２０５の拡大図である。FIG. 6 is an enlarged view of a ring 205 of the silicon carbide semiconductor device of Example 2. 実施例３の炭化珪素半導体装置の終端領域断面図である。FIG. 12 is a cross-sectional view of a termination region of the silicon carbide semiconductor device of Example 3. 実施例３の炭化珪素半導体装置の製造工程における終端領域断面図である。FIG. 12 is a cross-sectional view of a termination region in the manufacturing process of the silicon carbide semiconductor device of Example 3. 実施例４の炭化珪素半導体装置の終端領域断面図である。12 is a cross-sectional view of a termination region of the silicon carbide semiconductor device of Example 4. FIG. 実施例４による炭化珪素半導体装置の製造工程における終端領域断面図である。FIG. 12 is a cross-sectional view of a termination region in the process for manufacturing a silicon carbide semiconductor device according to Example 4; 図２６に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 27 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 26. 図２７に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 28 is a sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 27. 実施例５の炭化珪素半導体装置の終端領域断面図である。10 is a sectional view of a termination region of a silicon carbide semiconductor device of Example 5. FIG. 実施例５の炭化珪素半導体装置の製造工程を説明する終端領域断面図である。10 is a cross-sectional view of a termination region illustrating a manufacturing process for a silicon carbide semiconductor device of Example 5. FIG. 図３０に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 31 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 30. 図３１に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 32 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 31. 実施例６の炭化珪素半導体装置の終端領域断面図である。12 is a sectional view of a termination region of a silicon carbide semiconductor device of Example 6. FIG. 実施例６の製造工程を説明する終端領域断面図である。10 is a sectional view of a termination region, illustrating a manufacturing process according to Example 6. FIG. 図３４に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 35 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 34. 実施例７の炭化珪素半導体装置の終端領域断面図である。12 is a sectional view of a termination region of a silicon carbide semiconductor device of Example 7. FIG. 実施例７の製造工程における終端領域断面図である。12 is a sectional view of a termination region in the manufacturing process of Example 7. FIG. 図３７に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 38 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 37. 図３８に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 39 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 38. 図３９に続く製造工程を説明する炭化珪素半導体装置の終端領域断面図である。FIG. 40 is a cross-sectional view of a termination region of the silicon carbide semiconductor device, illustrating a manufacturing process following FIG. 39;
　以下の実施の形態で用いる図面においては、平面図であっても図面を見易くするためにハッチングを付す場合もある。また、以下の実施の形態を説明するための全図において、同一機能を有するものは原則として同一の符号を付し、その繰り返しの説明は省略する。以下、本発明の実施の形態を図面に基づいて詳細に説明する。 In the drawings used in the following embodiments, even a plan view may be hatched to make the drawings easy to see. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
［デバイス構造］
　実施例１の炭化珪素半導体装置について図１～図７を用いて説明する。図１は炭化珪素半導体装置の要部上面図、図２は実施例１の炭化珪素半導体装置の終端領域断面図、図３は実施例１の炭化珪素半導体装置の別構造における終端領域断面図、図４は実施例１の炭化珪素半導体装置の終端領域断面の詳細図、図５は図４におけるリングの不純物濃度について示した図、図６は実施例１の炭化珪素半導体装置の終端領域におけるコーナー部とライン部の断面図、図７は実施例１の炭化珪素半導体装置の終端領域の一部を拡大して示す模式断面図である。 [Device structure]
A silicon carbide semiconductor device of Example 1 will be described with reference to FIGS. 1 is a top view of a principal part of a silicon carbide semiconductor device, FIG. 2 is a sectional view of a termination region of the silicon carbide semiconductor device of Example 1, and FIG. 3 is a sectional view of a termination region in another structure of the silicon carbide semiconductor device of Example 1. 4 is a detailed view of a cross section of the termination region of the silicon carbide semiconductor device of Example 1, FIG. 5 is a diagram showing the impurity concentration of the ring in FIG. 4, and FIG. 6 is a corner in the termination region of the silicon carbide semiconductor device of Example 1. FIG. 7 is a schematic cross-sectional view showing a part of the termination region of the silicon carbide semiconductor device of Example 1 in an enlarged manner.
　図１に示すように、炭化珪素半導体装置１は、ダイオードやトランジスタが配置される炭化珪素半導体装置の中央のアクティブ領域２と、平面視においてアクティブ領域２を囲む終端領域に、ｐ型のウェル領域１０６と、互いに同心となるように多重に複数配置されたｐ型フローティング・フィールド・リミッティング・リング（以下、リングと記す）１０５と、さらに平面視において上記リング１０５を囲むｎ＋型のリング領域であるチャネルストッパ１０７がある。 As shown in FIG. 1, silicon carbide semiconductor device 1 includes a p-type well region in an active region 2 at the center of a silicon carbide semiconductor device in which a diode and a transistor are arranged, and a terminal region surrounding active region 2 in plan view. 106, a plurality of p-type floating field limiting rings (hereinafter, referred to as rings) 105 that are arranged in multiple concentric positions, and an n + -type ring region that surrounds the ring 105 in plan view There is a channel stopper 107.
　オフ時において、最大電界部分が順次外側のｐ型のリング１０５へ移り、最外周のリング１０５で降伏するようになるので、炭化珪素半導体装置を高耐圧とすることが可能となる。図１を用いて３重のリング１０５が形成されている例を図示しているが、本発明はこれに限定されるものではない。 When off, the maximum electric field portion sequentially moves to the outer p-type ring 105 and yields at the outermost ring 105, so that the silicon carbide semiconductor device can have a high breakdown voltage. Although the example in which the triple ring 105 is formed is illustrated using FIG. 1, the present invention is not limited to this.
　次に、本実施例１による炭化珪素半導体装置の構造を、図２を用いて説明する。 Next, the structure of the silicon carbide semiconductor device according to the first embodiment will be described with reference to FIG.
　ＳｉＣ基板１０１の裏面（第２主面）には電極１０４が形成されている。 An electrode 104 is formed on the back surface (second main surface) of the SiC substrate 101.
　ＳｉＣからなるｎ＋型のＳｉＣ基板１０１の表面（第１主面）上に、ＳｉＣ基板１０１よりも不純物濃度の低いＳｉＣからなるｎ－型のエピタキシャル層１０２が形成されている。ｎ＋型のＳｉＣ基板１０１とｎ－型のエピタキシャル層１０２の厚さを、５～２０μｍの範囲内で設定されている。 An n − type epitaxial layer 102 made of SiC having an impurity concentration lower than that of the SiC substrate 101 is formed on the surface (first main surface) of the n + type SiC substrate 101 made of SiC. The thicknesses of the n + type SiC substrate 101 and the n − type epitaxial layer 102 are set in the range of 5 to 20 μm.
　ｎ－型のエピタキシャル層１０２内にはｐ型のリング１０５が形成されている。リング１０５のエピタキシャル層１０２の表面からの深さは、０．５～２．０μｍの範囲内で設定され、リング１０５間の距離は０．５～２．５μｍの範囲内で設定されている。図３に示してあるように、リング１０５間の各距離は必ずしも一定である必要はない。図３は、図２のウェル領域１０６とチャネルストッパ１０７との間の距離を保ちながら、リング１０５同士の間隔を変えた構造を示している。具体的には、内側のリング１０５間距離を狭め、外側のリング１０５間距離を広げることで耐圧を更に向上させる構造としている。なお、チャネルストッパと最外周のリング１０５との距離も縮めることで、ｐ型ウェル領域１０６とリング間距離、リング１０５同士の距離、チャネルストッパ１０７と最外周のリング１０５との距離のうち、外側のリング１０５間距離が最も大きくなっている。 A p-type ring 105 is formed in the n − -type epitaxial layer 102. The depth of the ring 105 from the surface of the epitaxial layer 102 is set within a range of 0.5 to 2.0 μm, and the distance between the rings 105 is set within a range of 0.5 to 2.5 μm. As shown in FIG. 3, the distances between the rings 105 do not necessarily have to be constant. FIG. 3 shows a structure in which the distance between the rings 105 is changed while maintaining the distance between the well region 106 and the channel stopper 107 in FIG. Specifically, the pressure resistance is further improved by narrowing the distance between the inner rings 105 and widening the distance between the outer rings 105. In addition, by reducing the distance between the channel stopper and the outermost ring 105, the distance between the p-type well region 106 and the ring, the distance between the rings 105, and the distance between the channel stopper 107 and the outermost ring 105 is outside. The distance between the rings 105 is the largest.
　ｎ－型のエピタキシャル層１０２のリング１０５の内側にはｐ型のウェル領域１０６が形成されている。ｐ型のウェル領域１０６のエピタキシャル層１０２の表面からの深さは、０．５～２．０μｍの範囲内で設定されている。 A p-type well region 106 is formed inside the ring 105 of the n − -type epitaxial layer 102. The depth of the p-type well region 106 from the surface of the epitaxial layer 102 is set within a range of 0.5 to 2.0 μm.
　リング１０５とウェル領域１０６とは個別に深さを設定可能であるが、同じ深さに設定する場合、同じ工程で同時に形成することができるのは言うまでもない。 The depth of the ring 105 and the well region 106 can be set individually, but it goes without saying that when the same depth is set, they can be formed simultaneously in the same process.
　リング１０５の外側には、ｎ－型のエピタキシャル層１０２内にはｎ＋型の平面視形状がリング状であるチャネルストッパ１０７が形成されている。チャネルストッパ１０７のエピタキシャル層１０２の表面からの深さは、０．５～２μｍの範囲内で設定されている。 On the outside of the ring 105, a channel stopper 107 having an n + type planar view shape in a ring shape is formed in the n − type epitaxial layer 102. The depth of the channel stopper 107 from the surface of the epitaxial layer 102 is set within a range of 0.5 to 2 μm.
　なお、ここまでの説明で用いた「－」および「＋」は、導電型がｎ型またはｐ型の相対的な不純物濃度を表記した符号である。「ｎ－」、「ｎ」、「ｎ＋」の順にｎ型不純物の不純物濃度は高くなる。ｎ＋型のＳｉＣ基板１０１の不純物濃度の好ましい範囲は、１×１０１８～１×１０２１ｃｍ－３、ｎ－型のエピタキシャル層１０２の不純物濃度の好ましい範囲は、１×１０１４～１×１０１７ｃｍ－３、リング１０５及びｐ型のウェル領域は、１×１０１６～１×１０１９ｃｍ－３、ｎ＋型のチャネルストッパ１０７は、１×１０１９～１×１０２１ｃｍ－３の範囲内で設定されている。 Note that “ − ” and “ + ” used in the description so far are symbols representing the relative impurity concentration of n-type or p-type conductivity. The impurity concentration of the n-type impurity increases in the order of “n − ”, “n”, and “n + ”. The preferable range of the impurity concentration of the n + -type SiC substrate 101 is 1 × 10 18 to 1 × 10 21 cm −3 , and the preferable range of the impurity concentration of the n − -type epitaxial layer 102 is 1 × 10 14 to 1 ×. 10 17 cm −3 , the ring 105 and the p-type well region are 1 × 10 16 to 1 × 10 19 cm −3 , and the n + -type channel stopper 107 is 1 × 10 19 to 1 × 10 21 cm −3. Is set within the range.
　図４に示すように、リング１０５は不純物濃度が濃い高濃度領域１０５ａと、高濃度領域１０５ａを挟み込む不純物濃度が低い低濃度領域１０５ｂで構成されている。より詳細な構造を示すと、図７に示すようになっている。リング１０５の高濃度領域１０５ａの表面の位置は、リング１０５の低濃度領域及びリング１０５が形成されないｎ－型のエピタキシャル層の表面の位置よりも、０．０５μｍ低くなっている。これは、リング１０５の高濃度領域１０５ａを形成する際のエッチング工程において、表面を削ることにより形成されるものである。 As shown in FIG. 4, the ring 105 includes a high concentration region 105a having a high impurity concentration and a low concentration region 105b having a low impurity concentration sandwiching the high concentration region 105a. A more detailed structure is shown in FIG. The position of the surface of the high concentration region 105a of the ring 105 is 0.05 μm lower than the position of the surface of the low concentration region of the ring 105 and the n − type epitaxial layer where the ring 105 is not formed. This is formed by scraping the surface in the etching step when forming the high concentration region 105a of the ring 105.
　図５のグラフは、縦軸にリング１０５の不純物濃度、横軸にリング１０５の幅をとったものである。図５に示すようにその濃度分布はリングの中央で最も濃くなり（高濃度領域１０５ａ）、リング１０５の周辺部にいくにしたがって徐々に薄くなる（低濃度領域１０５ｂ）。本実施例では、リング中央部の高濃度領域１０５ａの不純物濃度は、１×１０１７～１×１０１８ｃｍ－３、リング周辺部の低濃度領域１０５ｂの不純物濃度は、１×１０１５～２×１０１７ｃｍ－３になっている。 In the graph of FIG. 5, the vertical axis represents the impurity concentration of the ring 105, and the horizontal axis represents the width of the ring 105. As shown in FIG. 5, the concentration distribution becomes the darkest at the center of the ring (high concentration region 105a), and gradually decreases toward the periphery of the ring 105 (low concentration region 105b). In the present embodiment, the impurity concentration of the high concentration region 105a at the center of the ring is 1 × 10 17 to 1 × 10 18 cm −3 , and the impurity concentration of the low concentration region 105b at the periphery of the ring is 1 × 10 15 to 2 × 10 17 cm -3
　図６に示すように、リング１０５のコーナー部における低濃度領域１０５ｂと、リング１０５のライン部における低濃度領域１０５ｂではリング１０５のコーナー部における低濃度領域１０５ｂの方が幅が大きくなっている。具体的には、ライン部のリング幅は実質的に一定であるが、ライン部とコーナー部との接続部から、コーナー部の中間にいくにしたがってリング１０５の幅は徐々に広くなり、リング１０５のコーナー部の最も中間で最も広くなっている。そして、コーナーブのリング幅の大きさはライン部のリング幅の１．３～１．６倍になっている。 As shown in FIG. 6, in the low concentration region 105b in the corner portion of the ring 105 and the low concentration region 105b in the line portion of the ring 105, the width of the low concentration region 105b in the corner portion of the ring 105 is larger. Specifically, the ring width of the line portion is substantially constant, but the width of the ring 105 gradually increases from the connecting portion between the line portion and the corner portion to the middle of the corner portion. It is widest in the middle of the corner. The corner ring has a ring width 1.3 to 1.6 times the ring width of the line portion.
　コーナー部とライン部では周辺部分の濃度も異なっている。具体的には、ライン部の低濃度領域１０５ｂの不純物濃度は実質的に一定であるが、ライン部とコーナー部との接続部から、コーナー部の中間にいくにしたがって低濃度領域１０５ｂの不純物濃度は徐々に薄くなり、リング１０５のコーナー部の最も中間で最も薄くなっている。リング１０５のコーナー部の中間点における濃度はライン部の概ね半分になっている。 The density of the peripheral part is different between the corner part and the line part. Specifically, although the impurity concentration in the low concentration region 105b in the line portion is substantially constant, the impurity concentration in the low concentration region 105b increases from the connection portion between the line portion and the corner portion to the middle of the corner portion. Is gradually thinner, and is the thinnest in the middle of the corner portion of the ring 105. The density at the midpoint of the corner portion of the ring 105 is approximately half that of the line portion.
　以上のように、本実施例によれば、ｐ型ウェル領域１０６にかかる電界集中が外側のリング１０５へと分散されやすくなっており、炭化珪素半導体装置を高耐圧にできる。 As described above, according to the present embodiment, the electric field concentration applied to the p-type well region 106 is easily dispersed to the outer ring 105, and the silicon carbide semiconductor device can have a high breakdown voltage.
　そして、以下の不純物の斜め注入による製造方法を採用可能になるので、再現性高く高耐圧の炭化珪素半導体装置を製造することも可能になる。
［炭化珪素半導体装置の製造方法］
　実施例１による炭化珪素半導体装置の製造方法について図８～図１９を用いて工程順に説明する。 Since the following manufacturing method by oblique implantation of impurities can be employed, it is possible to manufacture a silicon carbide semiconductor device with high reproducibility and high breakdown voltage.
[Method for Manufacturing Silicon Carbide Semiconductor Device]
A method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described in the order of steps with reference to FIGS.
　図１２は、実施例１の炭化珪素半導体装置の上面図で、図１のリング１０５を抜粋した図である。以下、リング１０５のコーナー部であるI―I線の断面に相当する断面図と、リング１０５のストライプ部であるII―II線の断面に相当する断面図を用いて、本実施例の炭化珪素半導体装置の製造方法を説明する。 FIG. 12 is a top view of the silicon carbide semiconductor device of Example 1, and is a diagram in which the ring 105 of FIG. 1 is extracted. Hereinafter, a silicon carbide according to the present embodiment will be described with reference to a cross-sectional view corresponding to a cross section taken along line II of the corner portion of the ring 105 and a cross-sectional view corresponding to a cross section taken along line II-II of the stripe portion of the ring 105. A method for manufacturing a semiconductor device will be described.
　まず、図８に示すように、４Ｈ－ＳｉＣ（炭化珪素）基板１０１を用意し、Ｓｉ面を上面とする。ＳｉＣ基板１０１としては、ｎ型不純物である窒素が導入されている基板を用いる。 First, as shown in FIG. 8, a 4H—SiC (silicon carbide) substrate 101 is prepared, and the Si surface is the upper surface. As the SiC substrate 101, a substrate into which nitrogen which is an n-type impurity is introduced is used.
　次に、ＳｉＣ基板１０１の表面（第１主面）にエピタキシャル成長法によりＳｉＣのｎ－型のエピタキシャル層１０２を形成する。エピタキシャル層１０２には、ＳｉＣ基板１０１の不純物濃度よりも低い濃度となるようにｎ型不純物が導入されている。エピタキシャル層１０２の不純物濃度は炭化珪素半導体装置の素子定格に依存するが、１×１０１４～１×１０１７ｃｍ－３の範囲で設定されている。また、エピタキシャル層１０２の厚さは、５～２０μｍの範囲で設定されている。以上の工程により、ＳｉＣ基板１０１およびエピタキシャル層１０２からなるＳｉＣエピタキシャル基板１０３が形成される。 Next, an SiC n − type epitaxial layer 102 is formed on the surface (first main surface) of the SiC substrate 101 by an epitaxial growth method. N-type impurities are introduced into epitaxial layer 102 so as to have a concentration lower than that of SiC substrate 101. The impurity concentration of epitaxial layer 102 depends on the element rating of the silicon carbide semiconductor device, but is set in the range of 1 × 10 14 to 1 × 10 17 cm −3 . The thickness of the epitaxial layer 102 is set in the range of 5 to 20 μm. Through the above steps, SiC epitaxial substrate 103 composed of SiC substrate 101 and epitaxial layer 102 is formed.
　次に、図９に示すように、エピタキシャル層１０２の表面上に、プラズマＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法により絶縁膜を堆積する。実施例ではＳｉＯ２膜１０９を堆積する。ＳｉＯ２膜１０９の厚さは、１～３μｍの範囲で設定されている。 Next, as shown in FIG. 9, an insulating film is deposited on the surface of the epitaxial layer 102 by a plasma CVD (Chemical Vapor Deposition) method. In the embodiment, a SiO 2 film 109 is deposited. The thickness of the SiO 2 film 109 is set in the range of 1 to 3 μm.
　続いて、図１０に示すようにレジストパターンをマスクとして、ＳｉＯ２膜１０９をドライエッチング法により加工することにより、ハードマスクパターン１０９ａをエピタキシャル層１０２の表面上に形成する。リング１０５に対応したハードマスクパターン１０９ａの幅は、１～２．５μｍの範囲で設定されている。この際、前述の図７を用いて説明したように、エピタキシャル層１０２の表面が数ｎｍ（５ｎｍ以下）削れて、ハードマスクパターン１０９ａの側面下のエピタキシャル層１０２に第１段差が形成される（図１０では図示せず）。 Subsequently, as shown in FIG. 10, the hard mask pattern 109 a is formed on the surface of the epitaxial layer 102 by processing the SiO 2 film 109 by a dry etching method using the resist pattern as a mask. The width of the hard mask pattern 109a corresponding to the ring 105 is set in the range of 1 to 2.5 μm. At this time, as described with reference to FIG. 7, the surface of the epitaxial layer 102 is shaved by several nm (5 nm or less), and a first step is formed in the epitaxial layer 102 below the side surface of the hard mask pattern 109a (see FIG. (Not shown in FIG. 10).
　次に、エピタキシャル層１０２にｐ型不純物をイオン注入する。実施例では、ｐ型不純物としてＡｌを用いた。これにより、エピタキシャル層１０２のリング１０５を形成する。 Next, p-type impurities are ion-implanted into the epitaxial layer 102. In the examples, Al was used as the p-type impurity. Thereby, the ring 105 of the epitaxial layer 102 is formed.
　図１１は図１２のI―I線の断面に相当する断面図とII―IIに相当する断面図である。図１２に示してある、Ｎ１、Ｎ２、Ｎ３、Ｎ４の方向から計４回、基板の法線から角度をつけて斜め不純物注入する。ここで、Ｎ１、Ｎ２、Ｎ３、Ｎ４は、リング１０５のライン部から４５度傾いている。また、斜め不純物注入時の角度（仰角）は、ＳｉＣエピタキシャル基板１０３の法線方向から１０～４５度（仰角４５～８０度）である。リング１０５のエピタキシャル層１０２の表面からの深さは、０．５～２μｍの範囲内で設定されている。 FIG. 11 is a cross-sectional view corresponding to the cross section taken along line II of FIG. 12 and a cross-sectional view corresponding to II-II. The oblique impurity implantation is performed four times in total from the directions of N1, N2, N3, and N4 shown in FIG. 12 and at an angle from the normal line of the substrate. Here, N1, N2, N3, and N4 are inclined 45 degrees from the line portion of the ring 105. The angle (elevation angle) at the time of oblique impurity implantation is 10 to 45 degrees (elevation angle 45 to 80 degrees) from the normal direction of SiC epitaxial substrate 103. The depth of the ring 105 from the surface of the epitaxial layer 102 is set in the range of 0.5 to 2 μm.
　ここで、図１３～図１６を用いて、斜め不純物注入によって図６のように、リング１０５のコーナー部とリング１０５のライン部で低濃度領域１０５ｂの幅・濃度を異ならしめる工程を説明する。 Here, using FIG. 13 to FIG. 16, a process of making the width / concentration of the low concentration region 105b different between the corner portion of the ring 105 and the line portion of the ring 105 by oblique impurity implantation as shown in FIG.
　図１３は図１２のＮ１方向から不純物注入したときのｐ型不純物分布である。本注入工程によるリングのみを示すとリング１０５ｃとなる。Ｎ１方向は、平面視した際にリング１０５の縦ラインから右４５度傾けた図の右上に向かう方向であるので、ハードマスクパターン１０９ａを右上方向にずらした領域に不純物が注入される。なお、リング１０５のコーナー部であるI―I断面での不純物の横方向への広がりとリング１０５のライン部であるII―II断面での不純物の横方向への広がりは異なり、コーナー部の方が大きく広がる。 FIG. 13 shows a p-type impurity distribution when impurities are implanted from the N1 direction of FIG. If only the ring by this injection process is shown, it will be the ring 105c. Since the N1 direction is a direction toward the upper right in the figure inclined 45 degrees to the right from the vertical line of the ring 105 when viewed in plan, impurities are implanted into a region where the hard mask pattern 109a is shifted in the upper right direction. In addition, the lateral spread of impurities in the II section, which is the corner portion of the ring 105, and the lateral spread of impurities in the II-II section, which is the line portion of the ring 105, are different. Will spread greatly.
　図１４は図１２のＮ２方向から不純物注入したときのｐ型不純物分布である。本注入工程によるリングのみを示すとリング１０５ｄとなる。Ｎ２方向は、平面視した際にリング１０５の縦ラインから左１３５度傾けた図の左下に向かう方向であるので、ハードマスクパターン１０９ａを左下方向にずらした領域に不純物が注入される。なお、リング１０５のコーナー部であるI―I断面での不純物の横方向への広がりとリング１０５のライン部であるII―II断面での不純物の横方向への広がりは異なり、コーナー部の方が大きく広がる。 FIG. 14 shows a p-type impurity distribution when impurities are implanted from the N2 direction of FIG. If only the ring by this injection process is shown, it will be the ring 105d. The N2 direction is a direction from the vertical line of the ring 105 toward the lower left in the figure tilted 135 degrees to the left when viewed in plan, so that the impurity is implanted into a region where the hard mask pattern 109a is shifted to the lower left. In addition, the lateral spread of impurities in the II section, which is the corner portion of the ring 105, and the lateral spread of impurities in the II-II section, which is the line portion of the ring 105, are different. Will spread greatly.
　図１５は図１２のＮ３方向から不純物注入したときのｐ型不純物分布である。本注入工程によるリングのみを示すとリング１０５ｅとなる。Ｎ３方向は、平面視した際にリング１０５の縦ラインから右１３５度傾けた図の右下に向かう方向であるので、ハードマスクパターン１０９ａを右下方向にずらした領域に不純物が注入される。なお、リング１０５のコーナー部であるI―I断面での不純物の横方向への広がりとリング１０５のライン部であるII―II断面での不純物の横方向への広がりは異なり、コーナー部の方が大きく広がる。 FIG. 15 is a p-type impurity distribution when impurities are implanted from the N3 direction of FIG. If only the ring by this injection process is shown, it will be the ring 105e. The N3 direction is a direction from the vertical line of the ring 105 toward the lower right in the drawing inclined 135 degrees to the right in the plan view, so that impurities are implanted into a region where the hard mask pattern 109a is shifted to the lower right. In addition, the lateral spread of impurities in the II section, which is the corner portion of the ring 105, and the lateral spread of impurities in the II-II section, which is the line portion of the ring 105, are different. Will spread greatly.
　図１６は図１２のＮ４方向から不純物注入したときのｐ型不純物分布である。本注入工程によるリングのみを示すとリング１０５ｆとなる。Ｎ３方向は、平面視した際にリング１０５の縦ラインから左４５傾けた図の左上に向かう方向であるので、ハードマスクパターン１０９ａを左上方向にずらした領域に不純物が注入される。なお、リング１０５のコーナー部であるI―I断面での不純物の横方向への広がりとリング１０５のライン部であるII―II断面での不純物の横方向への広がりは異なり、コーナー部の方が大きく広がる。 FIG. 16 shows a p-type impurity distribution when impurities are implanted from the N4 direction of FIG. If only the ring by this injection process is shown, it will be the ring 105f. Since the N3 direction is a direction from the vertical line of the ring 105 toward the upper left in the drawing when viewed in plan, an impurity is implanted into a region where the hard mask pattern 109a is shifted in the upper left direction. In addition, the lateral spread of impurities in the II section, which is the corner portion of the ring 105, and the lateral spread of impurities in the II-II section, which is the line portion of the ring 105, are different. Will spread greatly.
　以上、４つの斜め不純物工程を経ると、リング１０５ｃ～ｆを重ね打ちしたことになるので、図１１に示す高濃度領域１０５ａと低濃度領域１０５ｂを有するリング１０５が形成される。なお、リング１０５のコーナー部（Ｉ－Ｉ断面）における高濃度領域１０５ａを挟むようにリング内外に配置された低濃度領域１０５ｂにおける不純物濃度は不純物注入１回分であるのに対し、リング１０５のライン部（II―II断面）における低濃度領域１０５ｂの不純物濃度は不純物注入２回分である。つまり、リング１０５のコーナー部の低濃度領域１０５ｂは、リング１０５のライン部の低濃度領域１０５ｂの半分の濃度となる。また、リング１０５のコーナー部の低濃度領域１０５ｂの広がりは、注入角度を４５度にしているため、リング１０５のライン部の低濃度領域１０５ｂの広がりの最大１／√２となる。さらに、高濃度領域１０５ａの濃度を高める場合には、斜め注入の他に垂直注入を組み合わせる。 As described above, when the four oblique impurity steps are performed, the rings 105c to 105f are overlapped, so that the ring 105 having the high concentration region 105a and the low concentration region 105b shown in FIG. 11 is formed. The impurity concentration in the low concentration region 105b arranged inside and outside the ring so as to sandwich the high concentration region 105a in the corner portion (II cross section) of the ring 105 is one impurity implantation, whereas the line of the ring 105 The impurity concentration of the low concentration region 105b in the portion (II-II cross section) is equivalent to two impurity implantations. That is, the low concentration region 105 b at the corner portion of the ring 105 has half the concentration of the low concentration region 105 b at the line portion of the ring 105. Further, the spread of the low concentration region 105b at the corner portion of the ring 105 is 1 / √2 at the maximum of the spread of the low concentration region 105b at the line portion of the ring 105 because the implantation angle is 45 degrees. Further, in order to increase the concentration of the high concentration region 105a, vertical implantation is combined in addition to oblique implantation.
　なお、リング１０５の高濃度領域１０５ａの不純物濃度は１×１０１６～１×１０１９ｃｍ－３、低濃度領域１０５ｂの不純物濃度は１×１０１５～１×１０１８ｃｍ－３で設定されている。 The impurity concentration of the high concentration region 105a of the ring 105 is set to 1 × 10 16 to 1 × 10 19 cm −3 , and the impurity concentration of the low concentration region 105b is set to 1 × 10 15 to 1 × 10 18 cm −3. Yes.
　また、図１７に示すように、ウェル領域１０６を、斜め不純物注入によるリング１０５形成と同時に形成する場合、高濃度領域１０６ａの外側に低濃度領域１０６ｂが形成される。そして、この低濃度領域１０６ｂはウェル領域１０６のハードマスクパターン１０９ａの開口が大きいため、リング１０５の低濃度領域１０５ｂよりも幅が広くなる。高濃度領域１０６ａの濃度をさらに高める場合には、垂直注入を組み合わせる。なお、ウェル領域１０６の不純物濃度は、１×１０１６～１×１０１９ｃｍ－３の範囲で設定されている。 As shown in FIG. 17, when the well region 106 is formed simultaneously with the formation of the ring 105 by the oblique impurity implantation, the low concentration region 106b is formed outside the high concentration region 106a. The low concentration region 106b is wider than the low concentration region 105b of the ring 105 because the opening of the hard mask pattern 109a in the well region 106 is large. In order to further increase the concentration of the high concentration region 106a, vertical implantation is combined. The impurity concentration of the well region 106 is set in the range of 1 × 10 16 to 1 × 10 19 cm −3 .
　なお、図１８に示すように、ウェル領域１０６を斜め不純物注入によるリング１０５形成と別に形成する場合、ハードマスクパターン１０９ｂをマスクとして、不純物を垂直注入する。 As shown in FIG. 18, when the well region 106 is formed separately from the formation of the ring 105 by oblique impurity implantation, impurities are vertically implanted using the hard mask pattern 109b as a mask.
　次に、図１９に示すように、ハードマスクパターン１０９ｃをマスクとして、エピタキシャル層１０２にｎ型不純物として窒素をイオン注入して、ｎ＋型のチャネルストッパ１０７を形成する。チャネルストッパ１０７の不純物濃度は、１×１０１９～１×１０２１ｃｍ－３の範囲で設定されている。 Next, as shown in FIG. 19, using the hard mask pattern 109 c as a mask, nitrogen is ion-implanted as an n-type impurity into the epitaxial layer 102 to form an n + -type channel stopper 107. The impurity concentration of the channel stopper 107 is set in the range of 1 × 10 19 to 1 × 10 21 cm −3 .
　実施例１の製造方法によれば、リング１０５を不純物の斜め注入で形成した結果、リング１０５のコーナー部での不純物の広がりが大きくなるので、不純物の垂直注入よりも、電界が緩和されやすくなる。さらに、１枚のハードマスクで実現可能なので、マスクの位置ズレがなく再現性が高い。 According to the manufacturing method of the first embodiment, as a result of forming the ring 105 by oblique implantation of impurities, the spread of the impurities at the corners of the ring 105 becomes larger, so that the electric field is more easily relaxed than the vertical implantation of impurities. . Furthermore, since it can be realized with a single hard mask, the reproducibility is high with no mask displacement.
　実施例２と前述した実施例１との相違点は、リング２０５を斜め不純物注入で形成せず、２回以上の不純物注入工程で形成することである。 The difference between the second embodiment and the first embodiment described above is that the ring 205 is not formed by oblique impurity implantation but is formed by two or more impurity implantation steps.
　実施例２による炭化珪素半導体装置の製造方法について図２０～図２２を用いて工程順に説明する。 A method for manufacturing a silicon carbide semiconductor device according to Example 2 will be described in the order of steps with reference to FIGS.
　前述した実施例１と同様にして、ｎ＋型のＳｉＣ基板１０１の表面（第１主面）上にｎ－型のエピタキシャル層１０２を形成して、ＳｉＣ基板１０１とエピタキシャル層１０２とからなるＳｉＣエピタキシャル基板１０３を形成する。ＳｉＣ基板１０１の不純物濃度は、１×１０１８～１×１０２１ｃｍ－３の範囲で設定されており、エピタキシャル層１０２の不純物濃度は、１×１０１４～１×１０１７ｃｍ－３の範囲で設定されている。 In the same manner as in Example 1 described above, an n − type epitaxial layer 102 is formed on the surface (first main surface) of the n + type SiC substrate 101, and an SiC epitaxial layer comprising the SiC substrate 101 and the epitaxial layer 102 is formed. A substrate 103 is formed. The impurity concentration of the SiC substrate 101 is set in the range of 1 × 10 18 to 1 × 10 21 cm −3 , and the impurity concentration of the epitaxial layer 102 is in the range of 1 × 10 14 to 1 × 10 17 cm −3 . Is set in
　次に、図２０に示すように、ＳｉＯ２膜からなるハードマスクパターン２０９ａをマスクとして、エピタキシャル層１０２にｐ型不純物、Ａｌをイオン注入する。これにより、低濃度領域２０５ｂを形成する。このとき、隣り合うハードマスクパターン２０９ａの距離（開口幅）はライン部よりもコーナー部のほうが広く、ライン部で一定にとした開口幅がライン部とコーナー部との接続部からコーナー部の中間点に向かって広くなっている。この低濃度領域２０５ｂの不純物濃度は、１×１０１５～２×１０１７ｃｍ－３の範囲である。なお、上記ハードマスクパターン２０９ａをエピタキシャル層１０２の表面上に形成する際には、前述した実施例１と同様に、エピタキシャル層１０２の表面が１～５ｎｍ削れて、ハードマスクの側面下のエピタキシャル層１０２に第１段差が形成される。 Next, as shown in FIG. 20, p-type impurities and Al are ion-implanted into the epitaxial layer 102 using the hard mask pattern 209a made of the SiO 2 film as a mask. Thereby, the low concentration region 205b is formed. At this time, the distance (opening width) between the adjacent hard mask patterns 209a is wider in the corner portion than in the line portion, and the opening width that is constant in the line portion is intermediate between the connecting portion between the line portion and the corner portion. Widening towards the point. The impurity concentration of the low concentration region 205b is in the range of 1 × 10 15 to 2 × 10 17 cm −3 . When the hard mask pattern 209a is formed on the surface of the epitaxial layer 102, the surface of the epitaxial layer 102 is shaved by 1 to 5 nm as in the first embodiment, and the epitaxial layer below the side surface of the hard mask is formed. A first step is formed at 102.
　次に、図２１に示すように、ハードマスクパターン２０９ａよりハードマスク間の幅が狭い、ＳｉＯ２膜からなるハードマスクパターン２０９ｂをマスクとして、エピタキシャル層１０２にｐ型不純物であるＡｌを注入する。この高濃度領域２０５ａの不純物濃度は、１×１０１７～１×１０１８ｃｍ－３の範囲内で設定されている。これにより、低濃度領域２０５ｂの内側に高濃度領域２０５ａを形成する。この工程により、低濃度領域２０５ｂは高濃度領域２０５ａを挟むように配置されたことになる。 Next, as shown in FIG. 21, Al, which is a p-type impurity, is implanted into the epitaxial layer 102 using a hard mask pattern 209b made of a SiO 2 film whose width between the hard masks is narrower than that of the hard mask pattern 209a. The impurity concentration of the high concentration region 205a is set within the range of 1 × 10 17 to 1 × 10 18 cm −3 . Thereby, the high concentration region 205a is formed inside the low concentration region 205b. By this step, the low concentration region 205b is arranged so as to sandwich the high concentration region 205a.
　なお、上記ハードマスクパターン２をエピタキシャル層１０２の表面上に形成する際には、前述した第１段差と同様に、エピタキシャル層１０２の表面が１～５ｎｍ削れて、ハードマスクの側面下のエピタキシャル層１０２に第２段差が形成される（図２２参照）。 When the hard mask pattern 2 is formed on the surface of the epitaxial layer 102, the surface of the epitaxial layer 102 is shaved by 1 to 5 nm as in the first step, and the epitaxial layer below the side surface of the hard mask is formed. A second step is formed at 102 (see FIG. 22).
　次に、ハードマスクパターン２０９ｃをマスクとして、エピタキシャル層２０３にｐ型不純物、Ａｌをイオン注入することで、ウェル領域２０６を形成する（図は省略）。ウェル領域２０６の不純物濃度は、１×１０１６～１×１０１９ｃｍ－３の範囲である。なお、ウェル領域２０６は、リング２０５と同時に形成してもかまわない。また、ウェル領域２０６は、リング２０５と同時に２回以上の露光工程で形成してもかまわない。 Next, a well region 206 is formed by ion-implanting p-type impurities and Al into the epitaxial layer 203 using the hard mask pattern 209c as a mask (not shown). The impurity concentration of the well region 206 is in the range of 1 × 10 16 to 1 × 10 19 cm −3 . Note that the well region 206 may be formed simultaneously with the ring 205. Further, the well region 206 may be formed in two or more exposure steps simultaneously with the ring 205.
　次に、別のハードマスクパターンをマスクとして、エピタキシャル層１０２にｎ型不純物、窒素をイオン注入して、ｎ＋型のリングを形成する（図は省略）。ｎ型リングの不純物濃度は、１×１０１９～１×１０２１ｃｍ－３の範囲で設定してある。 Next, using another hard mask pattern as a mask, n-type impurities and nitrogen are ion-implanted into the epitaxial layer 102 to form an n + -type ring (not shown). The impurity concentration of the n-type ring is set in the range of 1 × 10 19 to 1 × 10 21 cm −3 .
　以上が２回の露光での製造方法であるが、リング形成時のハードマスクパターンを増やすことで、２回以上の露光でリングを形成してもかまわない。 Although the above is a manufacturing method with two exposures, a ring may be formed with two or more exposures by increasing the number of hard mask patterns during ring formation.
　本実施例２による炭化珪素半導体装置では、２つのハードマスクパターンで垂直に不純物注入するため、実施例１の斜めイオン注入とは異なり、最終的な低濃度領域２０５ｂの幅・不純物濃度を任意に設定できる。 In the silicon carbide semiconductor device according to the second embodiment, since impurities are implanted vertically with two hard mask patterns, unlike the oblique ion implantation of the first embodiment, the final width and impurity concentration of the low concentration region 205b can be arbitrarily set. Can be set.
　実施例３と前述した実施例１との相違点は、ウェル領域内３０６に、ｐ＋型の補助リング３１０を形成することである。 The difference between the third embodiment and the first embodiment described above is that a p + -type auxiliary ring 310 is formed in the well region 306.
　図２３に示すように、ウェル領域内に、ｐ＋型の補助リング３１０が形成されている。ｐ＋型の補助リング３１０のエピタキシャル層１０２の表面からの深さは、０．１～０．５μｍの範囲で設定してある。ｐ＋型の補助リング３１０の不純物濃度は、１×１０１９～１×１０２１ｃｍ－３の範囲で設定されている。 As shown in FIG. 23, a p + -type auxiliary ring 310 is formed in the well region. The depth of the p + -type auxiliary ring 310 from the surface of the epitaxial layer 102 is set in the range of 0.1 to 0.5 μm. The impurity concentration of the p + -type auxiliary ring 310 is set in the range of 1 × 10 19 to 1 × 10 21 cm −3 .
　ｐ＋型の補助リング３１０は図２４に示す工程にて形成される。ＳｉＯ２膜からなるハードマスク３０９ａをパターンとして、エピタキシャル層１０２にｐ型不純物、Ａｌを注入する。なお、リング１０５の形成、チャネルストッパ１０７の形成は、実施例１と同様である。 The p + type auxiliary ring 310 is formed by the process shown in FIG. A p-type impurity, Al, is implanted into the epitaxial layer 102 using the hard mask 309a made of the SiO 2 film as a pattern. The formation of the ring 105 and the channel stopper 107 are the same as in the first embodiment.
　このように、実施例３によれば、ｐ型ウェル領域３０６の濃度が薄くｐ型ウェル領域３０６内を空乏層が伸びていくときでも、不純物濃度の大きいｐ＋型の補助リング３１０によってウェル領域３０６内における空乏層の伸びがとまる。つまり、ウェル領域３０６における破壊が生じにくくなるため、アクティブ領域の終端構造に対してロバストとなる。 Thus, according to the third embodiment, even when the concentration of the p-type well region 306 is low and the depletion layer extends in the p-type well region 306, the well region is formed by the p + -type auxiliary ring 310 having a high impurity concentration. The elongation of the depletion layer in 306 stops. That is, the breakdown in the well region 306 is less likely to occur, so that it is robust against the termination structure of the active region.
　実施例４と前述した実施例１との相違点は、ｐ型のリングの深さが、リングによって異なることである。アクティブ領域に近いリングは浅く形成され、アクティブ領域から遠ざかるにつれて深く形成される。 The difference between Example 4 and Example 1 described above is that the depth of the p-type ring differs depending on the ring. The ring close to the active region is formed shallow and formed deeper as the distance from the active region increases.
　実施例４における炭化珪素半導体装置の構成の特徴を、図２５を用いて説明する。図２５は炭化珪素半導体装置の終端領域の断面図を示したものである。リング４０５の形成深さがアクティブ領域から遠ざかるにしたがって深くなっている。各リング４０５の深さは、０．５～４．０μｍで設定してある。リング４０５ｇの外側隣のリング４０５ｈの深さは第１リング以上、リング４０５ｈの外側隣のリング４０５ｉの深さはリング４０５ｈ以上となるように、アクティブ領域側のリングよりも外側のリングのうほうが深くなるように形成される。従って、よりロバストなターミネーションを形成することができる。 The characteristics of the structure of the silicon carbide semiconductor device in Example 4 will be described with reference to FIG. FIG. 25 shows a sectional view of the termination region of the silicon carbide semiconductor device. The formation depth of the ring 405 increases as the distance from the active region increases. The depth of each ring 405 is set to 0.5 to 4.0 μm. The ring on the outer side of the ring on the active region side is larger than the ring on the active region side so that the depth of the ring 405h adjacent to the outside of the ring 405g is not less than the first ring and the depth of the ring 405i on the outside of the ring 405h is not less than the ring 405h It is formed to be deep. Therefore, a more robust termination can be formed.
　実施例４における炭化珪素半導体装置の製造方法を図２６～２８を用いて説明する。なお、ｐ型リング以外の製造方法は実施例１と同様であるため記さない。 A method for manufacturing a silicon carbide semiconductor device in Example 4 will be described with reference to FIGS. Since the manufacturing method other than the p-type ring is the same as that of the first embodiment, it will not be described.
　図２６に示すようにエピタキシャル層１０２にｐ型不純物、Ａｌをイオン注入する。これにより、最も内側のリング４０５ｇを形成する。 As shown in FIG. 26, the epitaxial layer 102 is ion-implanted with a p-type impurity, Al. This forms the innermost ring 405g.
　次に、図２７に示すように、エピタキシャル層１０２にｐ型不純物、Ａｌを斜めイオン注入することで、リング４０５ｇの外側隣にリング４０５ｇよりも表面からの深さがあるｐ型のリング４０５ｈを形成する。 Next, as shown in FIG. 27, by obliquely implanting p-type impurities and Al into the epitaxial layer 102, a p-type ring 405h that is deeper from the surface than the ring 405g is adjacent to the outside of the ring 405g. Form.
　次に、図２８に示すように、エピタキシャル層１０２にｐ型不純物、Ａｌを斜めイオン注入することで、リング４０５ｇの外側隣にリング４０５ｇよりも表面からの深さがあるｐ型のリング４０５ｉを形成する。 Next, as shown in FIG. 28, p-type impurities and Al are obliquely ion-implanted into the epitaxial layer 102 to form a p-type ring 405i that is deeper from the surface than the ring 405g adjacent to the outside of the ring 405g. Form.
　各リングは実施例１と同様、斜めイオン注入で形成する。 Each ring is formed by oblique ion implantation as in the first embodiment.
　このように実施例４によれば、実施例１と同様に効果を得るだけでなく、リング形成深さがリングによって異なるリング４０５ｇ～ｉを形成しているので、よりロバストなターミネーションを形成することができる。 As described above, according to the fourth embodiment, not only the same effects as in the first embodiment are obtained, but also the rings 405g to 405i having different ring formation depths are formed, so that a more robust termination is formed. Can do.
　実施例５と前述した実施例１との相違点は、リングのエピタキシャル層をｐ型のウェル領域５０６で所定の深さ掘り込み、段差の下段にｐ型のリング５０５を形成することである。 The difference between the fifth embodiment and the first embodiment described above is that the ring epitaxial layer is dug to a predetermined depth by the p-type well region 506, and the p-type ring 505 is formed below the step.
　実施例５における炭化珪素半導体装置の特徴を、図２９を用いて説明する。図２９は炭化珪素半導体装置の終端領域の断面図を示したものである。 The characteristics of the silicon carbide semiconductor device in Example 5 will be described with reference to FIG. FIG. 29 shows a sectional view of the termination region of the silicon carbide semiconductor device.
　リング５０５ｂを形成する領域が、エピタキシャル層１０２の表面から所定の深さ掘り込んである。所定の深さは、０．５～１．５μｍである。 The region for forming the ring 505 b is dug to a predetermined depth from the surface of the epitaxial layer 102. The predetermined depth is 0.5 to 1.5 μm.
　ｐ型のウェル領域５０６の深さは掘り込んだ面から０．５～２．０μｍで、不純物濃度は、１×１０１６～１×１０１９ｃｍ－３の範囲である。 The depth of the p-type well region 506 is 0.5 to 2.0 μm from the dug surface, and the impurity concentration is in the range of 1 × 10 16 to 1 × 10 19 cm −3 .
　実施例５における炭化珪素半導体装置の製造方法を図３０～３３を用いて説明する。 A method for manufacturing a silicon carbide semiconductor device in Example 5 will be described with reference to FIGS.
　エピタキシャル層１０２の表面上に、プラズマＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法により絶縁膜、ＳｉＯ２膜を堆積する。ＳｉＯ２膜の厚さは、１～３μｍである。続いて、図３０に示すようにレジストパターンをマスクとして、ＳｉＯ２膜をドライエッチング法により加工することにより、ＳｉＯ２膜からなるハードマスクパターン５０９ａをエピタキシャル層１０２の表面上に形成する。 An insulating film and a SiO 2 film are deposited on the surface of the epitaxial layer 102 by plasma CVD (Chemical Vapor Deposition). The thickness of the SiO 2 film is 1 to 3 μm. Subsequently, as shown in FIG. 30, the hard mask pattern 509a made of the SiO 2 film is formed on the surface of the epitaxial layer 102 by processing the SiO 2 film by a dry etching method using the resist pattern as a mask.
　次に、図３１に示すように、ハードマスクが無いリング領域をドライエッチング法により加工する。加工された領域のエピタキシャル層１０２の表面からの深さは、０．５～１．５μｍである。 Next, as shown in FIG. 31, a ring region without a hard mask is processed by a dry etching method. The depth of the processed region from the surface of the epitaxial layer 102 is 0.5 to 1.5 μm.
　次に、図３２に示すように、掘り込まれることによってできた段差の下段に、実施例１と同様にして、ｐ型のリング５０５を形成する。このとき、ｐ型のウェル領域５０６も同時に形成される。 Next, as shown in FIG. 32, a p-type ring 505 is formed in the lower stage of the step formed by digging in the same manner as in the first embodiment. At this time, a p-type well region 506 is also formed at the same time.
　ｐ型のウェル領域５０６は、図３３に示すように、掘り込まれた段差にまたがっている。ｐ型のウェル領域５０６はリングと同様に斜め不純物注入にて形成されるため、通常の不純物注入では形成されない領域５０６ｂが形成される。これにより、ｐ型ウェル領域底部における段差部の側壁から表面の段差部までの距離が長くなり、ｐ型ウェル領域での破壊が生じなくなる。 As shown in FIG. 33, the p-type well region 506 straddles the stepped portion. Since the p-type well region 506 is formed by oblique impurity implantation similarly to the ring, a region 506b that is not formed by normal impurity implantation is formed. As a result, the distance from the side wall of the stepped portion at the bottom of the p-type well region to the stepped portion on the surface becomes longer, and the destruction in the p-type well region does not occur.
　このように実施例５によれば、実施例１の効果を得ることができるだけでなく、さらに、リングをエピタキシャル層１０２からの距離がアクティブ領域より深い位置に形成することができるので、より高耐圧な炭化珪素半導体装置をとなっている。 As described above, according to the fifth embodiment, not only the effects of the first embodiment can be obtained, but also the ring can be formed at a position deeper than the active region from the epitaxial layer 102, so that a higher breakdown voltage can be obtained. This is a silicon carbide semiconductor device.
　本実施例６と前述した実施例１との相違点は、ｐ型のリング６０５ｇ、６０５ｈ，６０５ｉの幅が一定でなく、アクティブ領域に近いリング幅は広く形成され、アクティブ領域から遠ざかるにつれて狭く形成される点である。 The difference between the sixth embodiment and the first embodiment described above is that the widths of the p-type rings 605g, 605h, and 605i are not constant, the ring width close to the active region is formed wider, and narrower as the distance from the active region increases. It is a point to be done.
　図３４は炭化珪素半導体装置の終端領域の断面図を示したものである。図３４に示すようにリングの幅がアクティブ領域から遠ざかるにしたがって小さくなっている。最もアクティブに近い第１リングの幅は、４．０～５．０μｍである。第１リングの外側の第２リングの幅は第１リング以下、第２リングの外側の第３リングの幅は第２リング以下、となるように、一つ内側のリング幅よりも外側のリング幅のほうが小さくなるように形成される。 FIG. 34 shows a cross-sectional view of the termination region of the silicon carbide semiconductor device. As shown in FIG. 34, the width of the ring decreases as the distance from the active region increases. The width of the first ring that is closest to the active is 4.0 to 5.0 μm. The outer ring is wider than the inner ring width so that the width of the second ring outside the first ring is equal to or smaller than the first ring, and the width of the third ring outside the second ring is equal to or smaller than the second ring. The width is formed to be smaller.
　本実施例６における炭化珪素半導体装置の製造方法を図３５～３６を用いて説明する。なお、ｐ型のリング６０５以外の製造方法は実施例１と同様であるため割愛する。 A method for manufacturing the silicon carbide semiconductor device according to the sixth embodiment will be described with reference to FIGS. Since the manufacturing method other than the p-type ring 605 is the same as that of the first embodiment, it is omitted.
　エピタキシャル層１０２の表面上に、プラズマＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法により絶縁膜、ＳｉＯ２膜を堆積する。ＳｉＯ２膜の厚さは、１～３μｍである。続いて、図３５に示すようにレジストパターンをマスクとして、ＳｉＯ２膜をドライエッチング法により加工することにより、ＳｉＯ２膜からなるハードマスクパターン６０９ａをエピタキシャル層１０２の表面上に形成する。ハードマスクパターン６０９ａにおいて、最も内側のパターン幅Ｌ１は、４．０～５．０μｍである。最も内側より１つ外側のパターン幅Ｌ２は、パターン幅Ｌ１よりも狭い。また、パターン幅Ｌ２の１つ外側のパターン幅Ｌ３は、パターン幅Ｌ２よりも狭い。以上のように、パターン幅Ｌｎはパターン幅Ｌｎ－１よりも狭く形成される。 An insulating film and a SiO 2 film are deposited on the surface of the epitaxial layer 102 by plasma CVD (Chemical Vapor Deposition). The thickness of the SiO 2 film is 1 to 3 μm. Subsequently, as shown in FIG. 35, the hard mask pattern 609a made of the SiO 2 film is formed on the surface of the epitaxial layer 102 by processing the SiO 2 film by the dry etching method using the resist pattern as a mask. In the hard mask pattern 609a, the innermost pattern width L1 is 4.0 to 5.0 μm. The outermost pattern width L2 from the innermost side is narrower than the pattern width L1. The pattern width L3 that is one outside of the pattern width L2 is narrower than the pattern width L2. As described above, the pattern width Ln is formed narrower than the pattern width Ln-1.
　次に、図３６に示すように、エピタキシャル層１０２にｐ型不純物、Ａｌを斜めイオン注入することで、リング６０５を形成する。この時、リング６０５の幅は図３６のパターン幅によるため、パターン幅同様、外側に行くほど狭くなる。 Next, as shown in FIG. 36, a ring 605 is formed by implanting oblique ions of p-type impurities and Al into the epitaxial layer 102. At this time, since the width of the ring 605 depends on the pattern width of FIG.
　このように実施例６によれば、アクティブに近い領域におけるリングの総不純物濃度は大きく、遠ざかるにつれて総不純物濃度が小さくなるため、よりロバストなターミネーションを形成することができる。 As described above, according to Example 6, the total impurity concentration of the ring in the region near the active is large, and the total impurity concentration is decreased as the distance is increased. Therefore, a more robust termination can be formed.
　実施例７と前述した実施例１との相違点は、ｐ型のリング７０５を構成する総不純物濃度が、内側のリングほど総不純物濃度が大きく、外側にいくにしたがって、総不純物濃度が小さくなる点である。 The difference between the seventh embodiment and the first embodiment described above is that the total impurity concentration constituting the p-type ring 705 is larger in the inner ring, and the total impurity concentration is smaller toward the outer side. Is a point.
　実施例７における炭化珪素半導体装置の終端領域の特徴を、図３７を用いて、同終端領域の製造方法を、図３８～４０を用いて説明する。 The characteristics of the termination region of the silicon carbide semiconductor device in Example 7 will be described with reference to FIG. 37 and the manufacturing method of the termination region with reference to FIGS.
　図３７は炭化珪素半導体装置の終端領域の断面図を示したものである。図３８～４０は実施例７における炭化珪素半導体装置の製造方法を示す図である。なお、ｐ型リング以外の製造方法は実施例１と同様であるため割愛する。 FIG. 37 shows a cross-sectional view of the termination region of the silicon carbide semiconductor device. 38 to 40 are diagrams showing a method of manufacturing the silicon carbide semiconductor device in the seventh embodiment. Since the manufacturing method other than the p-type ring is the same as that of the first embodiment, it is omitted.
　図３７に示すように、アクティブ領域に近い領域におけるリング７０５の総不純物濃度は大きく、アクティブ領域から遠ざかるにつれて総不純物濃度が小さくなるようにしたものである。 As shown in FIG. 37, the total impurity concentration of the ring 705 in the region close to the active region is large, and the total impurity concentration decreases as the distance from the active region increases.
　図３８に示すようにエピタキシャル層１０２にｐ型不純物、Ａｌをイオン注入することにより、エピタキシャル層１０２にｐ型の第１リング７０５ａを形成する。ここでリング７０５ｇは実施例１と同様、斜めイオン注入で形成する。 38, a p-type first ring 705a is formed in the epitaxial layer 102 by ion-implanting p-type impurities and Al into the epitaxial layer 102. As shown in FIG. Here, the ring 705g is formed by oblique ion implantation as in the first embodiment.
　次に、図３９に示すように、エピタキシャル層１０２にｐ型不純物、Ａｌを斜めイオン注入することで、第１リングの外側に第１リングの総不純物濃度よりも低い総不純物濃度を有したｐ型の第２リング７０５ｈを形成する。 Next, as shown in FIG. 39, p-type impurities and Al are obliquely ion-implanted into the epitaxial layer 102, whereby p having a total impurity concentration lower than the total impurity concentration of the first ring outside the first ring. A second ring 705h of the mold is formed.
　次に、図４０に示すように、エピタキシャル層１０２にｐ型不純物、Ａｌを斜めイオン注入することで、第２リングの外側に第２リングの総不純物濃度よりも低い総不純物濃度を有したｐ型の第３リング７０５ｉを形成する。 Next, as shown in FIG. 40, a p-type impurity, Al, is obliquely ion-implanted into the epitaxial layer 102, so that p having a total impurity concentration lower than the total impurity concentration of the second ring outside the second ring. A third ring 705i of the mold is formed.
　このように実施例７によれば、アクティブ領域に近い領域におけるリングの総不純物濃度は大きく、アクティブ領域に遠ざかるにつれて総不純物濃度が小さくなるため、よりロバストなターミネーションを形成することができる。 Thus, according to Example 7, the total impurity concentration of the ring in the region close to the active region is large, and the total impurity concentration decreases as the distance from the active region increases, so that a more robust termination can be formed.
１…炭化珪素半導体装置、２…アクティブ領域、３…リング、４…チャネルストッパ、５…ｐ型ウェル領域、１０１…ＳｉＣ基板、１０２…エピタキシャル層、１０３…ＳｉＣエピタキシャル基板、１０４…電極、１０５…ｐ型リング、１０５ａ…リング１０５の高濃度領域、１０５ｂ…リング１０５の低濃度領域、１０６…ｐ型ウェル領域、１０６ａ…ｐ型ウェル領域の高濃度領域、１０６ｂ…ｐ型ウェル領域の高濃度領域、１０７…チャネルストッパ、１０８…ＳｉＯ膜、１０９…ハードマスク、１０９ａ、１０９ｂ、１０９ｃ…ハードマスクパターン、Ｎ１…不純物注入方向、Ｎ２…不純物注入方向、Ｎ３…不純物注入方向、Ｎ４…不純物注入方向、 DESCRIPTION OF SYMBOLS 1 ... Silicon carbide semiconductor device, 2 ... Active region, 3 ... Ring, 4 ... Channel stopper, 5 ... P-type well region, 101 ... SiC substrate, 102 ... Epitaxial layer, 103 ... SiC epitaxial substrate, 104 ... Electrode, 105 ... p-type ring, 105a ... high concentration region of ring 105, 105b ... low concentration region of ring 105, 106 ... p-type well region, 106a ... high concentration region of p-type well region, 106b ... high concentration region of p-type well region , 107 ... channel stopper, 108 ... SiO film, 109 ... hard mask, 109a, 109b, 109c ... hard mask pattern, N1 ... impurity injection direction, N2 ... impurity injection direction, N3 ... impurity injection direction, N4 ... impurity injection direction,

Claims (6)

  1. 　第１導電型の炭化珪素基板と、前記炭化珪素基板の表面上に形成された第１導電型の炭化珪素エピタキシャル層と、前記エピタキシャル層上に配置された第１電極と、前記炭化珪素基板の裏面に配置された第２電極とを備えた炭化珪素半導体装置において、
    　前記エピタキシャル層は平面視領域として、アクティブ領域と、前記アクティブ領域を囲む端部領域とを備え、
    　前記端部領域は、前記アクティブ領域を前記リング状に囲む平面視形状となる第２導電型の不純物が注入され、前記第１電極に直接接していないリングを多重に備え、
    　前記リングは、平面視形状で直線状のライン部と、前記ライン部を繋ぐコーナー部とを備え、前記ライン部と前記コーナー部の接続部から前記コーナーの中間に向かうにしたがって前記リング間距離が徐々に狭くなり、
    　前記リングは、平面視形状で高濃度領域を低濃度領域で挟み込む構造を備え、前記ライン部と前記コーナー部の接続部から前記コーナーの中間に向かうにしたがって前記低濃度領域の不純物濃度が薄くなることを特徴とする炭化珪素半導体装置。     A first conductivity type silicon carbide substrate, a first conductivity type silicon carbide epitaxial layer formed on a surface of the silicon carbide substrate, a first electrode disposed on the epitaxial layer, and the silicon carbide substrate. In a silicon carbide semiconductor device comprising a second electrode disposed on the back surface,
    The epitaxial layer includes, as a plan view region, an active region and an end region surrounding the active region,
    The end region is provided with multiple rings that are implanted with a second conductivity type impurity in a plan view surrounding the active region in a ring shape and are not in direct contact with the first electrode,
    The ring includes a linear line portion in a plan view shape and a corner portion connecting the line portions, and the distance between the rings increases from the connecting portion of the line portion and the corner portion toward the middle of the corner. Gradually narrowing,
    The ring has a structure in which a high-concentration region is sandwiched between low-concentration regions in a plan view shape, and the impurity concentration in the low-concentration region becomes thinner from the connection portion between the line portion and the corner portion toward the middle of the corner. The silicon carbide semiconductor device characterized by the above-mentioned.
  2. 　請求項１において、
    　前記コーナー部のリング幅は、前記コーナー部の中間に向かって前記コーナー部内側と外側の両方に広がっていることを特徴とする炭化珪素半導体装置。     In claim 1,
    The silicon carbide semiconductor device according to claim 1, wherein a ring width of the corner portion extends both inside and outside the corner portion toward an intermediate portion of the corner portion.
  3. 　請求項２において、
    　前記リングの間隔がライン部から前記コーナー部に向かって徐々に狭くなっていることを特徴とした炭化珪素半導体装置。     In claim 2,
    A silicon carbide semiconductor device, wherein a distance between the rings gradually decreases from a line portion toward the corner portion.
  4. 　請求項３において、
    　前記リングの高濃度領域の不純物濃度は１×１０１６～１×１０１９ｃｍ－３、
    　前記リングの低濃度領域の不純物濃度は１×１０１５～１×１０１８ｃｍ－３であることを特徴とする炭化珪素半導体装置。     In claim 3,
    The impurity concentration of the high concentration region of the ring is 1 × 10 16 to 1 × 10 19 cm −3 ,
    The silicon carbide semiconductor device, wherein an impurity concentration in the low concentration region of the ring is 1 × 10 15 to 1 × 10 18 cm −3 .
  5. 　請求項１において、
    　前記リングは前記アクティブ領域より一段低い位置に設けられていることを特徴とする炭化珪素半導体装置。     In claim 1,
    The ring is provided at a position one step lower than the active region.
  6. 　炭化珪素基板上のエピタキシャル層に矩形のアクティブ領域と、
    　前記アクティブ領域を囲み、かつ、電極に直接接していないｐ型リングを備えた炭化珪素半導体装置の製造方法において、
    　前記ｐ型リングは、平面視で前記ｐ型リングの一辺に対して傾けた角度、かつ、前記炭化珪素基板平面に対して傾けた角度にイオン注入することを特徴とする炭化珪素半導体装置の製造方法。     A rectangular active region in the epitaxial layer on the silicon carbide substrate;
    In a method for manufacturing a silicon carbide semiconductor device including a p-type ring that surrounds the active region and is not in direct contact with an electrode,
    The p-type ring is ion-implanted at an angle inclined with respect to one side of the p-type ring in a plan view and an angle inclined with respect to the plane of the silicon carbide substrate. Method.
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