WO2014049774A1 - Structure of electrode of semiconductor element, and method for manufacturing structure of electrode of semiconductor element - Google Patents

Structure of electrode of semiconductor element, and method for manufacturing structure of electrode of semiconductor element Download PDF

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Publication number
WO2014049774A1
WO2014049774A1 PCT/JP2012/074883 JP2012074883W WO2014049774A1 WO 2014049774 A1 WO2014049774 A1 WO 2014049774A1 JP 2012074883 W JP2012074883 W JP 2012074883W WO 2014049774 A1 WO2014049774 A1 WO 2014049774A1
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WIPO (PCT)
Prior art keywords
side electrode
electrode
semiconductor element
semiconductor layer
led element
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PCT/JP2012/074883
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French (fr)
Japanese (ja)
Inventor
良崇 橋本
政利 藤田
雅登 鈴木
明宏 川尻
和裕 杉山
謙磁 塚田
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富士機械製造株式会社
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Priority to JP2014537949A priority Critical patent/JP6032823B2/en
Priority to PCT/JP2012/074883 priority patent/WO2014049774A1/en
Publication of WO2014049774A1 publication Critical patent/WO2014049774A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body

Definitions

  • the present invention relates to an electrode structure of a semiconductor element in which a p-type semiconductor layer and an n-type semiconductor layer are formed on the upper side of the semiconductor element, and a manufacturing method thereof.
  • wiring between the electrode part on the semiconductor element side and the electrode part on the mounting member side is generally performed by wire bonding.
  • Patent Document 1 Japanese Patent No. 3992038
  • the resin material liquid is discharged by a dispenser around the semiconductor element mounted on the wiring board and cured, so that the space between the upper surface of the semiconductor element and the surface of the wiring board is obtained.
  • conductive ink is ejected by a droplet ejection method such as ink jet along the wiring path connecting the electrode portion on the upper surface of the semiconductor element and the electrode portion of the wiring board. It has been proposed to form wiring.
  • the present invention provides a p-side electrode electrically connected to the p-type semiconductor layer in an electrode structure of a semiconductor element in which a p-type semiconductor layer and an n-type semiconductor layer are formed on an upper side of the semiconductor element.
  • the n-side electrode conducting to the n-type semiconductor layer is substantially the same height, and the p-side electrode is formed at a position lower than the p-type semiconductor layer.
  • the process of smoothing the wiring base becomes easy, and the step of the wiring base can be easily reduced. Thereby, it becomes easy to form a wiring, and a wiring with high connection reliability can be formed by a film forming method.
  • the p-side electrode may be formed so as to extend to a position that is almost the same height as the n-side electrode.
  • the p-side electrode and the n-side electrode may each be formed so as to extend to the lower end along the side surface of the semiconductor element. In this way, when the semiconductor element is mounted on the circuit board, the p-side electrode and the n-side electrode can be directly connected to the electrode portion of the circuit board without using wiring.
  • a semiconductor element having this configuration When manufacturing a semiconductor element having this configuration, a plurality of semiconductor elements are formed on a single wafer, and through holes are formed between the semiconductor elements. Of the surface of the semiconductor element and the inner peripheral surface of the through hole, After forming an insulating protective film in a portion that needs to be insulated from the p-side electrode and the n-side electrode, the p-side electrode and the n-side electrode are formed, and then the wafer is diced along the center line of the through-hole. What is necessary is just to divide
  • FIG. 1 is a longitudinal sectional view showing a mounting structure of an LED element according to Embodiment 1 of the present invention.
  • FIG. 2 is a longitudinal sectional view of the LED element for explaining the transparent electrode forming step of Example 1.
  • FIG. 3 is a vertical cross-sectional view of the LED element for explaining the insulating protective film forming step of the first embodiment.
  • FIG. 4 is a vertical cross-sectional view of the LED element for explaining the electrode forming process of the first embodiment.
  • FIG. 5 is a longitudinal sectional view of an LED element for explaining the chamfering process of the first embodiment.
  • FIG. 6 is a longitudinal sectional view showing an element structure in which the lower base material of the LED element of Example 1 is removed to reduce the height of the LED element.
  • FIG. 1 is a longitudinal sectional view showing a mounting structure of an LED element according to Embodiment 1 of the present invention.
  • FIG. 2 is a longitudinal sectional view of the LED element for explaining the transparent electrode forming step of Example 1.
  • FIG. 7 is a plan view of the LED element of Example 1.
  • FIG. FIG. 8 is a plan view showing a state before a dicing process in which a plurality of LED elements of Example 1 are formed on one wafer.
  • FIG. 9 is a longitudinal sectional view showing the mounting structure of the LED element of Example 2 of the present invention.
  • FIG. 10 is a plan view of a part of the wafer for explaining the through hole forming process of the second embodiment.
  • FIG. 11 is a longitudinal sectional view of a part of the wafer for explaining the through hole forming process of the second embodiment.
  • FIG. 12 is a longitudinal sectional view of a part of the wafer for explaining the insulating protective film forming step of the second embodiment.
  • FIG. 13 is a longitudinal sectional view of a part of the wafer for explaining the electrode forming process of the second embodiment.
  • FIG. 14 is a longitudinal sectional view of an LED element for explaining the dicing process of the second embodiment.
  • FIG. 15 is a plan view of the LED element of Example 2.
  • the LED element 11 is formed by sequentially forming an n-type semiconductor layer 13, a light emitting layer 14, a p-type semiconductor layer 15, etc. on a base material 12, and a transparent electrode 16 is formed on the p-type semiconductor layer 15. Yes.
  • An insulating protective film 19 is formed on a portion of the surface of the LED element 11 that needs to be insulated from the p-side electrode 17 and the n-side electrode 18.
  • a part of the p-side electrode 17 is formed on the transparent electrode 16 so as to conduct to the p-type semiconductor layer 15 through the transparent electrode 16, and the n-side electrode 18 is formed on the n-type semiconductor layer 13. As a result, the n-type semiconductor layer 13 is electrically connected.
  • the p-side electrode 17 is formed so as to extend to a position substantially the same height as the n-side electrode 18.
  • the p-side electrode 17 and the n-side electrode 18 have substantially the same height, and the p-side electrode 17 is formed at a position lower than the p-type semiconductor layer 15.
  • the LED element 11 is die-bonded on a circuit board 21 that is a mounting member.
  • a fluid resin material is discharged by a dispenser to form an insulating resin slope 22 that connects the upper surface of the LED element 11 and the upper surface of the circuit board 21 with an inclined surface.
  • conductive ink (ink containing conductive particles such as Ag) is ejected onto the resin slope 22 by a droplet ejection method such as inkjet or dispenser, and the pattern of the wirings 23 and 24 is formed on each electrode of the LED element 11. 17 and 18 and the electrode parts 25 and 26 on the upper surface of the circuit board 21 are drawn, dried and fired, and the electrodes 17 and 18 of the LED element 11 and the electrode parts 25 on the upper surface of the circuit board 21 are drawn. , 26 are connected by wirings 23, 24.
  • or FIG. 8 A large number of LED elements 11 are formed in a grid pattern on one wafer 31 (only part of which is shown in FIG. 8). Finally, one wafer 31 is diced along a cut line and divided into a large number of LED elements 11. Is done.
  • the manufacturing process will be described using the minimum configuration of the LED element 11 as an example.
  • the present invention is a technical idea of forming the electrode structure into a desired shape, and the semiconductor manufacturing process is A method similar to a known technique may be used except for the electrode structure and related parts.
  • an n-type semiconductor layer 13, a light-emitting layer 14, a p-type semiconductor layer 15, and the like are sequentially formed on the base material 12, and then the light-emitting layer 14 and the p-type semiconductor layer 15 are formed using a lithography technique, An etching technique is used to partially remove the n-type semiconductor layer 13 so that a part of the upper surface is exposed. Thereafter, a transparent electrode 16 having translucency and conductivity is formed on the upper surface of the p-type semiconductor layer 15 by using a lithography technique and an etching technique.
  • an insulating protective film forming step it is necessary to insulate the p-side electrode 17 and the n-side electrode 18 and the like on the surface of the LED element 11 using a lithography technique and an etching technique.
  • An insulating protective film 19 such as SiO 2 is formed on this part by CVD (chemical vapor deposition).
  • the film-forming method of the insulating protective film 19 is not limited to CVD, PVD (physical vapor deposition) such as sputtering, printing methods such as spraying and flexo, droplet discharging methods such as dispensers and inkjets, sol-gel methods, Techniques such as thermal oxidation and insulating sheet sticking may be used.
  • the patterning of the insulating protective film 19 is not limited to photolithography, but electrons, A method of using a mask such as a resist mask, a metal mask, or a tape by lithography with or without an ion or X-ray mask, a method of directly controlling the film formation range, or transfer may be used.
  • a mask such as a resist or metal is used, or the contact range of the etched product is finely controlled to remove the solvent.
  • the insulating protective film 19 may be partially etched by wet etching used, dry etching using electrons, ions, laser, or the like, or cutting or polishing with a machine.
  • a p-side electrode 17 and an n-side electrode 18 are formed on the surface of the LED element 11 by sputtering using a lithography technique and an etching technique.
  • the p-side electrode 17 is electrically connected to the p-type semiconductor layer 15 through the transparent electrode 16
  • the n-side electrode 18 is connected to the n-type semiconductor layer 13.
  • the n-side electrode 18 is brought into conduction with the n-type semiconductor layer 13.
  • the p-side electrode 17 is formed so as to extend to a position substantially the same height as the n-side electrode 18.
  • each of the electrodes 17 and 18 may be a metal such as gold or silver or an alloy thereof, a transparent conductive material such as ITO, or a paint in which particles of a minute conductive material are dispersed.
  • the film formation method of each electrode 17 and 18 is PVD (physical vapor deposition) such as vapor deposition, printing method such as spray and flexo, droplet ejection method such as dispenser and ink jet, sol-gel method, thermal oxidation, and conductive sheet sticking. A method such as the above may be used.
  • a plurality of film formation methods may be used in combination.
  • the patterning of the electrodes 17 and 18 may be performed using the same method as the patterning of the insulating protective film 19.
  • the electrodes 17 and 18 may be formed in a shape without a wire bonding pad, or may be formed in a shape with a wire bonding pad. When there is no wire bonding pad, there is an advantage that the area of each electrode 17, 18 that blocks the light emitted from the light emitting layer 14 of the LED element 11 can be reduced, and the light emitted from the light emitting layer 14 is reduced to each electrode 17, 18.
  • Each of the electrodes 17 and 18 can be formed to have a minimum area and a minimum thickness so that the ratio blocked by 18 is minimized.
  • droplet discharge as shown in FIG.
  • the process proceeds to a dicing process, and the wafer 31 on which a large number of LED elements 11 are formed is diced along a cut line (see FIG. 8) and divided into individual LED elements 11.
  • the process proceeds to the chamfering step, and the upper end corner of the cut surface by dicing is chamfered as shown in FIG. If the chamfered edge is sharp, the wires 23 and 24 are likely to be disconnected. Therefore, it is preferable to form the edge round.
  • An electrode (conductive film) connected to each of the electrodes 17 and 18 may be formed on the chamfered portion in order to reduce the underlying step of the wirings 23 and 24 connected to each of the electrodes 17 and 18.
  • Chamfering is a process for alleviating cracks due to impact, but is not essential and may be omitted.
  • the portion of the base 12 on the lower side of the LED element 11 may be removed by peeling or cutting to reduce the height of the LED element 11.
  • the p-type electrode 17 is electrically connected to the p-type semiconductor layer 15 while the p-type semiconductor layer 15 is higher than the n-type semiconductor layer 13 (n-side electrode 18). And the n-side electrode 18 conducting to the n-type semiconductor layer 13 have almost the same height.
  • the resin slope 22 which is the base of 3 and 24 becomes a symmetrical shape, the process of forming the resin slope 22 is facilitated, and the step of the base of the wirings 23 and 24 is easily reduced. As a result, the wirings 23 and 24 can be easily formed, and the wirings 23 and 24 having high connection reliability can be formed by a film forming method.
  • the manufacturing process of the LED element 11 and the formation of the wirings 23 and 24 are considered comprehensively, and unnecessary processes and techniques are performed. The demand can be reduced.
  • Embodiment 2 of the present invention will be described with reference to FIGS.
  • substantially the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted or simplified, and different parts are mainly described.
  • the difference from the first embodiment is an electrode structure and a mounting structure.
  • the p-side electrode 35 and the n-side electrode 36 of the LED element 11 are formed so as to extend along the side surface of the LED element 11 to the lower end thereof.
  • two half grooves 37 a formed by dividing the through hole 37 by dicing at the time of manufacturing the LED element 11 are formed, and the two half grooves A p-side electrode 35 and an n-side electrode 36 are formed on 37a so as to extend to the lower end of each half-groove 37a via an insulating protective film 38.
  • Example 2 As shown in FIG. 9, when the LED element 11 is mounted on the circuit board 21, the p-side electrode 35 and the n-side electrode 36 are connected to the electrode portions 25 of the circuit board 21. In this state, the p-side electrode 35 and the n-side electrode 36 may be connected to the electrode portions 25 and 26 of the circuit board 21 with a conductive adhesive 40, solder, or the like.
  • a large number of LED elements 11 are formed in a grid pattern on one wafer 31 (only part of which is shown in FIG. 8). Finally, one wafer 31 is diced along a cut line and divided into a large number of LED elements 11. Is done.
  • a through hole 37 is formed at a position on the line so as to penetrate the wafer 31 by a CO 2 laser or the like.
  • the center of each through hole 37 coincides with the cutting line for dicing.
  • the through hole 37 is not limited to the CO 2 laser, and excimer lasers other than CO 2 , ion, electronic, or mechanical cutting may be used.
  • the process proceeds to an insulating protective film forming step, and as shown in FIG. 12, the p-side electrode 35 and n of the surface of the LED element 11 and the inner peripheral surface of the through hole 37 are formed using a lithography technique and an etching technique.
  • An insulating protective film 38 such as SiO 2 is formed by CVD (Chemical Vapor Deposition) at a portion that needs to be insulated from the side electrode 36 and the like.
  • the process proceeds to an electrode forming process, and as shown in FIG. 13, the p-side electrode 35 and the n-side electrode 36 are formed on the surface of the LED element 11 and the inner peripheral surface of the through hole 37 by using a lithography technique and an etching technique. It is formed by sputtering.
  • the electrodes 35 and 36 may be formed by a method other than sputtering, as in the first embodiment.
  • the process proceeds to a dicing process, and the wafer 31 on which a large number of LED elements 11 are formed is diced along a cut line (center line of the through hole 37) and divided into the LED elements 11 having the structure shown in FIGS. To do.
  • a cut line center line of the through hole 37
  • half grooves 37a are formed on both side surfaces of each LED element 11, and each electrode 35, 36 is provided on the inner peripheral surface of each half groove 37a via the insulating protective film 38, and the lower end of each half groove 37a. It is formed to extend up to.
  • the process proceeds to a chamfering step, and the upper end corner of the cut surface by dicing of each LED element 11 is chamfered.
  • Chamfering is a process for alleviating cracks due to impact, but is not essential and may be omitted. Moreover, you may make it make the height of the LED element 11 low by removing the part of the base material 12 of the lower side of the LED element 11 by peeling or cutting.
  • the p-side electrode 35 and the n-side electrode 36 of the LED element 11 are formed so as to extend to the lower end along the side surfaces of the LED element 11, respectively.
  • the p-side electrode 35 and the n-side electrode 36 are in contact with the electrode portions 25 and 26 of the circuit board 21.
  • the p-side electrode 35 and the n-side electrode 36 are connected to the circuit. It can be connected to the electrode portions 25 and 26 of the substrate 21 with a conductive adhesive 40 or solder. For this reason, it is not necessary to form wirings or resin slopes for connecting the electrodes 35, 36 of the LED element 11 and the electrode portions 25, 26 on the upper surface of the circuit board 21, and the mounting process of the LED element 11 can be simplified.
  • each electrode 35, 36 has a predetermined height on the side surface of the LED element 11.
  • An extended configuration may be used.
  • the through hole 37 does not need to penetrate the wafer 31.
  • the step of the wiring substrate can be reduced by forming a minimum resin slope, and the resin material can be used for the electrodes 35 and 36. There is also a low possibility that the connection with the electrodes 35 and 36 will be lost due to the covering.
  • this invention is not limited to said each Example 1 and 2,
  • the shape of the base material of each LED element, each semiconductor layer, and an electrode is each conduction
  • the LED element 11 is mounted on the circuit board 21.
  • the LED element 11 may be mounted in the recess of the mounting member.
  • the present invention is not limited to light emitting elements such as LED elements, and can be implemented with various modifications without departing from the gist, such as being applicable to other semiconductor elements.
  • SYMBOLS 11 LED element (semiconductor element), 12 ... Base material, 13 ... N-type semiconductor layer, 14 ... Light emitting layer, 15 ... P-type semiconductor layer, 16 ... Transparent electrode, 17 ... P-side electrode, 18 ... N-side electrode, DESCRIPTION OF SYMBOLS 19 ... Insulating protective film, 21 ... Circuit board, 22 ... Resin slope, 23, 24 ... Wiring, 25, 26 ... Electrode part, 31 ... Wafer, 35 ... P side electrode, 36 ... N side electrode, 37 ... Through hole, 37a: Half groove, 38: Insulating protective film, 40: Conductive adhesive

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

A p-side electrode (17) is formed to extend to a position at a height substantially equal to that of an n-side electrode (18), taking into account that a p-type semiconductor layer (15) of an LED element (11) is higher than an n-type semiconductor layer (13) (n-side electrode (18)). Consequently, the p-side electrode (17) and the n-side electrode (18) are formed at the substantially same height, and the p-side electrode (17) is formed at a position lower than the p-type semiconductor layer (15). If the p-side electrode (17) and the n-side electrode (18) are at the substantially same height in such a manner, since a resin slope (22), i.e., a base for wiring (23, 24), has a symmetric shape, process of forming the resin slope (22) is facilitated, and a step in the base for the wiring (23, 24) becomes susceptible to be reduced. Consequently, the wiring (23, 24) having high connection reliability can be formed by means of a film-forming method.

Description

半導体素子の電極構造及びその製造方法Electrode structure of semiconductor element and manufacturing method thereof
　本発明は、半導体素子の上部側にｐ型半導体層とｎ型半導体層が形成された半導体素子の電極構造及びその製造方法に関する発明である。 The present invention relates to an electrode structure of a semiconductor element in which a p-type semiconductor layer and an n-type semiconductor layer are formed on the upper side of the semiconductor element, and a manufacturing method thereof.
　従来の半導体素子は、搭載部材（回路基板、リードフレーム等）にダイボンドした後に、該半導体素子側の電極部と搭載部材側の電極部との間をワイヤボンディングで配線するのが一般的である。 In the conventional semiconductor element, after die-bonding to a mounting member (circuit board, lead frame, etc.), wiring between the electrode part on the semiconductor element side and the electrode part on the mounting member side is generally performed by wire bonding. .
　しかし、特許文献１（特許第３９９２０３８号公報）に記載されているように、ワイヤボンディングを行うときの機械的なストレスによって不良が発生する可能性があるため、ワイヤボンディングに代わる接続信頼性の高い実装構造を低コストで実現することを目的として、配線基板上に搭載した半導体素子の周囲に樹脂材料の液をディスペンサで吐出して硬化させて、半導体素子の上面と配線基板の表面との間を傾斜面でつなぐ樹脂スロープを形成した後、半導体素子上面の電極部と配線基板の電極部との間を接続する配線の経路に沿ってインクジェット等の液滴吐出法で導電性インクを吐出して配線を形成することが提案されている。 However, as described in Patent Document 1 (Japanese Patent No. 3992038), there is a possibility that defects may occur due to mechanical stress when wire bonding is performed. Therefore, connection reliability that replaces wire bonding is high. For the purpose of realizing the mounting structure at low cost, the resin material liquid is discharged by a dispenser around the semiconductor element mounted on the wiring board and cured, so that the space between the upper surface of the semiconductor element and the surface of the wiring board is obtained. After forming a resin slope that connects the inclined surfaces, conductive ink is ejected by a droplet ejection method such as ink jet along the wiring path connecting the electrode portion on the upper surface of the semiconductor element and the electrode portion of the wiring board. It has been proposed to form wiring.
特許第３９９２０３８号公報Japanese Patent No. 3992038
　しかし、目標とする形状の樹脂スロープを形成するために、樹脂材料の充填精度等の技術的要求が高く、樹脂材料が電極を覆い隠して電極との導通が取れなくなってしまったり、配線の下地の段差を十分に低減できず、成膜した配線が断線しやすくなることがある。また、左右非対称の形状の半導体素子の場合は、形成する樹脂スロープの形状を左右で各々調整しなければならず、段差を低減するプロセスが難しくなる。このような問題が生まれる根本的な原因は、現在の半導体素子の電極がワイヤボンディングを前提として形成されており、半導体素子の表面に配線を成膜することを想定して製造されていないためである。 However, in order to form a resin slope of the target shape, technical requirements such as the filling accuracy of the resin material are high, and the resin material covers the electrode so that it cannot be connected to the electrode, or the wiring base This step may not be sufficiently reduced, and the formed wiring may be easily broken. Further, in the case of a semiconductor element having an asymmetrical shape, the shape of the resin slope to be formed must be adjusted on the left and right sides, and the process of reducing the step becomes difficult. The root cause of such problems is that the electrodes of current semiconductor elements are formed on the premise of wire bonding, and are not manufactured on the assumption that wiring is formed on the surface of the semiconductor elements. is there.
　上記課題を解決するために、本発明は、半導体素子の上部側にｐ型半導体層とｎ型半導体層が形成された半導体素子の電極構造において、前記ｐ型半導体層に導通するｐ側電極と前記ｎ型半導体層に導通するｎ側電極とがほぼ同一高さで、且つ、前記ｐ側電極が前記ｐ型半導体層より低い位置に形成された構成となっている。この構成では、ｐ側電極とｎ側電極とがほぼ同一高さであるため、配線の下地をなだらかにするプロセスが容易となり、配線の下地の段差を低減しやすくなる。これにより、配線を成膜しやすくなり、成膜法で接続信頼性の高い配線を形成できる。 In order to solve the above-described problems, the present invention provides a p-side electrode electrically connected to the p-type semiconductor layer in an electrode structure of a semiconductor element in which a p-type semiconductor layer and an n-type semiconductor layer are formed on an upper side of the semiconductor element. The n-side electrode conducting to the n-type semiconductor layer is substantially the same height, and the p-side electrode is formed at a position lower than the p-type semiconductor layer. In this configuration, since the p-side electrode and the n-side electrode are substantially the same height, the process of smoothing the wiring base becomes easy, and the step of the wiring base can be easily reduced. Thereby, it becomes easy to form a wiring, and a wiring with high connection reliability can be formed by a film forming method.
　この場合、ｐ型半導体層がｎ型半導体層（ｎ側電極）よりも高いことを考慮して、ｐ側電極がｎ側電極とほぼ同一高さの位置まで延びるように形成すれば良い。 In this case, considering that the p-type semiconductor layer is higher than the n-type semiconductor layer (n-side electrode), the p-side electrode may be formed so as to extend to a position that is almost the same height as the n-side electrode.
　本発明は、ｐ側電極とｎ側電極を、それぞれ半導体素子の側面に沿ってその下端まで延びるように形成しても良い。このようにすれば、半導体素子を回路基板上に実装したとき
に、ｐ側電極とｎ側電極を回路基板の電極部に配線を使用せずに直接接続することができる。 In the present invention, the p-side electrode and the n-side electrode may each be formed so as to extend to the lower end along the side surface of the semiconductor element. In this way, when the semiconductor element is mounted on the circuit board, the p-side electrode and the n-side electrode can be directly connected to the electrode portion of the circuit board without using wiring.
　この構成の半導体素子を製造する場合は、１枚のウエハに複数の半導体素子を形成すると共に、各半導体素子の間にスルーホールを形成し、半導体素子の表面及びスルーホールの内周面のうちｐ側電極及びｎ側電極に対する絶縁が必要な部分に絶縁保護膜を形成した後、ｐ側電極及びｎ側電極を形成した上で、ウエハをスルーホールの中心線に沿ってダイシングして各半導体素子に分割するようにすれば良い。 When manufacturing a semiconductor element having this configuration, a plurality of semiconductor elements are formed on a single wafer, and through holes are formed between the semiconductor elements. Of the surface of the semiconductor element and the inner peripheral surface of the through hole, After forming an insulating protective film in a portion that needs to be insulated from the p-side electrode and the n-side electrode, the p-side electrode and the n-side electrode are formed, and then the wafer is diced along the center line of the through-hole. What is necessary is just to divide | segment into an element.
図１は本発明の実施例１のＬＥＤ素子の実装構造を示す縦断面図である。1 is a longitudinal sectional view showing a mounting structure of an LED element according to Embodiment 1 of the present invention. 図２は実施例１の透明電極形成工程を説明するＬＥＤ素子の縦断面図である。FIG. 2 is a longitudinal sectional view of the LED element for explaining the transparent electrode forming step of Example 1. 図３は実施例１の絶縁保護膜形成工程を説明するＬＥＤ素子の縦断面図である。FIG. 3 is a vertical cross-sectional view of the LED element for explaining the insulating protective film forming step of the first embodiment. 図４は実施例１の電極形成工程を説明するＬＥＤ素子の縦断面図である。FIG. 4 is a vertical cross-sectional view of the LED element for explaining the electrode forming process of the first embodiment. 図５は実施例１の面取り工程を説明するＬＥＤ素子の縦断面図である。FIG. 5 is a longitudinal sectional view of an LED element for explaining the chamfering process of the first embodiment. 図６は実施例１のＬＥＤ素子の下部側の基材を除去してＬＥＤ素子の高さを低くした素子構造を示す縦断面図である。FIG. 6 is a longitudinal sectional view showing an element structure in which the lower base material of the LED element of Example 1 is removed to reduce the height of the LED element. 図７は実施例１のＬＥＤ素子の平面図である。FIG. 7 is a plan view of the LED element of Example 1. FIG. 図８は実施例１のＬＥＤ素子を１枚のウエハに複数形成したダイシング工程前の状態を示す平面図である。FIG. 8 is a plan view showing a state before a dicing process in which a plurality of LED elements of Example 1 are formed on one wafer. 図９は本発明の実施例２のＬＥＤ素子の実装構造を示す縦断面図である。FIG. 9 is a longitudinal sectional view showing the mounting structure of the LED element of Example 2 of the present invention. 図１０は実施例２のスルーホール形成工程を説明するウエハの一部分の平面図である。FIG. 10 is a plan view of a part of the wafer for explaining the through hole forming process of the second embodiment. 図１１は実施例２のスルーホール形成工程を説明するウエハの一部分の縦断面図である。FIG. 11 is a longitudinal sectional view of a part of the wafer for explaining the through hole forming process of the second embodiment. 図１２は実施例２の絶縁保護膜形成工程を説明するウエハの一部分の縦断面図である。FIG. 12 is a longitudinal sectional view of a part of the wafer for explaining the insulating protective film forming step of the second embodiment. 図１３は実施例２の電極形成工程を説明するウエハの一部分の縦断面図である。FIG. 13 is a longitudinal sectional view of a part of the wafer for explaining the electrode forming process of the second embodiment. 図１４は実施例２のダイシング工程を説明するＬＥＤ素子の縦断面図である。FIG. 14 is a longitudinal sectional view of an LED element for explaining the dicing process of the second embodiment. 図１５は実施例２のＬＥＤ素子の平面図である。FIG. 15 is a plan view of the LED element of Example 2. FIG.
　以下、本発明を実施するための形態をＬＥＤ素子に適用して具体化した２つの実施例１，２を説明する。 Hereinafter, two Examples 1 and 2, which are embodied by applying the mode for carrying out the present invention to the LED element, will be described.
　本発明の実施例１を図１乃至図８に基づいて説明する。
　まず、図１及び図５を用いて本実施例１のＬＥＤ素子１１の構造と実装構造を説明する。ＬＥＤ素子１１は、基材１２上に、ｎ型半導体層１３、発光層１４、ｐ型半導体層１５等を順に成膜して形成され、ｐ型半導体層１５上に透明電極１６が形成されている。ＬＥＤ素子１１の表面のうち、ｐ側電極１７及びｎ側電極１８等に対する絶縁が必要な部分に絶縁保護膜１９が形成されている。 A first embodiment of the present invention will be described with reference to FIGS.
First, the structure and mounting structure of the LED element 11 of Example 1 will be described with reference to FIGS. 1 and 5. The LED element 11 is formed by sequentially forming an n-type semiconductor layer 13, a light emitting layer 14, a p-type semiconductor layer 15, etc. on a base material 12, and a transparent electrode 16 is formed on the p-type semiconductor layer 15. Yes. An insulating protective film 19 is formed on a portion of the surface of the LED element 11 that needs to be insulated from the p-side electrode 17 and the n-side electrode 18.
　ｐ側電極１７は、その一部が透明電極１６上に形成されることで該透明電極１６を介してｐ型半導体層１５に導通し、ｎ側電極１８は、ｎ型半導体層１３上に形成されることで、ｎ型半導体層１３に導通している。 A part of the p-side electrode 17 is formed on the transparent electrode 16 so as to conduct to the p-type semiconductor layer 15 through the transparent electrode 16, and the n-side electrode 18 is formed on the n-type semiconductor layer 13. As a result, the n-type semiconductor layer 13 is electrically connected.
　この場合、ｐ型半導体層１５がｎ型半導体層１３（ｎ側電極１８）よりも高いことを考慮して、ｐ側電極１７がｎ側電極１８とほぼ同一高さの位置まで延びるように形成されている。これにより、ｐ側電極１７とｎ側電極１８とがほぼ同一高さで、且つ、ｐ側電極１７がｐ型半導体層１５より低い位置に形成された構成となっている。 In this case, in consideration of the fact that the p-type semiconductor layer 15 is higher than the n-type semiconductor layer 13 (n-side electrode 18), the p-side electrode 17 is formed so as to extend to a position substantially the same height as the n-side electrode 18. Has been. As a result, the p-side electrode 17 and the n-side electrode 18 have substantially the same height, and the p-side electrode 17 is formed at a position lower than the p-type semiconductor layer 15.
　以上のように構成したＬＥＤ素子１１の実装構造の一例を図１を用いて説明する。本例では、搭載部材である回路基板２１上にＬＥＤ素子１１をダイボンディングする。このＬＥＤ素子１１の周囲には、流動性の樹脂材料をディスペンサで吐出して、ＬＥＤ素子１１の上面と回路基板２１の上面との間を傾斜面でつなぐ絶縁性の樹脂スロープ２２を形成する。 An example of the mounting structure of the LED element 11 configured as described above will be described with reference to FIG. In this example, the LED element 11 is die-bonded on a circuit board 21 that is a mounting member. Around the LED element 11, a fluid resin material is discharged by a dispenser to form an insulating resin slope 22 that connects the upper surface of the LED element 11 and the upper surface of the circuit board 21 with an inclined surface.
　この後、インクジェット、ディスペンサ等の液滴吐出法により導電性のインク（Ａｇ等の導体粒子を含むインク）を樹脂スロープ２２上に吐出して、配線２３，２４のパターンをＬＥＤ素子１１の各電極１７，１８と回路基板２１上面の電極部２５，２６とに跨がって描画し、これを乾燥して焼成して、ＬＥＤ素子１１の各電極１７，１８と回路基板２１上面の電極部２５，２６との間を配線２３，２４で接続する。 Thereafter, conductive ink (ink containing conductive particles such as Ag) is ejected onto the resin slope 22 by a droplet ejection method such as inkjet or dispenser, and the pattern of the wirings 23 and 24 is formed on each electrode of the LED element 11. 17 and 18 and the electrode parts 25 and 26 on the upper surface of the circuit board 21 are drawn, dried and fired, and the electrodes 17 and 18 of the LED element 11 and the electrode parts 25 on the upper surface of the circuit board 21 are drawn. , 26 are connected by wirings 23, 24.
　次に、図２乃至図８を用いて本実施例１のＬＥＤ素子１１の製造方法を説明する。
　ＬＥＤ素子１１は、１枚のウエハ３１（図８に一部分のみ図示）に碁盤目状に多数形成され、最終的に、１枚のウエハ３１がカットラインでダイシングされて多数のＬＥＤ素子１１に分割される。ここでは、ＬＥＤ素子１１の最小限の構成を例にして、製造プロセスを説明する。実際には、犠牲層、バッファ層、クラッド層、コンタクト層等の機能を持った層が複数存在するが、本発明は電極構造を目的とする形状に形成する技術思想であり、半導体製造プロセスは、電極構造とそれに関連する部分を除いて、公知技術と同様の方法を使用すれば良い。 Next, the manufacturing method of the LED element 11 of the present Example 1 is demonstrated using FIG. 2 thru | or FIG.
A large number of LED elements 11 are formed in a grid pattern on one wafer 31 (only part of which is shown in FIG. 8). Finally, one wafer 31 is diced along a cut line and divided into a large number of LED elements 11. Is done. Here, the manufacturing process will be described using the minimum configuration of the LED element 11 as an example. Actually, there are a plurality of layers having functions such as a sacrificial layer, a buffer layer, a cladding layer, and a contact layer, but the present invention is a technical idea of forming the electrode structure into a desired shape, and the semiconductor manufacturing process is A method similar to a known technique may be used except for the electrode structure and related parts.
　図２に示すように、基材１２上に、ｎ型半導体層１３、発光層１４、ｐ型半導体層１５等を順に成膜した後、発光層１４とｐ型半導体層１５を、リソグラフィ技術、エッチング技術を使用して部分的に取り除いて、ｎ型半導体層１３の上面の一部を露出させた状態にする。この後、リソグラフィ技術、エッチング技術を使用して、ｐ型半導体層１５の上面に、透光性と導電性を持つ透明電極１６を形成する。 As shown in FIG. 2, an n-type semiconductor layer 13, a light-emitting layer 14, a p-type semiconductor layer 15, and the like are sequentially formed on the base material 12, and then the light-emitting layer 14 and the p-type semiconductor layer 15 are formed using a lithography technique, An etching technique is used to partially remove the n-type semiconductor layer 13 so that a part of the upper surface is exposed. Thereafter, a transparent electrode 16 having translucency and conductivity is formed on the upper surface of the p-type semiconductor layer 15 by using a lithography technique and an etching technique.
　この後、絶縁保護膜形成工程に進み、図３に示すように、リソグラフィ技術、エッチング技術を使用して、ＬＥＤ素子１１の表面のうち、ｐ側電極１７及びｎ側電極１８等に対する絶縁が必要な部分にＳｉＯ2 等の絶縁保護膜１９をＣＶＤ（化学気相蒸着）により形成する。尚、絶縁保護膜１９の成膜方法は、ＣＶＤに限定されず、スパッタリング等のＰＶＤ（物理気相蒸着）、スプレー、フレキソ等の印刷手法、ディスペンサ、インクジェット等の液滴吐出方法、ゾルゲル法、熱酸化、絶縁性シート貼付等の手法を用いても良い。 Thereafter, the process proceeds to an insulating protective film forming step, and as shown in FIG. 3, it is necessary to insulate the p-side electrode 17 and the n-side electrode 18 and the like on the surface of the LED element 11 using a lithography technique and an etching technique. An insulating protective film 19 such as SiO 2 is formed on this part by CVD (chemical vapor deposition). In addition, the film-forming method of the insulating protective film 19 is not limited to CVD, PVD (physical vapor deposition) such as sputtering, printing methods such as spraying and flexo, droplet discharging methods such as dispensers and inkjets, sol-gel methods, Techniques such as thermal oxidation and insulating sheet sticking may be used.
　また、絶縁保護膜１９のパターンニングも、フォトリソグラフィに限定されず、電子、
イオン、Ｘ線によるマスク有り又はマスク無しのリソグラフィによるレジストマスク、メタルマスク、テープ等のマスクを使用する方法や、成膜範囲を直接制御する方法や、転写を使用しても良い。また、マスク無しで、一旦、ＬＥＤ素子１１の表面全体に絶縁保護膜１９を形成した後に、レジスト又はメタル等のマスクを使用するか、または、エッチング物の接触範囲を微小制御して、溶剤を用いたウェットエッチングや、電子、イオン、レーザ等を用いたドライエッチングや、機械での切削や研磨により絶縁保護膜１９を部分的にエッチングして形成しても良い。 Also, the patterning of the insulating protective film 19 is not limited to photolithography, but electrons,
A method of using a mask such as a resist mask, a metal mask, or a tape by lithography with or without an ion or X-ray mask, a method of directly controlling the film formation range, or transfer may be used. In addition, without forming a mask, once the insulating protective film 19 is formed on the entire surface of the LED element 11, a mask such as a resist or metal is used, or the contact range of the etched product is finely controlled to remove the solvent. The insulating protective film 19 may be partially etched by wet etching used, dry etching using electrons, ions, laser, or the like, or cutting or polishing with a machine.
　この後、電極形成工程に進み、図４に示すように、リソグラフィ技術、エッチング技術を使用して、ＬＥＤ素子１１の表面にｐ側電極１７とｎ側電極１８をスパッタリングにより形成する。ｐ側電極１７の一部を透明電極１６上に形成することで、該ｐ側電極１７を該透明電極１６を介してｐ型半導体層１５に導通させ、ｎ側電極１８をｎ型半導体層１３上に形成することで、該ｎ側電極１８をｎ型半導体層１３に導通させる。ｐ側電極１７をｎ側電極１８とほぼ同一高さの位置まで延びるように形成する。 Thereafter, the process proceeds to an electrode forming step, and as shown in FIG. 4, a p-side electrode 17 and an n-side electrode 18 are formed on the surface of the LED element 11 by sputtering using a lithography technique and an etching technique. By forming a part of the p-side electrode 17 on the transparent electrode 16, the p-side electrode 17 is electrically connected to the p-type semiconductor layer 15 through the transparent electrode 16, and the n-side electrode 18 is connected to the n-type semiconductor layer 13. By forming it above, the n-side electrode 18 is brought into conduction with the n-type semiconductor layer 13. The p-side electrode 17 is formed so as to extend to a position substantially the same height as the n-side electrode 18.
　各電極１７，１８の材料は、金、銀等の金属又はそれらの合金、ＩＴＯ等の透明導電材料、微小の導電材料の粒子を分散させた塗料等を使用しても良い。各電極１７，１８の成膜方法は、蒸着等のＰＶＤ（物理気相蒸着）、スプレー、フレキソ等の印刷手法、ディスペンサ、インクジェット等の液滴吐出方法、ゾルゲル法、熱酸化、導電性シート貼付等の手法を用いても良い。また、１つの成膜方法で成膜が不十分の場合は、複数の成膜方法を組み合わせて使用しても良い。各電極１７，１８のパターンニングは、絶縁保護膜１９のパターンニングと同様の手法を用いれば良い。 The material of each of the electrodes 17 and 18 may be a metal such as gold or silver or an alloy thereof, a transparent conductive material such as ITO, or a paint in which particles of a minute conductive material are dispersed. The film formation method of each electrode 17 and 18 is PVD (physical vapor deposition) such as vapor deposition, printing method such as spray and flexo, droplet ejection method such as dispenser and ink jet, sol-gel method, thermal oxidation, and conductive sheet sticking. A method such as the above may be used. In addition, when film formation is insufficient with one film formation method, a plurality of film formation methods may be used in combination. The patterning of the electrodes 17 and 18 may be performed using the same method as the patterning of the insulating protective film 19.
　各電極１７，１８は、ワイヤボンディングのパッドが無い形状に形成しても良いし、ワイヤボンディングのパッドが有る形状に形成しても良い。ワイヤボンディングのパッド無しの場合は、ＬＥＤ素子１１の発光層１４から放射される光を遮る各電極１７，１８の面積を縮小できる利点があり、発光層１４から放射される光が各電極１７，１８で遮られる割合が最小となるように、各電極１７，１８を最小面積、最小厚みとするように形成することができる。一方、ワイヤボンディングのパッド有りの場合は、ＬＥＤ素子１１の各電極１７，１８と回路基板２１上面の電極部２５，２６との間を接続する配線手段として、図１に示すような液滴吐出法による配線２３，２４のパターンニングと、ワイヤボンディングのどちらも使用可能となり、ＬＥＤ素子１１の配線方法をユーザーが選択できる利点がある。 The electrodes 17 and 18 may be formed in a shape without a wire bonding pad, or may be formed in a shape with a wire bonding pad. When there is no wire bonding pad, there is an advantage that the area of each electrode 17, 18 that blocks the light emitted from the light emitting layer 14 of the LED element 11 can be reduced, and the light emitted from the light emitting layer 14 is reduced to each electrode 17, 18. Each of the electrodes 17 and 18 can be formed to have a minimum area and a minimum thickness so that the ratio blocked by 18 is minimized. On the other hand, when there is a wire bonding pad, droplet discharge as shown in FIG. 1 is used as wiring means for connecting the electrodes 17 and 18 of the LED element 11 and the electrode portions 25 and 26 on the upper surface of the circuit board 21. Both patterning of the wirings 23 and 24 by the method and wire bonding can be used, and there is an advantage that the user can select the wiring method of the LED element 11.
　電極形成工程終了後に、ダイシング工程に進み、多数のＬＥＤ素子１１を形成したウエハ３１をカットライン（図８参照）でダイシングして個々のＬＥＤ素子１１に分割する。 After completion of the electrode formation process, the process proceeds to a dicing process, and the wafer 31 on which a large number of LED elements 11 are formed is diced along a cut line (see FIG. 8) and divided into individual LED elements 11.
　この後、面取り工程に進み、図５に示すように、ダイシングによる切断面の上端角部を面取りする。面取りしたエッジが鋭いと、配線２３，２４が断線しやすくなるため、このエッジを丸く形成した方が良い。各電極１７，１８に接続する配線２３，２４の下地の段差をより少なくするために、面取りした部分に各電極１７，１８につながる電極（導電膜）を形成しても良い。面取りは衝撃によるクラックを緩和するための工程であるが、必須ではなく、省略しても良い。 After this, the process proceeds to the chamfering step, and the upper end corner of the cut surface by dicing is chamfered as shown in FIG. If the chamfered edge is sharp, the wires 23 and 24 are likely to be disconnected. Therefore, it is preferable to form the edge round. An electrode (conductive film) connected to each of the electrodes 17 and 18 may be formed on the chamfered portion in order to reduce the underlying step of the wirings 23 and 24 connected to each of the electrodes 17 and 18. Chamfering is a process for alleviating cracks due to impact, but is not essential and may be omitted.
　また、図７に示すように、ＬＥＤ素子１１の下部側の基材１２の部分を剥離又は切削により除去してＬＥＤ素子１１の高さを低くするようにしても良い。 Further, as shown in FIG. 7, the portion of the base 12 on the lower side of the LED element 11 may be removed by peeling or cutting to reduce the height of the LED element 11.
　以上説明した本実施例１のＬＥＤ素子１１は、ｐ型半導体層１５がｎ型半導体層１３（ｎ側電極１８）よりも高い構成でありながら、ｐ型半導体層１５に導通するｐ側電極１７とｎ型半導体層１３に導通するｎ側電極１８とがほぼ同一高さとなっているため、配線２
３，２４の下地である樹脂スロープ２２が左右対称の形状となって、樹脂スロープ２２を形成するプロセスが容易となり、配線２３，２４の下地の段差を低減しやすくなる。これにより、配線２３，２４を成膜しやすくなり、成膜法で接続信頼性の高い配線２３，２４を形成できる。しかも、ＬＥＤ素子１１の製造工程で、配線２３，２４の信頼性の対策を行うことができるため、ＬＥＤ素子１１の製造と配線２３，２４の形成を総合的に考えて、無駄な工程や技術要求を減らすことができる。 In the LED element 11 according to the first embodiment described above, the p-type electrode 17 is electrically connected to the p-type semiconductor layer 15 while the p-type semiconductor layer 15 is higher than the n-type semiconductor layer 13 (n-side electrode 18). And the n-side electrode 18 conducting to the n-type semiconductor layer 13 have almost the same height.
The resin slope 22 which is the base of 3 and 24 becomes a symmetrical shape, the process of forming the resin slope 22 is facilitated, and the step of the base of the wirings 23 and 24 is easily reduced. As a result, the wirings 23 and 24 can be easily formed, and the wirings 23 and 24 having high connection reliability can be formed by a film forming method. Moreover, since it is possible to take measures against the reliability of the wirings 23 and 24 in the manufacturing process of the LED element 11, the manufacturing process of the LED element 11 and the formation of the wirings 23 and 24 are considered comprehensively, and unnecessary processes and techniques are performed. The demand can be reduced.
　次に、図９乃至図１５を用いて本発明の実施例２を説明する。但し、上記実施例１と実質的に同一の部分については同一符号を付して説明を省略又は簡単化し、主として異なる部分を説明する。 Next, Embodiment 2 of the present invention will be described with reference to FIGS. However, substantially the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted or simplified, and different parts are mainly described.
　本実施例２において、上記実施例１と異なる部分は、電極構造と実装構造である。
　本実施例２では、ＬＥＤ素子１１のｐ側電極３５とｎ側電極３６を、それぞれＬＥＤ素子１１の側面に沿ってその下端まで延びるように形成している。具体的には、ＬＥＤ素子１１の側面には、ＬＥＤ素子１１の製造時にスルーホール３７をダイシングにより半割りして形成された２本の半割り溝３７ａが形成され、該２本の半割り溝３７ａに絶縁保護膜３８を介してｐ側電極３５とｎ側電極３６が各半割り溝３７ａの下端まで延びるように形成されている。 In the second embodiment, the difference from the first embodiment is an electrode structure and a mounting structure.
In the second embodiment, the p-side electrode 35 and the n-side electrode 36 of the LED element 11 are formed so as to extend along the side surface of the LED element 11 to the lower end thereof. Specifically, on the side surface of the LED element 11, two half grooves 37 a formed by dividing the through hole 37 by dicing at the time of manufacturing the LED element 11 are formed, and the two half grooves A p-side electrode 35 and an n-side electrode 36 are formed on 37a so as to extend to the lower end of each half-groove 37a via an insulating protective film 38.
　この電極構造により、本実施例２では、図９に示すように、ＬＥＤ素子１１を回路基板２１上に実装したときに、ｐ側電極３５とｎ側電極３６が回路基板２１の電極部２５，２６に接触した状態となり、この状態でｐ側電極３５とｎ側電極３６を回路基板２１の電極部２５，２６に導電性接着剤４０や半田等で接続すれば良い。 With this electrode structure, in Example 2, as shown in FIG. 9, when the LED element 11 is mounted on the circuit board 21, the p-side electrode 35 and the n-side electrode 36 are connected to the electrode portions 25 of the circuit board 21. In this state, the p-side electrode 35 and the n-side electrode 36 may be connected to the electrode portions 25 and 26 of the circuit board 21 with a conductive adhesive 40, solder, or the like.
　次に、図１０乃至図１５を用いて本実施例２のＬＥＤ素子１１の製造方法を説明する。
　ＬＥＤ素子１１は、１枚のウエハ３１（図８に一部分のみ図示）に碁盤目状に多数形成され、最終的に、１枚のウエハ３１がカットラインでダイシングされて多数のＬＥＤ素子１１に分割される。 Next, a method for manufacturing the LED element 11 according to the second embodiment will be described with reference to FIGS.
A large number of LED elements 11 are formed in a grid pattern on one wafer 31 (only part of which is shown in FIG. 8). Finally, one wafer 31 is diced along a cut line and divided into a large number of LED elements 11. Is done.
　前記実施例１と同様の方法で、透明電極形成工程まで実行した後、スルーホール形成工程に進み、図１０及び図１１に示すように、ウエハ３１の各ＬＥＤ素子１１間のうちのダイシングのカットライン上の位置に、スルーホール３７をＣＯ2 レーザ等によりウエハ３１を貫通するように形成する。各スルーホール３７の中心は、ダイシングのカットラインと一致している。尚、スルーホール３７の穴明け加工は、ＣＯ2 レーザに限定されず、ＣＯ2 以外のエキシマ等のレーザ、イオン、電子、機械での切削加工を用いても良い。 After performing the transparent electrode forming process in the same manner as in Example 1, the process proceeds to the through hole forming process, and as shown in FIGS. 10 and 11, the dicing cut between the LED elements 11 on the wafer 31 is cut. A through hole 37 is formed at a position on the line so as to penetrate the wafer 31 by a CO 2 laser or the like. The center of each through hole 37 coincides with the cutting line for dicing. The through hole 37 is not limited to the CO 2 laser, and excimer lasers other than CO 2 , ion, electronic, or mechanical cutting may be used.
　この後、絶縁保護膜形成工程に進み、図１２に示すように、リソグラフィ技術、エッチング技術を使用して、ＬＥＤ素子１１の表面及びスルーホール３７の内周面のうち、ｐ側電極３５及びｎ側電極３６等に対する絶縁が必要な部分にＳｉＯ2 等の絶縁保護膜３８をＣＶＤ（化学気相蒸着）により形成する。 Thereafter, the process proceeds to an insulating protective film forming step, and as shown in FIG. 12, the p-side electrode 35 and n of the surface of the LED element 11 and the inner peripheral surface of the through hole 37 are formed using a lithography technique and an etching technique. An insulating protective film 38 such as SiO 2 is formed by CVD (Chemical Vapor Deposition) at a portion that needs to be insulated from the side electrode 36 and the like.
　この後、電極形成工程に進み、図１３に示すように、リソグラフィ技術、エッチング技術を使用して、ＬＥＤ素子１１の表面とスルーホール３７の内周面にｐ側電極３５とｎ側電極３６をスパッタリングにより形成する。各電極３５，３６は、前記実施例１と同様に、スパッタリング以外の方法で形成しても良い。 Thereafter, the process proceeds to an electrode forming process, and as shown in FIG. 13, the p-side electrode 35 and the n-side electrode 36 are formed on the surface of the LED element 11 and the inner peripheral surface of the through hole 37 by using a lithography technique and an etching technique. It is formed by sputtering. The electrodes 35 and 36 may be formed by a method other than sputtering, as in the first embodiment.
　この後、ダイシング工程に進み、多数のＬＥＤ素子１１を形成したウエハ３１をカットライン（スルーホール３７の中心線）に沿ってダイシングして、図１４及び図１５に示す構造のＬＥＤ素子１１に分割する。これにより、各ＬＥＤ素子１１の両側面にそれぞれ半
割り溝３７ａが形成され、各半割り溝３７ａの内周面に絶縁保護膜３８を介して各電極３５，３６が各半割り溝３７ａの下端まで延びるように形成される。 Thereafter, the process proceeds to a dicing process, and the wafer 31 on which a large number of LED elements 11 are formed is diced along a cut line (center line of the through hole 37) and divided into the LED elements 11 having the structure shown in FIGS. To do. As a result, half grooves 37a are formed on both side surfaces of each LED element 11, and each electrode 35, 36 is provided on the inner peripheral surface of each half groove 37a via the insulating protective film 38, and the lower end of each half groove 37a. It is formed to extend up to.
　この後、面取り工程に進み、各ＬＥＤ素子１１のダイシングによる切断面の上端角部を面取りする。面取りは衝撃によるクラックを緩和するための工程であるが、必須ではなく、省略しても良い。また、ＬＥＤ素子１１の下部側の基材１２の部分を剥離又は切削により除去してＬＥＤ素子１１の高さを低くするようにしても良い。 Thereafter, the process proceeds to a chamfering step, and the upper end corner of the cut surface by dicing of each LED element 11 is chamfered. Chamfering is a process for alleviating cracks due to impact, but is not essential and may be omitted. Moreover, you may make it make the height of the LED element 11 low by removing the part of the base material 12 of the lower side of the LED element 11 by peeling or cutting.
　以上説明した本実施例２によれば、ＬＥＤ素子１１のｐ側電極３５とｎ側電極３６を、それぞれＬＥＤ素子１１の側面に沿ってその下端まで延びるように形成しているため、ＬＥＤ素子１１を回路基板２１上に実装したときに、ｐ側電極３５とｎ側電極３６が回路基板２１の電極部２５，２６に接触した状態となり、この状態でｐ側電極３５とｎ側電極３６を回路基板２１の電極部２５，２６に導電性接着剤４０や半田等で接続することができる。このため、ＬＥＤ素子１１の各電極３５，３６と回路基板２１上面の電極部２５，２６との間を接続する配線や樹脂スロープの形成が不要となり、ＬＥＤ素子１１の実装工程を簡略化できる。 According to the second embodiment described above, the p-side electrode 35 and the n-side electrode 36 of the LED element 11 are formed so as to extend to the lower end along the side surfaces of the LED element 11, respectively. Is mounted on the circuit board 21, the p-side electrode 35 and the n-side electrode 36 are in contact with the electrode portions 25 and 26 of the circuit board 21. In this state, the p-side electrode 35 and the n-side electrode 36 are connected to the circuit. It can be connected to the electrode portions 25 and 26 of the substrate 21 with a conductive adhesive 40 or solder. For this reason, it is not necessary to form wirings or resin slopes for connecting the electrodes 35, 36 of the LED element 11 and the electrode portions 25, 26 on the upper surface of the circuit board 21, and the mounting process of the LED element 11 can be simplified.
　但し、本発明は、必ずしも、ＬＥＤ素子１１のｐ側電極３５とｎ側電極３６をＬＥＤ素子１１の側面の下端まで延ばす必要はなく、各電極３５，３６がＬＥＤ素子１１の側面の所定高さまで延びた構成としても良い。この場合は、スルーホール３７がウエハ３１を貫通する必要はない。ＬＥＤ素子１１の各電極３５，３６をＬＥＤ素子１１の側面の下端まで延ばさない場合でも、最小限の樹脂スロープの形成により配線下地の段差を低減することができ、樹脂材料が電極３５，３６を覆い隠して電極３５，３６との導通が取れなくなってしまう可能性も低い。 However, in the present invention, it is not always necessary to extend the p-side electrode 35 and the n-side electrode 36 of the LED element 11 to the lower end of the side surface of the LED element 11, and each electrode 35, 36 has a predetermined height on the side surface of the LED element 11. An extended configuration may be used. In this case, the through hole 37 does not need to penetrate the wafer 31. Even when the electrodes 35 and 36 of the LED element 11 are not extended to the lower end of the side surface of the LED element 11, the step of the wiring substrate can be reduced by forming a minimum resin slope, and the resin material can be used for the electrodes 35 and 36. There is also a low possibility that the connection with the electrodes 35 and 36 will be lost due to the covering.
　尚、本発明は、上記各実施例１，２に限定されず、ＬＥＤ素子の基材や各半導体層、電極の形状は、「導通する」、「ｐｎ接合が起きている」等の各用途の目的を満たせば良く、また、各用途によっては、より良い形状を採用しても良い。 In addition, this invention is not limited to said each Example 1 and 2, The shape of the base material of each LED element, each semiconductor layer, and an electrode is each conduction | electrical_connection, "the pn junction is taking place", etc. It is sufficient to satisfy the above-mentioned purpose, and a better shape may be adopted depending on each application.
　また、上記各実施例１，２では、ＬＥＤ素子１１を回路基板２１上に搭載するようにしたが、搭載部材の凹部内にＬＥＤ素子１１を搭載するようにしても良い。 In each of the first and second embodiments, the LED element 11 is mounted on the circuit board 21. However, the LED element 11 may be mounted in the recess of the mounting member.
　その他、本発明は、ＬＥＤ素子等の発光素子に限定されず、それ以外の半導体素子に適用して実施できる等、要旨を逸脱しない範囲内で種々変更して実施できることは言うまでもない。 In addition, it goes without saying that the present invention is not limited to light emitting elements such as LED elements, and can be implemented with various modifications without departing from the gist, such as being applicable to other semiconductor elements.
　１１…ＬＥＤ素子（半導体素子）、１２…基材、１３…ｎ型半導体層、１４…発光層、１５…ｐ型半導体層、１６…透明電極、１７…ｐ側電極、１８…ｎ側電極、１９…絶縁保護膜、２１…回路基板、２２…樹脂スロープ、２３，２４…配線、２５，２６…電極部、３１…ウエハ、３５…ｐ側電極、３６…ｎ側電極、３７…スルーホール、３７ａ…半割り溝、３８…絶縁保護膜、４０…導電性接着剤 DESCRIPTION OF SYMBOLS 11 ... LED element (semiconductor element), 12 ... Base material, 13 ... N-type semiconductor layer, 14 ... Light emitting layer, 15 ... P-type semiconductor layer, 16 ... Transparent electrode, 17 ... P-side electrode, 18 ... N-side electrode, DESCRIPTION OF SYMBOLS 19 ... Insulating protective film, 21 ... Circuit board, 22 ... Resin slope, 23, 24 ... Wiring, 25, 26 ... Electrode part, 31 ... Wafer, 35 ... P side electrode, 36 ... N side electrode, 37 ... Through hole, 37a: Half groove, 38: Insulating protective film, 40: Conductive adhesive

Claims (8)

  1. 　半導体素子の上部側にｐ型半導体層とｎ型半導体層が形成された半導体素子の電極構造において、
    　前記ｐ型半導体層に導通するｐ側電極と前記ｎ型半導体層に導通するｎ側電極とがほぼ同一高さで、且つ、前記ｐ側電極が前記ｐ型半導体層より低い位置に形成されていることを特徴とする半導体素子の電極構造。     In an electrode structure of a semiconductor element in which a p-type semiconductor layer and an n-type semiconductor layer are formed on the upper side of the semiconductor element,
    The p-side electrode that conducts to the p-type semiconductor layer and the n-side electrode that conducts to the n-type semiconductor layer have substantially the same height, and the p-side electrode is formed at a position lower than the p-type semiconductor layer. An electrode structure of a semiconductor element, characterized by comprising:
  2. 　前記ｐ側電極が前記ｎ側電極とほぼ同一高さの位置まで延びるように形成されていることを特徴とする請求項１に記載の半導体素子の電極構造。 2. The electrode structure of a semiconductor element according to claim 1, wherein the p-side electrode is formed so as to extend to a position having substantially the same height as the n-side electrode.
  3. 　前記ｐ側電極と前記ｎ側電極は、それぞれ前記半導体素子の側面に沿ってその下端まで延びるように形成されていることを特徴とする請求項１又は２に記載の半導体素子の電極構造。 3. The semiconductor element electrode structure according to claim 1, wherein each of the p-side electrode and the n-side electrode is formed so as to extend along the side surface of the semiconductor element to a lower end thereof.
  4. 　前記半導体素子の側面には、該半導体素子の製造時にスルーホールをダイシングにより半割りして形成された２本の半割り溝が形成され、該２本の半割り溝に前記ｐ側電極と前記ｎ側電極が形成されていることを特徴とする請求項３に記載の半導体素子の電極構造。 On the side surface of the semiconductor element, two half grooves formed by dividing a through hole by dicing at the time of manufacturing the semiconductor element are formed, and the p-side electrode and the half groove are formed in the two half grooves. 4. The electrode structure of a semiconductor element according to claim 3, wherein an n-side electrode is formed.
  5. 　前記半導体素子は、発光素子であることを特徴とする請求項１乃至４のいずれかに記載の半導体素子の電極構造。 5. The electrode structure of a semiconductor element according to claim 1, wherein the semiconductor element is a light emitting element.
  6. 　前記ｐ側電極と前記ｎ側電極は、ワイヤボンディングのパッドの無い形状に形成されていることを特徴とする請求項１乃至５のいずれかに記載の半導体素子の電極構造。 6. The electrode structure of a semiconductor element according to claim 1, wherein the p-side electrode and the n-side electrode are formed in a shape without a wire bonding pad.
  7. 　請求項１乃至６のいずれかに記載の半導体素子の電極構造を製造する方法において、
    　前記半導体素子の表面のうち前記ｐ側電極及び前記ｎ側電極に対する絶縁が必要な部分に絶縁保護膜を形成した後、前記ｐ側電極及び前記ｎ側電極を形成することを特徴とする半導体素子の電極構造の製造方法。     In the method for manufacturing the electrode structure of the semiconductor element according to claim 1,
    An insulating protective film is formed on a portion of the surface of the semiconductor element that needs to be insulated from the p-side electrode and the n-side electrode, and then the p-side electrode and the n-side electrode are formed. Manufacturing method of the electrode structure.
  8. 　請求項４に記載の半導体素子の電極構造を製造する方法において、
    　１枚のウエハに複数の半導体素子を形成すると共に、各半導体素子の間にスルーホールを形成し、前記半導体素子の表面及び前記スルーホールの内周面のうち前記ｐ側電極及び前記ｎ側電極に対する絶縁が必要な部分に絶縁保護膜を形成した後、前記ｐ側電極及び前記ｎ側電極を形成した上で、前記ウエハを前記スルーホールの中心線に沿ってダイシングして各半導体素子に分割することを特徴とする半導体素子の電極構造の製造方法。     The method for manufacturing an electrode structure of a semiconductor device according to claim 4,
    A plurality of semiconductor elements are formed on a single wafer, and through holes are formed between the semiconductor elements. The p-side electrode and the n-side electrode are formed on the surface of the semiconductor element and the inner peripheral surface of the through-hole. After forming an insulating protective film on a portion that needs to be insulated from the substrate, the p-side electrode and the n-side electrode are formed, and then the wafer is diced along the center line of the through-hole to be divided into semiconductor elements. A method of manufacturing an electrode structure of a semiconductor element.
PCT/JP2012/074883 2012-09-27 2012-09-27 Structure of electrode of semiconductor element, and method for manufacturing structure of electrode of semiconductor element WO2014049774A1 (en)

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