JPWO2014049774A1 - Electrode structure of semiconductor element and manufacturing method thereof - Google Patents

Abstract

In consideration of the fact that the p-type semiconductor layer 15 of the LED element 11 is higher than the n-type semiconductor layer 13 (n-side electrode 18), the p-side electrode 17 extends to a position substantially the same height as the n-side electrode 18. Is formed. Thus, the p-side electrode 17 and the n-side electrode 18 are formed at substantially the same height, and the p-side electrode 17 is formed at a position lower than the p-type semiconductor layer 15. In this way, if the p-side electrode 17 and the n-side electrode 18 are substantially the same height, the resin slope 22 that is the base of the wirings 23 and 24 has a symmetrical shape, and therefore the process of forming the resin slope 22. It becomes easy to reduce the level difference of the base of the wirings 23 and 24. Thereby, the wirings 23 and 24 with high connection reliability can be formed by a film forming method.

Description

  The present invention relates to an electrode structure of a semiconductor element in which a p-type semiconductor layer and an n-type semiconductor layer are formed on the upper side of the semiconductor element, and a manufacturing method thereof.

  In the conventional semiconductor element, after die-bonding to a mounting member (circuit board, lead frame, etc.), wiring between the electrode part on the semiconductor element side and the electrode part on the mounting member side is generally performed by wire bonding. .

  However, as described in Patent Document 1 (Japanese Patent No. 3992038), there is a possibility that defects may occur due to mechanical stress when wire bonding is performed. Therefore, connection reliability that replaces wire bonding is high. For the purpose of realizing the mounting structure at low cost, the resin material liquid is discharged by a dispenser around the semiconductor element mounted on the wiring board and cured, so that the space between the upper surface of the semiconductor element and the surface of the wiring board is obtained. After forming a resin slope that connects the inclined surfaces, conductive ink is ejected by a droplet ejection method such as ink jet along the wiring path connecting the electrode portion on the upper surface of the semiconductor element and the electrode portion of the wiring board. It has been proposed to form wiring.

Japanese Patent No. 3992038

  However, in order to form a resin slope of the target shape, technical requirements such as the filling accuracy of the resin material are high, and the resin material covers the electrode so that it cannot be connected to the electrode, or the wiring base This step may not be sufficiently reduced, and the formed wiring may be easily broken. Further, in the case of a semiconductor element having an asymmetrical shape, the shape of the resin slope to be formed must be adjusted on the left and right sides, and the process of reducing the step becomes difficult. The root cause of such problems is that the electrodes of current semiconductor elements are formed on the premise of wire bonding, and are not manufactured on the assumption that wiring is formed on the surface of the semiconductor elements. is there.

  In order to solve the above-described problems, the present invention provides a p-side electrode electrically connected to the p-type semiconductor layer in an electrode structure of a semiconductor element in which a p-type semiconductor layer and an n-type semiconductor layer are formed on an upper side of the semiconductor element. The n-side electrode conducting to the n-type semiconductor layer is substantially the same height, and the p-side electrode is formed at a position lower than the p-type semiconductor layer. In this configuration, since the p-side electrode and the n-side electrode are substantially the same height, the process of smoothing the wiring base becomes easy, and the step of the wiring base can be easily reduced. Thereby, it becomes easy to form a wiring, and a wiring with high connection reliability can be formed by a film forming method.

  In this case, considering that the p-type semiconductor layer is higher than the n-type semiconductor layer (n-side electrode), the p-side electrode may be formed so as to extend to a position that is substantially the same height as the n-side electrode.

In the present invention, the p-side electrode and the n-side electrode may each be formed so as to extend to the lower end along the side surface of the semiconductor element. In this way, when the semiconductor element is mounted on the circuit board, the p-side electrode and the n-side electrode can be directly connected to the electrode portion of the circuit board without using wiring.

  When manufacturing a semiconductor element having this configuration, a plurality of semiconductor elements are formed on a single wafer, and through holes are formed between the semiconductor elements. Of the surface of the semiconductor element and the inner peripheral surface of the through hole, After forming an insulating protective film in a portion that needs to be insulated from the p-side electrode and the n-side electrode, the p-side electrode and the n-side electrode are formed, and then the wafer is diced along the center line of the through-hole. What is necessary is just to divide | segment into an element.

1 is a longitudinal sectional view showing a mounting structure of an LED element according to Embodiment 1 of the present invention. FIG. 2 is a longitudinal sectional view of the LED element for explaining the transparent electrode forming step of Example 1. FIG. 3 is a vertical cross-sectional view of the LED element for explaining the insulating protective film forming step of the first embodiment. FIG. 4 is a vertical cross-sectional view of the LED element for explaining the electrode forming process of the first embodiment. FIG. 5 is a longitudinal sectional view of an LED element for explaining the chamfering process of the first embodiment. FIG. 6 is a longitudinal sectional view showing an element structure in which the lower base material of the LED element of Example 1 is removed to reduce the height of the LED element. FIG. 7 is a plan view of the LED element of Example 1. FIG. FIG. 8 is a plan view showing a state before a dicing process in which a plurality of LED elements of Example 1 are formed on one wafer. FIG. 9 is a longitudinal sectional view showing the mounting structure of the LED element of Example 2 of the present invention. FIG. 10 is a plan view of a part of the wafer for explaining the through hole forming process of the second embodiment. FIG. 11 is a longitudinal sectional view of a part of the wafer for explaining the through hole forming process of the second embodiment. FIG. 12 is a longitudinal sectional view of a part of the wafer for explaining the insulating protective film forming step of the second embodiment. FIG. 13 is a longitudinal sectional view of a part of the wafer for explaining the electrode forming process of the second embodiment. FIG. 14 is a longitudinal sectional view of an LED element for explaining the dicing process of the second embodiment. FIG. 15 is a plan view of the LED element of Example 2. FIG.

  Hereinafter, two Examples 1 and 2 which embodied the form for implementing this invention to an LED element are demonstrated.

A first embodiment of the present invention will be described with reference to FIGS.
First, the structure and mounting structure of the LED element 11 of Example 1 will be described with reference to FIGS. 1 and 5. The LED element 11 is formed by sequentially forming an n-type semiconductor layer 13, a light emitting layer 14, a p-type semiconductor layer 15, etc. on a base material 12, and a transparent electrode 16 is formed on the p-type semiconductor layer 15. Yes. An insulating protective film 19 is formed on a portion of the surface of the LED element 11 that needs to be insulated from the p-side electrode 17 and the n-side electrode 18.

  A part of the p-side electrode 17 is formed on the transparent electrode 16 so as to conduct to the p-type semiconductor layer 15 through the transparent electrode 16, and the n-side electrode 18 is formed on the n-type semiconductor layer 13. As a result, the n-type semiconductor layer 13 is electrically connected.

  In this case, in consideration of the fact that the p-type semiconductor layer 15 is higher than the n-type semiconductor layer 13 (n-side electrode 18), the p-side electrode 17 is formed so as to extend to a position substantially the same height as the n-side electrode 18. Has been. As a result, the p-side electrode 17 and the n-side electrode 18 have substantially the same height, and the p-side electrode 17 is formed at a position lower than the p-type semiconductor layer 15.

  An example of the mounting structure of the LED element 11 configured as described above will be described with reference to FIG. In this example, the LED element 11 is die-bonded on a circuit board 21 that is a mounting member. Around the LED element 11, a fluid resin material is discharged by a dispenser to form an insulating resin slope 22 that connects the upper surface of the LED element 11 and the upper surface of the circuit board 21 with an inclined surface.

  Thereafter, conductive ink (ink containing conductive particles such as Ag) is ejected onto the resin slope 22 by a droplet ejection method such as inkjet or dispenser, and the pattern of the wirings 23 and 24 is formed on each electrode of the LED element 11. 17 and 18 and the electrode parts 25 and 26 on the upper surface of the circuit board 21 are drawn, dried and fired, and the electrodes 17 and 18 of the LED element 11 and the electrode parts 25 on the upper surface of the circuit board 21 are drawn. , 26 are connected by wirings 23, 24.

Next, the manufacturing method of the LED element 11 of the present Example 1 is demonstrated using FIG. 2 thru | or FIG.
A large number of LED elements 11 are formed in a grid pattern on one wafer 31 (only part of which is shown in FIG. 8). Finally, one wafer 31 is diced along a cut line and divided into a large number of LED elements 11. Is done. Here, the manufacturing process will be described using the minimum configuration of the LED element 11 as an example. Actually, there are a plurality of layers having functions such as a sacrificial layer, a buffer layer, a cladding layer, and a contact layer, but the present invention is a technical idea of forming the electrode structure into a desired shape, and the semiconductor manufacturing process is A method similar to a known technique may be used except for the electrode structure and related parts.

  As shown in FIG. 2, an n-type semiconductor layer 13, a light-emitting layer 14, a p-type semiconductor layer 15, and the like are sequentially formed on the base material 12, and then the light-emitting layer 14 and the p-type semiconductor layer 15 are formed using a lithography technique, An etching technique is used to partially remove the n-type semiconductor layer 13 so that a part of the upper surface is exposed. Thereafter, a transparent electrode 16 having translucency and conductivity is formed on the upper surface of the p-type semiconductor layer 15 by using a lithography technique and an etching technique.

Thereafter, the process proceeds to an insulating protective film forming step, and as shown in FIG. 3, it is necessary to insulate the p-side electrode 17 and the n-side electrode 18 among the surface of the LED element 11 using a lithography technique and an etching technique. An insulating protective film 19 such as SiO ₂ is formed on this part by CVD (chemical vapor deposition). In addition, the film-forming method of the insulating protective film 19 is not limited to CVD, PVD (physical vapor deposition) such as sputtering, printing methods such as spraying and flexo, droplet discharging methods such as dispensers and inkjets, sol-gel methods, Techniques such as thermal oxidation and insulating sheet sticking may be used.

Also, the patterning of the insulating protective film 19 is not limited to photolithography, but electrons,
A method of using a mask such as a resist mask, a metal mask, or a tape by lithography with or without an ion or X-ray mask, a method of directly controlling the film formation range, or transfer may be used. In addition, without forming a mask, once the insulating protective film 19 is formed on the entire surface of the LED element 11, a mask such as a resist or metal is used, or the contact range of the etched product is finely controlled to remove the solvent. The insulating protective film 19 may be partially etched by wet etching used, dry etching using electrons, ions, laser, or the like, or cutting or polishing with a machine.

  Then, it progresses to an electrode formation process, and as shown in FIG. 4, the p side electrode 17 and the n side electrode 18 are formed in the surface of the LED element 11 by sputtering using a lithography technique and an etching technique. By forming a part of the p-side electrode 17 on the transparent electrode 16, the p-side electrode 17 is electrically connected to the p-type semiconductor layer 15 through the transparent electrode 16, and the n-side electrode 18 is connected to the n-type semiconductor layer 13. By forming it above, the n-side electrode 18 is brought into conduction with the n-type semiconductor layer 13. The p-side electrode 17 is formed so as to extend to a position substantially the same height as the n-side electrode 18.

  As the material of each of the electrodes 17 and 18, a metal such as gold or silver or an alloy thereof, a transparent conductive material such as ITO, a paint in which particles of a minute conductive material are dispersed, or the like may be used. The film formation method of each electrode 17 and 18 is PVD (physical vapor deposition) such as vapor deposition, printing method such as spray and flexo, droplet ejection method such as dispenser and ink jet, sol-gel method, thermal oxidation, and conductive sheet sticking. A method such as the above may be used. In addition, when film formation is insufficient with one film formation method, a plurality of film formation methods may be used in combination. The patterning of the electrodes 17 and 18 may be performed using the same method as the patterning of the insulating protective film 19.

  Each of the electrodes 17 and 18 may be formed in a shape without a wire bonding pad, or may be formed in a shape with a wire bonding pad. When there is no wire bonding pad, there is an advantage that the area of each electrode 17, 18 that blocks the light emitted from the light emitting layer 14 of the LED element 11 can be reduced, and the light emitted from the light emitting layer 14 is reduced to each electrode 17, 18. Each of the electrodes 17 and 18 can be formed to have a minimum area and a minimum thickness so that the ratio blocked by 18 is minimized. On the other hand, when there is a wire bonding pad, droplet discharge as shown in FIG. 1 is used as wiring means for connecting the electrodes 17 and 18 of the LED element 11 and the electrode portions 25 and 26 on the upper surface of the circuit board 21. Both patterning of the wirings 23 and 24 by the method and wire bonding can be used, and there is an advantage that the user can select the wiring method of the LED element 11.

  After completion of the electrode formation process, the process proceeds to a dicing process, and the wafer 31 on which a large number of LED elements 11 are formed is diced along a cut line (see FIG. 8) and divided into individual LED elements 11.

  Then, it progresses to a chamfering process and chamfers the upper end corner of the cut surface by dicing as shown in FIG. If the chamfered edge is sharp, the wires 23 and 24 are likely to be disconnected. An electrode (conductive film) connected to each of the electrodes 17 and 18 may be formed on the chamfered portion in order to reduce the underlying step of the wirings 23 and 24 connected to each of the electrodes 17 and 18. Chamfering is a process for alleviating cracks due to impact, but is not essential and may be omitted.

  Moreover, as shown in FIG. 7, you may make it make the height of the LED element 11 low by removing the part of the base material 12 of the lower side of the LED element 11 by peeling or cutting.

In the LED element 11 according to the first embodiment described above, the p-type electrode 17 is electrically connected to the p-type semiconductor layer 15 while the p-type semiconductor layer 15 is higher than the n-type semiconductor layer 13 (n-side electrode 18). And the n-side electrode 18 conducting to the n-type semiconductor layer 13 have almost the same height.
The resin slope 22 which is the base of 3 and 24 becomes a symmetrical shape, the process of forming the resin slope 22 is facilitated, and the step of the base of the wirings 23 and 24 is easily reduced. As a result, the wirings 23 and 24 can be easily formed, and the wirings 23 and 24 having high connection reliability can be formed by a film forming method. Moreover, since it is possible to take measures against the reliability of the wirings 23 and 24 in the manufacturing process of the LED element 11, the manufacturing process of the LED element 11 and the formation of the wirings 23 and 24 are considered comprehensively, and unnecessary processes and techniques are performed. The demand can be reduced.

  Next, Embodiment 2 of the present invention will be described with reference to FIGS. However, substantially the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted or simplified, and different parts are mainly described.

In the second embodiment, the difference from the first embodiment is an electrode structure and a mounting structure.
In the second embodiment, the p-side electrode 35 and the n-side electrode 36 of the LED element 11 are formed so as to extend along the side surface of the LED element 11 to the lower end thereof. Specifically, on the side surface of the LED element 11, two half grooves 37 a formed by dividing the through hole 37 by dicing at the time of manufacturing the LED element 11 are formed, and the two half grooves A p-side electrode 35 and an n-side electrode 36 are formed on 37a so as to extend to the lower end of each half-groove 37a via an insulating protective film 38.

  With this electrode structure, in Example 2, as shown in FIG. 9, when the LED element 11 is mounted on the circuit board 21, the p-side electrode 35 and the n-side electrode 36 are connected to the electrode portions 25 of the circuit board 21. In this state, the p-side electrode 35 and the n-side electrode 36 may be connected to the electrode portions 25 and 26 of the circuit board 21 with a conductive adhesive 40, solder, or the like.

Next, a method for manufacturing the LED element 11 according to the second embodiment will be described with reference to FIGS.
A large number of LED elements 11 are formed in a grid pattern on one wafer 31 (only part of which is shown in FIG. 8). Finally, one wafer 31 is diced along a cut line and divided into a large number of LED elements 11. Is done.

After performing the transparent electrode forming process in the same manner as in Example 1, the process proceeds to the through hole forming process, and as shown in FIGS. 10 and 11, the dicing cut between the LED elements 11 on the wafer 31 is cut. A through hole 37 is formed at a position on the line so as to penetrate the wafer 31 by a CO ₂ laser or the like. The center of each through hole 37 coincides with the cutting line for dicing. The through hole 37 is not limited to the CO ₂ laser, and excimer lasers other than CO ₂ , ion, electronic, or mechanical cutting may be used.

Thereafter, the process proceeds to an insulating protective film forming step, and as shown in FIG. 12, the p-side electrode 35 and n of the surface of the LED element 11 and the inner peripheral surface of the through hole 37 are formed using a lithography technique and an etching technique. An insulating protective film 38 such as SiO ₂ is formed by CVD (Chemical Vapor Deposition) at a portion that needs to be insulated from the side electrode 36 and the like.

  Thereafter, the process proceeds to an electrode forming process, and as shown in FIG. 13, the p-side electrode 35 and the n-side electrode 36 are formed on the surface of the LED element 11 and the inner peripheral surface of the through hole 37 by using a lithography technique and an etching technique. It is formed by sputtering. The electrodes 35 and 36 may be formed by a method other than sputtering, as in the first embodiment.

Thereafter, the process proceeds to a dicing process, and the wafer 31 on which a large number of LED elements 11 are formed is diced along a cut line (center line of the through hole 37) and divided into the LED elements 11 having the structure shown in FIGS. To do. As a result, half grooves 37a are formed on both side surfaces of each LED element 11, and each electrode 35, 36 is provided on the inner peripheral surface of each half groove 37a via the insulating protective film 38, and the lower end of each half groove 37a. It is formed to extend up to.

  Then, it progresses to a chamfering process and chamfers the upper end corner of the cut surface by dicing of each LED element 11. Chamfering is a process for alleviating cracks due to impact, but is not essential and may be omitted. Moreover, you may make it make the height of the LED element 11 low by removing the part of the base material 12 of the lower side of the LED element 11 by peeling or cutting.

  According to the second embodiment described above, the p-side electrode 35 and the n-side electrode 36 of the LED element 11 are formed so as to extend to the lower end along the side surfaces of the LED element 11, respectively. Is mounted on the circuit board 21, the p-side electrode 35 and the n-side electrode 36 are in contact with the electrode portions 25 and 26 of the circuit board 21. In this state, the p-side electrode 35 and the n-side electrode 36 are connected to the circuit. It can be connected to the electrode portions 25 and 26 of the substrate 21 with a conductive adhesive 40 or solder. For this reason, it is not necessary to form wirings or resin slopes for connecting the electrodes 35, 36 of the LED element 11 and the electrode portions 25, 26 on the upper surface of the circuit board 21, and the mounting process of the LED element 11 can be simplified.

  However, in the present invention, it is not always necessary to extend the p-side electrode 35 and the n-side electrode 36 of the LED element 11 to the lower end of the side surface of the LED element 11, and each electrode 35, 36 has a predetermined height on the side surface of the LED element 11. An extended configuration may be used. In this case, the through hole 37 does not need to penetrate the wafer 31. Even when the electrodes 35 and 36 of the LED element 11 are not extended to the lower end of the side surface of the LED element 11, the step of the wiring substrate can be reduced by forming a minimum resin slope, and the resin material can be used for the electrodes 35 and 36. There is also a low possibility that the connection with the electrodes 35 and 36 will be lost due to the covering.

  In addition, this invention is not limited to said each Example 1 and 2, The shape of the base material of each LED element, each semiconductor layer, and an electrode is each conduction | electrical_connection, "the pn junction is taking place", etc. It is sufficient to satisfy the above-mentioned purpose, and a better shape may be adopted depending on each application.

  In each of the first and second embodiments, the LED element 11 is mounted on the circuit board 21. However, the LED element 11 may be mounted in the recess of the mounting member.

  In addition, it goes without saying that the present invention is not limited to light-emitting elements such as LED elements, and can be implemented with various modifications without departing from the gist, such as being applicable to other semiconductor elements.

  DESCRIPTION OF SYMBOLS 11 ... LED element (semiconductor element), 12 ... Base material, 13 ... N-type semiconductor layer, 14 ... Light emitting layer, 15 ... P-type semiconductor layer, 16 ... Transparent electrode, 17 ... P-side electrode, 18 ... N-side electrode, DESCRIPTION OF SYMBOLS 19 ... Insulating protective film, 21 ... Circuit board, 22 ... Resin slope, 23, 24 ... Wiring, 25, 26 ... Electrode part, 31 ... Wafer, 35 ... P side electrode, 36 ... N side electrode, 37 ... Through hole, 37a: Half groove, 38: Insulating protective film, 40: Conductive adhesive

Claims (8)

In an electrode structure of a semiconductor element in which a p-type semiconductor layer and an n-type semiconductor layer are formed on the upper side of the semiconductor element,
The p-side electrode that conducts to the p-type semiconductor layer and the n-side electrode that conducts to the n-type semiconductor layer have substantially the same height, and the p-side electrode is formed at a position lower than the p-type semiconductor layer. An electrode structure of a semiconductor element, characterized by comprising:   2. The electrode structure of a semiconductor element according to claim 1, wherein the p-side electrode is formed so as to extend to a position having substantially the same height as the n-side electrode.   3. The electrode structure of a semiconductor element according to claim 1, wherein each of the p-side electrode and the n-side electrode is formed to extend to a lower end thereof along a side surface of the semiconductor element.   On the side surface of the semiconductor element, two half grooves formed by dividing a through hole by dicing at the time of manufacturing the semiconductor element are formed, and the p-side electrode and the half groove are formed in the two half grooves. 4. The electrode structure of a semiconductor element according to claim 3, wherein an n-side electrode is formed.   The electrode structure of a semiconductor element according to claim 1, wherein the semiconductor element is a light emitting element.   6. The electrode structure of a semiconductor element according to claim 1, wherein the p-side electrode and the n-side electrode are formed in a shape without a wire bonding pad. In the method for manufacturing the electrode structure of the semiconductor element according to claim 1,
An insulating protective film is formed on a portion of the surface of the semiconductor element that needs to be insulated from the p-side electrode and the n-side electrode, and then the p-side electrode and the n-side electrode are formed. Manufacturing method of the electrode structure. The method for manufacturing an electrode structure of a semiconductor device according to claim 4,
A plurality of semiconductor elements are formed on a single wafer, and through holes are formed between the semiconductor elements. The p-side electrode and the n-side electrode are formed on the surface of the semiconductor element and the inner peripheral surface of the through-hole. After forming an insulating protective film on a portion that needs to be insulated from the substrate, the p-side electrode and the n-side electrode are formed, and then the wafer is diced along the center line of the through-hole to be divided into semiconductor elements. A method of manufacturing an electrode structure of a semiconductor element.

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