CN111509097A - High-power semiconductor light-emitting device and preparation method thereof - Google Patents
High-power semiconductor light-emitting device and preparation method thereof Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
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Abstract
The invention discloses a high-power semiconductor light-emitting device and a preparation method thereof, belonging to the field of semiconductor photoelectron. The device sequentially comprises an epitaxial layer, a conductive functional layer, a first insulating layer with an opening, a metal layer, a P electrode, an N electrode and a second insulating layer; the metal layer comprises an inner ring and an outer ring which are insulated and separated from each other, and the P electrode is positioned on the inner ring of the metal layer and is conducted with the P-type semiconductor layer in the epitaxial layer through the conductive function layer; an N-type conductive opening is formed in the epitaxial layer, the N electrode is located on the outer ring of the metal layer, and the outer ring of the metal layer enters the N-type conductive opening to be conducted with the N-type semiconductor layer. The equal thickness in the region that each rete is located P, N electrode under is even and level, designs the metal level for inner ring and outer loop, has both guaranteed that the rete of P, N electrode bottom is unanimous for the conduction of electric current is more abundant, even, has still avoided the difference in height of P electrode and N electrode, realizes the high car rule level product of welding roughness demand.
Description
Technical Field
The invention belongs to the field of semiconductor photoelectron, and particularly relates to a high-power semiconductor light-emitting device and a preparation method thereof.
Background
A light emitting diode (also called L ED chip) is designed by chip research personnel to avoid the influence on light emitting efficiency caused by the fact that electrodes occupy the light emitting area in a forward-mounted L ED chip, namely, the forward-mounted chip is inverted to enable light excited by a light emitting layer to be directly emitted from the other side of the electrodes (a substrate is finally stripped, chip materials are transparent), meanwhile, a structure convenient for bonding wires in a L ED packaging factory is designed aiming at the inverted chip, so that the whole chip is called an inverted L ED chip (FlipChip), the structure is mostly used in a high-power chip, and the inverted L ED chip has the advantages that the heat dissipation is not achieved through sapphire, large current can be used, the size can be smaller, the optics can be more easily matched, the heat dissipation function is improved, the service life of the chip is prolonged, the antistatic capability is improved, and a foundation is laid for the development of a subsequent packaging process.
When the inverted L ED chip is applied to an automobile lamp, higher requirements are put on L ED chips, such as high power, high stability, high heat dissipation performance, high electric stability and the like, however, due to the fact that a hole is formed in an etching conducting region of a conventional inverted L ED chip, the surface of an electrode is not flat, a welding gap cavity appears during eutectic welding, reliability and heat dissipation performance are affected, and meanwhile, due to the fact that the using power of the automobile specification chip is high, the cavity on the surface of the electrode causes too high local voltage to break down the chip, and the electric stability of the chip is affected.
In order to solve this problem, the prior art usually adopts a material filling method to fill the P-type and N-type electrodes to the same height, but the general filling process has two problems in implementation:
1. the etching depth of a conductive area corresponding to the N, P type electrode and the growth thickness of a filling film layer have error fluctuation in the production process, and the fluctuation can make the heights of the bonding pads at the P type and the N type difficult to be completely equal to each other;
2. in the whole chip manufacturing process, the coating film ends of a current expansion layer, a reflection layer, a barrier layer and a passivation layer exist on a P-type conductive region near an N-type conductive region, all the film layers have height differences, an N-type electrode is liable to be influenced by the height differences, in addition, a yellow light process is required to be used for pattern transfer during filling of the height differences of all the adjacent film layers, each film layer needs to be accurately aligned, for a traditional inverted L ED chip structure, at least five filling processes need to be added, meanwhile, the film thickness during filling needs to be accurately controlled, and the cost and the final effect cannot be well controlled.
Disclosure of Invention
Aiming at the defects or improvement requirements of the prior art, the invention provides a high-power semiconductor light-emitting device, and aims to solve the technical problems of uneven P, N electrode surface, poor heat dissipation, poor die bonding effect and the like caused by height difference and uneven current conduction in the prior art.
In order to achieve the above object, according to one aspect of the present invention, a high power semiconductor light emitting device is provided, which includes an epitaxial layer, a conductive functional layer, a first insulating layer with an opening, a metal layer, a P electrode, an N electrode, and a second insulating layer, in sequence, wherein each of the epitaxial layer, the conductive functional layer, the first insulating layer, and the metal layer is located in a region right below the P electrode and the N electrode, and has a uniform and flat thickness;
the metal layer comprises an inner ring and an outer ring which are insulated and separated from each other, the inner ring of the metal layer is in contact with the conductive function layer through the first insulating layer, and the P electrode is positioned on the inner ring of the metal layer and is conducted with the P-type semiconductor layer in the epitaxial layer through the conductive function layer;
the epitaxial layer is provided with a plurality of N-type conductive openings extending from the P-type semiconductor layer to the N-type semiconductor layer at the peripheral edge, the outer ring of the metal layer is in contact with the N-type semiconductor layer in the epitaxial layer through the first insulating layer and the N-type conductive openings, and the N electrode is positioned on the outer ring of the metal layer and is communicated with the N-type semiconductor layer.
Through above-mentioned technical scheme, all set up the upper surface at the metal level with P electrode and N electrode to with the metal level design for inner ring and outer loop, make N type semiconductor layer can switch on with the N electrode, P type semiconductor layer can switch on with the P electrode, from the structural improvement of chip itself, avoided the difference in height of P electrode and N electrode, can realize the high car rule level product of welding roughness demand, the advantage of the encapsulation of performance flip-chip structure no gold thread chip level. The N-type conductive opening is formed in the periphery of the N-type conductive opening, the thickness of each film layer in the area under the P electrode and the N electrode is uniform and flat, and steps are avoided from being formed under the P electrode and the N electrode, so that the film layers of the P electrode and the bottom of the N electrode are consistent, and the conduction of current is more sufficient and uniform.
In a second aspect of the present invention, a method for manufacturing a high power semiconductor light emitting device is provided, which is used for manufacturing the high power semiconductor light emitting device, and comprises the following steps:
s10, processing the epitaxial layer, etching and forming a plurality of N-type conductive openings extending from the P-type semiconductor layer to the N-type semiconductor layer at the peripheral edge of the epitaxial layer, and preparing a conductive function layer on the upper surface of the epitaxial layer;
s20, depositing a first insulating layer on the conductive function layer, etching and opening the first insulating layer, then depositing a metal layer on the first insulating layer, and correspondingly etching the metal layer into an inner ring and an outer ring which are insulated and separated from each other on the basis of etching and opening the first insulating layer, so that the inner ring of the metal layer is conducted with the P-type semiconductor layer in the epitaxial layer through the conductive function layer, and the outer ring of the metal layer is directly conducted with the N-type semiconductor layer in the epitaxial layer.
And S30, manufacturing a P electrode on the inner ring of the metal layer, and manufacturing an N electrode on the outer ring of the metal layer.
The preparation method can well control the thickness of each film layer at the bottom of the P, N electrode when the high-power semiconductor light-emitting device is formed, and has the advantages of less working procedures, low process difficulty and low production cost.
Drawings
FIG. 1 is a top view structural diagram of a chip;
FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1;
FIG. 3 is a schematic illustration of an epitaxial layer;
FIG. 4 is a schematic illustration of the epitaxial layer after processing;
fig. 5 is a schematic view after providing a conductive functional layer on the epitaxial layer;
fig. 6 is a schematic view after a first insulating layer is provided on the conductive functional layer;
FIG. 7 is a schematic view after a metal layer is disposed on a first insulating layer;
FIG. 8 is a schematic top view of a first insulating layer;
fig. 9 is a schematic top view of a metal layer.
In the figure, 1, an epitaxial layer; 10. a substrate; 11. an N-type semiconductor layer; 12. an active layer; 13. a P-type semiconductor layer; 14. forming an N-type conductive opening; 2. a conductive functional layer; 21. a current spreading layer; 22. a reflective layer; 23. a barrier layer; 3. a first insulating layer; 31. a small hole; 32. annular ring; 4. a metal layer; 41. an intermediate metal region; 5. a second insulating layer; 51. a P electrode; 52. and an N electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 1 and fig. 2, the present invention provides a high power semiconductor light emitting device, which sequentially comprises an epitaxial layer 1, a conductive functional layer 2, a first insulating layer 3 with an opening, a metal layer 4, a second insulating layer 5, an N electrode 52 and a P electrode 51, wherein the N electrode 52 and the P electrode are located in the second insulating layer 5 and are directly conducted with the metal layer 4. The epitaxial layer 1 is a growth buffer layer (omitted in the drawing), an N-type semiconductor layer 11, an active layer 12 and a P-type semiconductor layer 13 which are grown on a sapphire growth substrate 10 in sequence; the conductive function layer 2 is a current spreading layer 21, a reflecting layer 22 and a barrier layer 23 which are sequentially arranged on the upper surface of the P-type semiconductor layer 13. The first insulating layer 3 is disposed on the upper surface of the barrier layer 23, and the edge of the first insulating layer 3 sequentially covers the barrier layer 23, the reflective layer 22, the current spreading layer 21, the P-type semiconductor layer 13, the active layer 12, and the N-type semiconductor layer 11.
Specifically, each layer of the N-type semiconductor layer 11, the active layer 12, the P-type semiconductor layer 13, the current spreading layer 21, the reflective layer 22, the barrier layer 23, the first insulating layer 3, and the metal layer 4, which corresponds to the region directly below the P-electrode 51 and the N-electrode 52, has a uniform thickness and is flat, and no step is formed in the region directly below the P-electrode 51 and the N-electrode 52, so that the finally formed overall height is flat, the process level is not limited, and uniform deposition of each film layer directly below the electrodes is ensured without void faults.
The metal layer 4 comprises an inner ring and an outer ring which are insulated and separated from each other, the inner ring of the metal layer 4 is in contact with the barrier layer 23 in the conductive function layer 2 through the first insulating layer 3 with an opening, and the P electrode 51 is positioned on the inner ring of the metal layer 4 and is conducted with the P-type semiconductor layer 13 through conduction with the barrier layer 23;
as shown in fig. 3 and 4, a plurality of N-type conductive openings 14 extending from the P-type semiconductor layer 13 to the N-type semiconductor layer 11 are formed in the epitaxial layer 1, the outer ring of the metal layer 4 contacts the N-type semiconductor layer 11 through the first insulating layer 3 of the openings, and the N-electrode 52 is located on the outer ring of the metal layer 4 so as to be conductive to the N-type semiconductor layer 11.
The metal layer 4 is arranged on the upper surface of the first insulating layer 3, the metal layer 4 is divided into an inner ring and an outer ring, the P electrode 51 is arranged on the inner ring of the metal layer 4, the N electrode 52 is arranged on the outer ring of the metal layer 4, on the basis of avoiding the short circuit connection between the two, the heights of the N electrode 52 and the P electrode 51 which are arranged above the metal layer 4 are equal, the same film layer is ensured at the bottom, the N-type conductive open pore 14 is arranged at the edge, the thicknesses of all the film layers in the area right below the bottom of the electrode are uniform, flat and equal, and the step condition below the electrode is avoided, which is completely different from the prior art through a leveling technical means, the prior art has the defects that the surface of the electrode is not flat due to the fact that the conductive area of the conventional flip L chip is required to be etched and opened pores, welding gap holes appear during eutectic welding, which affect reliability and heat dissipation, the film layers have height difference, the N-type electrode is bound to be affected by the height difference, the,but stacked on the membrane layer several times In the process, the coating position of the side wall of the step is easy to generate holes and faults, especially the deposition process of metalBook and bookThe structure in the chip is directly improved, the step formation under the electrode is fundamentally avoided, the height difference caused by the limitation of the process level is avoided, the requirement and the manufacture of the vehicle-scale chip are favorably met, the surface of the electrode is smooth, the electrode is more attached to the substrate, the subsequent die bonding process is easier to perform, the die bonding effect is better, meanwhile, most of heat of the vehicle-scale chip L ED is conducted through the electrode, the surface of the electrode is free of holes, the radiating surface is enlarged, the vehicle-scale chip is high in power, the radiating requirement is higher, and the heat radiating aspect is also greatly superior.
Further, therefore, referring to fig. 6 and 7, a small hole 31 is opened in the first insulating layer 3 at a position corresponding to the N-type conductive opening 14, so that the outer circumferential edge of the metal layer 4 enters into the small hole 31 to be conductive with the N-type semiconductor layer 11 in the epitaxial layer 1.
As shown in fig. 8, the small holes 31 are arranged at the peripheral edge of the single chip, and the metal layer 4 fills the small holes 31, covers the first insulating layer 3, and is electrically connected to the N-type semiconductor layer 11.
Further, the annular hole 32 is formed in the first insulating layer 3, the first insulating layer 3 is separated into an inner ring and an outer ring through the annular hole 32, the shape of the annular hole 32 is not required, but the inner ring of the first insulating layer 3 separated through the annular hole 32 is preferably the same as the shape of the P electrode 51, the edge of the inner ring of the metal layer 4 is located in the annular hole 32 to directly contact with the barrier layer 23 in the conductive functional layer 2, and thus conduction with the P-type semiconductor layer 13 is achieved. In order to ensure that the inner ring edge of the metal layer 4 can enter the annular hole smoothly and uniformly, the opening width of the annular hole 32 is preferably 15-25 um.
Further, as shown in fig. 2, the inner ring area of the first insulating layer 3 is smaller than the inner ring area of the metal layer 4, and the inner ring of the metal layer 4 can cover the inner ring of the first insulating layer 3, and the edge of the inner ring enters the annular hole 32 to be in direct contact with the barrier layer 23, so as to be conducted with the P-type semiconductor. The area of the inner ring of the first insulating layer 3 is also larger than the area of the P electrode 51, and because when the pattern opening exists below the P electrode 51, the pattern opening may cause the pattern opening to be inconsistent with the film layer below the N electrode 52, and there is a height difference, the situation that the ring hole 32 is located below the P electrode 51 can be effectively avoided by controlling the area of the inner ring of the first insulating layer 3 to be larger than the area of the P electrode 51.
Further, as shown in fig. 9, an intermediate metal region 41 is provided at the center of the metal layer 4, and the intermediate metal region 41 is independent of the inner ring of the metal layer 4 and the outer ring of the metal layer 4.
In the testing process of the flip L ED chip, an ejector pin is arranged below a machine table of a die bonder in the packaging process, a suction nozzle is arranged above the machine table, the chip to be packaged is required to be arranged on the machine table, the ejector pin is used for upwards ejecting the chip to the center of the chip, then the suction nozzle is moved downwards to absorb the chip, and the chip is transferred to a substrate for supporting, when the ejector pin upwards ejects the center of the chip to pierce a second insulating layer 5, the ejector pin is connected with a metal layer 4, the chip is in leakage failure, and therefore the problem of leakage failure can be effectively solved by separating an independent middle metal area 41 from the center of the metal layer 4.
The invention also provides a preparation method of the high-power semiconductor light-emitting device, which can be used for preparing the high-power semiconductor light-emitting device and comprises the following steps:
s10, processing the epitaxial layer 1, and preparing a conductive function layer 2 on the upper surface of the epitaxial layer 1;
specifically, as shown in fig. 3, S101, a sapphire substrate 10 may be provided, on which a buffer layer and a light emitting structure are sequentially grown on the substrate 10 by a metal organic compound chemical vapor deposition technique, the light emitting structure including an N-type semiconductor layer 11, an active layer 12, and a P-type semiconductor layer 13 formed in sequence, forming an epitaxial layer 1;
s102, etching the whole epitaxial layer 1 to the bottom through inductively coupled plasma, wherein the specific etching depth penetrates through the whole epitaxial layer 1 according to the growth thickness of different epitaxial layers 1, generally 6-7 microns, so that each core particle is completely separated from the epitaxial layer 1 to form an independent unit;
s103, as shown in fig. 4, after the core particles are isolated, the N-type conductive region of a single core particle needs to be fabricated, specifically: forming a groove extending to the N-type semiconductor layer 11 from the P-type semiconductor layer 13 at the peripheral edge of the epitaxial layer 1 by inductively coupled plasma etching, wherein the specific etching depth is generally 1-1.5um according to the growth thickness of different epitaxial layers 1 to form an N-type conductive opening 14; the N-type conductive openings 14 are formed in a plurality and are respectively arranged around the single core particle, so that the current conduction is more uniform.
As shown in fig. 5, the conductive functional layer 2 on the upper surface of the epitaxial layer 1 sequentially includes a current spreading layer 21, a reflective layer 22, and a barrier layer 23, specifically:
s104, depositing an ITO layer with the thickness of 200-600 Å on the surface of the P-type semiconductor layer 13 by using a magnetron sputtering process, and annealing to form a P-type ohmic contact, namely a current expansion layer 21;
the ITO is mainly composed of indium tin oxide, is a semiconductor transparent conductive film, can simultaneously have the characteristics of low resistivity and high light transmittance, and meets the requirements of good conductivity and light transmittance; the ITO has the function of enabling the electrode to form good ohmic contact with the epitaxial layer 1, enabling current to be diffused on the surface of the electrode and to be better conducted into the electrode, and reducing voltage. Meanwhile, Mg-H bonds in the gallium nitride of the P-type semiconductor layer 13 are opened in an oxygen atmosphere through annealing, so that the effect of activating Mg is achieved, and ohmic contact is formed better;
s105, selecting Ag/Al/Rh and the like above the current expansion layer 21 as reflection layer metals, depositing 1000-2000 Å reflection metals through a magnetron sputtering method or a vacuum evaporation coating process, and continuously depositing a Ti/Pt or TiW film layer on the upper layer while coating the reflection metals to cover the reflection metals so as to inhibit the migration of the reflection metals and form a reflection layer 22;
s106, plating a barrier layer 23 on the reflecting layer 22 by using a vacuum evaporation plating method, wherein the component of the barrier layer 23 is mainly Au, and the rest components comprise one or more of Cr, Pt, Ti, Ni and Sn, and the barrier layer plays two roles of 1 protecting the reflecting layer 22 and avoiding the diffusion of the reflecting metal, 2 being beneficial to the current expansion of the P-type semiconductor layer 13, and the thickness of the barrier layer 23 is 5000-10000 Å.
S20, as shown in FIG. 6, a first insulating layer 3 is deposited on the barrier layer 23, specifically by using a plasma enhanced vapor deposition method at 250 deg.C-300 deg.C using SiO2、SiNx、Al2O3One or more laminated SiO2/SiNx、SiO2/SiNx/Al2O3Depositing a plated film with a thickness of 5000-8000 Å to form a first insulating layer 3, etching an opening on the first insulating layer 3, depositing a metal layer 4 on the first insulating layer 3, and etching the metal layer 4 into an inner ring and an outer ring correspondingly on the basis of the etching opening of the first insulating layer 3 as shown in fig. 7, so that the inner ring of the metal layer 4 is conducted with the P-type semiconductor layer 13 in the epitaxial layer 1 through the barrier layer 23 in the conductive functional layer 2, and the outer ring of the metal layer 4 is directly contacted and conducted with the N-type semiconductor layer 11 in the epitaxial layer 1, specifically, the metal layer 4 is deposited by using a vacuum plating method, the adhesion is the best when Cr or Ti is used in contact with the first insulating layer 3, the thickness is 200-500 Å, and then one or more of Pt/Ni/Au/Sn is evaporated, mainly comprising Au, and the thickness is 5000-7000 Å.
S30, as shown in fig. 2, a P electrode 51 is formed on the inner ring of the metal layer 4, and an N electrode 52 is formed on the outer ring of the metal layer 4.
Specifically, a passivation film layer is firstly deposited on the upper surface of the metal layer 4 at the temperature of 250-300 ℃ by using a plasma enhanced vapor deposition method, and the passivation film layer uses SiO2、SiNx、Al2O3One or more laminated SiO2/SiNx、SiO2/SiNx/Al2O3Depositing a coating film with the thickness of 5000-8000 Å to form a second insulating layer 5;
then, a yellow light glue homogenizing exposure development process is used for making a pad pattern, wherein the pad pattern is smaller than the inner ring area of the first insulating layer 3; etching SiO under pattern using wet etching BOE solution2Exposed at the surface is the underlying metal layer 4, which is cleaned by a plasma: o is2Processing the photoresist remained on the surface of the metal layer 4 in Asher 150W 1min, and respectively plating PN bonding pads by using a vacuum evaporation plating machine; the thickness of the bonding pad is 3-5 um; the procedure of crptaussn was used, thereby forming P electrodes 51, N electrodes 52.
As shown in fig. 6 and 7, in S20, before depositing the metal layer 4, the first insulating layer 3 is etched to form an opening, specifically: spreading photoresist on the upper surface of the first insulating layer 3, exposing and developing the photoresist at a position corresponding to the N-type conductive opening 14 to form a small hole 31 pattern, and etching the first insulating layer 3 corresponding to the small hole 31 pattern to form a small hole 31;
the outer ring of the metal layer 4 on the upper surface of the first insulating layer 3 enters the N-type conductive opening 14 through the small hole 31, and is directly conducted with the N-type semiconductor layer 11 in the epitaxial layer 1. The aperture of the small hole 31 is preferably 30-40um in width and 80-100um in length, and the size of the small hole 31 is set according to the following principle: 1. the etching stability of the first insulating layer is ensured, and the problem of incomplete etching SiO2 residue exists when the aperture is too small, so that the poor contact voltage between the electrode and the N-GaN is higher; 2. the Mesa area is controlled to be the minimum area while the current is ensured to be stably conducted, and the occupied area of a light emitting area is reduced; the N-type semiconductor 11 and the N-electrode 52 have the best electrical conduction effect through the metal layer 4 while the whole device has better structural regularity.
Further, in S20, while etching the small hole 31, an annular pattern is developed by exposing the photoresist, and the first insulating layer 3 corresponding to the annular pattern is etched to form an annular hole 32, the annular hole 32 separates the first insulating layer 3 into an inner ring and an outer ring, and the etching of the annular hole 32 and the etching of the small hole 31 may be performed simultaneously or sequentially, but both are performed after the first insulating layer 3 is formed and before the metal layer 4 is formed.
As shown in fig. 8, since the small hole 31 is located around the core grain corresponding to the N-type conductive opening 14, the small hole 31 is also located in the outer ring of the first insulating ring, and the outer ring of the metal layer 4 is located on the outer ring surface of the first insulating layer 3. The inner ring of the metal layer 4 is located on the inner ring surface of the first insulating layer 3, and the edge of the inner ring of the metal layer 4 is located in the annular hole 32, so as to directly contact the barrier layer 23 below the first insulating layer 3, thereby achieving conduction with the P-type semiconductor layer 13.
Further, the inner ring area of the first insulating layer 3 is smaller than the inner ring area of the metal layer 4, so that the inner ring of the first insulating layer 3 is completely covered by the inner ring of the metal layer 4; the area of the inner ring of the first insulating layer 3 is larger than that of the P electrode 51, so that a hole can be prevented from being formed at the bottom of the P electrode 51, and the height difference caused by the inconsistency of the bottom films of the P electrode 51 and the N electrode 52 is further avoided. The outer ring of the metal layer 4 is completely deposited above the outer ring of the first insulating layer 3, the distance between the inner end of the outer ring of the metal layer 4 and the inner end of the outer ring of the first insulating layer 3 is larger than 5um, when the edge of the inner ring of the metal layer 4 covers the annular hole 31, the contact between the inner end of the outer ring of the metal layer 4 and the edge of the inner ring can be effectively avoided, and therefore the effect of insulating between the inner ring and the outer ring of the metal layer 4 is achieved.
Further, as shown in fig. 9, at S20, the metal layer 4 is etched into an inner ring and an outer ring, and at the same time, an intermediate metal region 41 is also etched at the center of the metal layer 4, and the intermediate metal region 41 is independent of the inner ring and the outer ring of the metal layer 4. The intermediate metal region 41 may be located between the inner and outer rings of the metal layer 4, or may be located solely in the outer ring, or solely in the inner ring.
Further, S40 is included, and after the P-electrode 51 and the N-electrode 52 are prepared, the sapphire substrate 10 is cut along the cut-off positions of the core particles in S102, thereby forming L ED chips.
By the process disclosed by the invention, all the openings are not arranged below the P electrode 51 and the N electrode 52, so that the height difference of a film layer caused by the openings does not exist, the film layers below the P electrode 51 and the N electrode 52 are consistent, and the chip bonding pad and a substrate do not have a gap during eutectic welding, so that a bonding space cannot be generated, the reliability of a product is greatly improved, namely, the product has better conductivity, better heat dissipation and less possibility of electric leakage, and the advantage of the flip-chip structure gold-wire-free chip-level packaging is implemented in a vehicle-standard high-standard product.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. The high-power semiconductor light-emitting device is characterized by sequentially comprising an epitaxial layer, a conductive functional layer, a first insulating layer provided with an opening, a metal layer, a P electrode, an N electrode and a second insulating layer, wherein the epitaxial layer, the conductive functional layer, the first insulating layer and the metal layer are positioned in each layer corresponding to an area right below the P electrode and the N electrode, and the thickness of each layer is uniform and flat;
the metal layer comprises an inner ring and an outer ring which are insulated and separated from each other, the inner ring of the metal layer is in contact with the conductive function layer through the first insulating layer, and the P electrode is located on the inner ring of the metal layer and is conducted with the P-type semiconductor layer through the conductive function layer;
the epitaxial layer is provided with a plurality of N-type conductive openings extending from the P-type semiconductor layer to the N-type semiconductor layer at the peripheral edge, the outer ring of the metal layer is in contact with the N-type semiconductor layer through the first insulating layer and the N-type conductive openings, and the N electrode is positioned on the outer ring of the metal layer and is communicated with the N-type semiconductor layer.
2. The high power semiconductor light emitting device as claimed in claim 1, wherein a hole is formed in the first insulating layer corresponding to the N-type conductive opening, and the outer annular edge of the metal layer is located in the hole to communicate with the N-type semiconductor layer in the epitaxial layer.
3. The high power semiconductor light emitting device according to claim 1, wherein a ring hole is further formed in the first insulating layer, the ring hole separates the first insulating layer into an inner ring and an outer ring, and an edge of the inner ring of the metal layer is located in the ring hole to directly contact the conductive function layer.
4. The high power semiconductor light emitting device according to claim 3, wherein the inner annular area of the first insulating layer is larger than the area of the P electrode and smaller than the inner annular area of the metal layer.
5. The high power semiconductor light emitting device according to claim 1, wherein an intermediate metal region is disposed at the center of the metal layer, and the intermediate metal region is independent of the inner ring of the metal layer and the outer ring of the metal layer.
6. A preparation method of a high-power semiconductor light-emitting device is characterized by comprising the following steps:
s10, processing the epitaxial layer, etching and forming a plurality of N-type conductive openings extending from the P-type semiconductor layer to the N-type semiconductor layer at the peripheral edge of the epitaxial layer, and then preparing a conductive function layer on the upper surface of the epitaxial layer;
s20, depositing a first insulating layer on the conductive function layer, etching and opening a hole on the first insulating layer, then depositing a metal layer on the first insulating layer, and correspondingly etching the metal layer into an inner ring and an outer ring which are insulated and separated from each other on the basis of etching and opening the hole on the first insulating layer, so that the inner ring of the metal layer is conducted with the P-type semiconductor layer in the epitaxial layer through the conductive function layer, and the outer ring of the metal layer is directly conducted with the N-type semiconductor layer in the epitaxial layer;
and S30, manufacturing a P electrode on the inner ring of the metal layer, and manufacturing an N electrode on the outer ring of the metal layer.
7. The method for manufacturing a high power semiconductor light emitting device according to claim 6,
the etching of the first insulating layer in S20 includes: spreading photoresist on the upper surface of the first insulating layer, exposing and developing the photoresist at a position corresponding to the N-type conductive opening to form a small hole pattern, and etching the first insulating layer corresponding to the small hole pattern to form a small hole;
the outer ring of the metal layer is directly conducted with the N-type semiconductor layer in the epitaxial layer by covering the small hole.
8. The method for manufacturing a high power semiconductor light emitting device according to claim 6, wherein the etching of the first insulating layer in S20 further comprises:
spreading photoresist on the upper surface of the first insulating layer, exposing and developing the photoresist to form an annular pattern, etching the first insulating layer corresponding to the annular pattern to form an annular hole, and separating the first insulating layer into an inner ring and an outer ring by the annular hole;
the edge of the inner ring of the metal layer is positioned in the ring hole and directly contacted with the conductive functional layer.
9. The method for manufacturing a high power semiconductor light emitting device according to claim 8, wherein the inner ring of the first insulating layer is completely covered by the inner ring of the metal layer; the inner ring area of the first insulating layer is larger than the area of the P electrode.
10. The method for manufacturing a high power semiconductor light emitting device according to claim 6, wherein when the metal layer is etched into the inner ring and the outer ring corresponding to each other based on the etching of the first insulating layer in S20, an intermediate metal region is further etched at the center of the metal layer, and the intermediate metal region is independent of the inner ring of the metal layer and the outer ring of the metal layer.
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Denomination of invention: The invention relates to a high-power semiconductor light-emitting device and a preparation method thereof Effective date of registration: 20220210 Granted publication date: 20201020 Pledgee: Wuhan area branch of Hubei pilot free trade zone of Bank of China Ltd. Pledgor: HUAYINXIN (WUHAN) TECHNOLOGY CO.,LTD. Registration number: Y2022420000036 |