WO2014049383A1 - Adaptation de débit de rééchantillonneur par détection de bloqueur - Google Patents

Adaptation de débit de rééchantillonneur par détection de bloqueur Download PDF

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Publication number
WO2014049383A1
WO2014049383A1 PCT/IB2012/002221 IB2012002221W WO2014049383A1 WO 2014049383 A1 WO2014049383 A1 WO 2014049383A1 IB 2012002221 W IB2012002221 W IB 2012002221W WO 2014049383 A1 WO2014049383 A1 WO 2014049383A1
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WO
WIPO (PCT)
Prior art keywords
rate
blocker
signal
rational
converter
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Application number
PCT/IB2012/002221
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English (en)
Inventor
Pierre Didier
Stéphane Paquelet
Markus Nentwig
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Renesas Mobile Corporation
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Publication date
Application filed by Renesas Mobile Corporation filed Critical Renesas Mobile Corporation
Priority to PCT/IB2012/002221 priority Critical patent/WO2014049383A1/fr
Publication of WO2014049383A1 publication Critical patent/WO2014049383A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0294—Variable filters; Programmable filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing

Definitions

  • the present invention generally relates to a method and a device for digitizing an analogue signal for further demodulation in a radio receiving device.
  • a radio receiver must cope with strong unwanted signals, classically called as blockers.
  • a blocker refers to an interfering signal that occupies a frequency band that is close to the frequency band of the useful signal.
  • a frequency band is close to the one of the useful signal when the difference between the frequency bands is less than ten percent of the frequency band occupied by the useful signal.
  • a radio receiver If a radio receiver is lacking robustness towards blockers, the overall performance of the radio receiver itself, like the throughput, decreases significantly. Users of such a radio receiver are unsatisfied as they suffer from dropped calls and the licensed spectrum allocated to wireless cellular telecommunication operators is not used efficiently.
  • the present invention aims at providing a method and a device for digitizing an analogue signal for further demodulation in a radio receiving device which is robust against blocker.
  • the device adapts filtering according to the blocker intensity, but on the other hand minimizes the power consumption and latency when possible, in example when there are no strong blockers present.
  • the present invention concerns a method for digitizing an analogue signal for further demodulation in a radio receiving device, said method causing the device to perform:
  • the method may further cause the device to perform applying a rate matching by a rational rate converter, for generating an output signal at the target sample rate.
  • the conversion rate of the rate matching may be set to one, or the rate matching may be bypassed.
  • the present invention concerns also a radio receiving device for digitizing an analogue signal for further demodulation, the device comprising circuitry causing the device to implement:
  • the device may further comprise circuitry causing the device to implement a rational rate converter means for applying a rate matching for generating an output signal at the target sample rate.
  • the conversion rate of the rate matching may be set to one, or the rate matching may be bypassed.
  • the present invention concerns also a radio receiving device for digitizing an analogue signal for further demodulation, wherein the device comprises circuitry causing the device to perform:
  • the device may further comprise circuitry causing the device to implement a rational rate converter for applying a rate matching for generating an output signal at the target sample rate.
  • the conversion rate of the rate matching may be set to one, or the rate matching may be bypassed.
  • the radio receiving device is robust against blockers, but also allows for optimization for power consumption and latency.
  • the presence of blockers causes distortions like aliasing when the radio receiver applies rate conversions to the digital signal rendering the design of the rate conversion more difficult to implement in comparison with a case where there is presence of blockers.
  • the present invention by using different rate conversions according to the presence of blockers takes advantage of cases where there is no blocker and avoids that aliasing distortions problems occur.
  • the rate matching by the rational rate converter may be limited to a conversion ratio between the intermediate sample rate and the target sample rate that is a rational number, that is, the quotient of two integers.
  • a conversion ratio of the rational rate converter is 1 (one), where the rational rate converter may be effectively bypassed.
  • the radio receiving device may also configure a magnitude filter based on the blocker detection result.
  • the magnitude filter may be configured to compensate for an inaccuracy in a frequency response of the non- rational rate converter and/or the rational rate converter in a frequency range of the wanted signal as a result of the sample rate reconfiguration.
  • the magnitude filter may be a low-pass filter having a stopband outside the frequency range of the wanted signal.
  • the stopband may provide blocker suppression, and the equalizer may be configured to implement a variable trade-off between blocker suppression and compensation of the inaccuracy of the frequency response.
  • the intermediate sample rate is configured to a value higher than the input sample rate if the presence of a blocker is detected and to the target rate otherwise.
  • the magnitude filter is configured to provide improved blocker rejection if the presence of a blocker is detected, and improved compensation of the inaccuracy of the frequency response in the frequency range of the wanted signal otherwise.
  • a benefit of the present invention is that the intermediate sample rate may be adjusted to achieve a required robustness towards blockers, while minimizing the power consumption of the radio receiving device.
  • the power consumption of the non-rational rate converter may be substantially proportional to the intermediate sample rate, and operating the non- rational rate converter at a low intermediate sample rate may thus reduce power consumption.
  • operating the non-rational rate converter at a low intermediate sample rate may cause unwanted aliasing of blockers, causing degradation of the wanted signal.
  • the present invention may thus enable the radio receiving device to configure the non-rational rate converter and the rational rate converter for an optimal trade-off between power consumption and robustness towards blockers and thus improve efficiency.
  • the present invention also concerns, in at least one embodiment, a computer program that can be downloaded from a communication network and/or stored on a medium that can be read by a computer or a processing device.
  • This computer program comprises instructions for causing implementation of the aforementioned method, or any of its embodiments, when said program is run by a processor.
  • the present invention also concerns an information storage means, storing a computer program comprising a set of instructions causing implementation of the aforementioned method, or any of its embodiments, when the stored information is read from said information storage means and run by a processor.
  • Fig. 1 schematically represents an architecture of a receiver device in which the present invention is implemented
  • Fig. 2 illustrates the receiving part of the wireless interface of the receiver according to the present invention
  • Fig. 3 illustrates an algorithm executed by the receiver according to the present invention
  • Fig. 4 discloses the relative magnitude of an alias caused by a blocker signal
  • Fig. 5 shows the alias rejection of sample rate converter, when configured for improved blocker rejection
  • Fig. 6 illustrates an order 5 Lagrange Interpolation based Farrow structure according to a particular embodiment of the invention
  • Fig. 7 illustrates a possible implementation of the CIC decimator used in the given example as rational rate converter.
  • Fig. 1 schematically represents an architecture of a receiver device in which the present invention is to be implemented.
  • the receiver Rec device comprises the following components interconnected by a communications bus 101 : a processor, microprocessor, microcontroller or CPU
  • a wireless interface I/F interface (Central Processing Unit) 100; a RAM (Random-Access Memory) 103; a ROM (Read-Only Memory) 102; an SD (Secure Digital) card reader 104, or any other device adapted to read information stored on storage means; a wireless interface I/F interface
  • the wireless interface 105 allows the receiver Rec to wirelessly communicate with a transmitter device.
  • CPU 100 is able of executing instructions loaded into RAM 103 from ROM 102 or from an external memory, such as an SD card. When the receiver Rec is powered on, CPU 100 reads instructions from RAM 103 and executes the read instructions.
  • the instructions form one computer program that causes CPU 100 to perform some or all of the steps of the algorithm described hereafter with regard to Fig. 3. Any and all steps of the algorithm described hereafter with regard to Fig.
  • 3 may be implemented in software by execution of a set of instructions or program by a programmable computing machine, such as a PC ⁇ Personal Computer), a DSP ⁇ Digital Signal Processor) or a microcontroller; or else implemented in hardware by a machine or a dedicated component, such as an FPGA ⁇ Field-Programmable Gate Array) or an ASIC ⁇ Application-Specific Integrated Circuit).
  • a programmable computing machine such as a PC ⁇ Personal Computer
  • DSP Digital Signal Processor
  • microcontroller or else implemented in hardware by a machine or a dedicated component, such as an FPGA ⁇ Field-Programmable Gate Array) or an ASIC ⁇ Application-Specific Integrated Circuit.
  • the receiver Rec includes circuitry, or a device including circuitry, causing the receiver device to perform the steps of the algorithm described hereafter with regard to Fig. 3.
  • a device including circuitry causing the receiver device to perform the steps of the algorithm described hereafter with regard to Fig. 3 may be an external device connectable to the receiver Rec.
  • the receiver Rec may also be a part of another device, for example when the receiver Rec is a chip, a chipset, or a module.
  • the receiver Rec instead of being a part of another device or connected to a dedicated communication device, the receiver Rec, according to the invention, may provide communication capability to any suitable device, such as a computer device, a machine, for example a vending machine or a vehicle like a car or truck.
  • circuitry refers either to hardware implementation, consisting in analogue and/or digital processing, or to a combination of hardware and software implementation, including instructions of computer program associated with memories and processor causing the processor to perform any and all steps of the algorithm described hereafter with regard to Fig. 3.
  • non-rational rate converter is implemented using a Farrow structure.
  • any other non-rational rate converter type could be used instead, without departing from the invention.
  • Fig. 2 illustrates the receiving part of the wireless interface of the receiver according to the present invention.
  • the receiving part of the wireless interface 105 comprises an analogue filter 201 which filters the signal received by an antenna 200.
  • the signal received by the antenna 200 comprises useful signal in a bandwidth allocated for the communication and may comprise a blocker.
  • the blocker is likely to be only partially attenuated by the analog filter
  • the filtered signal is amplified by a low noise amplifier 202.
  • the signal outputted by the amplifier 202 is converted into base band signal by a mixer 203.
  • the signal After conversion to baseband signal by the mixer 203, the signal is filtered by an analogue baseband filter 204 and digitized by an analogue to digital converter (ADC) 205.
  • ADC an analogue to digital converter
  • the sampling rate of the analogue to digital converter 205 may depend on the input useful signal bandwidth and on radio -frequency performance requirements.
  • a sample rate converter 215 implements a variable rate conversion resulting in a signal at a fixed output rate for the modem 209.
  • the sample rate converter 215 performs the rate conversion of the samples provided by the ADC 205 in two steps according to the result of detecting a presence of a blocker in the received signal.
  • the sample rate converter 215 comprises a Farrow structure 206 followed by a rational rate converter which is, for example, a decimator 207.
  • the sample rate converter 215 performs, if presence of a blocker is detected by a blocker detection module 210, a rate conversion by the Farrow structure 206 to a first intermediate sample rate and performs a second rate conversion, or rate matching, by the decimator
  • the sample rate converter 215 performs, if presence of a blocker is not detected by the blocker detection module 210, a rate conversion by the Farrow structure 206 to a second intermediate sample rate, different from the first intermediate sample rate and performs a second rate conversion, or rate matching, by the decimator 207 to bring the digital signal from the second intermediate sample rate to the target sample rate required by the demodulation.
  • a rate conversion by the Farrow structure 206 or the second rate conversion by the decimator 207 may be bypassed.
  • rate converter architectures incur a cost that increases substantially with P or Q and thus makes these rate converter architectures unsuitable for fine-grained rate conversion.
  • the number of coefficients in a poly-phase filter may scale linearly with P, making it impractical to use large numbers such as 100000 for P.
  • a rate converter that is practically limited to small numbers of P and Q may be referred to as a substantially rational rate converter, or in short, a rational rate converter.
  • a rate converter for small integer values of P and Q may be referred to as substantially rational rate converter, or in short a rational rate converter.
  • a rational rate converter may allow a more efficient implementation of a non- rational rate converter for the same values of P and Q, thus saving cost and reducing power consumption.
  • a CIC filter does not require multiplications and thus can be implemented very efficiently.
  • a Farrow structure is used for such a rate conversion architecture, where large numbers of P and Q can be accommodated without substantial cost penalty, for example by selecting the bit width of internal processing appropriately.
  • other rate conversion architectures exist that can approximate an arbitrary non-rational conversion ratio by using large numbers for P and Q without a substantial increase in cost.
  • Such Farrow structure may be referred to as a substantially non-rational rate converter, or in short a non-rational rate converter.
  • a sampling stage may implement the functionality of a rate converter.
  • a magnitude filter 208 is configured based on the detection of presence of the blocker in the signal, the magnitude filter 208 filters the digital signal at the target sample rate.
  • the magnitude filter 208 is configured for improved blocker suppression if the presence of a blocker is detected in the signal, and for improved compensation of linear distortion introduced by both analogue stages and digital stages and especially by the rate conversion otherwise.
  • the receiving part of the wireless interface 105 comprises a blocker detection module 210 which detects the presence of a blocker in the received signal.
  • the blocker detection module 210 may perform power measurements and may detect a presence of a blocker in the analogue signal by performing a received signal strength comparison to a predetermined threshold. In one example embodiment, the blocker detection module 210 may detect the presence of a blocker by performing power measurements on at least one of: the digital signal at the output of ADC, the digital signal at the output of the Farrow structure 206, the digital signal, at the output of the decimator 207 and the digital signal at the output of the magnitude filter 208.
  • the blocker detection module 210 performs power measurement on samples provided by the ADC 205, performs a digital filtering on samples that remove out of band components from the received signal bandwidth, performs power measurement on filtered samples and if power measurements differ significantly, it determines that the blocker is in the received signal.
  • the blocker detection module 210 detects the presence of a blocker in the received signal.
  • the blocker detection module 210 may, in variant, perform power measurement on samples provided by the Farrow structure or by the decimator 207 as already stated.
  • the result of the determination whether there is a blocker in the received signal is provided to the CPU 100 which controls, through the links 216 and 217, the sample rate converter 215 in order to perform the rate conversion and, in a particular mode of realization of the present invention, controls the magnitude filter 208, through the link 218, in order to perform a equalization with rejection or without rejection by configuring a first or a second set of coefficients to the magnitude filter 218 resulting either in improved blocker rejection or improved equalization.
  • the signal is then amplified by a programmable digital gain followed by phase equalization, not shown in Fig. 2. Then the signal is ready to be demodulated by the modem 209.
  • the Farrow structure 206 may preserve the in-band signal spectrum flatness and may be based on a Lagrange interpolation or a Hermite interpolation. In one example embodiment, Farrow structure 206 applies a conversion ratio close to unity and the decimation module 207 applies a conversion ratio close to 1/2. The Farrow structure 206 may in this case act like a fine-grain rate converter.
  • the rational rate converter configured as a decimation module 207 is a CIC converter, known for example from document "An Economical Class of Digital Filters for Decimation and Interpolation" by Eugene B. HOGENAUER in IEEE TRANSACTIONS ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL. ASSP-29, NO. 2, APRIL 1981.
  • the CIC is able to apply a conversion rate expressed by a ratio U/D where U and D are integer values. This conversion may also be called as rate matching.
  • the value of U is typically 1 or 2 while the value of D is typically between 1 and several tens.
  • the decimator 207 is advantageously implemented as a CIC for flexibility, but it could be something else, such as a FIR filter implemented as a decimator.
  • the invention is not limited to the use of CIC as a decimator.
  • the Farrow structure 206 is a multi-rate filter structure which offers the option of continuously adjustable resample ratio.
  • the sample rate converter 215 takes into account aliases that are introduced in the receiving chain. This is due to the fact that the rate conversion is basically an up-sampling stage followed by a down-sampling stage.
  • the up-sampling stage brings some replica of the input signal at frequencies multiple of the input frequencies, while the down-sampling stage fold these replicas over in-band.
  • Blocker is strong interference signal in a frequency band close to the useful band of the input signal.
  • the rate conversion introduces some aliases of the blocker within the signal as it will be shown in reference to Fig. 4.
  • aliases of the blocker are cancelled by modifying the rate conversion of the Farrow structure 206 as it will be shown in an example given in reference to Fig. 5.
  • Fig. 3 illustrates an algorithm executed by the receiver according to the present invention.
  • the present algorithm may be executed periodically, for example every 50 ms or may be executed triggered by a change in the determined presence of a blocker.
  • the present algorithm may be executed by the CPU 100.
  • the CPU 100 commands the blocker detection module 210 in order to detect if a blocker is in the received signal.
  • the blocker detection module 210 performs blocker detection in the analogue signal and/or detects blocker in the digital signal at the output of ADC and/or detects blocker in the digital signal at the output of the Farrow structure 206 and/or detects blocker in the digital signal at the output of the decimator 207 and/or detects blocker in the digital signal at the output of the magnitude filter 208.
  • the CPU 100 checks if a blocker is in the received signal.
  • CPU 100 commands the sample rate converter 215 to perform a rate conversion by the Farrow structure 206 to a first intermediate sample rate, and to perform at step S303 a second rate conversion, i.e. by the decimator 207 to bring the digital signal from the first intermediate rate to a target sample rate required by the demodulation.
  • CPU 100 commands the sample rate converter 215 to perform the sample rate conversion in one step.
  • the Farrow structure 206 applies a conversion ratio close to or equal to 1 ⁇ 2 and the decimator 207 is bypassed.
  • a one-step conversion is commanded if the presence of a blocker is not detected, and a two-step conversion otherwise.
  • CPU 100 commands the equalizer 208 to perform an amplitude equalization by configuring a set of coefficients to the magnitude filter 208 resulting in improved blocker rejection. After S304, the algorithm ends.
  • step S305 CPU 100 commands the sample rate converter 215 to perform a rate conversion by the Farrow structure 206 to a second intermediate sample rate, different from the first intermediate sample rate and to perform at step S306 the second rate conversion by the decimator 207 to bring the digital signal from the second intermediate sample rate to the target sample rate.
  • the second intermediate sample rate is equal to the target sample rate
  • the CPU 100 may command the decimator 207 to a conversion ratio of 1, which effectively bypasses the decimator 207.
  • the decimator 207 may be bypassed. To indicate such optional nature of step S306, it has been marked with dashed line.
  • CPU 100 commands a rate conversion by Farrow structure 206 to a first intermediate sample rate that is higher than the sample rate of ADC 205.
  • a rate conversion value greater than unity is configured.
  • the rate conversion of the Farrow structure 206 to the first rate conversion value may be set to a value approximately equal to unity, where the approximately unity may mean i.e. that the rate conversion value is within 5-10% from unity, in example 0.95. Otherwise, if no blocker is detected, CPU 100 commands a rate conversion by Farrow structure 206 to a second intermediate sample rate that is lower than the sample rate of ADC 205, using a rate conversion value smaller than unity.
  • the rate conversion value configured to the Farrow structure if presence of a blocker is detected is greater than the rate conversion value configured if no presence of a blocker is detected.
  • commanding sample rate converter 215 to a two- step conversion configures Farrow structure 206 to apply a conversion ratio close to unity and the decimator 207 to apply a conversion ratio close to or equal to 1/2.
  • CPU 100 commands the magnitude filter 208 by configuring a set of coefficients to the magnitude filter 208 resulting in improved amplitude equalization.
  • CPU 100 obtains a signal to noise ratio (SNR) of the signal.
  • SNR is for example determined by the modem 209.
  • CPU 100 checks, whether or not the SNR exceeds a predetermined value, for example 25 dB.
  • the CPU 100 commands magnitude filter 208 to perform equalization with a root raised cosine filter (RRC), and the algorithm ends.
  • RRC root raised cosine filter
  • the CPU 100 commands the magnitude filter 208 to perform equalization without a root raised cosine filter.
  • Fig. 4 discloses the relative magnitude of an alias caused by a blocker signal at a specific frequency offset relative to the center frequency of the received signal, for a range of sampling frequencies that needs to be supported by ADC 205.
  • sample rate converter 215 may be configured for improved equalization or reduced power consumption.
  • a strong alias response 400 is visible at a frequency offset of 15.7 MHz with a level of approximately -65 dB, and a multitude of other alias responses 402, 403, 404 can be seen at higher frequency offsets.
  • Fig. 4 may represent a typical alias response of sample rate converter 215 in a one-step configuration.
  • Fig. 5 shows the alias rejection of sample rate converter, when configured for improved blocker rejection.
  • Fig. 5 may represent a typical alias response of a sample rate converter 215 in a two-step configuration.
  • Fig. 6 illustrates an order 5 Lagrange Interpolation based Farrow structure according to a particular embodiment of the invention.
  • the Farrow structure 206 it could be advantageously done using an order 5 Lagrange Interpolation based Farrow structure as illustrated on Fig. 6.
  • This implementation is preferable to a poly-phase based implementation because it offers the following properties: the in-band spectrum is flat as explained above, the coefficients are simple, the control is simple and the size is small, typically 20-25 kGates for order 5.
  • the interpolation parameter ⁇ is controlled according to the following pseudo code:
  • Fig. 7 illustrates a possible implementation of the CIC decimator used in the given example as rational rate converter.
  • the order N is a parameter.
  • the "Int/Comb" block 700 implements a first block 701 for up-sampling by a ratio U, followed by a succession of N max > N integrators 702, followed by decimation of factor D 703, followed by a succession of N max > N combs 704.
  • the hardware easily bypasses part of the N max steps allowing for only N order.
  • Re-synchronization can be performed in the decimation step by factor D in the "Int/Comb".
  • the step nominally keeps one data every D data. Every additional skipped data delays the output signal of T in /U, where Tin is the input sampling period.
  • the "Int/Comb” block is followed by a first coarse gain 705, typically of a factor an integer having the value [Log2(G CIC ) ⁇ , and where :
  • the fine gain 706 has a factor of SF.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

L'invention concerne un procédé permettant de numériser un signal analogique de sorte qu'un dispositif : -convertisse le signal analogique en un signal numérique à un débit d'échantillonnage d'entrée au moyen d'un CAN, -détecte un bloqueur dans le signal, -applique au signal numérique, si un bloqueur est détecté, une première conversion de débit à l'aide d'un convertisseur de débit non rationnel, -applique au signal numérique, si aucun bloqueur n'est détecté, une seconde conversion de débit à l'aide du convertisseur de débit non rationnel, différente de la première conversion de débit.
PCT/IB2012/002221 2012-09-26 2012-09-26 Adaptation de débit de rééchantillonneur par détection de bloqueur WO2014049383A1 (fr)

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PCT/IB2012/002221 WO2014049383A1 (fr) 2012-09-26 2012-09-26 Adaptation de débit de rééchantillonneur par détection de bloqueur

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CN104393854A (zh) * 2014-12-04 2015-03-04 华侨大学 基于fpga的时分复用级联积分梳状抽取滤波器及其实现方法

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US20040107078A1 (en) * 2002-12-03 2004-06-03 Che-Sheng Chiu Optimized filter parameters design for digital IF programmable downconverter
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SHEIKH F ET AL: "Efficient Sample Rate Conversion for Multi-Standard Software Defined Radios", 2007 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING 15-20 APRIL 2007 HONOLULU, HI, USA, IEEE, PISCATAWAY, NJ, USA, 15 April 2007 (2007-04-15), pages II - 329, XP031463183, ISBN: 978-1-4244-0727-9 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104393854A (zh) * 2014-12-04 2015-03-04 华侨大学 基于fpga的时分复用级联积分梳状抽取滤波器及其实现方法

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