WO2014044515A1 - Method for producing a circuit board element, and circuit board element - Google Patents
Method for producing a circuit board element, and circuit board element Download PDFInfo
- Publication number
- WO2014044515A1 WO2014044515A1 PCT/EP2013/067988 EP2013067988W WO2014044515A1 WO 2014044515 A1 WO2014044515 A1 WO 2014044515A1 EP 2013067988 W EP2013067988 W EP 2013067988W WO 2014044515 A1 WO2014044515 A1 WO 2014044515A1
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- WO
- WIPO (PCT)
- Prior art keywords
- component
- circuit board
- printed circuit
- board element
- film
- Prior art date
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/103—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by bonding or embedding conductive wires or strips
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1028—Thin metal strips as connectors or conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10287—Metal wires as connectors or conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
- H05K3/385—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by conversion of the surface of the metal, e.g. by oxidation, whether or not followed by reaction or removal of the converted layer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/30—Foil or other thin sheet-metal making or treating
- Y10T29/301—Method
- Y10T29/302—Clad or other composite foil or thin metal making
Definitions
- the invention relates to a method for producing a printed circuit board element, in which initially a component made of an electrically conductive material and this component is contacted with an electrically conductive film at least one contact point, before subsequently a cover layer is applied to the component contacting side of the film ,
- the invention relates to a printed circuit board element having at least one electrically conductive film, with a cover layer which covers the film on at least one side, and with at least one component made of an electrically conductive material, wherein the component at least one contact point with the film in Contact is and at least partially, preferably completely, embedded in the cover layer.
- wire-printed circuit boards in which lead wires are applied to the top and / or bottom of a copper foil.
- an electrically insulating cover layer usually a prepreg of an epoxy resin fiberglass fabric, the wires are inside the laminate, embedded in the prepreg.
- the additionally introduced into the interior of the circuit board wires can be designed as silver-plated copper wires.
- the silver layer galvanically applied to the copper core not only has a very good conductivity, but in particular is also very readily weldable.
- the silver layer due to their relatively smooth surface only a very poor adhesion to the surrounding layer of prepreg.
- This object is achieved according to claim 1 by a method for producing a printed circuit board element in which the surface of the component is at least partially roughened before applying the cover layer, so that when applying the cover layer to the film, the cover layer with the roughened surface of the device in contact is brought.
- the component embedded in the printed circuit board element having an at least partially roughened surface instead of a comparatively smooth surface, for example instead of a smooth silver metal surface, a significantly better adhesion is ensured between the component and the covering layer surrounding the component.
- components can be easily integrated into a multilayer, without starting from a detachment of the device from the adjacent cover layer to delamination of the circuit board.
- printed circuit boards with embedded components including in the form of wire-printed circuit boards
- open up new applications which previously appeared to be hardly feasible due to their extreme environmental conditions, for example, the use in high-temperature applications, for example in automotive electronics.
- the roughening of the surface of the component takes place prior to contacting the component with the foil.
- the roughened component surface has no negative influence on the quality of the contact between the component and the foil (for example by resistance welding) to be produced so that with little effort and high, continuous throughput, the entire surface of the components of an upstream roughening treatment can be subjected.
- the roughening of the surface of the device can be realized by chemical etching, wherein the chemical etching is preferably carried out by immersing the device in a liquid etching the material of the device or by spraying the device with such a liquid.
- the components to be treated are cleaned and their metal surfaces are degreased by an acidic or alkaline solution (cleaner).
- cleaning acidic or alkaline solution
- the micro-etching process which can be carried out, for example, in a flood module with splash nozzles (bond)
- residual residues of the etching liquid are removed in a cascade rinsing module before the components are finally dried without staining.
- the surface of the device can also be roughened by mechanical processing, for example by sandblasting or by the spraying of pumice or quartz powder under high pressure, thus making it more adhesive.
- Mechanical roughening methods have the advantage that the surface roughness is produced solely by mechanical removal, so that it is possible to dispense with the use of aggressive etching solutions, which are expensive to purchase and to dispose of.
- the application of a cover layer to the component contacting side of the film by pressing the side of the film is carried out with a prepreg of insulating material.
- the pressing is done in such a way that the stocked with the component copper foil and the prepreg (epoxy glass fiber fabric blank) is introduced into a laminate press and ejected after pressure and heat as pressed final product the circuit board element, which with the established processes (etching process of au Shen and equipping with SMD components) can be completed.
- a plurality of electrically conductive films of which at least one is contacted with at least one component made of an electrically conductive material, and a plurality of inserted respectively between the films prepreg of insulating material pressed together to form a multilayer printed circuit board element.
- sufficient interlaminar adhesion must be ensured between each layer position, since even individual local lifts, as can be caused by prepreg embedded components, can lead to delamination and thus total failure of the multilayer PCB element.
- the object underlying the invention is also achieved according to claim 8 by a printed circuit board element of the type mentioned, in which at least a part of the surface of the cover layer in contact surface of the device is roughened.
- the micro-fine roughening of the component surface results in the ideal surface topography for the optimum adhesion of the component and the surrounding cover layer, so that the risk of delamination of the printed circuit board element emanating from the embedded component can be virtually ruled out.
- applied component may in particular be a lead wire, in particular copper wire, which is arranged after pressing in the interior of the printed circuit board element and contacted via etched pads from the outside (so-called wire printed circuit boards) ,
- the component can also be embodied as a plate-shaped molded part extending in the printed circuit board element, in particular as a copper shaped part, whereby for example the required line cross-sections for mastering by means of such a molded part the occurring in the field of power electronics currents and heat quantities can be provided with little effort.
- FIG. 1a shows a schematic cross-sectional view of the layers of a multi-layer printed circuit board element according to the invention, as they lie on one another in the unpressed state,
- Figure 1 b is a schematic cross-sectional view of a multilayer printed circuit board element according to the invention in the compressed state.
- FIGS. 1 a and 1 b show, in cross-sectional view, the individual material layers of a printed circuit board element 1 according to the invention for better differentiation with another surface filling.
- the components 2, 3 are shown, which are embedded in the printed circuit board element 1.
- the copper foils 4 are shown, while in bright solid color, the epoxy glass fiber fabric layers 5, hereinafter generally called prepreg, can be seen in cross section.
- the components which are on the one hand to three circular cylindrical copper wires 2 and the other to a plate-shaped copper molding 3, z. B. in the form of a copper flat wire is, have been fixed in an upstream process step respectively on the side 4a, 4b of a copper foil 4.
- This process step of fixing the components 2, 3 to the copper foils 4, which is not shown in the figures, is carried out by means of a numerically controlled device for material-locking connection, which is preferably carried out at defined contact points by means of resistance spot welding.
- the wires 2 are actively tracked, held down in a defined desired position, cut and welded by means of a likewise controlled movable welding electrode.
- a component is preferably referred to, which is produced in a separation process in which the shape of a workpiece is changed, wherein the molded part 3 is separated from the workpiece and the final shape is contained in the initial shape.
- the upper copper foil 4 is provided on its underside 4 a with a Differentgeschennten from a copper plate, plate-shaped part 3, wherein copper foil 4 and molded part 3 also at precisely defined connection points a cohesive bonding method, such as by resistance spot welding, have been contacted with each other.
- FIG. 1 a shows the cross-sectional view of an intermediate product in the method for producing the multilayer printed circuit board element 1 according to the invention.
- This intermediate product shows the structure of a layer stack 6 of a plurality of superimposed electrically insulating layers of prepreg 5 and a plurality of conductive layers of copper foil 4, these layers have been shown only for better illustration with a vertical distance from each other.
- Two of the copper foils 4 have been equipped on a side 4a, 4b with additional components (wires 2 or molded part 3) according to the pre-formed method step, wherein these two copper foils 4 are oriented in the layer stack 6 so that the component 2, 3 contacting film side 4a, 4b points into the interior of the layer stack 6, so that the components 2, 3 always come to lie in the interior of the printed circuit board element 1 after being pressed.
- the layer stack 6 described above is introduced between the press plates 7 a, 7 b of a laminate press, wherein a pressure (see arrows directed towards one another in FIGS. 1 a and 1 b) by means of the press plates 7 a, 7 b on the At the same time the temperature of the layers to be laminated is increased to a desired temperature above the room temperature to be laminated together layers of the printed circuit board element 1.
- the production of a multilayer printed circuit board element 1 takes place in practice namely by means of a multi-stage process. Accordingly, first the middle layers of the layer stack 6 are pressed with layers of prepreg 5 placed between a lower and an upper copper foil 4 to form an intermediate product. Then, the outer copper foils 4 of this intermediate are first etched in a known manner from the outside. On the etched copper foils 4 more layers of prepreg 5 and final copper foils 4 are applied. This stack, not shown, already pressed intermediate product and additional externa ßeren layers is finally pressed to the finished multilayer printed circuit board element 1.
- each of the copper foils 4 prepreg 5 consists of an epoxy resin impregnated glass fiber fabric as Isolierstoffmasse that is plasticized under the pressure and heat described above and the subsequent curing a Bonding with the adjacent copper foils 4 causes.
- the plate-shaped molded part 3 attached to the underside 4 a of the upper copper foil 4 is embedded in the insulating material of the prepreg 5 during pressing in such a way that all sides of the molded part 3 are covered over its entire surface with the insulating material of the prepreg 5.
- at least one contact point is not enclosed by the prepreg 5.
- the circular cylindrical conductor wires 2 are also almost completely embedded in the insulating material of the prepreg 5 during pressing. Again, the at least one contact point between the respective wire 2 and the copper foil 4 is not covered by the prepreg 5 alone.
- the printed circuit board element 1 constructed in accordance with the present invention has particular challenges with regard to the delamination resistance, since a weakening of the adhesive bond of the printed circuit board element 1 occurs due to the additionally embedded in the insulating material of the prepreg 5 components 2, 3.
- the device surfaces 2o, 3o have only a very weak adhesion to the respectively adjacent prepreg 5.
- the present invention addresses and overcomes the problem of poor adhesion of embedded device 2, 3 and surrounding layer of prepreg 5 in that the surface 2o, 3o of the device 2, 3 in contact with the prepreg 5 "Roughened” here means that the surface 2o, 3o of the component 2, 3 before the application of the cover layer 5 on the copper foil 4 and the case thereby embedding the component 2, 3 in this cover layer 5 of a targeted Aufaufaut Since this micro-roughness has no significant effect on the quality of the welded joints between components 2, 3 and copper foils 4, the components 2, 3 can already be used in their semi-finished state Wire or sheet goods are pretreated with low expenditure in high throughput speed before they are fed to the actual circuit board manufacturing process.
- the roughening treatment can be a chemical roughening in which the component surface 2o, 3o is contacted with a corrosive solution in a multistage dipping and / or spraying process and the surface material is partially etched away, or can be a mechanical roughening, wherein the component surface 2o , 3o mechanical forces is subjected.
- the chemical roughening is advantageously carried out in multi-stage systems with several modules connected in series, wherein the surfaces 2o, 3o of the continuously guided through the system components 2, 3 before the actual microetching usually cleaned, rinsed and pre-immersed and after the micro-etching process rinsing again takes place to remove the corrosive solution residues.
- the mechanical roughening can be produced, for example, by using a dense mass of minute spheres of, for example, steel, glass, pumice, quartz powder or the like, or by brush roughening techniques. It would also be conceivable to achieve the roughening by introducing a simple profiling (for example of notches) into the component surface 2o, 3o.
- the roughened surface 2o, 3o of the component 2, 3 gives the component 2, 3 contacting layer of the prepreg 5 after pressing and curing a corresponding roughness, which is complementary to the roughness of the device surface 2o, 3o formed.
- the interlocking of the intermeshed roughness peaks of device surface 2o, 3o and adjacent layer of prepreg 5 explains the excellent adhesion of device 2, 3 and prepreg 5.
- components 2, 3 can be integrated into the inner layers of printed circuit board elements 1 without problems, without fear of delamination or cracking and thus functional failures of the printed circuit board element 1 have to. This is especially true for high temperature applications, such as automotive electronics or solar technology, where the connection between the surface 2o, 3o of the embedded device 2, 3 and the surrounding prepreg 5 is exposed to recurring heavy loads due to the different thermal expansion coefficients of both materials.
- the present invention thus contributes, on the one hand, to a further increase in the integration density of components 2, 3 in printed circuit board elements 1 and, on the other hand, increases the range of use of such printed circuit board elements 1 up to high-temperature applications.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The present invention relates to a method for producing a circuit board element and to a corresponding circuit board element with which it is possible to suppress the risk of delamination in the region of a component (e.g. a wire or a plate-shaped moulded part) that is embedded in the circuit board. To this end, according to the invention the surface of the component is at least partially roughened, in order to ensure a better adhesive bond with the surrounding cover layer (e. g. a prepreg made of insulating material compound). The component surface can be roughened by chemical methods such as etching or by purely mechanical methods such as sand blasting.
Description
Verfahren zur Herstellung eines Leiterplattenelements Method for producing a printed circuit board element
sowie Leiterplattenelement and PCB element
Die Erfindung betrifft ein Verfahren zur Herstellung eines Leiterplattenelements, bei dem zunächst ein Bauelement aus einem elektrisch leitenden Werkstoff bereitgestellt und dieses Bauelement mit einer elektrisch leitenden Folie an wenigstens einer Kontaktstelle kontaktiert wird, bevor anschließend eine Deckschicht auf die das Bauelement kontaktierende Seite der Folie aufgebracht wird. The invention relates to a method for producing a printed circuit board element, in which initially a component made of an electrically conductive material and this component is contacted with an electrically conductive film at least one contact point, before subsequently a cover layer is applied to the component contacting side of the film ,
Desweiteren bezieht sich die Erfindung auf ein Leiterplattenelement mit zumindest einer elektrisch leitenden Folie, mit einer Deckschicht, die die Folie auf zumindest einer Seite abdeckt, und mit zumindest einem Bauelement aus einem elektrisch leitenden Werkstoff, wobei das Bauelement an wenigstens einer Kontaktstelle mit der Folie in Kontakt ist und zumindest abschnittsweise, vorzugsweise vollständig, in die Deckschicht eingebettet ist. Furthermore, the invention relates to a printed circuit board element having at least one electrically conductive film, with a cover layer which covers the film on at least one side, and with at least one component made of an electrically conductive material, wherein the component at least one contact point with the film in Contact is and at least partially, preferably completely, embedded in the cover layer.
Der Trend zu immer kleineren und zugleich immer leistungsfähigeren elektronischen Geräten, wie zum Beispiel bei Smartphones oder Tablets, führt schon seit Jahren zu einer steigenden Integrationsdichte auf Leiterplatten. The trend towards smaller and more powerful electronic devices, such as smartphones and tablets, has been leading to increasing integration density on printed circuit boards for years.
Einen deutlichen Vorteil zeigen in dieser Hinsicht drahtbeschriebene Leiterplatten, bei denen Leitungsdrähte auf die Ober- und/oder Unterseite einer Kupferfolie aufgebracht werden. Nach dem Verpressen der Folie mit einer elektrisch isolierenden Deckschicht, üblicherweise einem Prepreg aus einem Epoxidharz-Glasfasergewebe, befinden sich die Drähte im Inneren des Laminates, eingebettet in das Prepreg. A clear advantage in this respect show wire-printed circuit boards, in which lead wires are applied to the top and / or bottom of a copper foil. After pressing the film with an electrically insulating cover layer, usually a prepreg of an epoxy resin fiberglass fabric, the wires are inside the laminate, embedded in the prepreg.
Durch diese beispielsweise in der WO 2008/055672 A1 beschriebene Drahtschreibetechnik lassen sich in Leiterplatten dreidimensionale Schaltungsgeometrien für extreme Packungsdichten realisieren. Wenngleich hierdurch viele technische Einschränkungen der herkömmlichen Leiterplattentechnik überwunden werden, sind drahtbeschriebene Leiterplatten hinsichtlich ihrer Delaminationsfestigkeit noch verbesserungsfähig. By means of this wire writing technique described, for example, in WO 2008/055672 A1, three-dimensional circuit geometries for extreme packing densities can be realized in printed circuit boards. Although this overcomes many technical limitations of conventional printed circuit board technology, wire-printed circuit boards can still be improved with regard to their delamination resistance.
Die Delamination von Leiterplattenelementen ist eine ernstzunehmende Herausforderung, zumal insbesondere mehrlagige Leiterplatten (Multilayer) immer größer werdenden thermischen und/oder mechanischen Belastungen ausgesetzt sind.
Die Haftwerte zwischen den einzelnen Lagen des Multilayers, also zwischen den einzelnen Kupferfolien und den jeweils zwischengefügten Prepreg-Schichten (Epoxidharz-Glasfasergewebe-Schichten), konnte dabei in den vergangenen Jahren durch eine vorgelagerte Behandlung der Oberfläche der Kupferfolien mit chemischen Mitteln („Braunoxid"- oder ,,Schwarzoxid"-Behandlung) und durch die Verwendung verbesserter Epoxidharzmischungen für Prepregs erheblich erhöht werden. The delamination of PCB elements is a serious challenge, especially since multilayer printed circuit boards (multilayer) are exposed to ever-increasing thermal and / or mechanical stresses. The adhesion values between the individual layers of the multilayer, ie between the individual copper foils and the respectively interposed prepreg layers (epoxy resin fiberglass fabric layers), could be improved in recent years by an upstream treatment of the surface of the copper foils with chemical agents ("brown oxide"). - or "black oxide" treatment) and significantly increased by the use of improved epoxy resin blends for prepregs.
Die Einbettung zusätzlicher Bauelemente in die Prepreg-Schichten der Leiterplatte führt jedoch zu eine Erhöhung der Delaminationsgefahr, da sich die Delamination zunächst an den„Schwachstellen" zwischen den Oberflächen der eingebetteten Bauelemente und dem umgebenden Prepreg und nicht an der deutlich haftfesteren Verbindung zwischen der behandelten Kupferfolienoberfläche und dem Prepreg bemerkbar macht. However, the incorporation of additional components into the prepreg layers of the printed circuit board leads to an increase in the risk of delamination, since the delamination is due first to the "weak points" between the surfaces of the embedded components and the surrounding prepreg and not to the much stronger bond between the treated copper foil surface and the prepreg noticeable.
Insbesondere in drahtbeschriebenen Leiterplatten erfolgt durch die im Prepreg eingebetteten Leitungsdrähte eine Schwächung des Haftverbundes. Particularly in wire-printed circuit boards, weakening of the adhesive bond takes place through the lead wires embedded in the prepreg.
Verstärkt wird dieses Problem noch dadurch, dass die in das Innere der Leiterplatte zusätzlich eingebrachten Drähte als versilberte Kupferdrähte ausgeführt sein können. Zwar weist die auf den Kupferkern galvanisch aufgebrachte Silberschicht nicht nur eine sehr gute Leitfähigkeit auf, sondern ist insbesondere auch sehr gut schweißbar. Neben den wirtschaftlichen Nachteilen (versilberte Kupferdrähte sind um ein vielfaches teurer als reine Kupferdrähte) weist die Silberschicht jedoch aufgrund ihrer verhältnismäßig glatten Oberfläche nur eine sehr schlechte Haftung zu der sie umgebenden Schicht aus Prepreg auf. This problem is compounded by the fact that the additionally introduced into the interior of the circuit board wires can be designed as silver-plated copper wires. Admittedly, the silver layer galvanically applied to the copper core not only has a very good conductivity, but in particular is also very readily weldable. In addition to the economic disadvantages (silver-plated copper wires are many times more expensive than pure copper wires), however, the silver layer due to their relatively smooth surface only a very poor adhesion to the surrounding layer of prepreg.
Demzufolge ist es nun Aufgabe der vorliegenden Erfindung, ein Verfahren zur Herstellung eines Leiterplattenelements bzw. ein Leiterplattenelement anzugeben, das eine ausgezeichnete Haftung zwischen den zusätzlich im Leiterplattenelement integrierten Bauelementen und der sie jeweils umgebenden Deckschicht ermöglicht, so dass keine Delaminierung des Leiterplattenelements im Bereich der in der Deckschicht eingebetteten Bauelemente stattfindet. Accordingly, it is an object of the present invention to provide a method for producing a printed circuit board element or a printed circuit board element, which allows excellent adhesion between the additionally integrated in the PCB element components and their respective surrounding cover layer, so that no delamination of the printed circuit board element in the region of the cover layer embedded components takes place.
Diese Aufgabe wird gemäß Patentanspruch 1 durch ein Verfahren zur Herstellung eines Leiterplattenelements gelöst, bei dem die Oberfläche des Bauelements vor dem Aufbringen der Deckschicht zumindest teilweise aufgeraut wird, so dass beim Aufbringen der Deckschicht auf die Folie die Deckschicht mit der aufgerauten Oberfläche der Bauelements in Kontakt gebracht wird.
Indem das im Leiterplattenelement eingebettete Bauelement anstatt einer vergleichsweise glatten Oberfläche, zum Beispiel anstatt einer glatten Silbermetall-Oberfläche, eine zumindest teilweise aufgeraute Oberfläche aufweist, wird eine deutlich bessere Haftung zwischen dem Bauelement und der das Bauelement umgebenden Deckschicht sichergestellt. Somit können problemlos Bauelemente in einen Multilayer integriert werden, ohne dass es ausgehend von einem Ablösen des Bauelements von der angrenzenden Deckschicht zu einer Delamination der Leiterplatte kommt. Somit eröffnen sich für Leiterplatten mit eingebetteten Bauelementen (unter anderem in Form von drahtbeschriebenen Leiterplatten) neue Einsatzgebiete, die aufgrund ihrer extremen Umgebungsbedingungen bisher als kaum realisierbar erschienen, zum Beispiel der Einsatz in Hochtemperaturanwendungen, beispielsweise in der Automobilelektronik. This object is achieved according to claim 1 by a method for producing a printed circuit board element in which the surface of the component is at least partially roughened before applying the cover layer, so that when applying the cover layer to the film, the cover layer with the roughened surface of the device in contact is brought. By virtue of the component embedded in the printed circuit board element having an at least partially roughened surface instead of a comparatively smooth surface, for example instead of a smooth silver metal surface, a significantly better adhesion is ensured between the component and the covering layer surrounding the component. Thus, components can be easily integrated into a multilayer, without starting from a detachment of the device from the adjacent cover layer to delamination of the circuit board. Thus, for printed circuit boards with embedded components (including in the form of wire-printed circuit boards) open up new applications, which previously appeared to be hardly feasible due to their extreme environmental conditions, for example, the use in high-temperature applications, for example in automotive electronics.
Bevorzugterweise erfolgt beim erfindungsgemäßen Verfahren das Aufrauen der Oberfläche des Bauelements vor dem Kontaktieren des Bauelements mit der Folie. Die aufgeraute Bauelementoberfläche hat keinerlei negativen Einfluss auf die Güte der zwischen Bauelement und Folie (beispielsweise durch Widerstandsschweißen) herzustellenden Kontaktie- rung, so dass mit geringem Aufwand und bei hohem, kontinuierlichen Durchsatz die gesamte Oberfläche der Bauelemente einer vorgelagerten Aufrauungsbehandlung unterzogen werden kann. Preferably, in the method according to the invention, the roughening of the surface of the component takes place prior to contacting the component with the foil. The roughened component surface has no negative influence on the quality of the contact between the component and the foil (for example by resistance welding) to be produced so that with little effort and high, continuous throughput, the entire surface of the components of an upstream roughening treatment can be subjected.
Insbesondere kann das Aufrauen der Oberfläche des Bauelements durch chemisches Ätzen realisiert werden, wobei das chemische Ätzen vorzugsweise durch Eintauchen des Bauelements in eine das Material des Bauelements ätzende Flüssigkeit oder durch das Besprühen des Bauelements mit einer solchen Flüssigkeit erfolgt. Vor dem eigentlichen Mikroätzpro- zess werden die zu behandelnden Bauelemente gereinigt und deren Metalloberflächen dabei durch eine saure oder alkalische Lösung entfettet (Cleaner). Nach dem Mikroätzprozess, der beispielsweise in einem Flutmodul mit Schwalldüsen (Bond) durchgeführt werden kann, werden Restrückstände der ätzenden Flüssigkeit in einem Kaskaden-Spülmodul entfernt, bevor die Bauelemente schließlich fleckenfrei getrocknet werden. In particular, the roughening of the surface of the device can be realized by chemical etching, wherein the chemical etching is preferably carried out by immersing the device in a liquid etching the material of the device or by spraying the device with such a liquid. Before the actual microetching process, the components to be treated are cleaned and their metal surfaces are degreased by an acidic or alkaline solution (cleaner). After the micro-etching process, which can be carried out, for example, in a flood module with splash nozzles (bond), residual residues of the etching liquid are removed in a cascade rinsing module before the components are finally dried without staining.
Alternativ kann die Oberfläche des Bauelements auch durch mechanisches Bearbeiten, zum Beispiel durch Sandstrahlen oder durch das Aufsprühen von Bims- oder Quarzmehl unter hohem Druck, aufgeraut und so haftfähiger gemacht werden. Mechanische Aufrauverfahren haben den Vorteil, dass die Oberflächenrauigkeit allein durch mechanischen Abtrag hergestellt wird, so dass auf die Verwendung aggressiver Ätzlösungen, welche teuer in Anschaffung und Entsorgung sind, verzichtet werden kann.
In weiter bevorzugter Weise erfolgt das Aufbringen einer Deckschicht auf die das Bauelement kontaktierende Seite der Folie durch Verpressen der Seite der Folie mit einem Prepreg aus Isolierstoffmasse. Das Verpressen geschieht in der Weise, dass die mit dem Bauelement bestückte Kupferfolie und das Prepreg (Epoxidharz-Glasfasergewebe-Zuschnitt) in eine Laminatpresse eingeführt und nach Druck- und Wärmeeinwirkung als verpresstes Endprodukt das Leiterplattenelement ausgestoßen wird, welches mit den etablierten Prozessen (Ätzprozess von au ßen und Bestücken mit SMD-Bauteilen) fertiggestellt werden kann. Alternatively, the surface of the device can also be roughened by mechanical processing, for example by sandblasting or by the spraying of pumice or quartz powder under high pressure, thus making it more adhesive. Mechanical roughening methods have the advantage that the surface roughness is produced solely by mechanical removal, so that it is possible to dispense with the use of aggressive etching solutions, which are expensive to purchase and to dispose of. In a further preferred manner, the application of a cover layer to the component contacting side of the film by pressing the side of the film is carried out with a prepreg of insulating material. The pressing is done in such a way that the stocked with the component copper foil and the prepreg (epoxy glass fiber fabric blank) is introduced into a laminate press and ejected after pressure and heat as pressed final product the circuit board element, which with the established processes (etching process of au Shen and equipping with SMD components) can be completed.
Vorzugsweise werden eine Mehrzahl von elektrisch leitfähigen Folien, von denen mindestens eine mit mindestens einem Bauelement aus einem elektrisch leitenden Werkstoff kontaktiert ist, und eine Mehrzahl von jeweils zwischen den Folien eingefügten Prepregs aus Isolierstoffmasse miteinander zu einem Multilayer-Leiterplattenelement verpresst. Insbesondere bei einer solchen Verpressung zum Multilayer muss zwischen jeder Schichtlage eine ausreichende interlaminare Haftung sichergestellt sein, da bereits einzelne lokale Abhebungen, wie sie durch im Prepreg eingebettete Bauelemente hervorgerufen werden können, zu einer Delamination und damit zum Totalausfall des Multilayer-Leiterplattenelements führen können. Preferably, a plurality of electrically conductive films, of which at least one is contacted with at least one component made of an electrically conductive material, and a plurality of inserted respectively between the films prepreg of insulating material pressed together to form a multilayer printed circuit board element. In particular, in such a compression to the multilayer sufficient interlaminar adhesion must be ensured between each layer position, since even individual local lifts, as can be caused by prepreg embedded components, can lead to delamination and thus total failure of the multilayer PCB element.
Die der Erfindung zugrunde liegende Aufgabe wird darüber hinaus gemäß Patentanspruch 8 durch ein Leiterplattenelement der eingangs genannten Art gelöst, bei dem zumindest ein Teil der mit der Deckschicht in Kontakt stehenden Oberfläche des Bauelements aufgeraut ist. Durch die mikrofeine Aufrauung der Bauelementoberfläche entsteht die ideale Oberflächentopographie für die optimale Haftung von Bauelement und umgebender Deckschicht, so dass die vom eingebetteten Bauelement ausgehende Gefahr der Delamination des Leiterplattenelements nahezu ausgeschlossen werden kann. The object underlying the invention is also achieved according to claim 8 by a printed circuit board element of the type mentioned, in which at least a part of the surface of the cover layer in contact surface of the device is roughened. The micro-fine roughening of the component surface results in the ideal surface topography for the optimum adhesion of the component and the surrounding cover layer, so that the risk of delamination of the printed circuit board element emanating from the embedded component can be virtually ruled out.
Bei dem auf die zu verpressende Folie, insbesondere Kupferfolie, aufgebrachten Bauelement kann es sich insbesondere um einen Leitungsdraht, insbesondere Kupferdraht, handeln, der nach dem Verpressen im Inneren des Leiterplattenelements angeordnet ist und über geätzte Pads von au ßen kontaktiert wird (sogenannte drahtbeschriebene Leiterplatten). In the on the film to be pressed, in particular copper foil, applied component may in particular be a lead wire, in particular copper wire, which is arranged after pressing in the interior of the printed circuit board element and contacted via etched pads from the outside (so-called wire printed circuit boards) ,
Das Bauelement kann jedoch auch als ein sich im Leiterplattenelement erstreckendes, plat- tenförmiges Formteil, insbesondere als Kupferformteil, ausgebildet sein, wobei mittels eines solchen Formteils beispielsweise die erforderlichen Leitungsquerschnitte zur Beherrschung
der im Bereich der Leistungselektronik auftretenden Ströme und Wärmemengen aufwandsarm bereitgestellt werden können. However, the component can also be embodied as a plate-shaped molded part extending in the printed circuit board element, in particular as a copper shaped part, whereby for example the required line cross-sections for mastering by means of such a molded part the occurring in the field of power electronics currents and heat quantities can be provided with little effort.
Die Erfindung wird nun nachfolgend unter Bezugnahme auf zwei Figuren noch weiter erläutert. Es zeigen im Einzelnen: The invention will now be explained below with reference to two figures. They show in detail:
Figur 1 a eine schematische Querschnittsansicht der Lagen eines Multi layer- Leiterplattenelements gemäß der Erfindung, wie sie im unverpressten Zustand aufeinanderliegen, FIG. 1a shows a schematic cross-sectional view of the layers of a multi-layer printed circuit board element according to the invention, as they lie on one another in the unpressed state,
Figur 1 b eine schematische Querschnittsansicht eines Multilayer-Leiterplattenelements gemäß der Erfindung im verpressten Zustand. Figure 1 b is a schematic cross-sectional view of a multilayer printed circuit board element according to the invention in the compressed state.
In den Figuren 1 a und 1 b sind jeweils in Querschnittsansicht die einzelnen Materiallagen eines erfindungsgemäßen Leiterplattenelements 1 zur besseren Unterscheidung mit anderer Flächenfüllung dargestellt. Mit jeweils schräger Schraffierung sind die Bauelemente 2, 3 dargestellt, die in das Leiterplattenelement 1 eingebettet werden. Mit dunklem Vollton sind die Kupferfolien 4 gezeigt, während in hellem Vollton die Epoxidharz-Glasfasergewebe- Schichten 5, nachstehend allgemein Prepreg genannt, im Querschnitt zu sehen sind. FIGS. 1 a and 1 b show, in cross-sectional view, the individual material layers of a printed circuit board element 1 according to the invention for better differentiation with another surface filling. With each oblique hatching, the components 2, 3 are shown, which are embedded in the printed circuit board element 1. With dark solid tone, the copper foils 4 are shown, while in bright solid color, the epoxy glass fiber fabric layers 5, hereinafter generally called prepreg, can be seen in cross section.
Die Bauelemente, bei denen es sich zum einen um drei kreiszylindrische Kupferdrähte 2 und zum anderen um ein plattenförmiges Kupferformteil 3, z. B. in Form eines Kupferflachdrahts, handelt, sind in einem vorgelagerten Verfahrensschritt jeweils auf die Seite 4a, 4b einer Kupferfolie 4 fixiert worden. Dieser in den Figuren nicht dargestellte Verfahrensschritt des Fixierens der Bauelemente 2, 3 an den Kupferfolien 4 wird mittels einer bereits in der WO 2006/077167 A2 beschriebenen, numerisch gesteuerten Vorrichtung zum stoffschlüssigen Verbinden durchgeführt, wobei das Verbinden vorzugsweise an definierten Kontaktstellen mittels Widerstandspunktschweißen erfolgt. Die Drähte 2 werden dabei aktiv nachgeführt, in einer definierten Sollposition niedergehalten, geschnitten und mittels einer ebenfalls kontrolliert verfahrbaren Schweißelektrode verschweißt. The components, which are on the one hand to three circular cylindrical copper wires 2 and the other to a plate-shaped copper molding 3, z. B. in the form of a copper flat wire is, have been fixed in an upstream process step respectively on the side 4a, 4b of a copper foil 4. This process step of fixing the components 2, 3 to the copper foils 4, which is not shown in the figures, is carried out by means of a numerically controlled device for material-locking connection, which is preferably carried out at defined contact points by means of resistance spot welding. The wires 2 are actively tracked, held down in a defined desired position, cut and welded by means of a likewise controlled movable welding electrode.
Als Formteil 3 im Sinne dieser Erfindung wird vorzugsweise ein Bauteil bezeichnet, das in einem Trennverfahren hergestellt ist, in welchem die Form eines Werkstücks verändert wird, wobei das Formteil 3 von dem Werkstück abgetrennt wird und die Endform in der Ausgangsform enthalten ist. In den Figuren 1 a und 1 b ist die obere Kupferfolie 4 an ihrer Unterseite 4a mit einem aus einer Kupferplatte herausgetrennten, plattenförmigen Formteil 3 versehen, wobei Kupferfolie 4 und Formteil 3 ebenfalls an genau definierten Anschlussstellen durch
ein stoffschlüssiges Verbindungsverfahren, wie zum Beispiel durch Widerstandspunktschweißen, miteinander kontaktiert worden sind. As a molded part 3 in the sense of this invention, a component is preferably referred to, which is produced in a separation process in which the shape of a workpiece is changed, wherein the molded part 3 is separated from the workpiece and the final shape is contained in the initial shape. In Figures 1 a and 1 b, the upper copper foil 4 is provided on its underside 4 a with a herausgeschennten from a copper plate, plate-shaped part 3, wherein copper foil 4 and molded part 3 also at precisely defined connection points a cohesive bonding method, such as by resistance spot welding, have been contacted with each other.
In Figur 1 a ist die Querschnittsansicht eines Zwischenprodukts in dem Verfahren zur Herstellung des erfindungsgemäßen Multilayer-Leiterplattenelements 1 zu sehen. Dieses Zwischenprodukt zeigt den Aufbau eines Schichtstapels 6 aus mehreren übereinander angeordneten elektrisch isolierenden Schichten aus Prepreg 5 und mehreren leitenden Schichten aus Kupferfolie 4, wobei diese Schichten nur zur besseren Veranschaulichung mit vertikalem Abstand voneinander dargestellt worden sind. Zwei der Kupferfolien 4 sind gemäß dem vorgeschilderten Verfahrensschritt auf einer Seite 4a, 4b mit zusätzlichen Bauelementen (Drähten 2 bzw. Formteil 3) bestückt worden, wobei diese beiden Kupferfolien 4 im Schichtstapel 6 so orientiert sind, dass die das Bauelement 2, 3 kontaktierende Folienseite 4a, 4b in das Innere des Schichtstapels 6 weist, so dass die Bauelemente 2, 3 nach dem Verpres- sen immer im Inneren des Leiterplattenelements 1 zu liegen kommen. FIG. 1 a shows the cross-sectional view of an intermediate product in the method for producing the multilayer printed circuit board element 1 according to the invention. This intermediate product shows the structure of a layer stack 6 of a plurality of superimposed electrically insulating layers of prepreg 5 and a plurality of conductive layers of copper foil 4, these layers have been shown only for better illustration with a vertical distance from each other. Two of the copper foils 4 have been equipped on a side 4a, 4b with additional components (wires 2 or molded part 3) according to the pre-formed method step, wherein these two copper foils 4 are oriented in the layer stack 6 so that the component 2, 3 contacting film side 4a, 4b points into the interior of the layer stack 6, so that the components 2, 3 always come to lie in the interior of the printed circuit board element 1 after being pressed.
Der vorstehend beschriebene Schichtstapel 6 ist gemäß Figur 1 a zwischen die Pressplatten 7a, 7b einer Laminatpresse eingebracht, wobei anschließend gemäß Figur 1 b ein Druck (siehe aufeinander zu gerichtete Pfeile in Figuren 1 a und 1 b) mittels der Pressplatten 7a, 7b auf die miteinander zu laminierenden Schichten des Leiterplattenelements 1 aufgebracht und dabei gleichzeitig die Temperatur der zu laminierenden Schichten auf eine gewünschte Temperatur oberhalb der Raumtemperatur erhöht wird. According to FIG. 1 a, the layer stack 6 described above is introduced between the press plates 7 a, 7 b of a laminate press, wherein a pressure (see arrows directed towards one another in FIGS. 1 a and 1 b) by means of the press plates 7 a, 7 b on the At the same time the temperature of the layers to be laminated is increased to a desired temperature above the room temperature to be laminated together layers of the printed circuit board element 1.
Es sei angemerkt, dass der durch den Übergang von Figur 1 a nach Figur 1 b illustrierte Pressvorgang in stark vereinfachter Weise wiedergegeben worden ist. Die Herstellung eines Multilayer-Leiterplattenelements 1 erfolgt in der Praxis nämlich mittels eines mehrstufigen Prozesses. Demnach werden zunächst die mittleren Lagen des Schichtstapels 6 mit zwischen einer unteren und einer oberen Kupferfolie 4 platzierten Schichten aus Prepreg 5 zu einem Zwischenprodukt verpresst. Daraufhin werden die äußeren Kupferfolien 4 dieses Zwischenprodukts in bekannter Weise zunächst von au ßen geätzt. Auf die geätzten Kupferfolien 4 werden weitere Schichten aus Prepreg 5 und abschließende Kupferfolien 4 aufgetragen. Dieser nicht dargestellte Stapel aus bereits verpresstem Zwischenprodukt und zusätzlichen äu ßeren Lagen wird schließlich zum fertigen Multilayer-Leiterplattenelement 1 gepresst. It should be noted that the pressing process illustrated by the transition from FIG. 1 a to FIG. 1 b has been reproduced in a highly simplified manner. The production of a multilayer printed circuit board element 1 takes place in practice namely by means of a multi-stage process. Accordingly, first the middle layers of the layer stack 6 are pressed with layers of prepreg 5 placed between a lower and an upper copper foil 4 to form an intermediate product. Then, the outer copper foils 4 of this intermediate are first etched in a known manner from the outside. On the etched copper foils 4 more layers of prepreg 5 and final copper foils 4 are applied. This stack, not shown, already pressed intermediate product and additional externa ßeren layers is finally pressed to the finished multilayer printed circuit board element 1.
Das jeweils zwischen die Kupferfolien 4 eingefügte Prepreg 5 besteht aus einem epoxidharzgetränkten Glasfasergewebe als Isolierstoffmasse, die unter der vorbeschriebenen Druck- und Wärmeeinwirkung plastifiziert wird und beim anschließenden Aushärten eine
Verklebung mit den angrenzenden Kupferfolien 4 bewirkt. Das an der Unterseite 4a der oberen Kupferfolie 4 angebrachte, plattenförmige Formteil 3 wird beim Verpressen derart in die Isolierstoffmasse des Prepregs 5 eingebettet, dass alle Seiten des Formteils 3 vollflächig mit der Isolierstoffmasse des Prepregs 5 bedeckt sind. Allein die zwischen Formteil 3 und Kupferfolie 4 vorgesehene, mindestens eine Kontaktstelle ist nicht vom Prepreg 5 umschlossen. Die kreiszylindrischen Leitungsdrähte 2 werden beim Verpressen ebenfalls nahezu vollumfänglich in die Isolierstoffmasse des Prepregs 5 eingebettet. Auch hier ist allein die mindestens eine Kontaktstelle zwischen dem jeweiligen Draht 2 und der Kupferfolie 4 nicht vom Prepreg 5 bedeckt. The inserted between each of the copper foils 4 prepreg 5 consists of an epoxy resin impregnated glass fiber fabric as Isolierstoffmasse that is plasticized under the pressure and heat described above and the subsequent curing a Bonding with the adjacent copper foils 4 causes. The plate-shaped molded part 3 attached to the underside 4 a of the upper copper foil 4 is embedded in the insulating material of the prepreg 5 during pressing in such a way that all sides of the molded part 3 are covered over its entire surface with the insulating material of the prepreg 5. However, provided between the molding 3 and copper foil 4, at least one contact point is not enclosed by the prepreg 5. The circular cylindrical conductor wires 2 are also almost completely embedded in the insulating material of the prepreg 5 during pressing. Again, the at least one contact point between the respective wire 2 and the copper foil 4 is not covered by the prepreg 5 alone.
Für eine bessere Haftung zwischen Prepreg 5 und Kupferfolie 4 ist es bekannt, die Oberflächen der Kupferfolien 4 durch einen Oxidationsprozess („Braunoxid" bzw. „Schwarzoxid") vorzubehandeln, so dass beim anschließenden Verpressen gemäß Figur 1 b zum Multilayer- Leiterplattenelement 1 ein besserer Haftverbund zwischen den Kupferfolien 4 und den isolierenden Deckschichten 5 (Prepregs) gewährleistet werden kann. Das gemäß der vorliegenden Erfindung aufgebaute Leiterplattenelement 1 weist jedoch besondere Herausforderungen hinsichtlich der Delaminationsfestigkeit auf, da durch die zusätzlich in die Isolierstoffmasse des Prepregs 5 eingebetteten Bauelemente 2, 3 eine Schwächung des Haftverbundes des Leiterplattenelements 1 eintritt. Im Gegensatz zu den Kupferfolienoberflächen weisen die Bauelementoberflächen 2o, 3o nämlich nur eine sehr schwache Haftung an dem jeweils angrenzenden Prepreg 5 auf. For a better adhesion between prepreg 5 and copper foil 4, it is known to pretreat the surfaces of the copper foils 4 by an oxidation process ("brown oxide" or "black oxide"), so that during the subsequent compression according to FIG. 1 b to the multilayer printed circuit board element 1 a better one Adhesive bond between the copper foils 4 and the insulating cover layers 5 (prepregs) can be ensured. However, the printed circuit board element 1 constructed in accordance with the present invention has particular challenges with regard to the delamination resistance, since a weakening of the adhesive bond of the printed circuit board element 1 occurs due to the additionally embedded in the insulating material of the prepreg 5 components 2, 3. In contrast to the copper foil surfaces, the device surfaces 2o, 3o have only a very weak adhesion to the respectively adjacent prepreg 5.
Der Grund dafür liegt unter anderem darin, dass in drahtbeschriebenen Leiterplatten (d. h. Leiterplatten, deren Kupferfolien 4 mit Drähten 2 verschweißt sind) zumeist galvanisch versilberte Kupferdrähte als eingebettete Bauelemente zum Einsatz gelangen. Die äußere Silberschicht dieser Drähte weist zwar sehr gute Schweißeigenschaften zur Erzielung einer sicheren Verbindung mit der Kupferfolie 4 auf, jedoch ist die Haftung der Silberschicht zum umgebenden Prepreg 5 bedingt durch die eher glatte Oberfläche der Silberschicht unzureichend. In der Folge kann es zu lokalen Abhebungen der Silberschicht des Bauelements vom umgebenden Prepreg 5 kommen, die im Extremfall zum Ausgangspunkt einer vollständigen Delamination und somit eines Totalausfalls des Leiterplattenelements 1 werden können. The reason for this is, inter alia, that in wire-printed circuit boards (that is to say printed circuit boards whose copper foils 4 are welded to wires 2), in most cases galvanically silver-plated copper wires are used as embedded components. Although the outer silver layer of these wires has very good welding properties for achieving a secure bond with the copper foil 4, the adhesion of the silver layer to the surrounding prepreg 5 is insufficient due to the rather smooth surface of the silver layer. As a consequence, local lifting off of the silver layer of the component from the surrounding prepreg 5 may occur, which in extreme cases may become the starting point for complete delamination and thus total failure of the printed circuit board element 1.
Hier setzt die vorliegende Erfindung an und beseitigt das Problem der schlechten Haftung von eingebettetem Bauelement 2, 3 und umgebender Schicht aus Prepreg 5 dadurch, dass die mit dem Prepreg 5 in Kontakt stehende Oberfläche 2o, 3o des Bauelements 2, 3 zumin-
dest teilweise aufgeraut ist.„Aufgeraut" bedeutet hierbei, dass die Oberfläche 2o, 3o des Bauelements 2, 3 vor dem Aufbringen der Deckschicht 5 auf die Kupferfolie 4 und dem dabei erfolgenden Einbetten des Bauelements 2, 3 in diese Deckschicht 5 einer gezielten Auf- rauungsbehandlung unterzogen worden ist, um die Oberfläche 2o, 3o mit einer definierten Mikrorauigkeit zu versehen. Da diese Mikrorauigkeit keine wesentlichen Auswirkungen auf die Qualität der Schweißverbindungen zwischen Bauelementen 2, 3 und Kupferfolien 4 hat, können die Bauelemente 2, 3 bereits in ihrem Halbfertigzustand als Draht- oder Plattenware in großer Durchsatzgeschwindigkeit aufwandsarm vorbehandelt werden, bevor sie dem eigentlichen Leiterplattenherstellungsprozess zugeführt werden. Here, the present invention addresses and overcomes the problem of poor adhesion of embedded device 2, 3 and surrounding layer of prepreg 5 in that the surface 2o, 3o of the device 2, 3 in contact with the prepreg 5 "Roughened" here means that the surface 2o, 3o of the component 2, 3 before the application of the cover layer 5 on the copper foil 4 and the case thereby embedding the component 2, 3 in this cover layer 5 of a targeted Aufaufaut Since this micro-roughness has no significant effect on the quality of the welded joints between components 2, 3 and copper foils 4, the components 2, 3 can already be used in their semi-finished state Wire or sheet goods are pretreated with low expenditure in high throughput speed before they are fed to the actual circuit board manufacturing process.
Die Aufrauungsbehandlung kann eine chemische Aufrauung sein, wobei die Bauelementoberfläche 2o, 3o in einem mehrstufigen Tauch- und /oder Sprühverfahren mit einer ätzenden Lösung in Berührung gebracht wird und das Oberflächenmaterial dabei teilweise weggeätzt wird, oder kann eine mechanische Aufrauung sein, wobei die Bauelementoberfläche 2o, 3o mechanischen Kräften unterzogen wird. The roughening treatment can be a chemical roughening in which the component surface 2o, 3o is contacted with a corrosive solution in a multistage dipping and / or spraying process and the surface material is partially etched away, or can be a mechanical roughening, wherein the component surface 2o , 3o mechanical forces is subjected.
Die chemische Aufrauung erfolgt vorteilhafterweise in mehrstufigen Anlagen mit mehreren in Reihe geschalteten Modulen, wobei die Oberflächen 2o, 3o der kontinuierlich durch die Anlage geführten Bauelemente 2, 3 vor dem eigentlichen Mikroätzprozess zumeist noch gereinigt, gespült und vorgetaucht werden und nach dem Mikroätzprozess ein neuerliches Spülen zum Entfernen der ätzenden Lösungsrückstände stattfindet. Die mechanische Aufrauung kann zum Beispiel durch Verwendung einer dichten Masse winziger Kugeln aus zum Beispiel Stahl, Glas, Bims-, Quarzmehl oder ähnlichem oder über Bürstenaufrauungstechni- ken erzeugt werden. Ebenfalls denkbar wäre es, die Aufrauung durch das Einbringen einer einfachen Profilierung (z. B. von Kerbungen) in die Bauelementoberfläche 2o, 3o zu erzielen. The chemical roughening is advantageously carried out in multi-stage systems with several modules connected in series, wherein the surfaces 2o, 3o of the continuously guided through the system components 2, 3 before the actual microetching usually cleaned, rinsed and pre-immersed and after the micro-etching process rinsing again takes place to remove the corrosive solution residues. The mechanical roughening can be produced, for example, by using a dense mass of minute spheres of, for example, steel, glass, pumice, quartz powder or the like, or by brush roughening techniques. It would also be conceivable to achieve the roughening by introducing a simple profiling (for example of notches) into the component surface 2o, 3o.
Durch die aufgeraute Oberfläche 2o, 3o des Bauelements 2, 3 erhält die das Bauelement 2, 3 kontaktierende Schicht des Prepregs 5 nach dem Verpressen und Aushärten eine entsprechende Rauheit, die komplementär zur Rauheit der Bauelementoberfläche 2o, 3o ausgebildet ist. Das Verhaken der ineinander verzahnten Rauigkeitsspitzen von Bauelementoberfläche 2o, 3o und angrenzender Schicht des Prepregs 5 erklärt die ausgezeichnete Haftung von Bauelement 2, 3 und Prepreg 5. The roughened surface 2o, 3o of the component 2, 3 gives the component 2, 3 contacting layer of the prepreg 5 after pressing and curing a corresponding roughness, which is complementary to the roughness of the device surface 2o, 3o formed. The interlocking of the intermeshed roughness peaks of device surface 2o, 3o and adjacent layer of prepreg 5 explains the excellent adhesion of device 2, 3 and prepreg 5.
Durch die erfindungsgemäße Verbesserung können Bauelemente 2, 3 problemlos in die Innenlagen von Leiterplattenelementen 1 integriert werden, ohne dass Delaminationen oder Rissbildungen und damit Funktionsausfälle des Leiterplattenelements 1 befürchtet werden
müssen. Dies gilt insbesondere auch für Hochtemperaturanwendungen, wie Automobilelektronik oder Solartechnik, wo die Verbindung zwischen der Oberfläche 2o, 3o des eingebetteten Bauelements 2, 3 und dem umgebenden Prepreg 5 aufgrund der unterschiedlichen thermischen Ausdehnungskoeffizienten beider Materialien immer wiederkehrenden starken Belastungen ausgesetzt wird. As a result of the improvement according to the invention, components 2, 3 can be integrated into the inner layers of printed circuit board elements 1 without problems, without fear of delamination or cracking and thus functional failures of the printed circuit board element 1 have to. This is especially true for high temperature applications, such as automotive electronics or solar technology, where the connection between the surface 2o, 3o of the embedded device 2, 3 and the surrounding prepreg 5 is exposed to recurring heavy loads due to the different thermal expansion coefficients of both materials.
Die vorliegende Erfindung trägt somit zum einen zu einer weiteren Erhöhung der Integrationsdichte von Bauelementen 2, 3 in Leiterplattenelementen 1 bei und vergrößert zum anderen das Einsatzspektrum solcher Leiterplattenelemente 1 bis hin zu Hochtemperaturanwendungen.
The present invention thus contributes, on the one hand, to a further increase in the integration density of components 2, 3 in printed circuit board elements 1 and, on the other hand, increases the range of use of such printed circuit board elements 1 up to high-temperature applications.
Claims
1 . Verfahren zur Herstellung eines Leiterplattenelements (1 ), umfassend die folgenden Schritte: a) Bereitstellen eines Bauelements (2, 3) aus einem elektrisch leitenden Werkstoff, b) Kontaktieren des Bauelements (2, 3) mit einer elektrisch leitenden Folie (4) an wenigstens einer Kontaktstelle, c) Aufbringen einer Deckschicht (5) auf die das Bauelement (2, 3) kontaktierende Seite (4a, 4b) der Folie (4), dadurch gekennzeichnet, dass die Oberfläche (2o, 3o) des Bauelements (2, 3) vor dem Schritt c) zumindest teilweise aufgeraut wird und die Deckschicht (5) im Schritt c) mit der aufgerauten Oberfläche (2o, 3o) des Bauelements (2, 3) in Kontakt gebracht wird. 1 . Method for producing a printed circuit board element (1), comprising the following steps: a) providing a component (2, 3) made of an electrically conductive material, b) contacting the component (2, 3) with an electrically conductive foil (4) at least a contact point, c) applying a cover layer (5) to the component (2, 3) contacting side (4a, 4b) of the film (4), characterized in that the surface (2o, 3o) of the component (2, 3 ) is at least partially roughened before step c) and the cover layer (5) in step c) with the roughened surface (2o, 3o) of the device (2, 3) is brought into contact.
2. Verfahren nach Anspruch 1 , dadurch gekennzeichnet, dass das Aufrauen der Oberfläche (2o, 3o) des Bauelements (2, 3) vor dem Kontaktieren des Bauelements (2, 3) mit der Folie (4) gemäß Schritt b) erfolgt. 2. The method according to claim 1, characterized in that the roughening of the surface (2o, 3o) of the device (2, 3) before contacting the device (2, 3) with the film (4) according to step b).
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass die Oberfläche (2o, 3o) des Bauelements (2, 3) durch chemisches Ätzen aufgeraut wird, wobei das chemische Ätzen vorzugsweise durch Eintauchen des Bauelements (2, 3) in eine das Material des Bauelements (2, 3) ätzende Flüssigkeit oder durch das Besprühen des Bauelements (2, 3) mit einer solchen Flüssigkeit erfolgt. 3. The method according to claim 1 or 2, characterized in that the surface (2o, 3o) of the device (2, 3) is roughened by chemical etching, wherein the chemical etching preferably by immersing the device (2, 3) in a the Material of the component (2, 3) corrosive liquid or by spraying the device (2, 3) is carried out with such a liquid.
4. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass die Oberfläche (2o, 3o) des Bauelements (2, 3) durch mechanisches Bearbeiten, zum Bei-
spiel durch Sandstrahlen oder durch das Aufsprühen von Bims- oder Quarzmehl unter hohem Druck, aufgeraut wird. 4. The method according to claim 1 or 2, characterized in that the surface (2o, 3o) of the component (2, 3) by mechanical processing, for example by sandblasting or by spraying pumice or quartz flour under high pressure, roughened.
5. Verfahren nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass das Kontaktieren des Bauelements (2, 3) mit der Folie (4) gemäß Schritt b) durch Schweißen, vorzugsweise durch Widerstandsschweißen, erfolgt. 5. The method according to any one of claims 1 to 4, characterized in that the contacting of the component (2, 3) with the film (4) according to step b) by welding, preferably by resistance welding takes place.
6. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass das Aufbringen einer Deckschicht (5) auf die das Bauelement (2, 3) kontaktierende Seite (4a, 4b) der Folie (4) gemäß Schritt c) durch Verpressen der Seite (4a, 4b) der Folie (4) mit einem Prepreg (5) aus Isolierstoffmasse erfolgt. 6. The method according to any one of claims 1 to 5, characterized in that the application of a cover layer (5) on the component (2, 3) contacting side (4a, 4b) of the film (4) according to step c) by pressing the Side (4a, 4b) of the film (4) with a prepreg (5) made of insulating material.
7. Verfahren nach Anspruch 6, dadurch gekennzeichnet, dass im Schritt c) eine Mehrzahl von elektrisch leitfähigen Folien (4), von denen mindestens eine mit mindestens einem Bauelement (2, 3) aus einem elektrisch leitenden Werkstoff kontaktiert ist, und eine Mehrzahl von jeweils zwischen den Folien eingefügten Prepregs (5) aus Isolierstoffmasse miteinander zu einem Mulitlayer-Leiterplatten- element (1 ) verpresst werden. 7. The method according to claim 6, characterized in that in step c) a plurality of electrically conductive films (4), of which at least one with at least one component (2, 3) made of an electrically conductive material is contacted, and a plurality of each inserted between the films prepregs (5) made of insulating material are pressed together to a multi-layer printed circuit board element (1).
8. Leiterplattenelement, umfassend 8. printed circuit board element comprising
- zumindest eine elektrisch leitende Folie (4), at least one electrically conductive foil (4),
- zumindest eine Deckschicht (5), die die Folie (4) auf zumindest einer Seite (4a, 4b) abdeckt, at least one covering layer (5) which covers the film (4) on at least one side (4a, 4b),
- zumindest ein Bauelement (2, 3) aus einem elektrisch leitenden Werkstoff, wobei das Bauelement (2, 3) an wenigstens einer Kontaktstelle mit der Folie (4) in Kontakt ist und zumindest abschnittsweise, vorzugsweise vollständig, in die Deckschicht (5) eingebettet ist, dadurch gekennzeichnet, dass zumindest ein Teil der mit der Deckschicht (5) in Kontakt stehenden Oberfläche (2o, 3o) des Bauelements (2, 3) aufgeraut ist.
- At least one component (2, 3) made of an electrically conductive material, wherein the component (2, 3) at least one contact point with the film (4) in contact and at least partially, preferably completely, embedded in the cover layer (5) characterized in that at least a part of the surface (2o, 3o) of the component (2, 3) which is in contact with the cover layer (5) is roughened.
9. Leiterplattenelement nach Anspruch 8, dadurch gekennzeichnet, dass das Bauelement als vorzugsweise aus Kupfer bestehender Leitungsdraht (2) mit kreisförmigem oder rechteckförmigem Querschnitt ausgebildet ist. 9. printed circuit board element according to claim 8, characterized in that the component is designed as preferably made of copper conductor wire (2) with a circular or rectangular cross-section.
10. Leiterplattenelement nach Anspruch 8, dadurch gekennzeichnet, dass das Bauelement als vorzugsweise aus Kupfer bestehendes, plattenförmiges Formteil (3) ausgebildet ist.
10. printed circuit board element according to claim 8, characterized in that the component is formed as preferably made of copper, plate-shaped molding (3).
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/429,070 US20150237738A1 (en) | 2012-09-20 | 2013-08-30 | Method for producing a circuit board element, and circuit board element |
CN201380049063.XA CN104756613B (en) | 2012-09-20 | 2013-08-30 | The method and circuit board component of processing circuit panel element |
JP2015532359A JP6067859B2 (en) | 2012-09-20 | 2013-08-30 | Circuit board element manufacturing method and circuit board element |
EP13756878.8A EP2898759B1 (en) | 2012-09-20 | 2013-08-30 | Method for producing a circuit board element, and circuit board element |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102012216926.1A DE102012216926A1 (en) | 2012-09-20 | 2012-09-20 | Method for producing a printed circuit board element and printed circuit board element |
DE102012216926.1 | 2012-09-20 |
Publications (1)
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WO2014044515A1 true WO2014044515A1 (en) | 2014-03-27 |
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PCT/EP2013/067988 WO2014044515A1 (en) | 2012-09-20 | 2013-08-30 | Method for producing a circuit board element, and circuit board element |
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US (1) | US20150237738A1 (en) |
EP (1) | EP2898759B1 (en) |
JP (1) | JP6067859B2 (en) |
CN (1) | CN104756613B (en) |
DE (1) | DE102012216926A1 (en) |
WO (1) | WO2014044515A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6084283B2 (en) * | 2013-02-12 | 2017-02-22 | 株式会社メイコー | Component built-in substrate and manufacturing method thereof |
DE102013226549B4 (en) * | 2013-12-19 | 2022-03-31 | Vitesco Technologies Germany Gmbh | Process for manufacturing a printed circuit board |
JP5999122B2 (en) * | 2014-02-20 | 2016-09-28 | 株式会社村田製作所 | Inductor manufacturing method |
DE102016211995A1 (en) | 2016-07-01 | 2018-01-04 | Schweizer Electronic Ag | Method for producing a printed circuit board and printed circuit board |
EP3691421A1 (en) | 2019-01-29 | 2020-08-05 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with embedded filament |
DE102020125140A1 (en) | 2020-09-25 | 2022-03-31 | Jumatech Gmbh | Process for the production of a printed circuit board and a molded part for use in this process |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1174625A (en) * | 1997-08-28 | 1999-03-16 | Kyocera Corp | Wiring board and method for manufacturing it |
DE202005001161U1 (en) * | 2005-01-24 | 2005-03-31 | Juma Leiterplattentechologie M | Circuit board with written wiring, has conductor wires with square or rectangular cross-section, preferably hollow and carrying cooling fluid |
US20090081426A1 (en) * | 2005-10-25 | 2009-03-26 | Masahiko Suzuki | Flexible Laminate Board, Process for Manufacturing of the Board, and Flexible Print Wiring Board |
US20100327044A1 (en) * | 2008-02-25 | 2010-12-30 | Panasonic Corporation | Method for manufacturing electronic component module |
Family Cites Families (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3489877A (en) * | 1966-09-23 | 1970-01-13 | Texas Instruments Inc | Method for forming brazed connections within a multilayer printed circuit board |
US3733685A (en) * | 1968-11-25 | 1973-05-22 | Gen Motors Corp | Method of making a passivated wire bonded semiconductor device |
GB1574699A (en) * | 1975-10-10 | 1980-09-10 | Luc Technologies Ltd | Conductive connections |
FR2344940A1 (en) * | 1976-03-18 | 1977-10-14 | Electro Resistance | PROCESS FOR THE MANUFACTURING OF ELECTRICAL RESISTORS FROM A METAL SHEET FIXED ON AN INSULATING SUPPORT AND RELATED DEVICE |
US4176445A (en) * | 1977-06-03 | 1979-12-04 | Angstrohm Precision, Inc. | Metal foil resistor |
US4325780A (en) * | 1980-09-16 | 1982-04-20 | Schulz Sr Robert M | Method of making a printed circuit board |
JPS58186951A (en) * | 1982-04-24 | 1983-11-01 | Toshiba Corp | Packaging method for electronic part |
US4487828A (en) * | 1983-06-03 | 1984-12-11 | At&T Technologies, Inc. | Method of manufacturing printed circuit boards |
JPS612552A (en) * | 1984-06-15 | 1986-01-08 | 日本写真印刷株式会社 | Filmy coil and manufacture thereof |
JPS6292495A (en) * | 1985-09-13 | 1987-04-27 | アドバンスト インターコネクション テクノロジー インコーポレイテッド | Manufacture of substrate for mutual connection of electronic parts and product manufactured by that method |
KR0122737B1 (en) * | 1987-12-25 | 1997-11-20 | 후루다 모또오 | Position detecting device |
DE69325936T2 (en) * | 1992-04-14 | 2000-03-30 | Hitachi Chemical Co Ltd | Process for the production of printed circuit boards |
JPH0621593A (en) * | 1992-04-14 | 1994-01-28 | Hitachi Chem Co Ltd | Manufacture of printed circuit board |
US5403869A (en) * | 1992-08-17 | 1995-04-04 | Hitachi Chemical Company, Ltd. | Adhesive of epoxy resins, epoxy-modified polybutadiene and photoinitiator |
US5373111A (en) * | 1993-11-19 | 1994-12-13 | Delco Electronics Corporation | Bond pad having a patterned bonding surface |
US5495668A (en) * | 1994-01-13 | 1996-03-05 | The Furukawa Electric Co., Ltd. | Manufacturing method for a supermicro-connector |
US5455390A (en) * | 1994-02-01 | 1995-10-03 | Tessera, Inc. | Microelectronics unit mounting with multiple lead bonding |
JPH08321681A (en) * | 1995-05-26 | 1996-12-03 | Hitachi Chem Co Ltd | Multi-wire wiring board and manufacture thereof |
EP0831528A3 (en) * | 1996-09-10 | 1999-12-22 | Hitachi Chemical Company, Ltd. | Multilayer wiring board for mounting semiconductor device and method of producing the same |
SG76530A1 (en) * | 1997-03-03 | 2000-11-21 | Hitachi Chemical Co Ltd | Circuit boards using heat resistant resin for adhesive layers |
TW366570B (en) * | 1997-03-26 | 1999-08-11 | Matsushita Electric Ind Co Ltd | Semiconductor device and the wiring unit |
TW373197B (en) * | 1997-05-14 | 1999-11-01 | Murata Manufacturing Co | Electronic device having electric wires and the manufacturing method thereof |
JP3192619B2 (en) * | 1997-10-07 | 2001-07-30 | 日本特殊陶業株式会社 | Wiring board and method of manufacturing the same |
US6046910A (en) * | 1998-03-18 | 2000-04-04 | Motorola, Inc. | Microelectronic assembly having slidable contacts and method for manufacturing the assembly |
JP3753218B2 (en) * | 1998-03-23 | 2006-03-08 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
JPH11298143A (en) * | 1998-04-10 | 1999-10-29 | Mitsubishi Gas Chem Co Inc | Manufacture of multilayered printed wiring board |
US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
JP3312246B2 (en) * | 1999-06-18 | 2002-08-05 | 松尾電機株式会社 | Manufacturing method of chip capacitor |
US6426241B1 (en) * | 1999-11-12 | 2002-07-30 | International Business Machines Corporation | Method for forming three-dimensional circuitization and circuits formed |
JP3269815B2 (en) * | 1999-12-13 | 2002-04-02 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
JP4459406B2 (en) * | 2000-07-27 | 2010-04-28 | ソニーケミカル&インフォメーションデバイス株式会社 | Flexible wiring board manufacturing method |
JP2002186136A (en) * | 2000-12-14 | 2002-06-28 | Yazaki Corp | Electrical junction box |
JP3849976B2 (en) * | 2001-01-25 | 2006-11-22 | 松下電器産業株式会社 | COMPOSITE PIEZOELECTRIC, ULTRASONIC PROBE FOR ULTRASONIC DIAGNOSTIC DEVICE, ULTRASONIC DIAGNOSTIC DEVICE, AND METHOD FOR PRODUCING COMPOSITE PIEZOELECTRIC |
ES2701884T3 (en) * | 2002-03-11 | 2019-02-26 | Nitto Denko Corp | Transdermal drug delivery patch system |
US7106167B2 (en) * | 2002-06-28 | 2006-09-12 | Heetronix | Stable high temperature sensor system with tungsten on AlN |
DE10237763B4 (en) * | 2002-08-17 | 2006-01-12 | Schott Ag | Process for the preparation of insoluble cohesive bonds of components made of oxide-dispersed (ODS) metallic materials by welding and components produced by the process |
DE10308928B4 (en) * | 2003-02-28 | 2009-06-18 | Siemens Ag | Method for producing self-supporting contacting structures of a non-insulated component |
US7389570B2 (en) * | 2004-06-28 | 2008-06-24 | Kyocera Corporation | Surface acoustic wave device manufacturing method, surface acoustic wave device, and communications equipment |
JP4610244B2 (en) * | 2004-06-28 | 2011-01-12 | 京セラ株式会社 | Manufacturing method of surface acoustic wave device |
CN1589093A (en) * | 2004-08-13 | 2005-03-02 | 广州金升阳科技有限公司 | Method for improving fine enamelled wire spot welding strengh in spot welding |
DE102005003370A1 (en) | 2005-01-24 | 2006-07-27 | Juma Pcb Gmbh | Method for the continuous laying of a conductor wire on a printed circuit board and apparatus for carrying out the method |
DE202006019817U1 (en) * | 2005-01-24 | 2007-04-12 | Jumatech Gmbh | Method for producing angled printed circuit board structure involves production of level printed circuit board comprising at least one conductor, which is embedded to great extent in printed circuit board |
JP5001542B2 (en) * | 2005-03-17 | 2012-08-15 | 日立電線株式会社 | Electronic device substrate, method for manufacturing the same, and method for manufacturing the electronic device |
TWI275149B (en) * | 2005-05-09 | 2007-03-01 | Phoenix Prec Technology Corp | Surface roughing method for embedded semiconductor chip structure |
DE102005024347B8 (en) * | 2005-05-27 | 2010-07-08 | Infineon Technologies Ag | Electrical component with fused power supply connection |
US7877866B1 (en) * | 2005-10-26 | 2011-02-01 | Second Sight Medical Products, Inc. | Flexible circuit electrode array and method of manufacturing the same |
JP4826248B2 (en) * | 2005-12-19 | 2011-11-30 | Tdk株式会社 | IC built-in substrate manufacturing method |
TWI296910B (en) * | 2005-12-27 | 2008-05-11 | Phoenix Prec Technology Corp | Substrate structure with capacitance component embedded therein and method for fabricating the same |
US7674751B2 (en) * | 2006-01-10 | 2010-03-09 | American Superconductor Corporation | Fabrication of sealed high temperature superconductor wires |
DE102006025162B3 (en) * | 2006-05-30 | 2008-01-31 | Epcos Ag | Flip-chip device and method of manufacture |
JP2008053670A (en) * | 2006-08-25 | 2008-03-06 | Taiyo Yuden Co Ltd | Inductor using dram-type core and manufacturing method therefor |
JP4865453B2 (en) * | 2006-08-30 | 2012-02-01 | 日東電工株式会社 | Wiring circuit board and manufacturing method thereof |
DE102006052706A1 (en) | 2006-11-08 | 2008-05-15 | Jumatech Gmbh | Wire-printed circuit board |
JP4866787B2 (en) * | 2007-05-11 | 2012-02-01 | 日東電工株式会社 | Wiring circuit board and manufacturing method thereof |
AT10247U8 (en) * | 2008-05-30 | 2008-12-15 | Austria Tech & System Tech | METHOD FOR INTEGRATING AT LEAST ONE ELECTRONIC COMPONENT INTO A PCB AND LADDER PLATE |
JP6068175B2 (en) * | 2013-02-12 | 2017-01-25 | 新光電気工業株式会社 | WIRING BOARD, LIGHT EMITTING DEVICE, WIRING BOARD MANUFACTURING METHOD, AND LIGHT EMITTING DEVICE MANUFACTURING METHOD |
-
2012
- 2012-09-20 DE DE102012216926.1A patent/DE102012216926A1/en not_active Ceased
-
2013
- 2013-08-30 JP JP2015532359A patent/JP6067859B2/en active Active
- 2013-08-30 US US14/429,070 patent/US20150237738A1/en not_active Abandoned
- 2013-08-30 EP EP13756878.8A patent/EP2898759B1/en active Active
- 2013-08-30 WO PCT/EP2013/067988 patent/WO2014044515A1/en active Application Filing
- 2013-08-30 CN CN201380049063.XA patent/CN104756613B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1174625A (en) * | 1997-08-28 | 1999-03-16 | Kyocera Corp | Wiring board and method for manufacturing it |
DE202005001161U1 (en) * | 2005-01-24 | 2005-03-31 | Juma Leiterplattentechologie M | Circuit board with written wiring, has conductor wires with square or rectangular cross-section, preferably hollow and carrying cooling fluid |
US20090081426A1 (en) * | 2005-10-25 | 2009-03-26 | Masahiko Suzuki | Flexible Laminate Board, Process for Manufacturing of the Board, and Flexible Print Wiring Board |
US20100327044A1 (en) * | 2008-02-25 | 2010-12-30 | Panasonic Corporation | Method for manufacturing electronic component module |
Also Published As
Publication number | Publication date |
---|---|
JP2015529402A (en) | 2015-10-05 |
US20150237738A1 (en) | 2015-08-20 |
DE102012216926A1 (en) | 2014-03-20 |
EP2898759A1 (en) | 2015-07-29 |
EP2898759B1 (en) | 2019-11-27 |
CN104756613A (en) | 2015-07-01 |
JP6067859B2 (en) | 2017-01-25 |
CN104756613B (en) | 2019-04-02 |
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