WO2014044003A1 - Cmos图像传感器列共享像素单元及像素阵列 - Google Patents

Cmos图像传感器列共享像素单元及像素阵列 Download PDF

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WO2014044003A1
WO2014044003A1 PCT/CN2012/086673 CN2012086673W WO2014044003A1 WO 2014044003 A1 WO2014044003 A1 WO 2014044003A1 CN 2012086673 W CN2012086673 W CN 2012086673W WO 2014044003 A1 WO2014044003 A1 WO 2014044003A1
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pixel
column
image sensor
transistor
pixel array
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PCT/CN2012/086673
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English (en)
French (fr)
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郭同辉
陈杰
刘志碧
旷章曲
唐冕
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北京思比科微电子技术股份有限公司
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Priority to JP2015532273A priority Critical patent/JP2015534271A/ja
Priority to KR1020157004568A priority patent/KR20150063365A/ko
Publication of WO2014044003A1 publication Critical patent/WO2014044003A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Definitions

  • the present invention relates to a CMOS image sensor, and more particularly to a CMOS image sensor column sharing pixel unit and a pixel array.
  • CMOS Complementary Metal Oxide Semiconductor
  • the arrangement of the pixel structure of the CMOS image sensor in the prior art is exemplified by 4T2S (four-transistor two-pixel sharing). Since the pixel structure itself depends on the structural characteristics of the pixel itself, the pixel array generally needs the first layer metal, the second layer metal. And the third layer of metal as a device interconnection line, between the adjacent rows of pixels or between adjacent columns of pixels, respectively, need to have multiple rows or columns of the first layer of metal, the second layer of metal or the third layer of metal wiring; and floating active area
  • the metal capacitor connected to the gate of the source follower transistor is parasitic.
  • the small-area pixel sensor has a small photosensitive area and low sensitivity, the information transmitted under the dark light is not clear enough.
  • the dielectric height on the surface of the photodiode Si is high, and the metal connection blocks part of the light from entering the photodiode.
  • the metal connection of the floating active region and the source follower transistor gate is closer to the power metal connection, and the floating active region capacitance is parasitic, resulting in a small amplitude (conversion gain) of signal electrons converted into a signal voltage. .
  • the CMOS image sensor column of the present invention shares a pixel unit, and the single pixel includes a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, a floating active region, and a metal connection.
  • Two column pixels are used as a group of pixel cells, and two pixels share a selection transistor, a source follower transistor, a reset transistor, and a floating active region in a column.
  • the CMOS image sensor pixel array of the present invention comprises a plurality of sets of the above-mentioned CMOS image sensor column shared pixel units, and the plurality of sets of pixel units are arranged in a vertical and horizontal direction to form a two-dimensional pixel array, and the two-dimensional pixel array uses two layers of metal Wire the connection, including the 0th metal wire and the 1st metal wire.
  • the CMOS image sensor column of the present invention shares a pixel unit and a CMOS image sensor pixel array. Since two columns of pixels are used as a group of pixel units, two pixels share a selection transistor and a source in a column. Following the transistor, the reset transistor, and the floating active region, the plurality of sets of pixel units are arranged in a vertical and horizontal direction to form a two-dimensional pixel array, wherein the two-dimensional pixel array is connected by using two metal wires, and the metal wiring is only used.
  • the 0-layer metal connection and the 1st-layer metal connection are used as the control lines of the device to realize the image information function, and the second layer or higher-level metal connection is not used as the device control line, which can reduce the dielectric height on the surface of the photodiode Si. So that more light is incident on the photodiode. Therefore, the CMOS image sensor column sharing pixel unit structure of the present invention can improve the light efficiency and conversion gain of the small-area pixel sensor, thereby improving the sensitivity, so that the image quality of the small-area pixel image sensor can be effectively improved.
  • FIG. 1 is a schematic diagram of a 4T2S structure circuit composed of two pixels in a specific embodiment 1 of a CMOS image sensor column shared pixel unit of the present invention
  • FIG. 2 is a schematic diagram of a 4T2S structure layout composed of two pixels in a specific embodiment 1 of a CMOS image sensor column shared pixel unit of the present invention
  • FIG. 3 is a schematic diagram of a 4 x 4 pixel array circuit in a specific embodiment 1 of a CMOS image sensor column shared pixel unit of the present invention
  • FIG. 4 is a schematic diagram of a 4 x 4 pixel array layout in a specific embodiment 1 of a CMOS image sensor column shared pixel unit of the present invention
  • FIG. 5 is a schematic diagram of a 4T2S structure circuit composed of two pixels in a second embodiment of the CMOS image sensor column shared pixel unit of the present invention
  • FIG. 6 is a schematic diagram of a 4 x 4 pixel array circuit in a second embodiment of the CMOS image sensor column shared pixel unit of the present invention.
  • the CMOS image sensor column of the present invention shares a pixel unit, and a preferred embodiment thereof is shown in FIGS. 1 to 4:
  • a single pixel includes a photodiode, a charge transfer transistor, a select transistor, a source follower transistor, a reset transistor, a floating active region, and a metal connection.
  • Two column pixels are used as a group of pixel cells, and two pixels share a selection transistor, a source follower transistor, a reset transistor, and a floating active region in a column.
  • the floating active region and the source follower transistor gate are connected in the column direction by a first layer of metal wiring, which is away from the power metal wiring.
  • the CMOS image sensor pixel array of the present invention comprises a plurality of sets of the above-mentioned CMOS image sensor column shared pixel units, and the plurality of sets of pixel units are arranged in a vertical and horizontal direction to form a two-dimensional pixel array, and the two-dimensional pixel array uses two layers of metal Wire the connection, including the 0th metal wire and the 1st metal wire.
  • a power line and a column signal output line between pixels in the same column in the column direction are connected by using a first layer metal connection;
  • the transistor device control lines between the pixels in the row direction are connected using a 0th metal wiring.
  • the invention solves the problem that the sensitivity of the small image pixel of the existing image sensor is low, and the metal connection uses only the 0th metal wire and the 1st metal wire as the control line of the device to realize the function of collecting image information, and does not use the second layer.
  • the higher-level metal wiring acts as a device control line that reduces the dielectric height on the surface of the photodiode Si, allowing more light to be incident on the photodiode.
  • the floating active area connection source follows the metal connection of the transistor gate away from the power metal connection, which can reduce the parasitic capacitance of the floating active area, thereby increasing the amplitude of the signal electrons converted into signal voltage.
  • the CMOS image sensor column shared pixel unit and the CMOS image sensor pixel array structure of the present invention can improve the light efficiency and conversion gain of the small-area pixel sensor, thereby improving the sensitivity, so that the image quality of the small-area pixel image sensor can be effectively improved.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the shared pixel unit of the CMOS image sensor column adopts a 4T2S structure, including two pixels, and the two pixels are arranged in the same structure above the same column.
  • 101 and 201 are two pixel photodiodes, 102 and 202 respectively two pixel charge transfer transistors; 103 is a reset transistor, 104 is a source follower transistor, 105 is a select transistor, and 106 is a column signal output line. , wherein two pixels share a reset transistor 103, a source follower transistor 104, a select transistor 105, and a column signal output line 106; FD (Floating Diffusion) is a floating active area with two pixels sharing the FD.
  • FD Floating Diffusion
  • the control line SX of the transistor is connected to the gate of the selection transistor 105, the control line TX1 is connected to the gate of the transfer transistor 102, the control line RX is connected to the gate of the reset transistor 103, and the control line TX2 is connected to the gate of the transfer transistor 202; the column signal output line
  • the source 106 is connected to the source of the transistor 104; Vdd is the supply voltage, and the drain of the reset transistor 103 and the drain of the selection transistor 105 are connected.
  • FIG. 2 it is a layout diagram corresponding to the schematic diagram of the circuit shown in FIG.
  • the transistor device control lines SX, TX1, RX, and TX2 use the 0th metal wiring
  • the power control line Vdd and the column signal output line 106 use the first layer metal wiring
  • the 0th layer metal device control line SX, TX1, RX, and TX2 are in contact with the gate polysilicon of 105, 102, 103, and 202, respectively, through the contact hole 0, and the drains of the first metal power supply control lines Vdd and 105 and the drain of 103 pass through the contact hole 1
  • the source of the first metal column signal output lines 106 and 104 are in contact with each other through the contact hole 1; the first layer of metal wiring is connected between the floating active regions FD and 104 through the contact hole 1 through the contact hole 1 contact.
  • the two pixels described above are recorded as a group of cells.
  • a plurality of groups of pixel units are arranged in a vertical and horizontal direction to form a two-dimensional pixel array, and a 4 ⁇ 4 pixel array is taken as an example for illustration.
  • the high-sensitivity small-area CMOS image sensor column shared pixel unit structure and the two-dimensional pixel array structure of the present invention include, but are not limited to, a 4 ⁇ 4 pixel array, and can be adapted to other multi-size pixel arrays.
  • FIG. 3 is a schematic diagram of a 4 ⁇ 4 pixel array circuit
  • FIG. 3 is a schematic diagram of a layout corresponding to a schematic diagram of a pixel array circuit shown in FIG.
  • 111, 121, 131, and 141 are photodiodes of the pixels of the first row, and 211, 221, 231, and 241 are photodiodes of the pixels of the second row, 311, 321, 331, 341
  • 411, 421, 431, 441 are the photodiodes of the fourth row of pixels; the pixel device control line SX1 is connected to the gate polysilicon of the peer selection transistors 115, 125, 135, 145, and the pixel device is controlled.
  • Line TX1 is coupled to gate polysilicon of peer charge transfer transistors 112, 122, 132, 142, pixel device control line RX1 is coupled to gate polysilicon of peer reset transistors 113, 123, 133, 143, pixel device control line TX2 and peer charge
  • the gate polysilicon of the transfer transistors 212, 222, 232, 242 are connected, and each group of pixel units FD are respectively connected to the gate polysilicon of the corresponding source follower transistors 114, 124, 134, 144; the pixel device control line SX3 and the peer selection transistor 315,
  • the gate polysilicon of 325, 335, and 345 is connected, and the pixel device control line TX3 is connected to the gate polysilicon of the same charge transfer transistors 312, 322, 332, and 342, and the pixel device control line RX3 and the peer are complex.
  • the gate polysilicon of the transistors 313, 323, 333, 343 is connected, and the pixel device control line TX4 is connected to the gate polysilicon of the peer charge transfer transistors 412, 422, 432, 442, and each group of pixel units FD and the corresponding source follower transistor 314,
  • the gate polysilicon of 324, 334, and 344 is connected; 16, 26, 36, and 46 are the column signal output lines of the pixels of the first column, the second column, the third column, and the fourth column, respectively, and the sources of the corresponding column pixels are followed.
  • the source of the transistor is connected; Vdd is the metal connection of the power supply.
  • the peer pixel device control lines SX1, TX1, RX1, TX2, SX3, TX3, RX3, TX4 use the 0th metal wiring; the same column signal output lines 16, 26, 36, 46 use the first layer metal connection.
  • the power line Vdd uses the first layer of metal wiring, and the FD of each group of pixel units and the gate line of the corresponding source follower transistor use the first layer of metal wiring.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the CMOS image sensor column shared pixel unit adopts a 4T2S structure, and includes two pixels, and the two pixels are arranged in the same structure above the same column.
  • 101' and 201' are two pixel photodiodes, 102' and 202' respectively two pixel charge transfer transistors;
  • 103' is a reset transistor,
  • 104' is a source follower transistor,
  • 105' is a select transistor, and
  • 106' is Column signal output line, wherein two pixels share reset transistor 103', source follower transistor 104', select transistor 105' and column signal output line 106';
  • FD' Floating Diffusion
  • the transistor control line SX' is connected to the gate of the selection transistor 105', the control line TX1' is connected to the gate of the transfer transistor 102', the control line RX' is connected to the gate of the reset transistor 103', and the control line TX2' is connected to the transfer transistor 202'.
  • the gate; column signal output line 106' is coupled to the source of the source follower transistor 104'; Vdd' is the supply voltage, connected to the drain of the reset transistor 103' and the drain of the select transistor 105'.
  • the two pixels described above are recorded as a group of cells.
  • a plurality of groups of pixel units are arranged in a vertical and horizontal direction to form a two-dimensional pixel array, and a 4 ⁇ 4 pixel array is taken as an example for illustration.
  • the high-sensitivity small-area CMOS image sensor column shared pixel unit structure and the two-dimensional pixel array structure of the present invention include, but are not limited to, a 4 ⁇ 4 pixel array, and can be adapted to other multi-size pixel arrays.
  • 111', 121', 131', 141' are photodiodes of pixels of the first row
  • 211', 221', 231', 241' are photodiodes of pixels of the second row
  • 311' 321', 331', 341' are photodiodes of the third row of pixels
  • 411', 421', 431', 441' are photodiodes of the fourth row of pixels
  • the pixel device control line SX1' and the peer selection transistor 115' The gate polysilicon of 125', 135', 145' is connected
  • the pixel device control line TX1' is connected to the gate polysilicon of the peer charge transfer transistors 112', 122', 132', 142'
  • the pixel device control line RX1' is The gate polysilicon of the peer reset transistors 113', 123', 133', 143' are connected, and the pixel device control line TX2' is connected
  • the metal connection is only The use of the 0th metal wire and the 1st metal wire as the control line of the device realizes the function of acquiring image information, without using the 2nd or higher layer metal wire as the device control line, reducing the number of layers used in the metal wire , effectively reducing the height of the medium on the surface of the photodiode Si, so that more light is incident on the photodiode, improving the light efficiency.
  • the use of the 0th metal wire and the first metal wire is not the only embodiment of the present invention, and the first metal wire and the second metal wire or other metal layer may be used.
  • the wire is used to realize the pixel structure advantages of the present invention.
  • the use of the Nth layer and the N+1th metal wiring can be determined according to the specific pixel design, and the effect of reducing the number of layers used in the metal connection, reducing the height of the medium, and improving the light efficiency can be achieved.
  • the core design method of the pixel structure of the metal connection level is the same as that of the first embodiment and the second embodiment, and details are not described herein.
  • the floating active area connection source of the shared pixel unit of the CMOS image sensor column of the present invention follows the metal connection of the transistor gate away from the power metal connection, thereby reducing the parasitic capacitance of the floating active area, thereby improving the signal electronic conversion to The amplitude of the signal voltage.
  • the CMOS image sensor column shared pixel unit and the CMOS image sensor pixel array structure of the present invention can improve the light efficiency and conversion gain of the small-area pixel sensor, thereby improving the sensitivity, so that the image quality of the small-area pixel image sensor can be effectively improved.

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Abstract

一种CMOS图像传感器列共享像素单元及像素阵列，由两个列像素作为一组像素单元，两个像素在列内共享选择晶体管、源跟随晶体管、复位晶体管和漂浮有源区，多组像素单元在垂直和水平方向上排列成为二维像素阵列，所述二维像素阵列中使用两层金属连线进行连接，金属连线仅使用第0层金属连线和第1层金属连线作为器件的控制线而实现采集图像信息功能，不使用第2层或更高层金属连线作为器件控制线，可降低光电二极管Si表面上的介质高度，使得更多的光入射到光电二极管，能够提高小面积像素传感器的用光效率和转换增益，从而提高灵敏度，可以有效提高小面积像素图像传感器的图像品质。

Description

CMOS图像传感器列共享像素单元及像素阵列
本申请要求于2012年9月24日提交中国专利局、申请号为201210359361.6、发明名称为“CMOS图像传感器列共享像素单元及像素阵列”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及一种CMOS图像传感器，尤其涉及一种CMOS图像传感器列共享像素单元及像素阵列。
发明背景
目前，图像传感器已经广泛应用于数码相机、移动手机、医疗器械、汽车和其他应用场合。特别是CMOS（互补型金属氧化物半导体）图像传感器的快速发展，使人们对低功耗小尺寸高分辨率图像传感器有了更高的要求。
现有技术中的CMOS图像传感器像素结构的排布方式以4T2S（四晶体管两个像素共享）为例，由于依赖于像素本身的结构特征，其像素阵列一般需要第1层金属，第2层金属和第3层金属作为器件互连线，相邻行像素间或相邻列像素间分别需要多行或多列第1层金属、第2层金属或第3层金属连线；并且漂浮有源区与源跟随晶体管栅极相连接的金属电容寄生较大。
上述现有技术至少包含以下缺点：
由于小面积像素传感器的感光面积小，灵敏度低，使得传递暗光下的信息不够清晰。尤其在使用第1层金属，第2层金属和第3层金属作为器件互连线时，光电二极管Si（硅）表面上的介质高度较高，金属连线阻挡了部分光线入射到光电二极管中；并且，漂浮有源区与源跟随晶体管栅极相连接的金属连线离电源金属连线较近，漂浮有源区电容寄生大，导致信号电子转换成信号电压的幅度（转换增益）不大。
发明内容
本发明的目的是提供一种灵敏度高的小面积CMOS图像传感器列共享像素单元及像素阵列。
本发明的目的是通过以下技术方案实现的：
本发明的CMOS图像传感器列共享像素单元，单个像素包括光电二极管、电荷传输晶体管、选择晶体管、源跟随晶体管、复位晶体管、漂浮有源区及金属连线， 由两个列像素作为一组像素单元，两个像素在列内共享选择晶体管、源跟随晶体管、复位晶体管和漂浮有源区。
本发明的CMOS图像传感器像素阵列，包括多组上述的CMOS图像传感器列共享像素单元，多组像素单元在垂直和水平方向上排列成为二维像素阵列，所述二维像素阵列中使用两层金属连线进行连接，包括第0层金属连线和第1层金属连线。
由上述本发明提供的技术方案可知，本发明的CMOS图像传感器列共享像素单元及CMOS图像传感器像素阵列，由于由两个列像素作为一组像素单元，两个像素在列内共享选择晶体管、源跟随晶体管、复位晶体管和漂浮有源区，多组像素单元在垂直和水平方向上排列成为二维像素阵列，所述二维像素阵列中使用两层金属连线进行连接，金属连线仅使用第0层金属连线和第1层金属连线作为器件的控制线而实现采集图像信息功能，不使用第2层或更高层金属连线作为器件控制线，可降低光电二极管Si表面上的介质高度，使得更多的光入射到光电二极管。因此，本发明的CMOS图像传感器列共享像素单元结构能够提高小面积像素传感器的用光效率和转换增益，从而提高灵敏度，所以可以有效提高小面积像素图像传感器的图像品质。
附图简要说明
图1是本发明的CMOS图像传感器列共享像素单元的具体实施例一中两个像素组成的4T2S结构电路示意图；
图2是本发明的CMOS图像传感器列共享像素单元的具体实施例一中两个像素组成的4T2S结构版图示意图；
图3是本发明的CMOS图像传感器列共享像素单元的具体实施例一中4 x 4像素阵列电路示意图；
图4是本发明的CMOS图像传感器列共享像素单元的具体实施例一中4 x 4像素阵列版图示意图；
图5是本发明的CMOS图像传感器列共享像素单元的具体实施例二中两个像素组成的4T2S结构电路示意图；
图6是本发明的CMOS图像传感器列共享像素单元的具体实施例二中4 x 4像素阵列电路示意图。
实施本发明的方式
下面结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明的保护范围。
本发明的CMOS图像传感器列共享像素单元，其较佳的具体实施方式如图1至图4所示：
单个像素包括光电二极管、电荷传输晶体管、选择晶体管、源跟随晶体管、复位晶体管、漂浮有源区及金属连线， 由两个列像素作为一组像素单元，两个像素在列内共享选择晶体管、源跟随晶体管、复位晶体管和漂浮有源区。
所述漂浮有源区与源跟随晶体管栅极在列方向上用第1层金属连线连接，此金属连线远离电源金属连线。
本发明的CMOS图像传感器像素阵列，包括多组上述的CMOS图像传感器列共享像素单元，多组像素单元在垂直和水平方向上排列成为二维像素阵列，所述二维像素阵列中使用两层金属连线进行连接，包括第0层金属连线和第1层金属连线。
所述二维像素阵列中，在列方向上同列像素间的电源线和列信号输出线使用第1层金属连线连接；
所述二维像素阵列中，在行方向上同行像素间的晶体管器件控制线使用第0层金属连线连接。
本发明解决现有图像传感器小面积像素灵敏度低的问题，金属连线仅使用第0层金属连线和第1层金属连线作为器件的控制线而实现采集图像信息功能，不使用第2层或更高层金属连线作为器件控制线，可降低光电二极管Si表面上的介质高度，使得更多的光入射到光电二极管。漂浮有源区连接源跟随晶体管栅极的金属连线远离电源金属连线，可降低漂浮有源区的寄生电容，从而提高了信号电子转换为信号电压的幅度。因此，本发明的CMOS图像传感器列共享像素单元及CMOS图像传感器像素阵列结构能够提高小面积像素传感器的用光效率和转换增益，从而提高灵敏度，所以可以有效提高小面积像素图像传感器的图像品质。
实施例一：
如图1所示电路示意图，CMOS图像传感器列共享像素单元采用4T2S结构，包括两个像素，此两个像素在同列以上下结构方式排列。
图1中：101和201分别为两个像素的光电二极管，102和202分别两个像素的电荷传输晶体管；103为复位晶体管，104为源跟随晶体管，105为选择晶体管，106为列信号输出线，其中两个像素共享复位晶体管103、源跟随晶体管104、选择晶体管105和列信号输出线106；FD（Floating Diffusion）为漂浮有源区，两个像素共享FD。晶体管的控制线SX连接选择晶体管105的栅极，控制线TX1连接传输晶体管102的栅极，控制线RX连接复位晶体管103的栅极，控制线TX2连接传输晶体管202的栅极；列信号输出线106连接源跟随晶体管104的源极；Vdd为电源电压，连接复位晶体管103的漏极和选择晶体管105的漏极。
如图2所示，为图1所示电路示意图对应的版图示意图。
图2中：晶体管器件控制线SX、TX1、RX、TX2使用第0层金属连线，电源控制线Vdd和列信号输出线106使用第1层金属连线；第0层金属器件控制线SX、TX1、RX和TX2分别与105、102、103和202的栅极多晶硅通过接触孔0相互接触，第1层金属电源控制线Vdd与105的漏极和103的漏极之间通过接触孔1相互接触，第1层金属列信号输出线106与104的源极之间通过接触孔1相互接触；漂浮有源区FD与104的栅极多晶硅之间使用第1层金属连线通过接触孔1相互接触。
上面所述的两个像素记为一组单元，本实施例中将多组像素单元在垂直和水平方向上排列成为二维像素阵列，并以4x4像素阵列为例进行示意。本发明的高灵敏度小面积CMOS图像传感器列共享像素单元结构及二维像素阵列结构包括但并不局限于4x4像素阵列，而可适应其他多种尺寸像素阵列。
如图3所示，为4 X 4像素阵列电路示意图；图3所示像素阵列电路示意图所对应的版图示意图如图4所示。
图3和图4所示像素阵列中，111、121、131、141为第1行像素的光电二极管，211、221、231、241为第2行像素的光电二极管，311、321、331、341为第3行像素的光电二极管，411、421、431、441为第4行像素的光电二极管；像素器件控制线SX1与同行选择晶体管115、125、135、145的栅极多晶硅相连，像素器件控制线TX1与同行电荷转移晶体管112、122、132、142的栅极多晶硅相连，像素器件控制线RX1与同行复位晶体管113、123、133、143的栅极多晶硅相连，像素器件控制线TX2与同行电荷转移晶体管212、222、232、242的栅极多晶硅相连，各组像素单元FD分别与相应源跟随晶体管114、124、134、144的栅极多晶硅相连；像素器件控制线SX3与同行选择晶体管315、325、335、345的栅极多晶硅相连，像素器件控制线TX3与同行电荷转移晶体管312、322、332、342的栅极多晶硅相连，像素器件控制线RX3与同行复位晶体管313、323、333、343的栅极多晶硅相连，像素器件控制线TX4与同行电荷转移晶体管412、422、432、442的栅极多晶硅相连，各组像素单元FD分别与相应源跟随晶体管314、324、334、344的栅极多晶硅相连；16、26、36、46分别为第1列、第2列、第3列、第4列像素的列信号输出线，分别与相应列像素的源跟随晶体管的源极相连；Vdd为电源金属连线。
上述像素阵列中，同行像素器件控制线SX1、TX1、RX1、TX2、SX3、TX3、RX3、TX4使用第0层金属连线；同列信号输出线16、26、36、46使用第1层金属连线，电源线Vdd使用第1层金属连线，各组像素单元的FD与相应源跟随晶体管的栅极连接线使用第1层金属连线。
实施例二：
实现本发明实施方式另一实施例如图5所示电路示意图，CMOS图像传感器列共享像素单元采用4T2S结构，包括两个像素，此两个像素在同列以上下结构方式排列。101’和201’分别为两个像素的光电二极管，102’和202’分别两个像素的电荷传输晶体管；103’为复位晶体管，104’为源跟随晶体管，105’为选择晶体管，106’为列信号输出线，其中两个像素共享复位晶体管103’、源跟随晶体管104’、选择晶体管105’和列信号输出线106’；FD’（Floating Diffusion）为漂浮有源区，两个像素共享FD’。晶体管控制线SX’连接选择晶体管105’的栅极，控制线TX1’连接传输晶体管102’的栅极，控制线RX’连接复位晶体管103’的栅极，控制线TX2’连接传输晶体管202’的栅极；列信号输出线106’连接源跟随晶体管104’的源极；Vdd’为电源电压，连接复位晶体管103’的漏极和选择晶体管105’的漏极。
上面所述的两个像素记为一组单元，本实施例中将多组像素单元在垂直和水平方向上排列成为二维像素阵列，并以4x4像素阵列为例进行示意。本发明的高灵敏度小面积CMOS图像传感器列共享像素单元结构及二维像素阵列结构包括但并不局限于4x4像素阵列，而可适应其他多种尺寸像素阵列。
图6所示像素阵列中，111’、121’、131’、141’为第1行像素的光电二极管，211’、221’、231’、241’为第2行像素的光电二极管，311’、321’、331’、341’为第3行像素的光电二极管，411’、421’、431’、441’为第4行像素的光电二极管；像素器件控制线SX1’与同行选择晶体管115’、125’、135’、145’的栅极多晶硅相连，像素器件控制线TX1’与同行电荷转移晶体管112’、122’、132’、142’的栅极多晶硅相连，像素器件控制线RX1’与同行复位晶体管113’、123’、133’、143’的栅极多晶硅相连，像素器件控制线TX2’与同行电荷转移晶体管212’、222’、232’、242’的栅极多晶硅相连，各组像素单元FD’分别与相应源跟随晶体管114’、124’、134’、144’的栅极多晶硅相连；像素器件控制线SX3’与同行选择晶体管315’、325’、335’、345’的栅极多晶硅相连，像素器件控制线TX3’与同行电荷转移晶体管312’、322’、332’、342’的栅极多晶硅相连，像素器件控制线RX3’与同行复位晶体管313’、323’、333’、343’的栅极多晶硅相连，像素器件控制线TX4’与同行电荷转移晶体管412’、422’、432’、442’的栅极多晶硅相连，各组像素单元FD’分别与相应源跟随晶体管314’、324’、334’、344’的栅极多晶硅相连；16’、26’、36’、46’分别为第1列、第2列、第3列、第4列像素的列信号输出线，分别与相应列像素的源跟随晶体管的源极相连；Vdd’为电源金属连线。
本发明两个实施例的CMOS图像传感器列共享像素单元及CMOS图像传感器像素阵列中，由于采用了上下结构方式排列的像素结构，并改进像素结构内晶体管及漂浮节点的连接方式，金属连线仅使用第0层金属连线和第1层金属连线作为器件的控制线而实现采集图像信息功能，没有使用第2层或更高层金属连线作为器件控制线，减少了金属连线使用层数，有效降低了光电二极管Si表面上的介质高度，使得更多的光入射到光电二极管，提高用光效率。
需要特别说明的是，使用第0层金属连线和第1层金属连线并不是实现本发明唯一实施方式，也可使用第1层金属连线和第2层金属连线或其它层金属连线来实现本发明像素结构优势。使用第N层及第N+1层金属连线可根据具体像素设计情况而定，均可实现本发明提出的减少金属连线使用层数，降低介质高度，提高用光效率的效果。由于改变金属连线层级的像素结构其核心设计方法与上述实施例一及实施例二雷同，在此不做赘述。
此外，本发明的CMOS图像传感器列共享像素单元的漂浮有源区连接源跟随晶体管栅极的金属连线远离电源金属连线，降低了漂浮有源区的寄生电容，从而提高了信号电子转换为信号电压的幅度。
因此，本发明的CMOS图像传感器列共享像素单元及CMOS图像传感器像素阵列结构能够提高小面积像素传感器的用光效率和转换增益，从而提高灵敏度，所以可以有效提高小面积像素图像传感器的图像品质。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明披露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求书的保护范围为准。

Claims (4)

  1. 一种CMOS图像传感器列共享像素单元，单个像素包括光电二极管、电荷传输晶体管、选择晶体管、源跟随晶体管、复位晶体管、漂浮有源区及金属连线，其特征在于：
    由两个列像素作为一组像素单元，两个像素在列内共享选择晶体管、源跟随晶体管、复位晶体管和漂浮有源区。
  2. 根据权利要求1所述的CMOS图像传感器列共享像素单元，其特征在于，所述漂浮有源区与源跟随晶体管栅极在列方向上用第1层金属连线连接，此金属连线远离电源金属连线。
  3. 一种CMOS图像传感器像素阵列，其特征在于，包括多组权利要求1或2所述的CMOS图像传感器列共享像素单元，多组像素单元在垂直和水平方向上排列成为二维像素阵列，所述二维像素阵列中使用两层金属连线进行连接，包括第0层金属连线和第1层金属连线。
  4. 根据权利要求3所述的CMOS图像传感器像素阵列，其特征在于：
    所述二维像素阵列中，在列方向上同列像素间的电源线和列信号输出线使用第1层金属连线连接；
    所述二维像素阵列中，在行方向上同行像素间的晶体管器件控制线使用第0层金属连线连接。
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