WO2014035021A1 - Non-polar substrate having hetero-structure, method for manufacturing the same, and nitride-based light emitting device using the same - Google Patents

Non-polar substrate having hetero-structure, method for manufacturing the same, and nitride-based light emitting device using the same Download PDF

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WO2014035021A1
WO2014035021A1 PCT/KR2013/001068 KR2013001068W WO2014035021A1 WO 2014035021 A1 WO2014035021 A1 WO 2014035021A1 KR 2013001068 W KR2013001068 W KR 2013001068W WO 2014035021 A1 WO2014035021 A1 WO 2014035021A1
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nitride
layer
semiconductor layer
nitride semiconductor
mask layer
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PCT/KR2013/001068
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French (fr)
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Sukkoo Jung
Kyuhyun Bang
Younghak Chang
Hyunggu Kim
Jina JEON
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Lg Electronics Inc.
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    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • the present invention relates to a semiconductor substrate, and more particularly, to a non-polar hetero substrate, a method for manufacturing the same, and a nitride-based light emitting device using the non-polar hetero substrate .
  • Gallium nitride used as a material for semiconductor devices such as blue light emitting diodes, has a Wurtzite crystal structure, and is mostly grown into a thin film in a c-surface crystal direction. The reason is that crystal growth in the c-surface crystal direction facilitates horizontal growth and high-quality thin films with few defects such as dislocation can be obtained.
  • the present invention is directed to a non-polar hetero substrate, a method for manufacturing the same, and a nitride-based light emitting device using the non-polar hetero substrate that substantially obviate one or more problems due to limitations and disadvantages of the related art.
  • An object, of the present invention is to provide a non-polar hetero substrate that may minimize the formation of crystal defects generated during hetero thin film growth.
  • Another object of the present invention is to provide a method for manufacturing the non-polar hetero substrate .
  • Another object of the present invention is to provide a nitride-based light emitting device using the non- polar hetero substrate.
  • a non-polar hetero substrate includes an r-surface sapphire substrate, a nucleation layer disposed on the r-surface sapphire substrate and including an a-surface or m-surface nitride-based semiconductor, a first nitride semiconductor layer .
  • the nucleation layer having a first defect density, and including a plurality of pits having inclined surfaces at an upper surface thereof, a porous mask layer disposed at least on the pits of the first nitride semiconductor layer, and a second nitride semiconductor layer disposed on the porous mask layer and having a second defect density that is lower than the first defect density.
  • a method for manufacturing a non-polar hetero substrate includes forming a nucleation layer on a first surface of an r-surface sapphire substrate using an a- or m-surface nitride-based semiconductor, forming a first nitride semiconductor layer including a plurality of pits having inclined surfaces on the nucleation layer, forming a porous mask layer blocking at least a portion of a crystal defect on the first nitride semiconductor layer, and forming a second nitride semiconductor layer on the porous mask layer.
  • a nitride-based light emitting device includes a non-polar hetero substrate including: an r- surface sapphire . substrate ; a first nitride semiconductor layer disposed on the r-surface sapphire substrate, having a first defect density, including an a-surface or m-surface nitride-based semiconductor, and including a plurality of pits having inclined surfaces at an upper surface thereof; a porous mask layer disposed at least on the pits of the first nitride semiconductor layer; and a second nitride semiconductor layer disposed on the porous mask layer and having a second defect density that is lower than the first defect density, a first conductive semiconductor layer disposed on the non-polar hetero substrate and including a nitride semiconductor, ' an active layer disposed on the first conductive semiconductor layer, a second conductive semiconductor layer disposed on the active layer and including a nitride semiconductor, a first electrode electrically connected to the first conductive semiconductor
  • dislocations having a first defect density are propagated upward along the first nitride semiconductor disposed on the nucleation layer.
  • the dislocations may be partially blocked effectively by the porous mask layer.
  • a propagation direction of dislocations that are propagated without being blocked by the porous mask layer may be diverted. Thus, some dislocations meet and combine with each other, and some dislocations proceed in a diagonal direction according to the formation of the second nitride semiconductor layer and then disappear.
  • the dislocations cannot be propagated to a growth surface of the second nitride semiconductor layer.
  • defects may be effectively reduced by the porous mask layer and by causing combination or disappearance of crystal defects by the pits having inclined surfaces.
  • FIG. 1 is a flowchart illustrating a process of manufacturing a non-polar hetero substrate, according to an embodiment
  • FIG. 2 is a cross-sectional view of a structure in which a nucleation layer is formed on a substrate
  • FIG. 3 is a cross-sectional view of a structure in which a first nitride semiconductor layer having pits is formed on the nucleation layer;
  • FIG. 4 is a micrograph showing a surface profile of the first nitride semiconductor layer having pits
  • FIG. 5 is a cross-sectional view of a structure in which the first nitride semiconductor layer is surface- etched;
  • FIG. 6 is a micrograph showing the profile of the structure in which the first nitride semiconductor layer is surface-etched
  • FIGs. 7 to 10 are micrographs showing surface shapes according to growth conditions
  • FIG. 11 is a cross-sectional view of a structure in which a porous mask layer is formed on the first nitride semiconductor layer;
  • FIGs. 12 and 13 are cross-sectional views illustrating a first example of the formation of a porous mask layer;
  • FIG. 14 is a micrograph showing the first example of the formation of a porous mask layer;
  • FIG. 15 is a cross-sectional view illustrating a second example of the formation of a porous mask layer
  • FIG. 16 is a micrograph showing the second example of the formation of a porous mask layer ;
  • FIG. 17 is a cross- sectional view illustrating a third example of the formation of a porous mask layer
  • FIG. 18 is a micrograph showing the third example of the formation of a porous mask layer
  • FIG. 19 is a cross-sectional view of a structure in which a second nitride semiconductor layer is formed on the porous mask layer;
  • FIG. 20 is a diagram illustrating propagation of dislocations of a hetero substrate
  • FIG. 21 is a micrograph showing a surface profile of a hetero substrate
  • FIG. 22 is a cross-sectional view illustrating a light emitting diode manufactured using a non-polar hetero substrate, according to an embodiment.
  • FIG. 23 is a cross-sectional view illustrating a light emitting diode manufactured using a non-polar hetero substrate, according to another embodiment. [Best Mode]
  • Non-polar nitride-based semiconductor means a crystal material in which a polarization phenomenon is not present in a growth direction and may be grown in a direction rotated 90 degrees with respect to the c- surface.
  • the nitride-based semiconductor used herein may include semiconductors of gallium nitride (GaN) , indium gallium nitride (InGaN) , aluminum gallium nitride (AlGaN) , aluminum indium gallium nitride (Al InGaN) , indium nitride (InN) , aluminum nitride (A1N) , and the like.
  • the number of nitrogen layers is the same as that of gallium layers within a plane, based on growth direction, and thus, an internal field in the growth direction is offset, preventing polarization. Accordingly, energy band distortion by piezoelectric polarization of common c-surface gallium nitride may not occur, and problems such as decrease in recombination efficiency of electrons and holes in an active layer may be addressed.
  • non-polar gallium nitride may significantly reduce such thickness limitation, and thus, may be used to form an active layer suitable for high current driving.
  • a method for growing a- or m-surface gallium nitride on an r-surface sapphire substrate has been used.
  • Photoelectric efficiency of a light emitting diode may be largely divided into three types: internal quantum efficiency, light extraction efficiency, and injection efficiency.
  • the internal quantum efficiency indicates what percentage of electrons injected from the outside of an active layer turn into photons by radiative recombination.
  • the light extraction efficiency indicates what percentage of the generated photons is emitted to the outside of a light emitting diode without optical loss by internal defects, and the like.
  • the injection efficiency indicates a drop in voltage by series resistances.
  • a patterned sapphire substrate (PSS) technology for forming an uneven portion on a sapphire substrate so as to extract an increased amount of light toward the top of a light emitting diode and a p-GaN surface roughening technology for reducing the probability of total internal reflection between a p-type gallium nitride layer and an external region by forming an uneven portion with a certain size on a p-type semiconductor surface region disposed at a top of a light emitting diode may be generally used.
  • PSS patterned sapphire substrate
  • Non-polar gallium nitride-based hetero thin film growth has an anisotropic thin film growth property in a planar direction and > in particular, has a priority of growth in the c-surface direction, unlike c-surface gallium nitride having an isotropic growth property in the planar direction.
  • a gallium nitride hetero thin film has a certain thickness or less, a semiconductor layer needs to have pits therein.
  • the density and size of the pits may be adjusted according to thin film growth conditions.
  • nitride-based semiconductor islands are formed on a nucleation layer, and the size of the islands increases as the growth thereof continuously progresses such that adjacent semiconductor islands are combined, thereby forming a nitride-based semiconductor layer having a planar shape.
  • the nitride-based semiconductor layer is continuously grown to a thickness of 1 to 10 ⁇ and the islands are then completely coalesced to form a planar surface .
  • a porous mask layer having a nano-porous structure may be formed on the nitride-based semiconductor layer with pits formed thereat as described above, and thus, the quality of the nitride-based semiconductor layer may be improved and a light extraction surface of a light emitting diode may be easily formed.
  • the porous mask layer having a nano-porous structure may be grown ex-situ, separately from growth of the nitride-based semiconductor. By using the porous mask layer disposed at least on the pits of the nitride-based semiconductor, the quality of the nitride-based semiconductor may be improved and a light extraction surface of a light emitting diode may be easily formed.
  • the growth of a thin film of a non-polar nitride- based semiconductor using a hetero substrate may be performed by growing a nitride-based semiconductor material such as a- or m-surface gallium nitride on an r-surface sapphire substrate.
  • a nitride-based semiconductor material such as a- or m-surface gallium nitride
  • a method for manufacturing a non- polar hetero substrate using the aforementioned process will be described in detail with reference to the accompanying drawings.
  • FIG. 1 is a flowchart illustrating an example of a process of manufacturing a non-polar hetero substrate. The following descriptions with reference to the drawings will be provided together with reference to FIG.l.
  • a nucleation layer 20 is formed on an r-surface sapphire substrate 10 (step S10) .
  • the substrate 10 may be a substrate having a crystal surface that enables growth of a non-polar nitride- based semiconductor, for example, an r-surface ([1-102] surface) sapphire substrate.
  • non-polar substrates may be used.
  • a substrate of a-surface silicon carbide (SiC) , an m-surface SiC, spinel, or the like may be used.
  • the nucleation layer 20 is formed on the r-surface sapphire substrate 10 by using a nitride-based semiconductor such as gallium nitride (GaN) , aluminum nitride (AlN) , or aluminum gallium nitride (AlGaN) , which is grown at a low temperature or a high temperature.
  • a nitride-based semiconductor such as gallium nitride (GaN) , aluminum nitride (AlN) , or aluminum gallium nitride (AlGaN) , which is grown at a low temperature or a high temperature.
  • the nitride-based semiconductor constituting the nucleation layer 20 may form a non-polar or semi -polar semiconductor layer. That is, the nucleation layer 20 may be formed using an a-surface or m-surface nitride-based semiconductor .
  • the nitride-based semiconductor constituting the nucleation layer 20 may be grown in a metal organic chemical vapor deposition (MOCVD) growth system or a hydride vapor phase epitaxy (HVPE) growth system.
  • MOCVD metal organic chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • the nucleation layer 20 may have a thickness of 10 to 2,000 nm.
  • growth conditions of the nucleation layer 20 are as follows: a temperature of 400 to 1,200 ° C , a ratio of a Group V material to a Group III material (V/III) of 500 to 10,000, and a growth pressure of 50 to 200 mbar.
  • the r-surface sapphire substrate 10 may be subjected to an annealing process in an ammonia (NH 3 ) atmosphere.
  • NH 3 ammonia
  • a first nitride semiconductor layer 30 is formed on the nucleation layer 20 using a nitride-based semiconductor (step S20) .
  • growth conditions are as follows: a growth temperature of 900 to 1,200°C, a growth pressure between 50 to 300 mbar, and a V/III ratio of 50 to 5,000.
  • the pit 31 has an inclined surface 32.
  • the upper surface of the first nitride semiconductor layer 30 has both planar surfaces and inclined surfaces.
  • the first nitride semiconductor layer 30 is formed of a semiconductor having the same crystal surface as that of the nucleation layer 20, for example, a nitride-based semiconductor having a crystal surface such as an a- surface or m-surface. A semiconductor layer to be grown thereafter may be grown along such a crystal surface.
  • the surface of the first nitride semiconductor layer 30 at which the pits 31 are formed may be etched (step S21) .
  • the size and width of the pits 31 may be increased by the etching process, and the percentage of inclined crystal surfaces may be increased by the pits 31.
  • FIG. 5 illustrates a resulting structure obtained after the etching process is completed and shows that the inclined surfaces 33 of the pits 31 are steeper than those of the pits 31 (having inclined surfaces 32) illustrated in FIG. 3.
  • the area percentage of the pits 31 by etching may be increased. In some cases, however, subsequent processes may be performed without the etching process. This is because the percentage of the pits 31 may be adjusted by growth conditions. Hereinafter, an example of the etching process will be described. [0078] A micrograph of a surface of the first nitride semiconductor layer 30 having the pits 31 that have been widened by the etching process is shown in FIG. 6.
  • the etching process may be performed inside or outside an MOCVD growth system by dry etching or wet etching.
  • SiH 4 , Cl 2 , BCL 2 , KOH, phosphoric acid, hydrochloric acid, or the like may be used.
  • a propagation direction of crystal defects may be changed by the inclined surfaces 32 and 33. That is, a propagation direction of defects such as threading dislocation may be bent or diverted.
  • the percentage of the pits 31 having the inclined surfaces 32 and 33 i.e., a ratio of inclined surfaces to planar surfaces, may act as one important factor in decreasing defects in the growth of a thin film.
  • the density of the pits 31 may be adjusted by adjusting growth conditions.
  • FIGs . 7 to 10 illustrate surface states of the first nitride semiconductor layer 30 according to growth conditions.
  • FIG. 8 is an enlarged view of FIG. 7
  • FIG. 10 is an enlarged view of FIG. 9.
  • FIGs. 9 and 10 it is confirmed that when the V/III ratio is relatively high (i.e., 500), the density of the pits 3 . 1 is increased.
  • An absolute value of the V/III ratio may vary according to the size and type of a reactor in which a nitride-based semiconductor is grown. However, a tendency of the density of pits generated as the V/III ratio is high or low is the same as described above. That is, as the V/III ratio increases, the density of the pits 31 increases.
  • a porous mask layer 40 having a nano-porous structure is formed on the first nitride semiconductor layer 30 having the pits 31 (step S30) .
  • the porous mask layer 40 may be formed such that unit structures 41 thereof are irregularly disposed on the first nitride semiconductor layer 30 or gaps are formed between the unit structures 41 thereof. That is, the porous mask layer 40 has a discontinuous porous structure. Thus, a portion of the first nitride semiconductor layer 30 is exposed.
  • the porous mask layer 40 is disposed on the pits 31.
  • the porous mask layer 40 may have a thickness of several nanometers to tens of nanometers, for example, a thickness of 1 nm to 10 nm in order to have porosity.
  • gaps or holes between the unit structures 41 of the porous mask layer 40 may have an average size of 10 to 100 nm.
  • the porous mask layer 40 may be formed using at least one of silicon nitride, aluminum nitride, silicon oxide, A1 2 0 3 , Ti0 2 , HfO, ZnO, Ni , Cu, Ag, ITO, Al , silica, and graphene .
  • the porous mask layer 40 may be formed outside a growth system after the formation of the first nitride semiconductor layer 30 having the pits 31. However, the porous mask layer 40 may be directly formed inside a semiconductor thin film growth system according to materials selected.
  • porous mask layer 40 When the porous mask layer 40 is formed outside the growth system, a material thereof is relatively freely selected and it is easy to form a pattern.
  • the porous mask layer 40 may be formed by plasma enhanced chemical vapor deposition (PECVD) or via sputtering.
  • PECVD plasma enhanced chemical vapor deposition
  • the porous mask layer 40 may be formed such that a silicon oxide layer is deposited on the first nitride semiconductor layer 30 after being taken out of a semiconductor growth system and then etched to form a pattern. [0094] The porous mask layer 40 may block crystal defects that are propagated from the nucleation layer 20 and the first nitride semiconductor layer 30.
  • the propagation of crystal defects generated on the sapphire substrate 10 and generated at an initial stage of the growth of a nitride-based semiconductor may be effectively blocked by the porous mask layer 40.
  • the porous mask layer 40 may be formed using various methods. For example, when a dielectric layer having a very small thickness (i.e., 1 to 10 nm) is formed as the porous mask layer 40, the dielectric layer may be formed as a porous thin film that does not entirely cover the first nitride semiconductor layer 30.
  • porous mask layer 40 is formed outside a semiconductor growth system (i.e., ex-situ formation), various other methods may be used.
  • the porous mask layer 40 may be formed by forming a thin film that entirely covers the first nitride semiconductor layer 30 by using one of the above- listed materials including silicon oxide, forming a mask pattern thereon, and performing an etching process using the mask pattern.
  • the porous mask layer 40 may be formed using various other methods.
  • the porous mask layer 40 may be formed in the form of nano-dots by heat treatment, a regular array of unit structures using a nano- imprinting method, nano-sized silica particles, or the like.
  • a dielectric thin film 42 is formed on the first nitride semiconductor layer 30.
  • a pattern mask 43 having openings 43a is formed or positioned on the dielectric thin film 42 and the dielectric thin film 42 is etched using the pattern mask 43, thereby forming the porous mask layer 40.
  • the pattern mask 43 may be formed using a metal, for example, nickel (Ni) or silver (Ag) . That is, a thin metal film of Ni or Ag is deposited on the dielectric thin film 42 and heat-treated, thereby forming nano-dots. Then, the dielectric thin film 42 may be etched using the nano-dots as the pattern mask 43. [00105] In FIG. 14, the shape such as particles indicates the pattern mask 43 formed of Ni or Ag described above, and the remaining portion indicates the dielectric thin film 42.
  • a metal for example, nickel (Ni) or silver (Ag) . That is, a thin metal film of Ni or Ag is deposited on the dielectric thin film 42 and heat-treated, thereby forming nano-dots. Then, the dielectric thin film 42 may be etched using the nano-dots as the pattern mask 43.
  • the shape such as particles indicates the pattern mask 43 formed of Ni or Ag described above, and the remaining portion indicates the dielectric thin film 42.
  • a material such as a resist 44 may be coated on the dielectric thin film 42 and the resist 44 may be imprinted in a desired shape using a mold 45 having certain convex shapes 45a, and thus, a pattern of the resist 44 may be formed.
  • the dielectric thin film 42 may be etched using the resist 44 as a mask so that the convex shapes 45a of the mold 45 are transferred to the dielectric thin film 42, thereby forming the porous mask layer 40.
  • FIG. 16 An image of the porous mask layer 40 formed using the imprinting process is shown in FIG. 16.
  • a pattern of the porous mask layer 40 may be formed using nano-spheres.
  • FIG. 18 shows an image of the silica particles 46 attached to the dielectric thin film 42.
  • the dielectric thin film 42 may be etched using the silica particles 46 as a mask to form the porous mask layer 40.
  • the porous mask layer 40 may also be formed using various other methods, and any method that may be used to form an insertion layer capable of blocking defects, which is the function of the porous mask layer 40, may be used.
  • the growth of the nitride-based semiconductor is continuously performed in the semiconductor growth system, and thus, as illustrated in FIG. 19, a second nitride semiconductor layer 50 is formed on the first nitride semiconductor layer 30 on which the porous mask layer 40 is formed (step S40) .
  • the nitride-based semiconductor is grown through an open region of the nano-porous structure of the porous mask layer 40 and is not grown through a non-open region of the nano-porous structure thereof.
  • air gaps may be formed on a portion of the porous mask layer 40 on which horizontal direction growth is not performed.
  • the air gaps may be used as a light extraction structure in the manufactured light emitting diode.
  • the second nitride semiconductor layer 50 formed by the above-described process may have thin film characteristics with largely reduced crystal defects and high quality.
  • the second nitride semiconductor layer 50 may have a much lower crystal defect density than that of the first nitride semiconductor layer 30.
  • FIG. 20 is a diagram illustrating the propagation of dislocations of a hetero substrate with largely reduced crystal defects in the above-described process.
  • dislocations having a first defect density are propagated upward along the first nitride semiconductor 30 disposed on the nucleation layer 20.
  • the dislocations a may be partially blocked effectively by the porous mask layer 40.
  • a propagation direction of dislocations b and c that are propagated without being blocked by the porous mask layer 40 may be diverted.
  • some dislocations b meet and combine with each other, and some dislocations c proceed in a diagonal direction according to the formation of the second nitride semiconductor layer 50" and then disappear.
  • the dislocations b and c cannot be propagated to a growth surface of the second nitride semiconductor layer 50.
  • defects may be effectively reduced by the porous mask layer 40 and by causing combination or disappearance of crystal defects by the pits 31 having inclined surfaces.
  • dislocations d may be propagated to an upper surface of the hetero substrate manufactured by the above -described process, and thus, a high-quality hetero substrate may be manufactured.
  • a second defect density by the dislocation d may be much lower than the first defect density.
  • FIG. 21 is a micrograph showing a surface profile of the hetero substrate manufactured by the above-described process .
  • Examples of the semiconductor devices include light emitting diodes such as a nitride-based light emitting diode and a laser diode and transistor devices such as an insulated gate bipolar transistor (IGBT) and a high electron mobility transistor (HEMT) .
  • IGBT insulated gate bipolar transistor
  • HEMT high electron mobility transistor
  • a semiconductor structure 60 including an n-type semiconductor layer 61, an active layer 62, and a p-type semiconductor layer 63 is grown on the hetero substrate 10 over which the second nitride semiconductor layer 50 is disposed.
  • a transparent conductive layer 70 may be formed on the semiconductor structure 60, and a p-type electrode 80 may be formed on the transparent conductive layer 70.
  • the n-type semiconductor layer 60 is etched to be exposed and an n-type electrode 90 is then formed on the n-type semiconductor layer 61, thereby completing manufacture of a horizontal -type light-emitting diode.
  • a vertical -type light -emitting diode as illustrated in FIG. 23 may be manufactured.
  • Such a vertical- ype light-emitting diode may be manufactured as follows.
  • a semiconductor structure 60 including an n-type semiconductor layer 61, an active layer 62, and a p-type semiconductor layer 63 is grown on a hetero substrate over which a second nitride semiconductor layer 50 is disposed.
  • a p-type electrode 81 is formed on the p-type semiconductor layer 63, and a support layer 83 is attached to the p-type electrode 81 by a solder layer 82.
  • the support layer 83 may include a metal or a semiconductor.
  • the pits 31 having inclined surfaces are exposed.
  • the shape of the pits 31 and air gaps is transferred onto the n-type semiconductor 61 by etching, and consequently, a light extraction structure 64 to which such a shape is transferred may be formed.
  • the pits 31 and the air gaps may act as a light extraction structure, the optical output of a light emitting diode may be improved.
  • the present invention can provide a non-polar hetero substrate that may minimize the formation of crystal defects generated during hetero thin film growth.

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Abstract

A semiconductor substrate, in particular, a non-polar hetero substrate, a method for manufacturing the same, and a nitride-based light emitting device manufactured using the non-polar hetero substrate are disclosed. The non-polar hetero substrate includes an r-surface sapphire substrate; a nucleation layer disposed on the sapphire substrate and including an a-surface or m-surface nitride-based semiconductor; a first nitride semiconductor layer disposed on the nucleation layer, having a first defect density, and including a plurality of pits having inclined surfaces at an upper surface thereof; a porous mask layer disposed at least on the pits of the first nitride semiconductor layer; and a second nitride semiconductor layer disposed on the porous mask layer and having a second defect density that is lower than the first defect density.

Description

[DESCRIPTION]
[invention Title]
NOM-POLAR SUBSTRATE HAVING HETERO-STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND NITRIDE-BASED LIGHT EMITTING DEVICE USING THE SAME
[Technical Field]
[0001] The present invention relates to a semiconductor substrate, and more particularly, to a non-polar hetero substrate, a method for manufacturing the same, and a nitride-based light emitting device using the non-polar hetero substrate .
[Background Art]
[0002] Gallium nitride, used as a material for semiconductor devices such as blue light emitting diodes, has a Wurtzite crystal structure, and is mostly grown into a thin film in a c-surface crystal direction. The reason is that crystal growth in the c-surface crystal direction facilitates horizontal growth and high-quality thin films with few defects such as dislocation can be obtained.
[0003] In this regard, a crystal structure in which nitrogen layers and gallium layers repeatedly cross each other based on growth direction is present. Accordingly, a strong internal field is present between nitrogen and gallium, thereby causing a polarization phenomenon. [ 0004 ] The formed internal field is divided into two components: spontaneous polarization and piezo-electric field When a layer having different lattice constants such as an InAlGaN layer is inserted, polarization effects increase and thus quantum confined stark effects may occur.
[ 0005 ] For example, in a structure in which an InAlGaN active layer is inserted between p- and n-type GaN layers, such as a blue light emitting diode, deformation between layers is caused by differences in lattice constant. This may cause generation of an internal field and bending of an energy band structure of the active layer.
[ 0006 ] Consequently, wave functions of electrons and holes in the active layer are spatially separated and the size of the energy gap decreases, which may be a main factor of deterioration in recombination efficiency.
[Disclosure]
[Technical Problem]
[ 0007 ] Accordingly, the present invention is directed to a non-polar hetero substrate, a method for manufacturing the same, and a nitride-based light emitting device using the non-polar hetero substrate that substantially obviate one or more problems due to limitations and disadvantages of the related art. [0008] An object, of the present invention is to provide a non-polar hetero substrate that may minimize the formation of crystal defects generated during hetero thin film growth.
[0009] Another object of the present invention is to provide a method for manufacturing the non-polar hetero substrate .
[0010] Another object of the present invention is to provide a nitride-based light emitting device using the non- polar hetero substrate.
[Technical Solution]
[0011] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings .
[0012] To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a non-polar hetero substrate includes an r-surface sapphire substrate, a nucleation layer disposed on the r-surface sapphire substrate and including an a-surface or m-surface nitride-based semiconductor, a first nitride semiconductor layer . disposed on the nucleation layer, having a first defect density, and including a plurality of pits having inclined surfaces at an upper surface thereof, a porous mask layer disposed at least on the pits of the first nitride semiconductor layer, and a second nitride semiconductor layer disposed on the porous mask layer and having a second defect density that is lower than the first defect density.
[0013] In another aspect of the present invention, a method for manufacturing a non-polar hetero substrate includes forming a nucleation layer on a first surface of an r-surface sapphire substrate using an a- or m-surface nitride-based semiconductor, forming a first nitride semiconductor layer including a plurality of pits having inclined surfaces on the nucleation layer, forming a porous mask layer blocking at least a portion of a crystal defect on the first nitride semiconductor layer, and forming a second nitride semiconductor layer on the porous mask layer.
[0014] In another aspect of the present invention, a nitride-based light emitting device includes a non-polar hetero substrate including: an r- surface sapphire . substrate ; a first nitride semiconductor layer disposed on the r-surface sapphire substrate, having a first defect density, including an a-surface or m-surface nitride-based semiconductor, and including a plurality of pits having inclined surfaces at an upper surface thereof; a porous mask layer disposed at least on the pits of the first nitride semiconductor layer; and a second nitride semiconductor layer disposed on the porous mask layer and having a second defect density that is lower than the first defect density, a first conductive semiconductor layer disposed on the non-polar hetero substrate and including a nitride semiconductor,' an active layer disposed on the first conductive semiconductor layer, a second conductive semiconductor layer disposed on the active layer and including a nitride semiconductor, a first electrode electrically connected to the first conductive semiconductor layer, and a second electrode electrically connected to the second conductive semiconductor layer.
[0015] It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed .
[Advantageous Effects!
[0016] In nitride semiconductor, dislocations having a first defect density are propagated upward along the first nitride semiconductor disposed on the nucleation layer. The dislocations may be partially blocked effectively by the porous mask layer. [0017] In addition, a propagation direction of dislocations that are propagated without being blocked by the porous mask layer may be diverted. Thus, some dislocations meet and combine with each other, and some dislocations proceed in a diagonal direction according to the formation of the second nitride semiconductor layer and then disappear.
[0018] That is, the dislocations cannot be propagated to a growth surface of the second nitride semiconductor layer.
[0019] As described above, defects may be effectively reduced by the porous mask layer and by causing combination or disappearance of crystal defects by the pits having inclined surfaces.
[0020] Consequently, very few dislocations may be propagated to an upper surface of the hetero substrate, and thus, a high-quality hetero substrate may be manufactured. A second defect density by the dislocation may be much lower than the first defect density.
[Description of Drawings]
[0021] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment (s) of the invention and together with the description serve to explain the principle of the invention. In the drawings: [ 0022 ] FIG. 1 is a flowchart illustrating a process of manufacturing a non-polar hetero substrate, according to an embodiment ;
[ 0023 ] FIG. 2 is a cross-sectional view of a structure in which a nucleation layer is formed on a substrate;
[ 0024 ] FIG. 3 is a cross-sectional view of a structure in which a first nitride semiconductor layer having pits is formed on the nucleation layer;
[ 0025] FIG. 4 is a micrograph showing a surface profile of the first nitride semiconductor layer having pits;
[ 0026 ] FIG. 5 is a cross-sectional view of a structure in which the first nitride semiconductor layer is surface- etched;
[ 0027 ] FIG. 6 is a micrograph showing the profile of the structure in which the first nitride semiconductor layer is surface-etched;
[ 0028] FIGs. 7 to 10 are micrographs showing surface shapes according to growth conditions;
[ 0029 ] FIG. 11 is a cross-sectional view of a structure in which a porous mask layer is formed on the first nitride semiconductor layer;
[ 0030 ] FIGs. 12 and 13 are cross-sectional views illustrating a first example of the formation of a porous mask layer; [0031] FIG. 14 is a micrograph showing the first example of the formation of a porous mask layer;
[0032} FIG. 15 is a cross-sectional view illustrating a second example of the formation of a porous mask layer;
[0033] FIG. 16 is a micrograph showing the second example of the formation of a porous mask layer ;
[0034] FIG. 17 is a cross- sectional view illustrating a third example of the formation of a porous mask layer;
[0035] FIG. 18 is a micrograph showing the third example of the formation of a porous mask layer;
[0036] FIG. 19 is a cross-sectional view of a structure in which a second nitride semiconductor layer is formed on the porous mask layer;
[0037] FIG. 20 is a diagram illustrating propagation of dislocations of a hetero substrate;
[0038] FIG. 21 is a micrograph showing a surface profile of a hetero substrate;
[0039] FIG. 22 is a cross-sectional view illustrating a light emitting diode manufactured using a non-polar hetero substrate, according to an embodiment; and
[0040] FIG. 23 is a cross-sectional view illustrating a light emitting diode manufactured using a non-polar hetero substrate, according to another embodiment. [Best Mode]
[0041] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
[0042] However, the present invention allows various modifications and variations and specific embodiments thereof are described in drawings and will be described in detail. The present invention should not be construed as limited to the embodiments set forth herein and includes modifications, variations, equivalents, and substitutions compliant with the spirit or scope of the present invention defined by the appended claims.
[0043] It will be understood that when an element such as a layer, area, or substrate is referred to as being "on" another element, it can be directly on the element, or one or more intervening elements may also be present.
[0044] Also, it will be understood that although terms such as "first" and "second" may be used herein to describe elements, components, areas, layers and/or regions, the elements, components, areas, layers and/or regions should not be limited by these terms.
[0045] Non-polar nitride-based semiconductor means a crystal material in which a polarization phenomenon is not present in a growth direction and may be grown in a direction rotated 90 degrees with respect to the c- surface. The nitride-based semiconductor used herein may include semiconductors of gallium nitride (GaN) , indium gallium nitride (InGaN) , aluminum gallium nitride (AlGaN) , aluminum indium gallium nitride (Al InGaN) , indium nitride (InN) , aluminum nitride (A1N) , and the like.
[0046] In the GaN semiconductor, for example, the number of nitrogen layers is the same as that of gallium layers within a plane, based on growth direction, and thus, an internal field in the growth direction is offset, preventing polarization. Accordingly, energy band distortion by piezoelectric polarization of common c-surface gallium nitride may not occur, and problems such as decrease in recombination efficiency of electrons and holes in an active layer may be addressed.
[0047] In addition, unlike a c-surface gallium nitride material in which the formation of an active layer is limited to a certain thickness or less, non-polar gallium nitride may significantly reduce such thickness limitation, and thus, may be used to form an active layer suitable for high current driving. To date, in thin film growth of non-polar gallium nitride using such a hetero substrate, a method for growing a- or m-surface gallium nitride on an r-surface sapphire substrate has been used. [0048] Photoelectric efficiency of a light emitting diode may be largely divided into three types: internal quantum efficiency, light extraction efficiency, and injection efficiency. The internal quantum efficiency indicates what percentage of electrons injected from the outside of an active layer turn into photons by radiative recombination. The light extraction efficiency indicates what percentage of the generated photons is emitted to the outside of a light emitting diode without optical loss by internal defects, and the like. The injection efficiency indicates a drop in voltage by series resistances.
[0049] To increase the light extraction efficiency, a design method for minimizing total internal reflection effects generated predominantly between layers having different indexes of refraction may be used.
[0050] In a c-surface gallium nitride-based light emitting diode, a patterned sapphire substrate (PSS) technology for forming an uneven portion on a sapphire substrate so as to extract an increased amount of light toward the top of a light emitting diode and a p-GaN surface roughening technology for reducing the probability of total internal reflection between a p-type gallium nitride layer and an external region by forming an uneven portion with a certain size on a p-type semiconductor surface region disposed at a top of a light emitting diode may be generally used. [0051] Non-polar gallium nitride-based hetero thin film growth has an anisotropic thin film growth property in a planar direction and> in particular, has a priority of growth in the c-surface direction, unlike c-surface gallium nitride having an isotropic growth property in the planar direction.
[0052] Accordingly, when a gallium nitride hetero thin film has a certain thickness or less, a semiconductor layer needs to have pits therein. The density and size of the pits may be adjusted according to thin film growth conditions.
[0053] In general, at an initial stage of thin film growth, nitride-based semiconductor islands are formed on a nucleation layer, and the size of the islands increases as the growth thereof continuously progresses such that adjacent semiconductor islands are combined, thereby forming a nitride-based semiconductor layer having a planar shape.
[0054] Subsequently, the nitride-based semiconductor layer is continuously grown to a thickness of 1 to 10 μπι and the islands are then completely coalesced to form a planar surface .
[0055] Then, a porous mask layer having a nano-porous structure may be formed on the nitride-based semiconductor layer with pits formed thereat as described above, and thus, the quality of the nitride-based semiconductor layer may be improved and a light extraction surface of a light emitting diode may be easily formed. [ 0056 ] The porous mask layer having a nano-porous structure may be grown ex-situ, separately from growth of the nitride-based semiconductor. By using the porous mask layer disposed at least on the pits of the nitride-based semiconductor, the quality of the nitride-based semiconductor may be improved and a light extraction surface of a light emitting diode may be easily formed.
[ 0057 ] The growth of a thin film of a non-polar nitride- based semiconductor using a hetero substrate may be performed by growing a nitride-based semiconductor material such as a- or m-surface gallium nitride on an r-surface sapphire substrate. Hereinafter, a method for manufacturing a non- polar hetero substrate using the aforementioned process will be described in detail with reference to the accompanying drawings.
[ 0058 ] FIG. 1 is a flowchart illustrating an example of a process of manufacturing a non-polar hetero substrate. The following descriptions with reference to the drawings will be provided together with reference to FIG.l.
[ 0059 ] To manufacture the non-polar hetero substrate, as illustrated in FIG. 2, a nucleation layer 20 is formed on an r-surface sapphire substrate 10 (step S10) .
[ 0060 ] Here, the substrate 10 may be a substrate having a crystal surface that enables growth of a non-polar nitride- based semiconductor, for example, an r-surface ([1-102] surface) sapphire substrate.
[0061] Also, various other non-polar substrates may be used. For example, a substrate of a-surface silicon carbide (SiC) , an m-surface SiC, spinel, or the like may be used.
[0062] Hereinafter, an example of using the r-surface sapphire substrate 10 will be described.
[0063] The nucleation layer 20 is formed on the r-surface sapphire substrate 10 by using a nitride-based semiconductor such as gallium nitride (GaN) , aluminum nitride (AlN) , or aluminum gallium nitride (AlGaN) , which is grown at a low temperature or a high temperature.
[0064] The nitride-based semiconductor constituting the nucleation layer 20 may form a non-polar or semi -polar semiconductor layer. That is, the nucleation layer 20 may be formed using an a-surface or m-surface nitride-based semiconductor .
[0065] The nitride-based semiconductor constituting the nucleation layer 20 may be grown in a metal organic chemical vapor deposition (MOCVD) growth system or a hydride vapor phase epitaxy (HVPE) growth system. Hereinafter, an example of using the MOCVD growth system will be described.
[0066] The nucleation layer 20 may have a thickness of 10 to 2,000 nm. [0067] In addition, growth conditions of the nucleation layer 20 are as follows: a temperature of 400 to 1,200 °C , a ratio of a Group V material to a Group III material (V/III) of 500 to 10,000, and a growth pressure of 50 to 200 mbar.
[0068] Before the formation of the nucleation layer 20, the r-surface sapphire substrate 10 may be subjected to an annealing process in an ammonia (NH3) atmosphere.
[0069] Subsequently, as illustrated in FIG. 3, a first nitride semiconductor layer 30 is formed on the nucleation layer 20 using a nitride-based semiconductor (step S20) .
[0070] Here, growth conditions are as follows: a growth temperature of 900 to 1,200°C, a growth pressure between 50 to 300 mbar, and a V/III ratio of 50 to 5,000.
[0071] In this regard, growth of a thin film of the nitride-based semiconductor is stopped in a state in which the shape of the grown nitride-based semiconductor is maintained in the form of an island, i.e., in a state in which pits 31 are formed at an upper surface of the first nitride semiconductor layer 30.
[0072] The pit 31 has an inclined surface 32. Thus, the upper surface of the first nitride semiconductor layer 30 has both planar surfaces and inclined surfaces.
[0073] A micrograph of a surface of the first nitride semiconductor layer 30 having the pits 31 is shown in FIG. 4. [ 0074 ] The first nitride semiconductor layer 30 is formed of a semiconductor having the same crystal surface as that of the nucleation layer 20, for example, a nitride-based semiconductor having a crystal surface such as an a- surface or m-surface. A semiconductor layer to be grown thereafter may be grown along such a crystal surface.
[ 0075] Subsequently, in some cases, the surface of the first nitride semiconductor layer 30 at which the pits 31 are formed may be etched (step S21) . The size and width of the pits 31 may be increased by the etching process, and the percentage of inclined crystal surfaces may be increased by the pits 31.
[ 0076 ] FIG. 5 illustrates a resulting structure obtained after the etching process is completed and shows that the inclined surfaces 33 of the pits 31 are steeper than those of the pits 31 (having inclined surfaces 32) illustrated in FIG. 3.
[ 0077 ] As described above, the area percentage of the pits 31 by etching may be increased. In some cases, however, subsequent processes may be performed without the etching process. This is because the percentage of the pits 31 may be adjusted by growth conditions. Hereinafter, an example of the etching process will be described. [0078] A micrograph of a surface of the first nitride semiconductor layer 30 having the pits 31 that have been widened by the etching process is shown in FIG. 6.
[0079] - The etching process may be performed inside or outside an MOCVD growth system by dry etching or wet etching. In the etching process, SiH4, Cl2, BCL2, KOH, phosphoric acid, hydrochloric acid, or the like may be used.
[0080] As described above, when the pits 31 each have the inclined surfaces 32 and 33, a propagation direction of crystal defects may be changed by the inclined surfaces 32 and 33. That is, a propagation direction of defects such as threading dislocation may be bent or diverted.
[0081] Thus, combination and disappearance of the defects may occur, and consequently, the density of the defects is significantly decreased. That is, the percentage of the pits 31 having the inclined surfaces 32 and 33, i.e., a ratio of inclined surfaces to planar surfaces, may act as one important factor in decreasing defects in the growth of a thin film.
[0082] In addition, the density of the pits 31 may be adjusted by adjusting growth conditions. FIGs . 7 to 10 illustrate surface states of the first nitride semiconductor layer 30 according to growth conditions. FIG. 8 is an enlarged view of FIG. 7 and FIG. 10 is an enlarged view of FIG. 9. [ 0083 ] That is, as shown in FIGs .. 7 and 8, it is confirmed that the density of the pits 31 is decreased when a V/III ratio is 200. As shown in FIGs. 9 and 10, on the other hand, it is confirmed that when the V/III ratio is relatively high (i.e., 500), the density of the pits 3.1 is increased.
[ 0084 ] An absolute value of the V/III ratio may vary according to the size and type of a reactor in which a nitride-based semiconductor is grown. However, a tendency of the density of pits generated as the V/III ratio is high or low is the same as described above. That is, as the V/III ratio increases, the density of the pits 31 increases.
[ 0085 ] Next, as illustrated in FIG. 11, a porous mask layer 40 having a nano-porous structure is formed on the first nitride semiconductor layer 30 having the pits 31 (step S30) .
[ 0086 ] The porous mask layer 40 may be formed such that unit structures 41 thereof are irregularly disposed on the first nitride semiconductor layer 30 or gaps are formed between the unit structures 41 thereof. That is, the porous mask layer 40 has a discontinuous porous structure. Thus, a portion of the first nitride semiconductor layer 30 is exposed.
[ 0087 ] As described above, at least a portion of the porous mask layer 40 is disposed on the pits 31. The porous mask layer 40 may have a thickness of several nanometers to tens of nanometers, for example, a thickness of 1 nm to 10 nm in order to have porosity.
[0088] In addition, gaps or holes between the unit structures 41 of the porous mask layer 40 may have an average size of 10 to 100 nm.
[0089] The porous mask layer 40 may be formed using at least one of silicon nitride, aluminum nitride, silicon oxide, A1203, Ti02, HfO, ZnO, Ni , Cu, Ag, ITO, Al , silica, and graphene .
[0090] The porous mask layer 40 may be formed outside a growth system after the formation of the first nitride semiconductor layer 30 having the pits 31. However, the porous mask layer 40 may be directly formed inside a semiconductor thin film growth system according to materials selected.
[0091] When the porous mask layer 40 is formed outside the growth system, a material thereof is relatively freely selected and it is easy to form a pattern.
[0092] The porous mask layer 40 may be formed by plasma enhanced chemical vapor deposition (PECVD) or via sputtering.
[0093] For example, the porous mask layer 40 may be formed such that a silicon oxide layer is deposited on the first nitride semiconductor layer 30 after being taken out of a semiconductor growth system and then etched to form a pattern. [0094] The porous mask layer 40 may block crystal defects that are propagated from the nucleation layer 20 and the first nitride semiconductor layer 30.
[0095] That is, the propagation of crystal defects generated on the sapphire substrate 10 and generated at an initial stage of the growth of a nitride-based semiconductor may be effectively blocked by the porous mask layer 40.
[0096] Moreover, through combination with a method for changing a propagation direction of crystal defects using the inclined pits 31 so as to cause combination and disappearance of the crystal defects, crystal defects of the nitride-based semiconductor may be decreased, and thus a high-quality semiconductor may be manufactured.
[0097] The porous mask layer 40 may be formed using various methods. For example, when a dielectric layer having a very small thickness (i.e., 1 to 10 nm) is formed as the porous mask layer 40, the dielectric layer may be formed as a porous thin film that does not entirely cover the first nitride semiconductor layer 30.
' [0098] When the porous mask layer 40 is formed outside a semiconductor growth system (i.e., ex-situ formation), various other methods may be used.
[0099] As an example, the porous mask layer 40 may be formed by forming a thin film that entirely covers the first nitride semiconductor layer 30 by using one of the above- listed materials including silicon oxide, forming a mask pattern thereon, and performing an etching process using the mask pattern.
[00100] Also, the porous mask layer 40 may be formed using various other methods. For example, the porous mask layer 40 may be formed in the form of nano-dots by heat treatment, a regular array of unit structures using a nano- imprinting method, nano-sized silica particles, or the like.
[00101] Hereinafter, a process of forming the porous mask layer 40" will be described in detail.
[00102] In an embodiment, as illustrated in FIG. 12, first, a dielectric thin film 42 is formed on the first nitride semiconductor layer 30.
[00103] Subsequently, as illustrated in FIG. 13, a pattern mask 43 having openings 43a is formed or positioned on the dielectric thin film 42 and the dielectric thin film 42 is etched using the pattern mask 43, thereby forming the porous mask layer 40.
[00104] The pattern mask 43 may be formed using a metal, for example, nickel (Ni) or silver (Ag) . That is, a thin metal film of Ni or Ag is deposited on the dielectric thin film 42 and heat-treated, thereby forming nano-dots. Then, the dielectric thin film 42 may be etched using the nano-dots as the pattern mask 43. [00105] In FIG. 14, the shape such as particles indicates the pattern mask 43 formed of Ni or Ag described above, and the remaining portion indicates the dielectric thin film 42.
[00106] Also, as illustrated in FIG. 15, a material such as a resist 44 may be coated on the dielectric thin film 42 and the resist 44 may be imprinted in a desired shape using a mold 45 having certain convex shapes 45a, and thus, a pattern of the resist 44 may be formed.
[00107] Then, the dielectric thin film 42 may be etched using the resist 44 as a mask so that the convex shapes 45a of the mold 45 are transferred to the dielectric thin film 42, thereby forming the porous mask layer 40.
[00108] An image of the porous mask layer 40 formed using the imprinting process is shown in FIG. 16.
[00109] Alternatively, as illustrated in FIG. 17, a pattern of the porous mask layer 40 may be formed using nano-spheres.
[00110] For example, when a liquid 47 containing silica particles 46 such as silica nano-spheres is coated on the dielectric thin film 42, the silica particles 46 are attached onto a surface of the dielectric thin film 42. FIG. 18 shows an image of the silica particles 46 attached to the dielectric thin film 42.
[00111] Subsequently, the dielectric thin film 42 may be etched using the silica particles 46 as a mask to form the porous mask layer 40. [00112] The porous mask layer 40 may also be formed using various other methods, and any method that may be used to form an insertion layer capable of blocking defects, which is the function of the porous mask layer 40, may be used.
[00113] After the formation of the porous mask layer 40, the growth of the nitride-based semiconductor is continuously performed in the semiconductor growth system, and thus, as illustrated in FIG. 19, a second nitride semiconductor layer 50 is formed on the first nitride semiconductor layer 30 on which the porous mask layer 40 is formed (step S40) .
[00114] In the process of forming the second nitride semiconductor layer 50, the nitride-based semiconductor is grown through an open region of the nano-porous structure of the porous mask layer 40 and is not grown through a non-open region of the nano-porous structure thereof.
[00115] Subsequently, when a thin film of the nitride-based semiconductor is continuously grown, the grown nitride-based semiconductors are combined through the growth of the thin film in a horizontal direction, thereby forming the second nitride semiconductor layer 50 having a planar surface. Thus, a high-quality hetero substrate may be obtained.
[00116] In this regard, air gaps (not shown) may be formed on a portion of the porous mask layer 40 on which horizontal direction growth is not performed. The air gaps may be used as a light extraction structure in the manufactured light emitting diode.
[00117] The second nitride semiconductor layer 50 formed by the above-described process may have thin film characteristics with largely reduced crystal defects and high quality.
[00118] That is, the second nitride semiconductor layer 50 may have a much lower crystal defect density than that of the first nitride semiconductor layer 30.
[00119] FIG. 20 is a diagram illustrating the propagation of dislocations of a hetero substrate with largely reduced crystal defects in the above-described process.
[00120] As illustrated in FIG. 20, dislocations having a first defect density are propagated upward along the first nitride semiconductor 30 disposed on the nucleation layer 20. The dislocations a may be partially blocked effectively by the porous mask layer 40.
[00121] In addition, a propagation direction of dislocations b and c that are propagated without being blocked by the porous mask layer 40 may be diverted. Thus, some dislocations b meet and combine with each other, and some dislocations c proceed in a diagonal direction according to the formation of the second nitride semiconductor layer 50" and then disappear. [00122] That is, the dislocations b and c cannot be propagated to a growth surface of the second nitride semiconductor layer 50.
[00123] As described above, defects may be effectively reduced by the porous mask layer 40 and by causing combination or disappearance of crystal defects by the pits 31 having inclined surfaces.
[00124] Consequently, very few dislocations d may be propagated to an upper surface of the hetero substrate manufactured by the above -described process, and thus, a high-quality hetero substrate may be manufactured. A second defect density by the dislocation d may be much lower than the first defect density.
[00125] FIG. 21 is a micrograph showing a surface profile of the hetero substrate manufactured by the above-described process .
[00126] By using such a hetero substrate, various semiconductor devices using a nitride-based semiconductor may be manufactured.
[00127] Examples of the semiconductor devices include light emitting diodes such as a nitride-based light emitting diode and a laser diode and transistor devices such as an insulated gate bipolar transistor (IGBT) and a high electron mobility transistor (HEMT) . [00128] Hereinafter, a process of manufacturing a light emitting device such as a light emitting diode on a hetero substrate will be briefly described.
[00129] First, as illustrated in FIG. 22, a semiconductor structure 60 including an n-type semiconductor layer 61, an active layer 62, and a p-type semiconductor layer 63 is grown on the hetero substrate 10 over which the second nitride semiconductor layer 50 is disposed.
[00130] Subsequently, a transparent conductive layer 70 may be formed on the semiconductor structure 60, and a p-type electrode 80 may be formed on the transparent conductive layer 70.
[00131] Then, the n-type semiconductor layer 60 is etched to be exposed and an n-type electrode 90 is then formed on the n-type semiconductor layer 61, thereby completing manufacture of a horizontal -type light-emitting diode.
[00132] Alternatively, a vertical -type light -emitting diode as illustrated in FIG. 23 may be manufactured.
[00133] Such a vertical- ype light-emitting diode may be manufactured as follows. A semiconductor structure 60 including an n-type semiconductor layer 61, an active layer 62, and a p-type semiconductor layer 63 is grown on a hetero substrate over which a second nitride semiconductor layer 50 is disposed. [00134] Subsequently, a p-type electrode 81 is formed on the p-type semiconductor layer 63, and a support layer 83 is attached to the p-type electrode 81 by a solder layer 82. The support layer 83 may include a metal or a semiconductor.
[00135] Then, when the hetero substrate is removed in a state in which the resulting structure is supported by the support layer 83, the n-type semiconductor layer 61 is exposed, and an n-type electrode 91 is formed on an exposed surface thereof, thereby completing the manufacture of the vertical -type light-emitting diode as illustrated in FIG. 23.
[00136] In this regard, in the process of removing the hetero substrate, the pits 31 having inclined surfaces are exposed. When an etching process is performed on the pits 31, the shape of the pits 31 and air gaps is transferred onto the n-type semiconductor 61 by etching, and consequently, a light extraction structure 64 to which such a shape is transferred may be formed.
[00137] Accordingly, since the pits 31 and the air gaps may act as a light extraction structure, the optical output of a light emitting diode may be improved.
[00138] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents,
[industrial Applicability]
[00139] The present invention can provide a non-polar hetero substrate that may minimize the formation of crystal defects generated during hetero thin film growth.

Claims

[CLAIMS] [Claim 1]
1. A non-polar hetero substrate comprising:
an r- surface sapphire substrate;
a nucleation layer disposed on the sapphire substrate and comprising an a-surface or m-surface nitride-based semiconductor;
a first nitride semiconductor layer disposed on the nucleation layer, having a first defect density, and comprising a plurality of pits having inclined surfaces at an upper surface thereof;
a porous mask layer disposed at least on the pits of the first nitride semiconductor layer; and
a second nitride semiconductor layer disposed on the porous mask layer and having a second defect density that is lower than the first defect density.
2. The non-polar hetero substrate according to claim 1, wherein the porous mask layer comprises any one of silicon nitride, aluminum nitride, silicon oxide, Al203, Ti02, HfO, ZnO, Ni, Cu, Ag, ITO, Al, silica, and graphene .
3. The non-polar hetero substrate according to claim 1, wherein the first nitride semiconductor layer and the second nitride semiconductor layer have the same crystal surface as that of the nucleation layer.
4. The non-polar hetero substrate according to claim 1, wherein the porous mask layer has a thickness of 1 to 10 ran.
5. The non-polar hetero substrate according to claim 1, wherein pores of the porous mask layer have an average size of 10 to 100 nm.
6. The non-polar hetero substrate according to claim 1, wherein air gaps are disposed on the porous mask layer.
7. A method for manufacturing a non-polar hetero substrate, the method comprising:
forming a nucleation layer on a first surface of an r- surface sapphire substrate using an a-surface or m-surface nitride-based semiconductor;
forming a first nitride semiconductor layer comprising a plurality of pits having inclined surfaces on the nucleation layer;
forming a porous mask layer blocking at least a portion of a crystal defect on the first nitride semiconductor layer; and forming a second nitride semiconductor layer on the porous mask layer.
8. The method according to claim 7, wherein the pits are disposed at an interface between the first nitride semiconductor layer and the porous mask layer.
9. The method according to claim 7, wherein the pits are configured so as to divert a direction of a crystal defect of the nitride-based semiconductor.
10. The method according to claim 7, further comprising, after the formation of the first nitride semiconductor layer, etching a surface of the first nitride semiconductor layer at which the pits are formed.
11. The method according to claim 7, further comprising heat treating the first surface of the sapphire substrate in an ammonia gas atmosphere.
12. The method according to claim 7, wherein forming of the porous mask layer comprises forming a thin film on a surface of the first nitride semiconductor layer, forming a pattern mask on the thin film, and etching the thin film using the pattern mask.
13. The method according to claim 7, wherein the forming of the porous mask layer further comprises forming a thin film on a surface of the first nitride semiconductor layer, and forming a pattern mask on the thin film by imprinting.
14. The method according to claim 7, wherein the forming of the porous mask layer further comprises forming a thin film on an entire surface of the first nitride semiconductor layer, coating a liquid comprising particles on the thin film, and etching the thin film using the particles as a mask.
15. A nitride-based light emitting device comprising: a non-polar hetero substrate comprising an r-surface sapphire substrate, a first nitride semiconductor layer disposed on the sapphire substrate, having a first defect density, comprising an a-surface or m-surface nitride-based semiconductor, and comprising a plurality of pits having inclined surfaces at an upper surface thereof, a porous mask layer disposed at least on the pits of the first nitride semiconductor layer; and a second nitride semiconductor layer disposed on the porous mask layer and having a second defect density that is lower than the first defect density, a first conductive semiconductor layer disposed on the hetero substrate and comprising a nitride semiconductor,
an active layer disposed on the first conductive semiconductor layer,
a second conductive semiconductor layer disposed on the active layer and comprising a nitride semiconductor,
a first electrode electrically connected to the first conductive semiconductor layer, and
a second electrode electrically connected to the second conductive semiconductor layer.
16. The nitride-based light emitting device according to claim 15, wherein the porous mask layer comprises any one of silicon nitride, aluminum nitride, silicon oxide, AI2O3, Ti02, HfO, ZnO, Ni , Cu, Ag, ITO, Al , silica, and graphene .
17. The nitride-based light emitting device according to claim 15, wherein the porous mask layer has a thickness of 1 to 10 nm.
18. The nitride-based light emitting device according to claim 15, wherein pores of the porous mask layer have an average size of 10 to 100 nm.
19. The nitride-based light emitting device according to claim 15, wherein air gaps are disposed on the porous mask layer .
20. The nitride-based light emitting device according to claim 15, further comprising a nucleation layer comprising an a-surface or m-surface nitride-based semiconductor, between the r-surface sapphire substrate and the first nitride semiconductor layer.
PCT/KR2013/001068 2012-08-29 2013-02-12 Non-polar substrate having hetero-structure, method for manufacturing the same, and nitride-based light emitting device using the same WO2014035021A1 (en)

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