KR20150097182A - Non-polar substrate having hetero-structure and method for manufacturing the same, nitride semiconductor light emitting device using the same - Google Patents

Abstract

The present invention relates to a semiconductor substrate and device, and, specifically, relates to a non-polar substrate having a hetero-structure, a method for manufacturing the same, and a nitride semiconductor light emitting device using the same. The method of the present invention comprises the steps of: forming a nucleation layer using a nitride semiconductor on an r-plane sapphire substrate by using a-plane nitride semiconductor; forming a first semiconductor layer including a nitride semiconductor on which several pits having inclinations are formed on the nucleation layer; forming a porous mask layer on the first semiconductor layer; forming a second semiconductor layer including a nitride semiconductor on the porous mask layer; and forming a buffer layer to flatten an inclined plane on which a shape of the pit is spread on the second semiconductor layer.

Description

[0001] The present invention relates to a non-polarized heterogeneous substrate, a method of manufacturing the same, and a nitride semiconductor light emitting device using the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a device, and more particularly, to a non-polarization heterogeneous substrate, a manufacturing method thereof, and a nitride semiconductor light emitting device using the same.

Gallium nitride used as a material of a semiconductor device such as a blue light-emitting diode is a material having a hexagonal crystal structure, and a thin film is grown mainly in the crystal direction of the c-plane. This is because the case of growing in the crystal direction of the c-plane facilitates horizontal growth, and a thin film of high quality with few defects such as dislocations can be obtained.

At this time, when the growth direction is taken as a reference, the nitride layer and the gallium layer are crossed and repeated on the same plane. There is a strong internal field between nitrogen and gallium, which causes polarization.

The inner field formed is divided into two components, spontaneous polarization and piezo-electric field. When a layer having different lattice constants such as an InAlGaN material is inserted, the polarization effect is increased so that quantum confinement A quantum confined Stark effect may occur.

For example, in a structure in which a gallium aluminum indium gallium nitride (InAlGaN) active layer is inserted between p-type and n-type gallium nitride (GaN) layers as in a blue light emitting diode, deformation occurs between layers due to a difference in lattice constant An internal field may be generated to cause bending of the active layer energy band structure.

As a result, the wave function of electrons and holes in the active layer is spatially separated and the size of the energy gap is reduced, which may be a main cause of deterioration of recombination efficiency.

In order to overcome this problem, studies are being conducted to form a non-polar nitride semiconductor layer. However, the nonpolarized GaN thin film grown on a heterogeneous substrate up to now can cause a lot of defects in the thin film due to the poor growth condition compared to polar GaN. Such defects are caused by a large amount of light output Can cause problems.

The present invention is directed to a non-polarized hetero-substrate capable of minimizing the formation of crystal defects occurring in the process of growing a non-polarized hetero thin film and improving surface characteristics, a method for manufacturing the same, a nitride- .

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a nucleation layer using an a-plane nitride semiconductor on an r-plane sapphire substrate; Forming a first semiconductor layer on the nucleation layer, the first semiconductor layer including a plurality of pits having a slope on the nucleation layer; Forming a porous mask layer on the first semiconductor layer; Forming a second semiconductor layer including a nitride semiconductor on the porous mask layer; And forming a buffer layer on the second semiconductor layer to planarize an inclined surface on which the shape of the pit is propagated.

Here, the buffer layer can be formed by using nitrogen gas as a carrier gas.

Here, the pits may be for changing the direction of crystal defects of the nitride-based semiconductor.

The porous mask layer may include at least one of a silicon nitride layer, an aluminum nitride layer, a silicon oxide layer, Al ₂ O ₃ , TiO ₂ , HfO ₂ , ZnO, Ni, Cu, Ag, ITO, Al, .

Forming a third semiconductor layer including a nitride semiconductor on the buffer layer; And forming a fourth semiconductor layer including a nitride semiconductor on the third semiconductor layer.

At this time, at least one of the first semiconductor layer and the third semiconductor layer may be grown in a three-dimensional growth mode in which vertical growth predominates.

Also, at least one of the second semiconductor layer and the fourth semiconductor layer may be grown in a two-dimensional growth mode in which horizontal growth is dominant.

According to a second aspect of the present invention, the present invention provides an r-plane sapphire substrate; A nucleation layer located on the sapphire substrate and comprising an a-plane nitride-based semiconductor; A first semiconductor layer located on the nucleation layer and having a first defect density and including a nitride semiconductor in which a plurality of pits having slopes on an upper surface are located; A porous mask layer located on at least the pit on the first semiconductor layer; A second semiconductor layer located on the porous mask layer and including a nitride semiconductor having a second defect density lower than the first defect density; And a buffer layer positioned on the second semiconductor layer and planarizing an inclined surface on which the shape of the pit is propagated.

The porous mask layer may include at least one of a silicon nitride layer, an aluminum nitride layer, a silicon oxide layer, Al ₂ O ₃ , TiO ₂ , HfO ₂ , ZnO, Ni, Cu, Ag, ITO, Al, .

Here, the first nitride semiconductor layer and the second nitride semiconductor layer may have the same crystal plane as the nucleation layer.

A third semiconductor layer located on the buffer layer and including a nitride semiconductor; And a fourth semiconductor layer located on the third semiconductor layer and including a nitride semiconductor and being planarized.

According to a third aspect of the present invention, there is provided a semiconductor device comprising: the above-described heterogeneous substrate; A first conductive semiconductor layer located on the heterogeneous substrate and including a nitride semiconductor; An active layer located on the first conductive semiconductor layer; A second conductive semiconductor layer located on the active layer and including a nitride semiconductor; A first electrode electrically connected to the first conductive semiconductor layer; And a second electrode electrically connected to the second conductive semiconductor layer.

The present invention has the following effects.

Initially, along the first semiconductor layer located on the nucleation layer, the dislocations propagate upward with a first defect density, some of which may be effectively blocked by the porous mask layer.

Further, the potentials that are propagated without being blocked by the porous mask layer are switched in the propagation direction by the pits having the inclined faces. Therefore, some of the dislocations may be merged with each other, and some dislocations may be extinguished in the oblique direction according to the formation of the second semiconductor layer.

As described above, it is possible to effectively reduce the defects by inducing the merging or disappearance of the crystal defects by the pits having the porous mask layer and the inclined surface.

On the other hand, after the growth of the buffer layer described above, continuous growth can achieve complete sealing of the shape in which the pits formed in the upper semiconductor structure are transferred. Three-dimensional and two-dimensional mode crossing growth can be applied to further reduce the defect density, and as a result, defects and surface characteristics of the thin film constituting the different substrate can be improved.

Further, in order to reduce crystal defects, it is possible to increase the density and roughness of the island shape or to increase the thickness of the porous mask layer through three-dimensional growth in which vertical growth predominates, and the density and roughness or porosity The choice of the thickness of the mask layer is widened, and the defects of the thin film can be controlled more effectively.

As a result, only a very small number of defects can be propagated to the upper surface of the heterogeneous substrate formed in this process, and thus a high-quality heterogeneous substrate can be produced.

1 is a flow chart showing an example of a process of manufacturing a non-polarization heterogeneous substrate.
2 is a cross-sectional view showing an example of a state in which a nucleation layer is formed on a substrate.
3 is a cross-sectional view showing an example of a state in which a first semiconductor layer having pits is formed on a nucleation layer.
4 is a cross-sectional view showing an example of a state in which a porous mask layer is formed on a first semiconductor layer.
5 is a cross-sectional view showing an example of a state in which a second semiconductor layer is formed on a porous mask layer.
6 and 7 are surface photographs showing an example of a state in which the second semiconductor layer is formed on the porous mask layer.
8 is a cross-sectional view showing an example of a state in which a buffer layer is formed on the second semiconductor layer.
9 is a cross-sectional view showing an example of a state in which a third semiconductor layer and a fourth semiconductor layer are formed on a buffer layer, respectively.
10 is a photograph showing the surface of the thin film after the formation of the buffer layer.
11 is a photograph showing the surface of the final dissimilar substrate on which the fourth semiconductor layer is formed.
12 is an electron microscope image of the surface of the finally grown heterogeneous substrate.
13 is a cross-sectional view showing an example of a light emitting device manufactured using a different substrate.
14 is a cross-sectional view showing another example of a light emitting device manufactured using a different substrate.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. Rather, the intention is not to limit the invention to the particular forms disclosed, but rather, the invention includes all modifications, equivalents and substitutions that are consistent with the spirit of the invention as defined by the claims.

It will be appreciated that when an element such as a layer, region or substrate is referred to as being present on another element "on," it may be directly on the other element or there may be an intermediate element in between .

Although the terms first, second, etc. may be used to describe various elements, components, regions, layers and / or regions, such elements, components, regions, layers and / And should not be limited by these terms.

The non-polarization nitride-based semiconductor means a crystal material having no polarization phenomenon in the growth direction, and can be realized by growing in a direction rotated in the 90 ° direction with the c-plane. Here, the nitride-based semiconductor is formed of a semiconductor such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), indium nitride (InN) It can mean.

In this case, when the growth direction is taken as a reference, for example, since the nitrogen layer and the gallium layer have the same number in the plane, the internal field in the growth direction is canceled and the polarization characteristic does not appear. Therefore, distortion of the energy band due to the piezoelectric polarization of the conventional c-plane gallium nitride does not occur, and the problems such as reduction of recombination efficiency of electrons and holes in the active layer can be improved.

Unlike the c-plane gallium nitride-based material, which is limited in the active layer design to a certain thickness or less, the thickness limitation can be largely mitigated and the active layer design suitable for high current driving can be realized. Up to now, a technique for growing a-plane or m-plane gallium nitride on a r-plane sapphire substrate is utilized for growing a thin film of a non-polarized gallium nitride using such a dissimilar substrate.

The photovoltaic efficiency of a light emitting diode is roughly composed of three kinds of efficiencies. An internal quantum efficiency indicating how much electrons injected from the outside of the active layer are converted into photons by light emission recombination and a degree of emission of the generated photons to the outside of the light emitting diode Light extraction efficiency, and injection efficiency, which represents the voltage drop due to the series resistance component.

As a technique for improving the light extraction efficiency, a design method that minimizes a total internal reflection effect mainly occurring between layers having different refractive indexes is adopted.

Unlike c-plane gallium nitride, which has an isotropic growth characteristic in the planar direction, the growth of a non-polarized gallium nitride-based thin film has an anisotropic thin film growth characteristic in a planar direction, and particularly a growth in a c-plane direction is preferred .

Accordingly, the pit is contained in the semiconductor layer below the specific thickness of gallium nitride. The density and size of such pits can be controlled according to the growth conditions of the thin film.

Generally, in the initial stage of the growth of the thin film, nitride-based semiconductor islands are formed on the nucleation layer, and thereafter, as the growth progresses, the size of the islands gradually increases to be combined with neighboring islands, Layer.

Thereafter, through continuous growth, the nitride-based semiconductor layer is coalesced with islands to form a flat surface after a certain thickness of growth.

The quality of the nitride-based semiconductor can be improved by forming a porous mask layer having a nano-porous structure on the nitride-based semiconductor layer with the above-described pits formed thereon.

The porous mask layer having the nanoporous structure can be continuously grown with the growth of the nitride-based semiconductor, and the quality of the nitride-based semiconductor can be improved by using at least the porous mask layer located on the pit of the nitride-based semiconductor.

Hereinafter, in the thin film growth of the non-polarization nitride based semiconductor using the above-mentioned heterogeneous substrate, a nitride-based semiconductor material such as an a-plane or m-plane gallium nitride may be grown on a r-plane sapphire substrate. A manufacturing process of a non-polarization heterogeneous substrate manufactured by the above process will be described in detail with reference to the accompanying drawings.

1 is a flow chart showing an example of a process of manufacturing a non-polarization heterogeneous substrate. BRIEF DESCRIPTION OF THE DRAWINGS The following description with reference to the drawings is made with reference to FIG.

2 is a cross-sectional view showing an example of a state in which a nucleation layer is formed on a substrate. 2, a nucleation layer 20 is formed on a substrate 10 (S10).

Here, the substrate 10 uses a substrate 10 having a crystal plane capable of growing a non-polar nitride-based semiconductor, and an r-plane ([1-102] plane) sapphire substrate can be used.

It goes without saying that various substrates having other non-polarization can be used. That is, a substrate such as a-plane silicon carbide (SiC), m-plane SiC, spinel, or the like may be used.

Hereinafter, an example using the r-plane sapphire substrate 10 will be described.

That is, the nucleation layer 20 may be formed by forming a nitride-based semiconductor such as gallium nitride (GaN), aluminum nitride (AlN), or aluminum gallium nitride (AlGaN) on the r-plane sapphire substrate 10 grown at low temperature or high temperature .

The nitride semiconductor constituting the nucleation layer 20 may be a nonpolar (nonpolar) or semi-polar semiconductor layer. That is, the nucleation layer 20 can be formed using an a-plane or m-plane nitride-based semiconductor.

The nitride-based semiconductor including the nucleation layer 20 may be grown on growth equipment such as metal organic chemical vapor deposition (MOCVD) or hydride vapor phase epitaxy (HVPE). An example using MOCVD will be described below.

It is advantageous that the thickness of the nucleation layer 20 has a thickness of 10 to 2,000 nm.

The growth conditions of the nucleation layer 20 are such that the V / III ratio of the Group 5 material and the Group 3 material is in the range of 500 to 10,000 and the growth pressure is in the range of 50 to 200 It is advantageous to grow in mbar.

A process of annealing the sapphire substrate 10 in an ammonia (NH ₃ ) atmosphere may be further included before forming the nucleation layer 20.

3 is a cross-sectional view showing an example of a state in which a first semiconductor layer having pits is formed on a nucleation layer.

3, a first semiconductor layer 30 is formed on the nucleation layer 20 by using a nitride-based semiconductor (S20).

At this time, it is advantageous to grow the growth conditions at a growth temperature of 900 to 1,200 DEG C, a growth pressure of 50 to 300 mbar, and a V / III ratio of 50 to 5,000.

At this time, the growth of the thin film is stopped in a state in which the shape of the grown nitride-based semiconductor maintains the island shape, that is, the pit 31 is located on the upper side.

The pits 31 have inclined faces 33. [ Therefore, the upper surface of the first semiconductor layer 30 becomes a plane in which the flat surface and the inclined surface exist simultaneously.

In addition, the first semiconductor layer 30 is formed of a semiconductor having the same crystal plane as the nucleation layer 20, that is, a nitride semiconductor having an a-plane or an m-plane crystal plane. All the semiconductor layers to be grown thereafter can be grown along these crystal planes. Hereinafter, the case where the nitride-based semiconductor has an a-plane will be described as an example.

Thereafter, the etching of the surface of the first semiconductor layer 30 in which such pits 31 are present may be proceeded as occasion demands. By this etching, the size and the width of the pit 31 can be enlarged, and the ratio of the inclined crystal face by the pit 31 can be increased.

As described above, although the area ratio occupied by the pits 31 by etching may increase, the following process may be performed without performing etching depending on the case. One of the reasons is that the ratio of the pits 31 can be controlled by the growth conditions.

As described above, in the case where the pit 31 having the inclined face 33 exists, the direction in which the crystal defect propagates due to the inclined face 33 can be changed, that is, a defect such as threading dislocation The propagating direction can be bent or switched.

Therefore, the merging and destruction of defects may occur through this, resulting in a marked reduction in the density of defects. As a result, the ratio of the pits 31 having the inclined plane 33, that is, the ratio between the inclined plane and the flat plane can act as one of important parameters in the thin film growth for reducing defects.

In addition, the density of the pits 31 can be adjusted by controlling the growth conditions. Although the absolute value of the V / III ratio may vary depending on the size and type of the reactor for growing the nitride semiconductor, the tendency of density in which pits are generated according to the ratio of V / III ratio is as described above. That is, as the ratio of V / III increases, the density of pits increases.

4 is a cross-sectional view showing an example of a state in which a porous mask layer is formed on a first semiconductor layer.

4, a porous mask layer 40 having a nano-porous structure is formed on the first semiconductor layer 30 in which the pits 31 are present (S30).

The porous mask layer 40 may be formed such that the unit structures 41 are irregularly positioned on the first semiconductor layer 30 or a gap is located between the unit structures 41. That is, it has a porous structure that is not continuous. Therefore, a part of the first semiconductor layer 30 becomes exposed.

As such, at least a portion of the porous mask layer 40 is located on the pit 31. The thickness of the porous mask layer 40 is several nanometers to tens of nanometers, and it is advantageous to form the porous mask layer 40 to have a thickness of 1 nm to 10 nm in order to achieve porosity.

The porous mask layer 40 may include at least one of a silicon nitride film, an aluminum nitride film, a silicon oxide film, Al ₂ O ₃ , TiO ₂ , HfO ₂ , ZnO, Ni, Cu, Ag, ITO, Al, Can be formed.

The porous mask layer 40 can be formed outside the growth equipment after the first semiconductor layer 30 having the pits 31 is completely grown. However, depending on the material selected, it can also be formed directly inside the semiconductor thin film growth equipment.

In the case where the porous mask layer 40 is formed outside the growth equipment, the material is relatively freely selected and the pattern is easily formed.

The porous mask layer 40 may be formed by a plasma enhanced chemical vapor deposition (PECVD) method or a sputtering method.

The porous mask layer 40 may function to block crystal defects propagated from the nucleation layer 20 and the first semiconductor layer 30.

That is, the diffusion of crystal defects generated at the top of the sapphire substrate 10 and at the initial growth of the nitride-based semiconductor can be effectively blocked by the porous mask layer 40.

Further, this is a method of generating defects by merging and disappearing by changing the direction in which the crystal defects propagate by using the inclined pits 31 described above, and by forming crystal of high quality by decreasing crystal defects of the nitride-based semiconductor It will be possible.

The porous mask layer 40 may be formed by various methods. When a dielectric film having a very thin thickness of 1 to 10 nm is formed, a porous thin film that does not cover the entire first semiconductor layer 30 is formed .

A nitride semiconductor layer may be continuously formed on the porous mask layer 40 to form a heterogeneous substrate having a smooth surface. Therefore, a semiconductor device can be manufactured using the thus-formed heterogeneous substrate.

5 is a cross-sectional view showing an example of a state in which a second semiconductor layer is formed on a porous mask layer.

For formation of a heterogeneous substrate having a smooth surface, an upper semiconductor structure 50 may be formed on the porous mask layer 40. That is, as shown in FIG. 5, the second semiconductor layer 51 may be formed first on the porous mask layer 40 (S40).

The second semiconductor layer 51 may be formed in a two-dimensional growth mode in which growth in the horizontal direction is more dominant by adjusting growth conditions.

On the other hand, there is a limit in forming the upper semiconductor structure 50 formed on the porous mask layer 40 in a flat manner.

For example, in order to reduce crystal defects, it is possible to increase the density and roughness of the island shape or to increase the thickness of the porous mask layer 40 through three-dimensional growth in which vertical growth is dominant. May result in a higher probability of incomplete coalescence. Therefore, it may be difficult to realize a thin film on a flat surface.

6 and 7 are surface photographs showing an example of a state in which the second semiconductor layer is formed on the porous mask layer.

6, the pits 31 formed in the first semiconductor layer 30 are retained without being sealed. If the growth of the second semiconductor layer 51 continues in this state, the state of the surface can be formed as shown in FIG.

That is, the pit 31 may exist in a state in which the pit 31 is not sealed, or may have a non-uniform property in the sealing process and may grow in a mound form in some areas.

Therefore, a technique for overcoming such a phenomenon is needed. That is, a process of promoting coalescence during the growth of the a-plane thin film of the nitride semiconductor may be required. As an example of such a process, it may be necessary to change the state of the surface of the nitride semiconductor.

As described above, the a-plane gallium nitride (GaN) thin film has different growth rates depending on crystal directions, and horizontal growth (two-dimensional growth) is not easy compared with the polar c-plane GaN thin film, Can be relatively more difficult to complete planarization (suture) of the rough surface caused.

Since the a-plane GaN thin film having a certain degree of thin film growth has the property of maintaining the crystal plane state, the shape of the pit 31 may remain even in the growth of the thin film.

8 is a cross-sectional view showing an example of a state in which the buffer layer 52 is formed on the second semiconductor layer 51. FIG.

In order to planarize the shape due to the pits 31, a buffer layer 52 for planarizing the inclined surface 33 in which the shape of the pits 31 propagate may be formed (S50).

By forming the buffer layer 52, the dependence on the already formed crystal plane can be canceled and the planarization can be facilitated in the process of stacking the GaN semiconductor structure 50 to be formed later.

The buffer layer 52 may be formed using gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the thickness of the buffer layer 52 may be 1 to 1000 nm.

At this time, the growth condition can be in the range of 400 to 1200 ° C, the V / III ratio can be in the range of 500 to 10,000, and the growth pressure can be advantageously grown at 50 to 200 mbar. Further, a carrier gas such as nitrogen or helium in the growth process can be used. That is, the buffer layer 52 can be formed in a nitrogen or helium atmosphere.

A thin film can be formed on the buffer layer 52 by alternately using the two-dimensional growth mode and the three-dimensional growth mode growth.

That is, after the growth of the buffer layer 52, complete sealing can be achieved by continuous growth. Through this method, it is possible to apply three-dimensional and two-dimensional mode crossing growth for the purpose of further reducing the defect density, and as a result, it is possible to improve defects and surface characteristics of the thin film constituting the different substrate.

Further, in order to reduce crystal defects, it is possible to increase the density and roughness of the island shape or to increase the thickness of the porous mask layer 40 through three-dimensional growth in which vertical growth is dominant. The width of the roughness and the thickness of the porous mask layer 40 can be widened, and the defects of the thin film can be controlled more effectively.

The three-dimensional growth mode may have a relatively higher V / III ratio than the two-dimensional growth mode. For example, the three-dimensional growth mode may be 1500 or more, and the two-dimensional growth mode may be 1000 or less.

The three-dimensional growth mode may be 1000 占 폚 or lower and the two-dimensional growth mode may be 1100 占 폚 or higher at the growth temperature.

On the other hand, at the growth pressure, the three-dimensional growth mode may be 500 mbar or less, and the two-dimensional growth mode may be 150 mbar or more and 500 mbar or less.

By alternately using the two-dimensional growth mode and the three-dimensional growth mode thin film growth, the thin film formed on the buffer layer 52 can be planarized.

9 is a cross-sectional view showing an example of a state in which a third semiconductor layer and a fourth semiconductor layer are formed on a buffer layer, respectively.

The third semiconductor layer 53 may be formed on the buffer layer 52 in the three-dimensional growth mode described above (S60).

The fourth semiconductor layer 54 may be formed on the third semiconductor layer 53 in a two-dimensional growth mode (S70).

In some cases, the third semiconductor layer 53 in the three-dimensional growth mode and the fourth semiconductor layer 54 in the two-dimensional growth mode may be additionally formed alternately several times.

As described above, at least one of the first semiconductor layer 30 and the third semiconductor layer 53 can be formed in a three-dimensional growth mode, and at least one of the second semiconductor layer 51 and the fourth semiconductor layer 54 One of which may be formed in a two-dimensional growth mode.

10 is a photograph showing the surface of the thin film after the formation of the buffer layer, and Fig. 11 is a photograph showing the surface of the final different substrate on which the fourth semiconductor layer is formed.

Compared with the case of FIG. 7, it can be confirmed that the buffer layer 52 and the subsequent additional GaN thin films 53 and 54 are finally grown to form a greatly improved thin film.

FIG. 12 is a transmission electron microscope (TEM) image of the surface of the finally grown heterogeneous substrate, and the dislocation density was measured at a level of 9 × 10 ⁸ / cm ² .

On the other hand, in the embodiment of the present invention described above, the nitride semiconductor grows through the open region of the porous structure of the porous mask layer 40, and growth does not proceed where it is plugged.

Thereafter, when the thin film growth continues, the nitride semiconductor is merged with each other through the thin film growth in the horizontal direction to form the upper semiconductor structure 50 having a flat surface. Thus, a heterogeneous substrate having high quality can be produced.

The upper semiconductor structure 50 may have a high-quality thin film characteristic in which crystal defects are largely reduced by the process described above.

That is, the upper semiconductor structure 50 including the second semiconductor layer 51, the third semiconductor layer 53, and the fourth semiconductor layer 54 has a significantly reduced crystal defect density than the first semiconductor layer 30 Lt; / RTI >

The potentials that are propagated without being blocked by the porous mask layer 40 are switched in the propagation direction by the pits 31 having the inclined faces 33. [ Therefore, some of the potentials may be merged with each other, and some of the potentials may be extinguished in the oblique direction as the upper semiconductor structure 50 is formed.

As described above, it is possible to effectively reduce defects by inducing the merging or disappearance of crystal defects by the porous mask layer 40 and the pits 31 having inclined faces.

As a result, only a very small number of defects can be propagated to the upper surface of the heterogeneous substrate formed in such a process, so that a high-quality heterogeneous substrate can be manufactured. The second defect density due to such a defect has a defect density which is greatly reduced from the first defect density.

On the other hand, after the growth of the buffer layer 52 described above, continuous growth can achieve complete sealing of the shape in which the pits 31 formed in the upper semiconductor structure 50 are transferred. Three-dimensional and two-dimensional mode crossing growth can be applied to further reduce the defect density, and as a result, defects and surface characteristics of the thin film constituting the different substrate can be improved.

Further, in order to reduce crystal defects, it is possible to increase the density and roughness of the island shape or to increase the thickness of the porous mask layer 40 through three-dimensional growth in which vertical growth is dominant. The width of the roughness and the thickness of the porous mask layer 40 can be widened, and the defects of the thin film can be controlled more effectively.

Various semiconductor devices using nitride-based semiconductors can be manufactured using such a different substrate.

Such semiconductor devices may include light emitting devices such as nitride-based light emitting diodes or laser diodes, and transistor devices such as IGBTs and HEMTs.

Hereinafter, a process of fabricating a light emitting device such as a light emitting diode on a different substrate will be briefly described.

First, as shown in Fig. 13, a horizontal light emitting diode can be manufactured.

First, an n-type semiconductor layer 61, an active layer 62, and a p-type semiconductor layer (not shown) are formed on a heterogeneous substrate having an upper semiconductor structure 50 located on the upper side of the fourth semiconductor layer 54 63 are grown.

Thereafter, a transparent conductive layer 70 can be formed on the semiconductor layer 60, and a p-type electrode 80 is formed on the transparent conductive layer 70.

After the n-type semiconductor layer 61 is etched so as to be exposed, the n-type electrode 90 is formed on the n-type semiconductor layer 61 to complete the horizontal light emitting diode as shown in FIG.

On the other hand, it is also possible to fabricate a vertical type light emitting diode as shown in Fig.

The vertical light emitting diode includes a semiconductor layer including an n-type semiconductor layer 61, an active layer 62, and a p-type semiconductor layer 63 on a different substrate on which the fourth semiconductor layer 54 is disposed. The structure 60 is grown.

A p-type electrode 81 is formed on the p-type semiconductor layer 63 and a supporting layer 83 is attached to the p-type electrode 81 by using a solder layer 82. [ The support layer 83 may comprise a metal or a semiconductor.

Next, when the dissimilar substrate is removed while being supported by the supporting layer 83, the n-type semiconductor layer 61 is exposed. When the n-type electrode 91 is formed on the exposed surface, The light emitting diode structure is formed.

On the other hand, in the process of removing the dissimilar substrate, the surface on which the pits 31 having the inclined surfaces described above are formed can be exposed. When this surface is etched, the shape due to the pits 31 or air gaps is etched The light extracting structure 64 having such a shape propagated can be formed when the light extracting structure 64 is exposed and propagated and etched to the n-type semiconductor layer 61.

Therefore, such a pit 31 and the air gap can act as a light extracting structure, so that the light output of the light emitting device can be improved.

It should be noted that the embodiments of the present invention disclosed in the present specification and drawings are only illustrative of specific examples for the purpose of understanding and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

10: sapphire substrate 20: nucleation layer
30: first semiconductor layer 31: pit
33: sloped surface 40: porous mask layer
41: unit structure 50: upper semiconductor structure
51: second semiconductor layer 52: buffer layer
53: third semiconductor layer 54: fourth semiconductor layer

Claims (12)

forming a nucleation layer using an a-plane nitride-based semiconductor on an r-plane sapphire substrate;
Forming a first semiconductor layer on the nucleation layer, the first semiconductor layer including a plurality of pits having a slope on the nucleation layer;
Forming a porous mask layer on the first semiconductor layer;
Forming a second semiconductor layer including a nitride semiconductor on the porous mask layer; And
And forming a buffer layer on the second semiconductor layer for planarizing an inclined surface on which the shape of the pit is propagated. The method of manufacturing a non-polarization heterogeneous substrate according to claim 1, wherein the buffer layer is formed by using nitrogen gas as a carrier gas. The method of manufacturing a non-polarization heterogeneous substrate according to claim 1, wherein the pits are for changing the direction of crystal defects of the nitride-based semiconductor. 2. The method of claim 1, wherein the porous mask layer comprises at least one of a silicon nitride film, an aluminum nitride film, a silicon oxide film, Al ₂ O ₃ , TiO ₂ , HfO ₂ , ZnO, Ni, Cu, Ag, ITO, Al, Wherein the substrate is a single crystal substrate. The method according to claim 1,
Forming a third semiconductor layer including a nitride semiconductor on the buffer layer; And
And forming a fourth semiconductor layer including a nitride semiconductor on the third semiconductor layer. ≪ RTI ID = 0.0 > 31. < / RTI > 6. The method of claim 5, wherein at least one of the first semiconductor layer and the third semiconductor layer is grown in a three-dimensional growth mode in which vertical growth is dominant. 6. The method of claim 5, wherein at least one of the second semiconductor layer and the fourth semiconductor layer is grown in a two-dimensional growth mode in which horizontal growth predominates. r-plane sapphire substrate;
A nucleation layer located on the sapphire substrate and comprising an a-plane nitride-based semiconductor;
A first semiconductor layer located on the nucleation layer and having a first defect density and including a nitride semiconductor in which a plurality of pits having slopes on an upper surface are located;
A porous mask layer located on at least the pit on the first semiconductor layer;
A second semiconductor layer located on the porous mask layer and including a nitride semiconductor having a second defect density lower than the first defect density; And
And a buffer layer positioned on the second semiconductor layer and planarizing an inclined surface on which the shape of the pit is propagated. 9. The method according to claim 8, wherein the porous mask layer comprises at least one of a silicon nitride film, an aluminum nitride film, a silicon oxide film, Al ₂ O ₃ , TiO ₂ , HfO ₂ , ZnO, Ni, Cu, Ag, ITO, Al, Wherein the substrate is a single crystal substrate. The non-polarization heterogeneous substrate according to claim 8, wherein the first nitride semiconductor layer and the second nitride semiconductor layer have the same crystal plane as the nucleation layer. 9. The method of claim 8,
A third semiconductor layer located on the buffer layer and including a nitride semiconductor; And
And a fourth semiconductor layer disposed on the third semiconductor layer and including a nitride semiconductor and planarized. 12. A heterogeneous substrate according to any one of claims 9 to 11;
A first conductive semiconductor layer located on the heterogeneous substrate and including a nitride semiconductor;
An active layer located on the first conductive semiconductor layer;
A second conductive semiconductor layer located on the active layer and including a nitride semiconductor;
A first electrode electrically connected to the first conductive semiconductor layer; And
And a second electrode electrically connected to the second conductive semiconductor layer.

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