WO2014034003A1 - Control device for rectifier circuit device and rectifier circuit device - Google Patents

Control device for rectifier circuit device and rectifier circuit device Download PDF

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Publication number
WO2014034003A1
WO2014034003A1 PCT/JP2013/004091 JP2013004091W WO2014034003A1 WO 2014034003 A1 WO2014034003 A1 WO 2014034003A1 JP 2013004091 W JP2013004091 W JP 2013004091W WO 2014034003 A1 WO2014034003 A1 WO 2014034003A1
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Prior art keywords
voltage
chopping
rectifier circuit
circuit device
phase width
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PCT/JP2013/004091
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French (fr)
Japanese (ja)
Inventor
吉田 泉
京極 章弘
吉朗 土山
川崎 智広
シンホイ 戴
Original Assignee
パナソニック株式会社
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Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to CN201380044880.6A priority Critical patent/CN104604113B/en
Priority to JP2014532739A priority patent/JP6145896B2/en
Publication of WO2014034003A1 publication Critical patent/WO2014034003A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0083Converters characterised by their input or output configuration
    • H02M1/0085Partially controlled bridges
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/42Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208Arrangements for improving power factor of AC input
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/42Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208Arrangements for improving power factor of AC input
    • H02M1/4225Arrangements for improving power factor of AC input using a non-isolated boost converter
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/12Arrangements for reducing harmonics from ac input or output
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/46Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a control device for a rectifier circuit device that rectifies alternating current from an alternating current power source into direct current, and more particularly, to a rectifier circuit device that rectifies alternating current from a single-phase alternating current power source such as home to form substantially direct current.
  • the present invention relates to a control device and a rectifier circuit device.
  • the rectifier circuit device is applied to a circuit device for driving a direct current load, and a device for converting the formed direct current again to an alternating current of an arbitrary frequency by an inverter circuit to drive a motor as a load at variable speed. Be done.
  • the rectifier circuit device according to the present invention constitutes, for example, a heat pump by compressing a refrigerant with a compressor, and is applied to a device that performs cooling, heating, refrigeration of food or the like, and is included in the power supply current in such a device.
  • the load on the transmission system is reduced by reducing the harmonic components to be reduced and improving the power factor to perform drive control with high efficiency.
  • FIG. 18 is a circuit diagram showing a configuration of a rectifier circuit device disclosed in Patent Document 1
  • FIG. 19 is a block diagram showing a configuration of a control unit in the rectifier circuit device of FIG.
  • both output terminals of the AC power supply 1 form a closed circuit by the on state of the semiconductor switch 3c via the rectifier bridge 2 and the reactor 3a, and charge the reactor 3a with current.
  • the semiconductor switch 3c is turned off, a current is supplied to the load 4 by the diode 3b.
  • the rectifier circuit device of FIG. 18 has a configuration in which the power supply current flows even in a period when the instantaneous voltage of the AC power supply 1 is low, the harmonic component of the power supply current decreases, and the power factor is improved.
  • the semiconductor switch 3 c is finely turned on / off at a frequency sufficiently higher than the frequency of the AC power supply 1 to chop the AC voltage of the AC power supply 1 (hereinafter, “semiconductor When the switch is operated for chopping operation or “chopping by semiconductor switch”, a current flows through the semiconductor switch 3c, which causes a problem of circuit loss.
  • the AC voltage from AC power supply 1 is rectified by rectifier bridge 2 and converted to a DC voltage including pulsation, and then the power is smoothed through reactor 3a and diode 3b.
  • the capacitor 3 d and the load 4 are supplied.
  • a rectifier circuit device with a power factor improving function by the known step-up chopper circuit 3 can be obtained by configuring so that the output voltage from the rectifier bridge 2 can be shorted by the semiconductor switch 3c via the reactor 3a. It is configured.
  • the step-up chopper circuit 3 detects the input current by the input current detector 6 and the input current detection unit 10, and the input voltage detected by the input voltage detection unit 11 of the waveform of the input current
  • the semiconductor switch 3c is subjected to chopping operation so as to have the same shape as the waveform (power supply voltage waveform), and the magnitude of the input current is adjusted so that the output voltage becomes a desired voltage.
  • Patent Document 1 proposes reducing the loss of the circuit by chopping the semiconductor switch only in the minimum section for reducing the number of harmonics.
  • FIG. 19 is a block diagram showing a control method for the proposal.
  • the phase of the power supply voltage is detected by the power supply zero cross detection means 5, and the chopping operation of the semiconductor switch 3c of FIG. 18 is permitted only for a fixed period by the pulse counter 13a. Is held to be off.
  • this control method a rectifier circuit device with low loss without increasing the power supply harmonics is realized.
  • the input current is substituted by the current after being rectified once, information on the absolute value of the input current is obtained, and the magnitude of this absolute value is calculated. It is a configuration to adjust. It is widely known that adjusting the magnitude of the absolute value of the input current in this manner is equivalent to adjusting the amplitude of the input current.
  • the output voltage is controlled to be constant under the condition that the load is determined, and the period during which the semiconductor switch is chopping is also fixed. Therefore, when the detected output voltage includes an error, the current waveform is changed.
  • the current waveform changes largely when the DC voltage changes by only 1 V.
  • the accuracy of 1 V with respect to 280 V of the DC voltage corresponds to 0.3%, and in the case of dividing the voltage by resistors to form a low voltage, a resistor with very high accuracy is required.
  • the control method in such a conventional rectifier circuit device is generally realized using a digital computer
  • the DC voltage has high resolution, that is, the number of bits.
  • a large number of analog-to-digital conversion (hereinafter referred to as "AD conversion") units are required, which increases the circuit load.
  • AD conversion analog-to-digital conversion
  • the object of the present invention is to solve the above-mentioned problems, and to reduce the power supply harmonic current according to the status of the connected load or an external command regardless of the detection accuracy of the output voltage. It is an object of the present invention to provide a control device and a rectifier circuit device of a rectifier circuit device which can reduce the loss of the circuit.
  • the control device of the rectifier circuit device is The chopping operation of the semiconductor switch shorts or opens the alternating voltage from the single phase alternating current power supply or the pulsating voltage obtained by rectifying the alternating current voltage through the reactor to rectify the single phase alternating current power supply into the direct current voltage.
  • Control device of the rectifier circuit device for supplying power to the load is A waveform forming unit that forms a target current waveform having the same frequency as the waveform of the AC voltage; An alternating current detection unit that detects an alternating current flowing from the single-phase alternating current power supply; A DC voltage detection unit that detects the DC voltage; A first control unit configured to control a chopping operation of the semiconductor switch such that a waveform of the detected alternating current substantially becomes the target current waveform; A second control unit configured to control an amplitude of the target current waveform such that the detected DC voltage substantially becomes a predetermined target DC voltage; The predetermined target DC voltage is controlled such that the chopping operation phase width in which the semiconductor switch is in the chopping operation state or the chopping pause phase width in which the semiconductor switch is in the chopping pause state is substantially equal to the predetermined phase width. And a third control unit.
  • the rectifier circuit device is The chopping operation of the semiconductor switch shorts or opens the alternating voltage from the single phase alternating current power supply or the pulsating voltage obtained by rectifying the alternating current voltage through the reactor to rectify the single phase alternating current power supply into the direct current voltage.
  • a rectifier circuit device for supplying power to the load A waveform forming unit that forms a target current waveform having the same frequency as the waveform of the AC voltage; An alternating current detection unit that detects an alternating current flowing from the single-phase alternating current power supply; A DC voltage detection unit that detects the DC voltage; A first control unit configured to control a chopping operation of the semiconductor switch such that a waveform of the detected alternating current substantially becomes the target current waveform; A second control unit configured to control an amplitude of the target current waveform such that the detected DC voltage substantially becomes a predetermined target DC voltage; The predetermined target DC voltage is controlled such that the chopping operation phase width in which the semiconductor switch is in the chopping operation state or the chopping pause phase width in which the semiconductor switch is in the chopping pause state is substantially equal to the predetermined phase width. And a third control unit.
  • the present invention it is possible to change a desired phase width in accordance with the status of a connected load or an external command, and a chopping operation to compare with a desired phase width regardless of the load fluctuation status.
  • a control device and a rectifier circuit device of a rectifier circuit device capable of realizing a rectification operation with less circuit loss and less harmonic current by accurately measuring a phase width or chopping idle phase width.
  • FIG. 1 is a circuit diagram showing a configuration of a rectifier circuit device according to a first embodiment of the present invention.
  • FIG. 2A is a block diagram showing a configuration of a control circuit in the rectifier circuit device of FIG.
  • FIG. 2B is a diagram showing a modification of control in the rectifier circuit device of FIG. 1, and is a block diagram showing a case where an output signal of a waveform shaper is used in processing of a chopping phase detector of a control circuit.
  • FIG. 2C is a diagram showing a modified example of control in the rectifier circuit device of FIG. 1 and is a block diagram showing a case where the output of the current detector is used in the processing of the chopping phase detector of the control circuit.
  • FIG. 2A is a block diagram showing a configuration of a control circuit in the rectifier circuit device of FIG.
  • FIG. 2B is a diagram showing a modification of control in the rectifier circuit device of FIG. 1, and is a block diagram showing a case where an output signal
  • FIG. 2D is a diagram showing a modification of control in the rectifier circuit device of FIG. 1, and is a block diagram showing a case where the output of the DC voltage detector is used in the processing of the chopping phase detector of the control circuit.
  • FIG. 2E is a diagram showing a modified example of control in the rectifier circuit device of FIG. 1, and is a block diagram showing a case where the output of the PWM modulator is used in the processing of the chopping phase detector of the control circuit.
  • FIG. 3A is a characteristic diagram of a target phase width setting unit when the desired phase width is a chopping operation phase width in the rectifier circuit device according to the present invention.
  • FIG. 3B is a characteristic diagram of a target phase width setting unit when the desired phase width is the chopping pause phase width in the rectifier circuit device according to the present invention.
  • FIG. 4A is a diagram for explaining a control operation according to a first operation example of the control device in the rectifier circuit device of FIG. 1, and (a) alternating voltage (hereinafter referred to as AC voltage) and rectified; A signal indicating the relationship with a direct current voltage (hereinafter referred to as a DC voltage), (b) a target current waveform to be controlled, and (c) an alternating current after actual control (hereinafter referred to as an AC current).
  • FIG. 4B is a diagram for explaining a control operation according to a second operation example of the control device in the rectifier circuit device of FIG. 1, and (a) relationship between AC voltage and DC voltage after rectification; b) A signal waveform diagram showing a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 5A is a diagram for explaining a control operation according to a third operation example of the control device in the rectifier circuit device of the second embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 5B is a diagram for explaining the control operation according to the fourth operation example of the control device in the rectifier circuit device of the second embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 6A is a diagram for explaining the control operation according to the fifth operation example of the control device in the rectifier circuit device of the embodiment 3 of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 6B is a diagram for explaining the control operation according to the sixth operation example of the control device in the rectifier circuit device of the embodiment 3 of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 7A is a diagram for explaining a control operation according to a seventh operation example of the control device in the rectifier circuit device of the fourth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 7B is a diagram for explaining the control operation according to the eighth operation example of the control device in the rectifier circuit device of the fourth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 8A is a diagram for explaining the control operation according to the ninth operation example of the control device in the rectifier circuit device of the fifth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification;
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 8B is a diagram for explaining the control operation according to the tenth operation example of the control device in the rectifier circuit device of the fifth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 9A is a diagram for explaining a control operation according to an eleventh operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 9B is a diagram for explaining the control operation according to the twelfth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 10A is a diagram for illustrating a control operation according to a thirteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 10A is a diagram for illustrating a control operation according to a thirteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is
  • FIG. 10B is a diagram for explaining the control operation according to the fourteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 10C is a diagram for illustrating the control operation according to the fifteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 10B is a diagram for explaining the control operation according to the fourteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship
  • FIG. 10D is a diagram for explaining the control operation according to the sixteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control.
  • FIG. 11 is a circuit diagram showing a configuration of a rectifier circuit device according to a seventh embodiment of the present invention.
  • FIG. 12 is a circuit diagram showing a configuration of a rectifier circuit device according to an eighth embodiment of the present invention.
  • FIG. 13 is a circuit diagram showing a configuration of a rectifier circuit device according to a ninth embodiment of the present invention.
  • FIG. 14A is a diagram for explaining a first operation example of the binarization processing of the voltage level comparator in the rectifier circuit device according to the first to ninth embodiments of the present invention, in which It is a signal waveform diagram which shows the relationship with a threshold voltage (Vth), and the binary signal from (b) voltage level comparator.
  • FIG. 14B is a diagram for explaining a second operation example of the binarization processing of the voltage level comparator in the rectifier circuit device according to the first to ninth embodiments of the present invention; It is a signal waveform diagram which shows the relationship with a threshold voltage (Vth), and the binary signal from (b) voltage level comparator.
  • Vth threshold voltage
  • Vth binary signal from (b) voltage level comparator
  • FIG. 15 is a block diagram showing a detailed configuration of a control circuit in a rectifier circuit device according to a tenth embodiment of the present invention.
  • FIG. 16 is a block diagram showing a detailed configuration of a low pass filter computing unit (hereinafter referred to as “LPF computing unit”) in the rectifier circuit device of FIG.
  • FIG. 17 is a diagram showing the operation of the rectifier circuit device of FIG. 15, and (a) AC current (Iac) from AC power supply, (b) DC voltage (Vdc), (c) AD converter
  • FIG. 7 is a signal waveform diagram showing an AD conversion value (Vad) (the DC voltage Vdc is indicated by a dotted line). It is a circuit diagram which shows the structure of the conventional rectifier circuit apparatus. It is a block diagram which shows the detailed structure of the control part in the conventional rectifier circuit apparatus of FIG.
  • the control device for a rectifier circuit device according to the first aspect of the present invention is The chopping operation of the semiconductor switch shorts or opens the alternating voltage from the single phase alternating current power supply or the pulsating voltage obtained by rectifying the alternating current voltage through the reactor to rectify the single phase alternating current power supply into the direct current voltage.
  • the controller is A waveform forming unit (201, 202) for forming a target current waveform having the same frequency as the waveform of the AC voltage; An alternating current detection unit (103) for detecting an alternating current flowing from the single-phase alternating current power supply; A DC voltage detection unit (110) for detecting the DC voltage; A first control unit (208, 209, 210, 211) for controlling the chopping operation of the semiconductor switch so that the waveform of the detected alternating current (Iac) substantially becomes the target current waveform; A second control unit (206, 207) for controlling the amplitude of the target current waveform such that the detected DC voltage (Vdc) substantially becomes a predetermined target DC voltage (Vdc * ); The predetermined value is set such that the chopping operation phase width ( ⁇ w ON ) in which the semiconductor switch is in the chopping operation state or the chopping pause phase width ( ⁇ w OFF ) in which the semiconductor switch is in the chopping pause state
  • the load state is such that the predetermined phase width in the first aspect is in the range of 0 degrees to 180 degrees with respect to a power supply half cycle Alternatively, it is configured to be changed and set in accordance with an external command.
  • the load status in the second aspect is the value of the alternating current, the input power calculated based on the alternating current, or It is configured as indicated by the output power of the rectifier circuit device.
  • the polarity of the alternating voltage is fixed in the third control unit according to any one of the first to third aspects.
  • the predetermined target DC voltage so that the chopping pause phase width or the instantaneous value of the chopping operation phase width detected within the period, or the average value by the number of times set in advance, substantially becomes the predetermined phase width are configured to control the
  • the third control unit according to any one of the first to third aspects is characterized in that the direct current in the predetermined period is lowest.
  • the predetermined target DC voltage so that the chopping pause phase width or chopping operation phase width detected within a period in which the polarity of the AC voltage is fixed, including voltage time, is substantially equal to the predetermined phase width.
  • the third control unit according to any one of the first to third aspects is the largest alternating current in a predetermined period.
  • the predetermined target DC voltage is set so that the chopping pause phase width or chopping operation phase width detected within a period in which the polarity of the AC voltage is fixed, including current, is substantially equal to the predetermined phase width. It is configured to control.
  • the polarity of the alternating voltage is fixed in the third control unit according to any one of the first to sixth aspects.
  • any phase width in the period or a total phase width is substantially a predetermined phase.
  • the predetermined target DC voltage is controlled to have a width.
  • the target current waveform according to any one of the first to seventh aspects has an instantaneous absolute value of the target current waveform (A) Within a period in which the polarity of the AC voltage is fixed, (a) From the start point of the period to a predetermined midpoint, at least increase or at least increase with time, and a partial period And (b) from the midpoint to the end point at least decrease or at least decrease with time and substantially constant so as to be constant over a period of time. After monotonically decreasing, it is set to have a period which becomes zero.
  • the target current waveform according to any one of the first to seventh aspects has an instantaneous absolute value of the target current waveform (A) Within a period in which the polarity of the alternating voltage is fixed, (a) from the start point of the period to a predetermined first intermediate point has a period which becomes zero with the passage of time, (b) From the first midpoint to the predetermined second midpoint, at least increasing, or at least increasing, and substantially monotonically increasing so as to be constant over a period of time, and (c) the second From the middle point to the end point is set to have a period that decreases at least or at least decreases with time and substantially monotonically decreases and then becomes zero so as to be constant in part of the period doing.
  • the control device for a rectifier circuit device is the control method according to any one of the first to ninth aspects, wherein the AC voltage is compared with a predetermined threshold voltage. It further comprises a phase detection unit (109) that generates a binary signal, The waveform forming unit detects a cycle and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the cycle and the phase of the detected AC voltage.
  • Form The third control unit is configured to detect a chopping operation phase width in which the semiconductor switch is in the chopping operation state or a chopping pause phase width in which the semiconductor switch is in the chopping suspension state based on the binary signal. ing.
  • control device for a rectifier circuit device according to an eleventh aspect of the present invention, in any one of the first to tenth aspects, the control device further includes: the DC voltage detection unit; An AD conversion unit (230) for AD converting the detected DC voltage to a digital voltage, and between the AD conversion unit and the second control unit, And a calculation unit (231) for outputting the voltage of the calculation result as the detected direct current voltage to the second control unit after the low-pass filter calculation is performed on the digital voltage.
  • the control device of a rectifier circuit device is set such that the sampling frequency of the AD converter in the eleventh aspect is sufficiently higher than the frequency of the single-phase AC power supply. ing.
  • the low-pass filter computation in the eleventh aspect or the twelfth aspect further includes “(2 n ⁇ 1) / After multiplying by a factor (2 n ) (where n is an integer), it is added to the input digital voltage and executed using the value of the addition result as the next calculation result.
  • a rectifier circuit device includes the control device of the rectifier circuit device according to any one of the first to thirteenth aspects.
  • the DC voltage is adjusted to a relatively appropriate value, and the current waveform becomes the same as the input voltage waveform, and the load condition Or, by changing the desired phase width according to an external command, or by accurately measuring the chopping operation phase width or chopping pause phase width to be compared with the desired phase width regardless of the load fluctuation state. It is always possible to realize a rectification operation with low circuit loss and low harmonic current.
  • the DC voltage is converted into a digital signal by the AD conversion unit and detected, and the obtained digital signal is subjected to low pass filter calculation (LPF calculation) for each period.
  • LPF calculation low pass filter calculation
  • rectifier circuit device and control circuit of the present invention are not limited to the configurations of the rectifier circuit device and control circuit described in the following embodiments, and are equivalent to the technical idea described in the following embodiments. Including those based on the technical ideas of Further, in each of the following embodiments, components having the same functions will be described with the same reference numerals.
  • FIG. 1 is a circuit diagram showing a configuration of a rectifier circuit device according to a first embodiment of the present invention.
  • a single loop is configured by shorting both output terminals of single-phase AC power supply 1 with semiconductor switch 104 via reactor 102.
  • the current detector 103 which is an alternating current detection unit, detects the current of the loop, and outputs a signal indicating the detected current value Iac to the control circuit 100.
  • the semiconductor switch 104 is turned on, the current of the reactor 102 is increased.
  • the semiconductor switch 104 is turned off, the current flowing to the reactor 102 is rectified by the diode bridge circuit 105, and the rectified current flows to the smoothing capacitor 106 and the load 4 to drive the load 4.
  • the DC voltage Vdc across the smoothing capacitor 106 applied to the load 4 is detected by the DC voltage detector 110, and the DC voltage detector 110 outputs a signal indicating the detected DC voltage Vdc to the control circuit 100.
  • the voltage level comparator 109 which is a phase detection unit of the AC voltage input from the AC power supply 1, compares the AC voltage level of the AC power supply 1 with a predetermined threshold voltage to obtain the threshold voltage or more. Is generated and output to the control circuit 100.
  • the control circuit 100 detects the phase of the AC voltage output from the AC power supply 1 based on the period and the phase of the binary signal Scom.
  • the control circuit 100 generates a target current waveform having substantially the same frequency as the AC voltage and having a similar shape to the AC voltage based on the phase of the detected AC voltage, and is detected by the current detector 103.
  • the semiconductor switch 104 is controlled to chopping so that the current value Iac approaches the similar shape of the generated target current waveform.
  • control circuit 100 is similar to the target current waveform to be generated according to the deviation so that DC voltage Vdc detected by DC voltage detector 110 becomes the desired voltage set in control circuit 100. Adjust the ratio.
  • the control circuit 100 increases the similarity ratio of the target current waveform to control so as to be a large current, and the actual DC voltage Vdc is desired. If it is higher than the DC voltage, control is made to be a small current.
  • the control circuit 100 detects a phase width driving the semiconductor switch 104 by pulse width modulation (hereinafter referred to as "PWM") based on the chopping state of the semiconductor switch 104, and the phase width and a desired value. And the desired DC voltage value is adjusted according to the deviation.
  • PWM pulse width modulation
  • FIG. 2A is a block diagram showing the detailed configuration of the control circuit 100 of FIG.
  • the final control target as the control system is to control the chopping operation phase width ⁇ w ON in which chopping driving is performed to a desired phase width ⁇ w ON * from the target phase width setter 203.
  • the AC voltage phase detector 201 detects an AC phase based on a binary signal Scom binarized by comparing the voltage level of the AC power supply 1 with a predetermined threshold voltage Vth, and detects AC.
  • a signal indicating the phase is output to the target current waveform shaper 202 and the chopping phase width detector 212.
  • the target current waveform former 202 generates a predetermined target current waveform, which will be described in detail later, and outputs it to the multiplier 208.
  • a waveform forming unit that forms a target current waveform having the same frequency as the waveform of AC voltage by AC voltage phase detector 201 and target current waveform shaper 202 in control circuit 100 is provided. It is configured.
  • the chopping phase width detector 212 is an AC voltage indicated by the signal from the AC voltage phase detector 201 based on the original signal of the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation operator 210 to the PWM modulator 211.
  • Phase width in the chopping state (hereinafter referred to as “chopping operation phase width” or simply “chopping phase width”) ⁇ w ON is detected, and a signal indicating the chopping phase width ⁇ w ON is subtracted from the phase of the phase Output to 204.
  • the target phase width setting unit 203 subtracts a signal indicating a desired chopping phase width ⁇ w ON * according to a preset relationship from the actual current value Iac detected by the current detector 103 which is a current detection unit. Output to
  • FIG. 3A shows the desired chopping phase width ⁇ w ON * output from the target phase width setter 203 and the actual current value Iac detected by the current detector 103 input to the target phase width setter 203.
  • the desired chopping phase width ⁇ w ON * increases as the actual current value Iac increases.
  • the front and back are made flat, and between them is assumed to be connected by a smooth straight line, but as characteristics showing the relationship between the chopping phase width ⁇ w ON * and the current value Iac, it is shown in FIG. It is not limited to the following characteristics.
  • the horizontal axis is described as the actual current value Iac, but the input power calculated based on the current value Iac or the current detector 112 for detecting the current flowing to the load 4 Similar results can be obtained using the output and the output power of the rectifier circuit device obtained from the output of the DC voltage detector 110 which is the DC voltage detector.
  • the subtractor 204 is a so-called phase comparator, which subtracts the desired chopping phase width ⁇ w ON * from the actual chopping phase width ⁇ w ON to calculate the deviation of the phase width and phase the signal indicating the deviation It is output to the width compensation computing unit 205.
  • the phase width compensation computing unit 205 generates a command voltage Vdc * of the DC voltage to be output by the rectifier circuit device by performing a predetermined compensation operation to keep the phase width of the PWM drive state stable.
  • a signal indicating command voltage Vdc * is output to subtractor 206.
  • a signal indicating the actual output DC voltage Vdc detected by the DC voltage detector 110 which is a DC voltage detection unit is input to the subtractor 206.
  • the subtractor 206 subtracts the actual output DC voltage Vdc from the command voltage Vdc * of the DC voltage to calculate a voltage deviation, generates a signal indicating the voltage deviation, and outputs the signal to the Vdc compensation computing unit 207.
  • the Vdc compensation computing unit 207 multiplies the signal indicating the voltage deviation after the compensation operation by executing the compensation operation for the actual DC voltage Vdc to substantially coincide with the command voltage Vdc * and become stable.
  • the multiplier 208 multiplies the target current waveform from the target current waveform former 202 by the voltage deviation after the compensation operation, forms an instantaneous current command value Iac * which is the multiplication result, and outputs the current command value Iac * to the subtractor 209 Do.
  • the amplitude of the target current waveform is increased when the actual voltage Vdc is lower than the command voltage Vdc *, while the amplitude of the target current waveform is increased when the actual voltage Vdc is higher than the command voltage Vdc *.
  • the subtractor 209 subtracts the actual current value Iac detected by the current detector 103 from the instantaneous current command value Iac * to output a signal indicating a current deviation as a subtraction result to the Iac compensation computing unit 210.
  • the Iac compensation operation unit 210 performs a predetermined compensation operation so that the current input from the AC power supply 1 stably and promptly substantially matches the current command value Iac * , and the current deviation after the compensation operation is calculated.
  • the signal shown is output to the PWM modulator 211 and the chopping phase width detector 212.
  • the PWM modulator 211 generates a chopping drive signal Sch for turning on / off the semiconductor switch 104 by performing PWM modulation on the current deviation after the compensation operation indicated by the input signal, and outputs the chopping drive signal Sch to the semiconductor switch 104.
  • the chopping phase width detector 212 generates the AC voltage phase detector 201 based on the original signal of the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation operation unit 210 to the PWM modulator 211.
  • the chopping phase width ⁇ w ON is detected on the basis of the phase of the AC voltage indicated by the signal from the signal D.2 and a signal indicating the chopping phase width ⁇ w ON is output to the subtractor 204. This constitutes a control loop of chopping phase width.
  • the amplitude of the target current is controlled to perform chopping drive control so that the DC voltage Vdc substantially matches the desired DC voltage Vdc * indicated by the phase width compensation computing unit 205. Furthermore, in the loop on the right side of the subtractor 209 in FIG. 2A (the loop from 209 to 210, 211, 104, and 103 to return to 209), the current Iac detected by the current detector 103 is the target current waveform The chopping drive is controlled so as to substantially match the target current Iac * generated based on the target current waveform formed by the former 202.
  • FIG. 4A is a diagram for explaining a control operation according to a first operation example of the control device in the embodiment 1, wherein (a) relationship between AC voltage and DC voltage after rectification; (b) It is a signal waveform diagram which shows the target current waveform which should be controlled, and (c) AC current after actually controlling.
  • FIG. 4B is a diagram for explaining the control operation according to the second operation example of the control device in the first embodiment, and (a) relationship between AC voltage and DC voltage after rectification; b) A signal waveform diagram showing a target current waveform to be controlled and (c) an AC current after actual control.
  • the DC voltage to be output is relatively low, and the chopping phase width (for example, the minimum phase width) ⁇ w ON for the semiconductor switch 104 is smaller than the desired phase width ⁇ w ON * It is the case.
  • the chopping phase width for example, the minimum phase width
  • ⁇ w ON for the semiconductor switch 104
  • the current flowing from the AC power supply 1 to the DC side via the reactor 102 and the diode bridge circuit 105 increases. Therefore, the waveform of the AC current is sharpened, and the harmonic component of the AC current is increased.
  • the output DC voltage is relatively high, and the chopping phase width (for example, maximum phase width) ⁇ w ON for the semiconductor switch 104 is larger than the desired phase width ⁇ w ON * This is the case.
  • the phase period in which the AC voltage is higher than the DC voltage decreases in comparison with the first operation example, the current flowing from the AC power supply 1 to the DC side via the reactor 102 and the diode bridge circuit 105 also decreases. , The harmonic component of the AC current is reduced.
  • the period during which the semiconductor switch 104 is chopping is increased as compared to the waveform in the first operation example of FIG. Resulting in.
  • the chopping phase width detector 212 may select the chopping phase width close to 0 degree or 180 degrees of the phase of the AC voltage as the control chopping phase width to perform the chopping control. Also, the chopping phase width detector 212 controls the phase width closer to the reference phase for determining the polarity of the AC current or the AC voltage instead of 0 degree or 180 degrees of the phase of the AC voltage. May be selected to perform the chopping control. Furthermore, the chopping phase width detector 212 may perform the chopping control by adding the plurality of obtained chopping phase widths and using the phase width of the addition result as the control chopping phase width.
  • the control device in the rectifier circuit device includes, together with the control circuit 100, a current detector 103 which is an alternating current detection unit, and a current detector 112 which is a direct current detection unit. It includes a DC voltage detector 110 which is a DC voltage detection unit, and a voltage level comparator 109.
  • control circuit 100 in the first embodiment is functionally divided into a waveform shaping unit, a first control unit, a second control unit, and a third control unit.
  • the first control unit controls the chopping operation of the semiconductor switch 104 so that the waveform of the detected alternating current Iac substantially becomes the target current waveform.
  • the first control unit is composed of a multiplier 208, a subtractor 209, an Iac compensation operation unit 210, and a PWM modulator 211.
  • the second control unit controls the amplitude of the target current waveform so that the detected DC voltage Vdc substantially becomes a predetermined target DC voltage Vdc * .
  • the second control unit is configured of a subtractor 206 and a Vdc compensation computing unit 207.
  • the third control unit sets a predetermined target such that the chopping operation phase width in which the semiconductor switch 104 is in the chopping operation state or the chopping pause phase width in which the semiconductor switch 104 is in the chopping pause state is substantially the predetermined phase width.
  • the DC voltage Vdc * is controlled.
  • the third control unit is configured of the target phase width setting unit 203, the subtractor 204, the phase width compensation computing unit 205, and the chopping phase width detector 212.
  • the target phase width setting unit 203 is configured to obtain a desired chopping phase width ⁇ w ON * according to a preset relationship from the actual current value Iac detected by the current detector 103. It is also possible to cope with other configurations. For example, the target phase width setting unit 203 sequentially stores the maximum current (instantaneous value) obtained by the current detector 103 within the period in which the polarity of the AC voltage is fixed, and the most among the preset number. A large current may be extracted and used as the phase width setting current Iacp, and may be used instead of the actual current Iac. Alternatively, in the target phase width setting unit 203, the average value using the maximum current (instantaneous value) stored in the preset number of times may be used as the phase width setting current Iacp and used instead of the actual current Iac. Good.
  • the target phase width setter 203 is calculated based on the input power calculated based on the actual current Iac, not the actual current Iac, or the DC voltage detector 110 and the current detector 112. Output power may be used.
  • an instruction signal may be given from the outside so that a desired chopping phase width ⁇ w ON * is switched by a rotation speed command to the motor.
  • an instruction signal (not shown) is externally provided so that the desired chopping phase width ⁇ w ON * is switched from the requirement of the entire system including the rectifier circuit device such as requiring a high power factor or a high DC voltage under a specific condition. It may be a method. In this method, the desired chopping phase width ⁇ w ON * may be 180 degrees to perform the entire area switching. Furthermore, a method combining these methods may be used.
  • the AC voltage phase detector 201 is used based on the original signal of the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation operator 210 to the PWM modulator 211.
  • the chopping operation phase width .theta.w ON is detected based on the phase of the AC voltage indicated by the signal C.
  • FIG. 2B, FIG. 2C, FIG. 2D or FIG. The same effects can be obtained even with the configuration as shown.
  • a waveform shaper 111 to which a chopping drive signal Sch is input is provided, and a binary signal of a portion in which the waveform shaper 111 continuously switches the chopping drive signal Sch and a portion in which the switching is stopped. And outputs the binary signal to the chopping phase width detector 212.
  • the chopping phase width detector 212 extracts the chopping phase width from a portion corresponding to a portion in which switching of the binary signal is continuous based on the phase of the AC voltage indicated by the signal from the AC voltage phase detector 201 and extracts the chopping phase width.
  • the chopping phase width is set to the chopping operation phase width ⁇ w ON .
  • the configuration shown in FIG. 2B as described above also has the same effects as the configuration shown in FIG. 2A described above.
  • the chopping phase width detector 212 detects the chopping phase width during the period in which the polarity is fixed and the actual current value Iac output from the current detector 103 during the measurement period.
  • the chopping phase width at which the actual current value Iac is maximum may be extracted from a plurality of continuous measurement results in association with the maximum value, and the extracted chopping phase width may be set as the chopping operation phase width ⁇ w ON .
  • the reason why the maximum value of the actual current value Iac is linked and stored is that the chopping phase width is controlled focusing on the current waveform where the power supply harmonic level becomes the largest since the power supply harmonic level is proportional to the input current Thus, the power supply harmonics are controlled to the target level or less.
  • the reason why the chopping phase width detector 212 extracts from a plurality of continuous measurement results is that the measurement value of the chopping phase width once is different when the load 4 has a characteristic with pulsation.
  • the chopping phase width detector 212 detects the chopping phase width during the period in which the polarity is fixed and the DC voltage Vdc output from the DC voltage detector 110 during the measurement period.
  • the chopping phase width having the minimum DC voltage Vdc is extracted from a plurality of continuous measurement results in association with the minimum value, and the extracted chopping phase width is set as the chopping operation phase width ⁇ w ON .
  • the level of power supply harmonics is proportional to the input current. If this relationship is replaced with the DC voltage Vdc, the voltage drop of the DC voltage Vdc becomes large at the place where the load is the largest. Therefore, in the configuration shown in FIG. 2D, power harmonics are stored by being correlated with the minimum value of DC voltage Vdc, focusing on the current waveform where the power supply harmonic level is maximized, and chopping phase width control. It can be controlled below the target level.
  • the reason why extraction is performed from a plurality of continuous measurement results is that, in the case where the load 4 has a characteristic with pulsation, the measurement values of the chopping phase width once are different.
  • the chopping phase width detector 212 measures the number of pulses which is the output of the PWM modulator 211 during the period in which the polarity is fixed, and chopping period is measured
  • the chopping phase width may be calculated by multiplying the chopping phase width by the chopping operation phase width ⁇ w ON .
  • the power supply harmonic can be controlled to a target level or less by controlling the chopping phase width from the number of pulses actually driving the semiconductor switch.
  • the chopping phase width ⁇ w ON is detected and the DC voltage command Vdc * is adjusted using the phase width ⁇ w ON .
  • the phase width hereinafter referred to as “chopping pause phase width”
  • ⁇ w OFF in which chopping is in the pause state
  • the DC voltage command Vdc is detected using the chopping pause phase width ⁇ w OFF. Similar effects can be obtained by adjusting * .
  • the configurations of the rectifier circuit device and the control device of the second embodiment according to the present invention are substantially the same as the configurations of FIG. 1 and FIG. 2A described in the first embodiment,
  • the second embodiment will be described using the same reference numerals as the reference numerals in the first embodiment.
  • the relationship between the desired chopping phase width ⁇ w OFF * output from the target phase width setter 203 and the actual current value Iac detected by the current detector 103 input to the target phase width setter 203 is implemented. It is different from Form 1.
  • the figure shows an example of the relationship between the desired chopping phase width ⁇ w OFF * output from the target phase width setter 203 and the actual current value Iac detected by the current detector 103 input to the target phase width setter 203. Shown in 3B.
  • FIG. 3B shows the relationship between the desired chopping phase width ⁇ w OFF * output from the target phase width setter 203 and the actual current value Iac detected by the current detector 103 input to the target phase width setter 203.
  • An example is shown.
  • the characteristic shown in FIG. 3B is a characteristic in which the desired chopping phase width ⁇ w OFF * decreases as the actual current value Iac detected by the current detector 103 increases. With such characteristics, it is possible to give a characteristic that emphasizes reduction of the harmonic current at high input while emphasizing loss reduction since the magnitude of the harmonic current itself is small at low input. As a result, it is possible to provide characteristics aiming for loss reduction and suppression of harmonic current.
  • the horizontal axis is described as the actual current value Iac, but the input power calculated based on the current value Iac or the current detector 112 for detecting the current flowing to the load 4 Similar results are obtained using the output and the output power of the rectifier circuit device obtained from the output and the output of the DC voltage detector 110.
  • FIG. 5A is a diagram for explaining a control operation according to a third operation example of the control device in the rectifier circuit device of the second embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control.
  • FIG. 5B is a diagram for explaining a control operation according to a fourth operation example of the control device in the rectifier circuit device of the second embodiment of the present invention, and (a) after the rectification with the AC voltage. It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
  • the output DC voltage is relatively low, and the chopping pause phase width (for example, maximum phase width) ⁇ w OFF in which the semiconductor switch 104 is not chopping operated is large.
  • the chopping pause phase width for example, minimum phase width
  • ⁇ w OFF in which the output DC voltage is higher than in the third operation example and the semiconductor switch 104 is not chopping This is a case where the size is smaller than that of the third operation example. Since the chopping pause phase width ⁇ w OFF is complementary to the chopping operation phase width ⁇ w ON , the same function and effect can be obtained.
  • a section in which chopping is performed may appear a plurality of times during a half cycle of the AC voltage.
  • the chopping phase width detector 212 selects the chopping pause phase width ⁇ w OFF of the off period close to 90 degrees of the phase of the AC voltage as the chopping phase width for control and performs the chopping control. Good.
  • the chopping phase width detector 212 may perform the chopping control by adding the plurality of chopping pause phase widths obtained above and using the phase width of the addition result as the control chopping phase width.
  • FIGS. 5A and 5B show waveforms of only half cycles of the AC voltage, as is apparent from FIGS. 4A and 4B and the prior art, the remaining half cycles also have absolute values.
  • the waveform is the same as (instantaneous absolute value), and thus omitted.
  • the desired phase width setting unit 203 obtains the desired chopping pause phase width ⁇ w OFF * from the actual current value Iac detected by the current detector 103 according to a preset relationship.
  • the target phase width setting unit 203 sequentially stores the maximum current obtained by the current detector 103 within the period in which the polarity of the AC voltage is fixed, and extracts the largest current from the preset number of times.
  • the phase width setting current Iacp may be used instead of the actual current Iac.
  • the target phase width setting unit 203 may use an average value using the stored maximum current as the phase width setting current Iacp instead of the actual current Iac.
  • the target phase width setter 203 is calculated based on the input power calculated based on the actual current Iac, not the actual current Iac, or the DC voltage detector 110 and the current detector 112. Output power may be used.
  • an instruction signal may be given from the outside so that the desired chopping pause phase width ⁇ w OFF * is switched by a rotation speed command to the motor.
  • an instruction signal (not shown) is externally supplied so that the desired chopping pause phase width ⁇ w OFF * is switched from the requirement of the entire system including a rectifier circuit device such as a high power factor or a high DC voltage desired in a specific condition. It may be a method of giving. In this case, the desired chopping pause phase width ⁇ w OFF * may be set to 0 degrees to perform the entire region switching. Furthermore, a combined method of these methods may be used.
  • the AC voltage phase detector 201 is used based on the original signal of the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation operation unit 210 to the PWM modulator 211.
  • the chopping pause phase width ⁇ w OFF is detected on the basis of the phase of the AC voltage indicated by the signal of FIG. 2B, but the present invention is described with reference to FIGS. 2B, 2C, and 2 described in the first embodiment, for example. The same function and effect can be obtained with the configuration as shown in 2D or FIG. 2E.
  • a waveform shaper 111 to which the chopping drive signal Sch is input is provided, and a portion where the waveform shaper 111 continuously switches the chopping drive signal Sch and a portion where the switching stops
  • the binary signal is formed into a binary signal, and the binary signal is output to the chopping phase width detector 212.
  • the chopping phase width detector 212 extracts the chopping pause phase width from a portion corresponding to a portion where switching of the binary signal is paused based on the phase of the AC voltage indicated by the signal from the AC voltage phase detector 201,
  • the extracted chopping pause phase width may be set as the chopping pause phase width ⁇ w OFF .
  • the rectifier circuit device of the second embodiment has the configuration shown in FIG. 2B, it has the same function and effect as the configuration shown in FIG. 2A described above.
  • the chopping phase width detector 212 is outputted from the current detector 103 during the chopping pause phase width during the period in which the polarity is fixed and during the measurement period.
  • Chopping pause phase width in which the actual current value Iac is maximum is extracted from the continuous plural measurement results in association with the maximum value (instantaneous value) of the actual current value Iac.
  • the width may be a chopping pause phase width ⁇ w OFF .
  • the maximum value (instantaneous value) of the actual current value Iac is linked and stored for use because the power supply harmonic level is proportional to the input current, and focusing on the current waveform where the power supply harmonic level becomes the largest, the chopping phase width To control the power supply harmonics below the target level.
  • the reason why the chopping phase width detector 212 extracts from a plurality of continuous measurement results is that the measurement value of the chopping phase width once is different when the load 4 has a characteristic with pulsation.
  • the chopping phase width detector 212 is outputted from the DC voltage detector 110 during the chopping pause phase width during the period in which the polarity is fixed and the measurement period.
  • Chopping pause phase width with the minimum DC voltage Vdc is extracted from a plurality of continuous measurement results in association with the minimum value of the DC voltage Vdc, and the extracted chopping pause phase width is the chopping pause phase width ⁇ w OFF And
  • the level of power supply harmonics is proportional to the input current. If this relationship is replaced with the DC voltage Vdc, the voltage drop of the DC voltage Vdc becomes large at the place where the load is the largest. Therefore, in the configuration shown in FIG. 2D, the power harmonics are targeted by storing them in association with the minimum value of DC voltage Vdc, focusing on the current waveform where the power harmonics level becomes the largest, and controlling the chopping phase width. It can be controlled below the level.
  • the reason why extraction is performed from a plurality of continuous measurement results is that, in the case where the load 4 has a characteristic with pulsation, the measurement values of the chopping phase width once are different.
  • the rectifier circuit device according to the second embodiment has the configuration shown in FIGS. 2B to 2D, even if the load 4 has a characteristic with pulsation, it is excellent as in the configuration shown in FIG. 2A. It has an effect.
  • the rectifier circuit device of the third embodiment according to the present invention is a simplification of the control method of the rectifier circuit device of the first embodiment described above.
  • Chopping phase width detector 212 in the rectifier circuit device according to the third embodiment is a section (positive value) in which the polarity (sign) of AC voltage does not change and is fixed from 0 degrees or 180 degrees until chopping is stopped.
  • the phase width ⁇ 1w ON (chopping phase width) of the first half in the section or negative section) is detected, and the chopping control is performed using the phase width ⁇ 1w ON .
  • the configurations of the rectifier circuit device and the control device of the third embodiment according to the present invention are substantially the same as the configurations of FIG. 1 and FIG. 2A described in the first embodiment,
  • the third embodiment will be described using the same reference numerals as in the first embodiment.
  • FIG. 6A is a diagram for explaining the control operation according to the fifth operation example of the control device in the rectifier circuit device of the embodiment 3 of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control.
  • FIG. 6B is a diagram for explaining the control operation according to the sixth operation example of the control device in the rectifier circuit device of the third embodiment of the present invention, and (a) after rectification with AC voltage; It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
  • the output DC voltage is relatively low, and the phase width ⁇ 1w ON at which the semiconductor switch 104 is chopped is relatively small.
  • the output DC voltage is higher than that in the fifth operation example, and the phase width ⁇ 1w ON at which the semiconductor switch 104 is chopped is higher than that in the fifth operation example. It is the case of getting bigger.
  • the phase width ⁇ 1w ON where chopping of the first half is performed in the half cycle period of the AC voltage in the operation example shown in FIGS. 6A and 6B corresponds to FIG. 4A and FIG. Since there is a tendency similar to the tendency shown in, it is possible to obtain the same effect as that of the first embodiment.
  • Embodiment 4 a rectifier circuit device of a fourth embodiment according to the present invention and a control device in the rectifier circuit device will be described.
  • the rectifier circuit device of the fourth embodiment according to the present invention is a simplification of the control method in the rectifier circuit device of the first embodiment, similarly to the rectifier circuit device of the third embodiment described above.
  • the chopping phase width detector 212 in the rectifier circuit device according to the fourth embodiment is a section (positive value) in which the polarity (sign) of the AC voltage does not change and is fixed from 0 degrees or 180 degrees until chopping stops.
  • the chopping control is performed by detecting the second half phase width ⁇ 2w ON in the section or the negative section).
  • the configuration of the rectifier circuit device and the control device of the fourth embodiment according to the present invention is substantially the same as the configuration of FIG. 1 and FIG. 2A described in the first embodiment,
  • the fourth embodiment will be described using the same reference numerals as the reference numerals in the first embodiment.
  • FIG. 7A is a diagram for explaining a control operation according to a seventh operation example of the control device in the rectifier circuit device of the fourth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control.
  • FIG. 7B is a view for explaining the control operation according to the eighth operation example of the control device in the rectifier circuit device of the fourth embodiment of the present invention, and (a) after rectification with AC voltage; It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
  • the output DC voltage is relatively low, and the phase width ⁇ 2w ON (chopping phase width) at which the semiconductor switch 104 is chopping is relatively small.
  • the output DC voltage is higher than that in the seventh operation example, and the phase width ⁇ 2w ON at which the semiconductor switch 104 is chopped is higher than that in the seventh operation example. It is the case of getting bigger.
  • the phase width ⁇ 2w ON in which chopping in the second half is performed in the half cycle section of the AC power supply 1 in the operation example shown in FIGS. 7A and 7B corresponds to FIG. Since there is a tendency similar to the tendency shown in 4B, the same function and effect as those of Embodiment 1 can be obtained.
  • Rectifier circuit device of Embodiment 5 the chopping phase width Shitadaburyu1 ON in the rectifier circuit device of the third embodiment described above, the sum of the chopping phase width Shitadaburyu2 ON in the rectifier circuit of the fourth embodiment
  • the phase width ( ⁇ w1 ON + ⁇ w2 ON ) is detected by the chopping phase width detector 212, and the DC voltage is controlled so that the total phase width ( ⁇ w1 ON + ⁇ w2 ON ) becomes a desired phase width.
  • FIG. 8A is a diagram for explaining the control operation according to the ninth operation example of the control device in the rectifier circuit device of the fifth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification;
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control.
  • FIG. 8B is a diagram for explaining a control operation according to a tenth operation example of the control device in the rectifier circuit device of the fifth embodiment of the present invention, and (a) after the rectification with the AC voltage; It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
  • a ninth operation example in FIG. 8A DC voltage output is relatively low, the chopping phase width Shita1w ON of the first half of the semiconductor switch 104 is chopped, and the second half of the chopping phase width Shita2w ON is relatively small That's the case.
  • the output DC voltage is high compared to the ninth operation example, and the first half chopping phase width ⁇ 1w ON where the semiconductor switch 104 is chopping, and the second half chopping phase width In this case, ⁇ 2w ON is larger than that in the ninth operation example.
  • the rectifier circuit device of the fifth embodiment the half cycle of the period of the AC power supply 1 in the operation example shown in FIGS. 8A and 8B, the first half of the chopping phase width Shita1w ON, and the second half of the chopping phase width Shita2w ON is above Since there is a tendency similar to the tendency shown in FIGS. 4A and 4B, the same function and effect as those of Embodiment 1 to Embodiment 4 can be obtained.
  • FIG. 9A is a diagram for explaining a control operation according to an eleventh operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control.
  • FIG. 9B is a diagram for explaining the control operation according to a twelfth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) after rectification with AC voltage; It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
  • the control device in the rectifier circuit device of the sixth embodiment is characterized in that the circuit loss can be further reduced by setting the target current waveform to a waveform other than a sine wave, for example, a triangular wave.
  • a waveform other than a sine wave for example, a triangular wave.
  • the eleventh operation example of FIG. 9A is a case where the output DC voltage is relatively low, and the phase width ⁇ w ON at which the semiconductor switch 104 is chopped is smaller than the desired phase width ⁇ w ON * . Also at this time, since the phase period in which the AC voltage is higher than the DC voltage increases, the current flowing from the AC power supply 1 to the DC side via the reactor 102 and the diode bridge circuit 105 increases. Therefore, the waveform of the AC current is sharpened, and the harmonic component of the AC current is increased.
  • the output DC voltage is higher than in the eleventh operation example, and the phase width ⁇ w ON at which the semiconductor switch 104 is chopped is higher than the desired phase width ⁇ w ON * It is the case of getting bigger.
  • the phase period in which the AC voltage is higher than the DC voltage decreases, the AC current flowing from the AC power supply 1 to the DC side via the reactor 102 and the diode bridge circuit 105 decreases, and harmonic components of the AC current Decrease.
  • a period (phase width) in which the chopping of the semiconductor switch 104 is performed as compared with the waveform of the eleventh operation example of FIG. The loss of the circuit will increase because
  • the absolute value of the instantaneous value of the target current waveform is 0 degrees (start point) to 180 degrees (end point) of the AC voltage with the passage of time.
  • start point start point
  • end point 180 degrees
  • the absolute value of the instantaneous value of the target current waveform is 0 degrees (start point) to 180 degrees (end point) of the AC voltage with the passage of time.
  • chopping control may be performed based on the phase width of any of the two chopping pause phase widths, or the total phase width.
  • the chopping phase width ⁇ w ON is subtracted from the half cycle of the AC voltage to obtain the chopping pause phase width ⁇ w OFF .
  • control may be performed based on the obtained chopping pause phase width ⁇ w OFF by directly obtaining the chopping pause phase width ⁇ w OFF .
  • Modification of Embodiment 6 Modification of Embodiment 6
  • modifications of the rectifier circuit device and the control device according to the sixth embodiment of the present invention will be described with reference to FIGS. 10A to 10D.
  • the modification of the sixth embodiment according to the present invention has another shape different from the target current waveform shown in FIGS. 9A and 9B.
  • FIG. 10A is a diagram for illustrating a control operation according to a thirteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification
  • FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control.
  • FIG. 10B is a diagram for explaining the control operation according to the fourteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control. Furthermore, FIG.
  • FIG. 10C is a diagram for explaining a control operation according to a fifteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) after rectification with AC voltage. It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
  • FIG. 10D is a diagram for explaining a control operation according to a sixteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) after the rectification with the AC voltage. It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
  • the target current waveform in the thirteenth operation example of FIG. 10A is a predetermined value exceeding 90 degrees in the latter half, instead of a monotonically decreasing section with time. It is a triangular waveform configured to have a section (zero and constant section) which is instantaneously zeroed at the midpoint Tm of the phase (for example, 110 degrees).
  • the target current waveform in the fourteenth operation example of FIG. 10B is sinusoidally increased in a monotonously increasing section with time as compared with the target current waveform in the thirteenth operation example of FIG.
  • the waveform has a section (zero and constant section) which is instantaneously zero at a midpoint Tm of a predetermined phase (for example, 110 degrees) exceeding 90 degrees.
  • the target current waveform in the fifteenth operation example of FIG. 10C provides a constraint condition in the target current waveform in the fourteenth operation example of FIG. 10B, and the midpoint Tm before 90 degrees in the first half sine wave waveform.
  • the waveform is instantaneously zeroed at a phase of (for example, 70 degrees).
  • the target current waveform in the sixteenth operation example of FIG. 10D is zero (zero) for a predetermined period from 0 degrees to the first midpoint Tm1 over time in the target current waveform in the fifteenth operation example of FIG. And a constant interval), and thereafter, it is a waveform configured to monotonously increase up to the second midpoint Tm2.
  • the target current is set to zero before 90 degrees, but the chopping operation of the semiconductor switch 104 is before chopping operation before the phase to be zeroed. You can use it with a heavy load.
  • the DC voltage is lower than the maximum instantaneous voltage of the AC voltage, current flows from the AC power supply 1 via the reactor 102 and the diode bridge circuit 105 in the vicinity of 90 degrees. Therefore, even if the target current is zero, the AC current continues to flow for a while, and a current with few harmonic components can be realized with high efficiency.
  • the monotonous increase or decrease of the target current waveform may include a fixed period, that is, it may be substantially monotonically increased or substantially monotonically decreased.
  • substantially monotonically increasing refers to a monotonous increase in a broad sense having a relationship of f ( ⁇ 1) ⁇ f ( ⁇ 2) when the phase ⁇ 1 ⁇ 2 of the target current waveform. Over time, substantially monotonically increasing so as to at least increase or at least increase and be constant over a period.
  • substantially monotonically decreasing refers to a monotonous decrease in a broad sense in which f ( ⁇ 1) ⁇ f ( ⁇ 2) when the phase ⁇ 1 ⁇ 2 of the target current waveform. And substantially monotonically decreasing so as to at least decrease or at least decrease and be constant over a period of time.
  • FIG. 11 is a circuit diagram showing a configuration of a rectifier circuit device according to a seventh embodiment of the present invention.
  • the AC voltage from AC power supply 1 is rectified by a bridge circuit constituted of semiconductor switches 604a and 604b and diodes 605a, 605b, 605c and 605d via reactor 602,
  • the load 4 is driven via the smoothing capacitor 106.
  • the chopping control method in the rectifier circuit device of the seventh embodiment is the same as that of the control device in the rectifier circuit device of the first embodiment shown in FIG. 1 described above, and chopping drive signals for two semiconductor switches 604a and 604b. It drives simultaneously using Sch.
  • the chopping drive signal Sch in the rectifier circuit device of the seventh embodiment can be formed with the same configuration as that described with reference to FIGS. 2A to 2E in the first embodiment. Also in the rectifier circuit device of the seventh embodiment, similar effects can be obtained by performing the chopping control described in each of the above-described embodiments.
  • FIG. 12 is a circuit diagram showing a configuration of a rectifier circuit device according to an eighth embodiment of the present invention.
  • the rectifier circuit device according to the eighth embodiment rectifies AC voltage from AC power supply 1 with a bridge circuit configured of semiconductor switches 704a and 704b and diodes 705a, 705b, 705c and 705d via reactor 702. , Drive the load 4 via the smoothing capacitor 106.
  • the chopping control method in the rectifier circuit device of the eighth embodiment only one of the semiconductor switches 704a or 704b is selected using two chopping drive signals Sch1 and Sch2 according to the polarity of the AC voltage from AC power supply 1. It is what makes chopping work. For example, if the period in which the polarity of the AC voltage is connected to the reactor 702 is high, the chopping drive signal Sch2 is used to chopping the semiconductor switch 704b and the polarity of the AC voltage is connected to the reactor 702 is low If it is a period, the chopping drive signal Sch1 is used to chopping the semiconductor switch 704a.
  • the rectifier circuit device when the semiconductor switches 704 a and 704 b are simultaneously turned on, the DC output voltage to the load 4 is short-circuited. It may be necessary to set so that neither switch 704a nor 704b will be in an ON state.
  • the phase in which the chopping operation changes to the pause state can occur even near 0 degrees and 180 degrees.
  • the chopping operation is intentionally stopped to prevent a short circuit of the DC output voltage, so in the rectifier circuit device according to the eighth embodiment of the present invention, the chopping operation is performed near 0 degrees and 180 degrees. This can be easily realized by not handling the phase changed to the resting state.
  • the chopping drive signals Sch1 and Sch2 in the rectifier circuit device of the eighth embodiment can be formed with the same configuration as that described with reference to FIGS. 2A to 2E in the first embodiment described above. Also in the rectifier circuit device of the eighth embodiment, the same operation and effect can be achieved by performing the chopping control described in each of the above-described embodiments for each semiconductor switch.
  • FIG. 13 is a circuit diagram showing a configuration of a rectifier circuit device according to a ninth embodiment of the present invention.
  • the rectifier circuit device according to the ninth embodiment when the semiconductor switch 104 is on via the rectifier bridge 105 and the reactor 102 at both output terminals of the AC power supply 1, the reactor 102 is charged with current, and the semiconductor switch 104 is off. When it becomes, the smoothing capacitor 106 and the load 4 are driven by the diode 304.
  • the chopping drive signal Sch in the rectifier circuit device of the ninth embodiment can be formed with the same configuration as the configuration described using FIG. 2A to FIG. 2E in the first embodiment described above. Also in the rectifier circuit device of the ninth embodiment, similar effects can be obtained by performing the chopping control described in each of the above-described embodiments for each semiconductor switch.
  • FIG. 14A is a waveform diagram for describing a first operation example of the binarization processing of the voltage level comparator 109 in the rectifier circuit device according to the first to ninth embodiments of the present invention.
  • the waveform diagram of FIG. 14A shows (a) the relationship between the AC voltage and the threshold voltage Vth and (b) the binary signal from the voltage level comparator 109.
  • FIG. 14B is a waveform diagram for describing a second operation example of the binarization processing of the voltage level comparator 109 in the rectifier circuit device according to the first to ninth embodiments of the present invention.
  • the waveform chart of FIG. 14B shows (a) the relationship between the AC voltage and the threshold voltage Vth and (b) the binary signal from the voltage level comparator 109.
  • FIGS. 14A and 14B show a method of detecting a voltage phase from information on whether the AC voltage is equal to or higher than a certain level. This information is used to obtain, as a binary signal, whether the instantaneous voltage of the AC voltage exceeds a threshold. That is, the voltage level comparator 109 compares the AC voltage with the threshold voltage Vth, and outputs a high level signal when the AC voltage is higher than the threshold voltage Vth, while the AC voltage is lower than the threshold voltage Vth. When low level signal is output.
  • the cycle of the binary signal is the same as the power supply frequency, and if the middle point of the high level side or the low level side of the binary signal is determined, the AC voltage phase is 90 degrees. Or you can know the time of 270 degrees. Also, the midpoint of the AC voltage phase of 90 degrees and 270 degrees is 180 degrees and 0 degrees of phase. If the information obtained in this manner is multiplied using a PLL or the like, it is possible to accurately know the instantaneous phase.
  • the phase width during chopping operation becomes a desired phase width.
  • the same current waveform is obtained, and it is possible to realize the rectification operation with less circuit loss and less harmonic current.
  • FIG. 15 is a block diagram showing a detailed configuration of the control circuit 100 in the rectifier circuit device of the tenth embodiment according to the present invention.
  • the control circuit 100 in the rectifier circuit device of the tenth embodiment is between the DC voltage detector 110 and the subtractor 206 in comparison with the control circuit 100 in the rectifier circuit device of the first embodiment shown in FIG. 2A described above.
  • an AD converter 230 which is an AD conversion unit
  • a low pass filter operation unit (hereinafter referred to as “LPF operation unit”) 231 which is an operation unit.
  • the rectifier circuit device of the tenth embodiment provides an embodiment that is particularly effective when implemented by digital operation.
  • differences from the control circuit 100 shown in FIG. 2A will be described.
  • an analog signal indicating the DC voltage Vdc detected by the DC voltage detector 110 indicates an AD conversion value Vad by the AD converter 230 that AD converts at a sampling frequency sufficiently higher than the frequency of the AC power supply 1. It is converted to a digital signal.
  • the AD conversion value Vad from the AD converter 230 is input to the LPF computing unit 231 that performs computation (details will be described later) having low-pass filter characteristics, and is subjected to LPF computation.
  • a signal (LPF calculation value Vdca) indicating the calculation result in the LPF calculator 231 is output to the subtractor 206.
  • the frequency of the AC power supply 1 is 60 Hz
  • the sampling frequency is 600 kHz.
  • FIG. 16 is a block diagram showing a detailed configuration of the LPF computing unit 231 in the control circuit 100 shown in FIG.
  • the signal indicating the AD conversion value Vad from the AD converter 230 is input to the adder 253 in the LPF computing unit 231.
  • the adder 253 adds the signal indicating the AD conversion value Vad to be input and the signal from the constant multiplier 251, and outputs a signal indicating the LPF operation value Vdca which is the addition result to the subtractor 206.
  • the signal is output to the constant multiplier 251 via the delay unit 252 delayed by one clock time.
  • the constant multiplier 251 multiplies the input signal by a predetermined constant (2 n -1) / (2 n ), and outputs a signal indicating the multiplication result to the adder 253.
  • This LPF calculation processing is a linear low-pass filter having a time constant of “2 n ” times the calculation cycle, and the amplitude is “2 n ” times. Therefore, by executing this LPF calculation process, n bits of information after the decimal point are added to the AD conversion value Vad.
  • FIG. 17 is a signal waveform diagram representing an operation of control circuit 100 in the rectifier circuit device shown in FIG.
  • (b) DC voltage Vdc, and (c) AD conversion value Vad of AD converter 230 are shown.
  • the DC voltage Vdc is indicated by a dotted line. That is, FIG. 17 shows an operation principle capable of improving voltage detection accuracy by performing low-pass filter processing with a single-phase AC rectifier circuit.
  • FIG. 17 shows a DC voltage Vdc indicated by a dotted line and an AD conversion value Vad when the DC voltage Vdc is AD converted at a sampling frequency sufficiently higher than the frequency of the AC power supply 1.
  • a sufficiently high sampling frequency means a frequency twice or more that of the AC power supply 1.
  • the obtained AD conversion value Vad takes values of K, K + 1, K + 2, K + 3,.
  • the low-pass filter calculation is performed on the AD conversion value Vad, in the case of FIG. 17, the value converges to a value between (K + 1) and (K + 2). Furthermore, as shown in FIG.
  • command voltage Vdc * also needs to have the same resolution as that of the AD converter 230. Since command voltage Vdc * is only information, it is possible to easily realize an increase in resolution as in the above-described tenth embodiment.
  • the LPF operation has been described as an example using a power of 2, if the constant of the constant multiplier 251 is set to a value between 0 and 1, the LPF operation can be realized similarly. Further, as is clear from the operation principle of FIG. 17, similar effects can be obtained by methods other than the configuration shown in FIG.
  • the method for improving the voltage detection accuracy in the rectifier circuit device of the tenth embodiment can be implemented in combination with the first to ninth embodiments described above.
  • the term “substantially” is used to mean approximately or on average.
  • the DC voltage is adjusted to a relatively appropriate value.
  • the same current waveform can be obtained, and the desired phase width can be changed in accordance with the load condition or an external command.
  • circuit loss is always reduced and harmonic current is constantly measured by accurately measuring the chopping operation phase width or chopping pause phase width to be compared with the desired phase width regardless of the load fluctuation state. Can realize a rectification operation with less
  • the DC voltage is converted into a digital signal by the A / D conversion unit and detected at a sampling frequency sufficiently higher than the frequency of the AC power supply, and the obtained digital signal is subjected to LPF calculation for each cycle. Then, it is added to the digital signal so as to interpolate minute information below the resolution. Furthermore, in the present invention, a digital signal obtained by interpolating minute information is used as DC voltage information, and the digital signal obtained by interpolating the minute information is adjusted so that the phase width actually being chopping becomes a desired value. .
  • the power supply frequency component contained in the smoothed voltage of the DC voltage has fluctuations, and even if the resolution of the digital information is coarse, the digital signals are dispersed by the fluctuations. It is possible to obtain a digital signal equivalent to By this, in the present invention, even if coarse resolution AD conversion means are used, the average value of DC voltage can be adjusted with high accuracy, and a rectification operation with less loss and less harmonic current is always realized. can do. Therefore, the rectifier circuit device according to the present invention can realize the rectification operation with less loss and less harmonic current by changing the desired phase width according to the state of the connected load.
  • the configuration of the rectifier circuit device and the control circuit of the present invention can be easily realized by not treating the chopping in the present invention as a phase changed to the inactive state.
  • the AC voltage phase detector 201 detects the phase of the AC voltage, and the chopping phase width is detected based on the detected phase. It is not limited to such a configuration.
  • the chopping phase width may be detected based on information such as the zero cross of the AC power supply.
  • the time of the chopping phase width may be measured by counting by the number of pulses of the carrier signal for realizing the PWM control which is an example of the chopping method.
  • the rectifier circuit device can achieve both suppression of harmonic current and reduction of circuit loss. Therefore, a heat pump is configured by compressing a refrigerant with a compressor, and cooling, heating, food, etc. It can be widely applied to various applications such as those that perform refrigeration.
  • Reference Signs List 1 AC power supply 4 load 100 control circuit 102, 602, 702 reactor 103, 112 current detector 104, 604a, 604b, 704a, 704b semiconductor switch 105 diode bridge circuit 106 smoothing capacitor 109 voltage level comparator 110 DC voltage detector 111 waveform Shaper 201 AC voltage phase detector 202 Target current waveform shaper 203 Target phase width setter 204, 206, 209 Subtractor 205 Phase width compensation computing unit 207 Vdc compensation computing unit 208 Multiplier 210 Iac compensation computing unit 211 PWM modulator 212 Chopping phase width detector 230 AD converter 231 low pass filter calculator (LPF calculator) 251 constant multiplier 252 delay device 253 adder 605a to 605d, 705a to 705d diode

Abstract

The rectifier circuit device of the present invention comprises a control device that is configured to: control the chopping of a semiconductor switch (104) so that the waveform of a detected current becomes a target current waveform; control the amplitude of the target current waveform so that a detected DC voltage becomes a predetermined target DC voltage; and to control the target DC voltage so that either a chopping operation phase width that is a state in which chopping operation is performed by the semiconductor switch (104) or a chopping pause phase width that is a state in which chopping by the semiconductor switch (104) is paused becomes a predetermined phase width set in accordance with load conditions and a command from the outside.

Description

整流回路装置の制御装置および整流回路装置Control device for rectifier circuit device and rectifier circuit device
 本発明は、交流電源からの交流を直流に整流する整流回路装置の制御装置および整流回路装置に関し、特に、家庭などの単相交流電源からの交流を整流して略直流を形成する整流回路装置の制御装置および整流回路装置に関する。 The present invention relates to a control device for a rectifier circuit device that rectifies alternating current from an alternating current power source into direct current, and more particularly, to a rectifier circuit device that rectifies alternating current from a single-phase alternating current power source such as home to form substantially direct current. The present invention relates to a control device and a rectifier circuit device.
 本発明に係る整流回路装置は、直流負荷を駆動する回路装置や、形成された直流をインバータ回路により、再度、任意周波数の交流に変換して、負荷である電動機を可変速度駆動する装置に適用される。本発明に係る整流回路装置は、例えば、圧縮機により冷媒を圧縮することによりヒートポンプを構成し、冷房、暖房、又は食品などの冷凍を行う装置に適用され、そのような装置において電源電流に含まれる高調波成分の低減や、力率を改善することにより、送電系統の負担を軽減させて、高効率に駆動制御を行うものである。 The rectifier circuit device according to the present invention is applied to a circuit device for driving a direct current load, and a device for converting the formed direct current again to an alternating current of an arbitrary frequency by an inverter circuit to drive a motor as a load at variable speed. Be done. The rectifier circuit device according to the present invention constitutes, for example, a heat pump by compressing a refrigerant with a compressor, and is applied to a device that performs cooling, heating, refrigeration of food or the like, and is included in the power supply current in such a device. The load on the transmission system is reduced by reducing the harmonic components to be reduced and improving the power factor to perform drive control with high efficiency.
 一般にこの種の整流回路装置としては種々のものが提案されている(例えば、特許文献1参照)。図18は特許文献1に開示された整流回路装置の構成を示す回路図であり、図19は図18の整流回路装置における制御部の構成を示すブロック図である。 In general, various types of rectifier circuit devices of this type have been proposed (see, for example, Patent Document 1). FIG. 18 is a circuit diagram showing a configuration of a rectifier circuit device disclosed in Patent Document 1, and FIG. 19 is a block diagram showing a configuration of a control unit in the rectifier circuit device of FIG.
 図18に示した整流回路装置においては、交流電源1の両出力端子を整流ブリッジ2とリアクタ3aを介して半導体スイッチ3cのオン状態により閉回路を形成して、リアクタ3aに電流を充電し、半導体スイッチ3cがオフ状態になったときに、ダイオード3bにより負荷4に電流を供給する構成である。このように構成することにより、図18の整流回路装置は交流電源1の瞬時電圧が低い期間においても電源電流が流れ、電源電流の高調波成分が少なくなり、力率が改善する構成である。 In the rectifier circuit device shown in FIG. 18, both output terminals of the AC power supply 1 form a closed circuit by the on state of the semiconductor switch 3c via the rectifier bridge 2 and the reactor 3a, and charge the reactor 3a with current. When the semiconductor switch 3c is turned off, a current is supplied to the load 4 by the diode 3b. With this configuration, the rectifier circuit device of FIG. 18 has a configuration in which the power supply current flows even in a period when the instantaneous voltage of the AC power supply 1 is low, the harmonic component of the power supply current decreases, and the power factor is improved.
 ところが、従来の整流回路装置においては、半導体スイッチ3cを、交流電源1の周波数よりも十分に高い周波数で、きめ細かくオン/オフ駆動して、交流電源1の交流電圧をチョッピングする(以下、「半導体スイッチをチョッピング動作させる」又は「半導体スイッチによるチョッピング」という。)とき、半導体スイッチ3cに電流が流れるため、回路の損失が発生するという課題があった。 However, in the conventional rectifier circuit device, the semiconductor switch 3 c is finely turned on / off at a frequency sufficiently higher than the frequency of the AC power supply 1 to chop the AC voltage of the AC power supply 1 (hereinafter, “semiconductor When the switch is operated for chopping operation or “chopping by semiconductor switch”, a current flows through the semiconductor switch 3c, which causes a problem of circuit loss.
 この課題を解決するため、半導体スイッチ3cを常にチョッピング動作させるのではなく、交流位相の特定の期間だけチョッピング動作させ、残りの期間は休止させる方法が提案されている(例えば、特許文献1参照)。 In order to solve this problem, a method has been proposed in which the semiconductor switch 3c is not chopping constantly, but chopping only during a specific period of the AC phase and rested for the remaining period (for example, see Patent Document 1). .
 図18に示した整流回路装置においては、交流電源1からの交流電圧を整流ブリッジ2で整流して、脈動を含む直流電圧に変換した後、その電力がリアクタ3a、ダイオード3bを介して、平滑コンデンサ3dおよび負荷4に供給されている。さらに、図18においては、リアクタ3aを介して、整流ブリッジ2からの出力電圧を半導体スイッチ3cで短絡できるように構成することにより、周知の昇圧チョッパ回路3による力率改善機能つきの整流回路装置が構成されている。図18に示した整流回路装置においては、昇圧チョッパ回路3が、入力電流検出器6および入力電流検出部10で入力電流を検出し、入力電流の波形が入力電圧検出部11で検出した入力電圧波形(電源電圧波形)と同じ形状になるように半導体スイッチ3cをチョッピング動作させ、かつ、出力電圧が所望の電圧になるように、入力電流の大きさを調整している。 In the rectifier circuit device shown in FIG. 18, the AC voltage from AC power supply 1 is rectified by rectifier bridge 2 and converted to a DC voltage including pulsation, and then the power is smoothed through reactor 3a and diode 3b. The capacitor 3 d and the load 4 are supplied. Further, in FIG. 18, a rectifier circuit device with a power factor improving function by the known step-up chopper circuit 3 can be obtained by configuring so that the output voltage from the rectifier bridge 2 can be shorted by the semiconductor switch 3c via the reactor 3a. It is configured. In the rectifier circuit device shown in FIG. 18, the step-up chopper circuit 3 detects the input current by the input current detector 6 and the input current detection unit 10, and the input voltage detected by the input voltage detection unit 11 of the waveform of the input current The semiconductor switch 3c is subjected to chopping operation so as to have the same shape as the waveform (power supply voltage waveform), and the magnitude of the input current is adjusted so that the output voltage becomes a desired voltage.
 特に、特許文献1では、半導体スイッチを高調波が少なくなるための最低限の区間のみチョッピング動作させることにより、回路の損失を低減させることを提案している。図19はその提案のための制御方法をブロック図で示したものである。図19において、電源ゼロクロス検出手段5により、電源電圧の位相を検出し、パルスカウンタ13aにより一定の期間のみ、図18の半導体スイッチ3cのチョッピング動作を許可し、それ以外の期間では、半導体スイッチ3cがオフになるように保持している。この制御方法により、電源高調波をほとんど増加させることなく、かつ低損失となる整流回路装置を実現している。 In particular, Patent Document 1 proposes reducing the loss of the circuit by chopping the semiconductor switch only in the minimum section for reducing the number of harmonics. FIG. 19 is a block diagram showing a control method for the proposal. In FIG. 19, the phase of the power supply voltage is detected by the power supply zero cross detection means 5, and the chopping operation of the semiconductor switch 3c of FIG. 18 is permitted only for a fixed period by the pulse counter 13a. Is held to be off. By this control method, a rectifier circuit device with low loss without increasing the power supply harmonics is realized.
 また、特許文献1の整流回路装置の制御方法においては、電源電圧の波形を必要とする構成であるが、電源電圧の波形を使用することなく、予め決めた波形により同様の動作を実現する制御方法も提案されている(例えば、特許文献2参照)。さらに、目標となる電流波形を有することなく、同様の効果が発揮されることを目的とする簡便な方法も提案されている(例えば、特許文献3参照)。 Moreover, in the control method of the rectifier circuit device of Patent Document 1, although the configuration of requiring the waveform of the power supply voltage, control for realizing the same operation by the predetermined waveform without using the waveform of the power supply voltage A method has also been proposed (see, for example, Patent Document 2). Furthermore, a simple method has also been proposed which aims to exhibit the same effect without having a target current waveform (see, for example, Patent Document 3).
 なお、図18に示した整流回路装置の場合には、入力電流がいったん整流された後の電流で代用されており、その入力電流の絶対値の情報を得て、この絶対値の大きさを調整する構成である。このように入力電流の絶対値の大きさを調整することは、入力電流の振幅を調整することと等価であることは、広く知られている。 In the case of the rectifier circuit device shown in FIG. 18, the input current is substituted by the current after being rectified once, information on the absolute value of the input current is obtained, and the magnitude of this absolute value is calculated. It is a configuration to adjust. It is widely known that adjusting the magnitude of the absolute value of the input current in this manner is equivalent to adjusting the amplitude of the input current.
特開2005-253284号公報JP 2005-253284 A 特開2007-129849号公報Unexamined-Japanese-Patent No. 2007-129849 特開2000-224858号公報JP 2000-224858 A 特開2001-045763号公報JP, 2001-045763, A
 前記従来技術に係る整流回路装置の構成では、負荷が決まっている条件では、出力電圧が一定になるように制御され、また、半導体スイッチをチョッピング動作させる期間も固定されている。このため、検出された出力電圧が誤差を含む場合、電流波形が変化してしまう。例えば、実効値200Vの交流を整流して約280Vの直流を得る場合に、直流電圧が1V変化するだけで電流波形が大きく変化する。直流電圧の280Vに対して1Vの精度は、0.3%に相当し、抵抗で電圧を分圧して低い電圧を形成する場合には、非常に高い精度の抵抗が必要になってしまう。このため、従来の整流回路装置においては、出力電圧の検出精度を加味して、変化した電流波形でも高調波が少なくなるように、チョッピングする期間をより長く設定する必要があった。したがって、このような従来の整流回路装置においては、回路の損失が増加するという課題を有している。 In the configuration of the rectifier circuit device according to the prior art, the output voltage is controlled to be constant under the condition that the load is determined, and the period during which the semiconductor switch is chopping is also fixed. Therefore, when the detected output voltage includes an error, the current waveform is changed. For example, in the case where an alternating current with an effective value of 200 V is rectified to obtain a direct current of about 280 V, the current waveform changes largely when the DC voltage changes by only 1 V. The accuracy of 1 V with respect to 280 V of the DC voltage corresponds to 0.3%, and in the case of dividing the voltage by resistors to form a low voltage, a resistor with very high accuracy is required. Therefore, in the conventional rectifier circuit device, in consideration of the detection accuracy of the output voltage, it is necessary to set the chopping period longer so as to reduce harmonics even in the changed current waveform. Therefore, such a conventional rectifier circuit device has a problem that the loss of the circuit increases.
 また、このような従来の整流回路装置における制御方法は、一般にデジタルコンピュータを用いて実現されるが、高精度な直流電圧の電圧制御を実現しようとすると、直流電圧を高分解能、すなわちビット数の多いアナログ-デジタル変換(以下、「AD変換」という。)器が必要になり、回路負担が大きくなってしまう。この場合においても、実際に制御回路が検出できる検出精度を加味して、変化した電流波形でも高調波が少なくなるように、チョッピングする期間をより長く設定して、回路の損失を少し増加させる必要があるという課題を有している。 In addition, although the control method in such a conventional rectifier circuit device is generally realized using a digital computer, in order to realize voltage control of a DC voltage with high accuracy, the DC voltage has high resolution, that is, the number of bits. A large number of analog-to-digital conversion (hereinafter referred to as "AD conversion") units are required, which increases the circuit load. Even in this case, it is necessary to set a longer chopping period to slightly increase the loss of the circuit so that harmonics are reduced even in the changed current waveform, in consideration of detection accuracy which can actually be detected by the control circuit. Have the challenge of
 さらに、このような従来の整流回路装置では、出力電圧が低いほど回路の損失が少なくなるが、電源電圧の瞬時値よりも低い電圧に出力電圧を設定しようとした場合、半導体スイッチをチョッピング動作させる期間の交流電圧が出力電圧より低くても、半導体スイッチをチョッピング動作させる期間に昇圧動作により出力電圧が上昇してしまう現象が発生する。このため、従来の整流回路装置においては、回路の損失がより少なく、より低い出力電圧に設定することが難しいという課題を有している。 Furthermore, in such a conventional rectifier circuit device, the loss of the circuit decreases as the output voltage decreases, but if it is attempted to set the output voltage to a voltage lower than the instantaneous value of the power supply voltage, the semiconductor switch is chopping operated. Even if the alternating voltage in the period is lower than the output voltage, a phenomenon occurs in which the output voltage rises due to the step-up operation during the period in which the semiconductor switch is subjected to the chopping operation. For this reason, in the conventional rectifier circuit device, there is a problem that it is difficult to set a lower output voltage with less circuit loss.
 また、このような従来の整流回路装置では、チョッピングする期間が一律に設定されており、チョッピングする期間は、想定された最大の入力電力に対して設定されている。このため、このような従来の整流回路装置は、入力電力が小さく電源高調波電流の規制レベルに対して余裕のある状況においても、規定のチョッピング動作を実行しなければならず、その結果、回路の損失を最小に出来ないという課題を有している。 Further, in such a conventional rectifier circuit device, the chopping period is uniformly set, and the chopping period is set for the assumed maximum input power. For this reason, such a conventional rectifier circuit device has to execute a prescribed chopping operation even in a situation where the input power is small and there is room for the regulation level of the power supply harmonic current, and as a result, the circuit The problem is that we can not minimize the loss of
 本発明の目的は、上記の問題点を解決することであり、出力電圧の検出精度によらず、接続されている負荷の状況、或いは外部からの指令に応じて電源高調波電流を低減することができ、かつ回路の損失を低減することができる整流回路装置の制御装置および整流回路装置を提供することにある。 The object of the present invention is to solve the above-mentioned problems, and to reduce the power supply harmonic current according to the status of the connected load or an external command regardless of the detection accuracy of the output voltage. It is an object of the present invention to provide a control device and a rectifier circuit device of a rectifier circuit device which can reduce the loss of the circuit.
 本発明に係る整流回路装置の制御装置は、
 半導体スイッチをチョッピング動作させることにより、単相交流電源からの交流電圧、或いは該交流電圧を整流した脈動電圧を、リアクタを介して短絡又は開放して、前記単相交流電源から直流電圧に整流して、負荷に電力を供給する整流回路装置の制御装置であって、
 前記制御装置は、
 前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成部と、
 前記単相交流電源から流れる交流電流を検出する交流電流検出部と、
 前記直流電圧を検出する直流電圧検出部と、
 前記検出された交流電流の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第1の制御部と、
 前記検出された直流電圧が実質的に所定の目標直流電圧となるように前記目標電流波形の振幅を制御する第2の制御部と、
 前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、若しくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第3の制御部と、を備えている。
The control device of the rectifier circuit device according to the present invention is
The chopping operation of the semiconductor switch shorts or opens the alternating voltage from the single phase alternating current power supply or the pulsating voltage obtained by rectifying the alternating current voltage through the reactor to rectify the single phase alternating current power supply into the direct current voltage. Control device of the rectifier circuit device for supplying power to the load,
The controller is
A waveform forming unit that forms a target current waveform having the same frequency as the waveform of the AC voltage;
An alternating current detection unit that detects an alternating current flowing from the single-phase alternating current power supply;
A DC voltage detection unit that detects the DC voltage;
A first control unit configured to control a chopping operation of the semiconductor switch such that a waveform of the detected alternating current substantially becomes the target current waveform;
A second control unit configured to control an amplitude of the target current waveform such that the detected DC voltage substantially becomes a predetermined target DC voltage;
The predetermined target DC voltage is controlled such that the chopping operation phase width in which the semiconductor switch is in the chopping operation state or the chopping pause phase width in which the semiconductor switch is in the chopping pause state is substantially equal to the predetermined phase width. And a third control unit.
 本発明に係る整流回路装置は、
 半導体スイッチをチョッピング動作させることにより、単相交流電源からの交流電圧、或いは該交流電圧を整流した脈動電圧を、リアクタを介して短絡又は開放して、前記単相交流電源から直流電圧に整流して、負荷に電力を供給する整流回路装置であって、
 前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成部と、
 前記単相交流電源から流れる交流電流を検出する交流電流検出部と、
 前記直流電圧を検出する直流電圧検出部と、
 前記検出された交流電流の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第1の制御部と、
 前記検出された直流電圧が実質的に所定の目標直流電圧となるように前記目標電流波形の振幅を制御する第2の制御部と、
 前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、若しくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第3の制御部と、を備えている。
The rectifier circuit device according to the present invention is
The chopping operation of the semiconductor switch shorts or opens the alternating voltage from the single phase alternating current power supply or the pulsating voltage obtained by rectifying the alternating current voltage through the reactor to rectify the single phase alternating current power supply into the direct current voltage. A rectifier circuit device for supplying power to the load,
A waveform forming unit that forms a target current waveform having the same frequency as the waveform of the AC voltage;
An alternating current detection unit that detects an alternating current flowing from the single-phase alternating current power supply;
A DC voltage detection unit that detects the DC voltage;
A first control unit configured to control a chopping operation of the semiconductor switch such that a waveform of the detected alternating current substantially becomes the target current waveform;
A second control unit configured to control an amplitude of the target current waveform such that the detected DC voltage substantially becomes a predetermined target DC voltage;
The predetermined target DC voltage is controlled such that the chopping operation phase width in which the semiconductor switch is in the chopping operation state or the chopping pause phase width in which the semiconductor switch is in the chopping pause state is substantially equal to the predetermined phase width. And a third control unit.
 本発明によれば、接続された負荷の状況、或いは外部からの指令に応じて所望の位相幅を変化させることが可能であり、負荷の変動状況によらず所望の位相幅と比較するチョッピング動作位相幅、若しくはチョッピング休止位相幅を的確に計測することにより、常に回路損失が少なく、かつ高調波電流が少ない整流動作を実現することができる整流回路装置の制御装置および整流回路装置を提供することができる。 According to the present invention, it is possible to change a desired phase width in accordance with the status of a connected load or an external command, and a chopping operation to compare with a desired phase width regardless of the load fluctuation status. To provide a control device and a rectifier circuit device of a rectifier circuit device capable of realizing a rectification operation with less circuit loss and less harmonic current by accurately measuring a phase width or chopping idle phase width. Can.
図1は、本発明に係る実施の形態1の整流回路装置の構成を示す回路図である。FIG. 1 is a circuit diagram showing a configuration of a rectifier circuit device according to a first embodiment of the present invention. 図2Aは、図1の整流回路装置における制御回路の構成を示すブロック図である。FIG. 2A is a block diagram showing a configuration of a control circuit in the rectifier circuit device of FIG. 図2Bは、図1の整流回路装置における制御の変形例を示す図であり、制御回路のチョッピング位相検出器の処理において波形成形器の出力信号を利用する場合を示すブロック図である。FIG. 2B is a diagram showing a modification of control in the rectifier circuit device of FIG. 1, and is a block diagram showing a case where an output signal of a waveform shaper is used in processing of a chopping phase detector of a control circuit. 図2Cは、図1の整流回路装置における制御の変形例を示す図であり、制御回路のチョッピング位相検出器の処理において電流検出器の出力を利用する場合を示すブロック図である。FIG. 2C is a diagram showing a modified example of control in the rectifier circuit device of FIG. 1 and is a block diagram showing a case where the output of the current detector is used in the processing of the chopping phase detector of the control circuit. 図2Dは、図1の整流回路装置における制御の変形例を示す図であり、制御回路のチョッピング位相検出器の処理においてDC電圧検出器の出力を利用する場合を示すブロック図である。FIG. 2D is a diagram showing a modification of control in the rectifier circuit device of FIG. 1, and is a block diagram showing a case where the output of the DC voltage detector is used in the processing of the chopping phase detector of the control circuit. 図2Eは、図1の整流回路装置における制御の変形例を示す図であり、制御回路のチョッピング位相検出器の処理においてPWM変調器の出力を利用する場合を示すブロック図である。FIG. 2E is a diagram showing a modified example of control in the rectifier circuit device of FIG. 1, and is a block diagram showing a case where the output of the PWM modulator is used in the processing of the chopping phase detector of the control circuit. 図3Aは、本発明に係る整流回路装置において、所望の位相幅がチョッピング動作位相幅である場合の目標位相幅設定器の特性図である。FIG. 3A is a characteristic diagram of a target phase width setting unit when the desired phase width is a chopping operation phase width in the rectifier circuit device according to the present invention. 図3Bは、本発明に係る整流回路装置において、所望の位相幅がチョッピング休止位相幅である場合の目標位相幅設定器の特性図である。FIG. 3B is a characteristic diagram of a target phase width setting unit when the desired phase width is the chopping pause phase width in the rectifier circuit device according to the present invention. 図4Aは、図1の整流回路装置における制御装置の第1の動作例に係る制御動作を説明するための図であって、(a)交流電圧(以下、AC電圧という。)と整流後の直流電圧(以下、DC電圧という。)との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後の交流電流(以下、AC電流という。)と、を示す信号波形図である。FIG. 4A is a diagram for explaining a control operation according to a first operation example of the control device in the rectifier circuit device of FIG. 1, and (a) alternating voltage (hereinafter referred to as AC voltage) and rectified; A signal indicating the relationship with a direct current voltage (hereinafter referred to as a DC voltage), (b) a target current waveform to be controlled, and (c) an alternating current after actual control (hereinafter referred to as an AC current). FIG. 図4Bは、図1の整流回路装置における制御装置の第2の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 4B is a diagram for explaining a control operation according to a second operation example of the control device in the rectifier circuit device of FIG. 1, and (a) relationship between AC voltage and DC voltage after rectification; b) A signal waveform diagram showing a target current waveform to be controlled and (c) an AC current after actual control. 図5Aは、本発明に係る実施の形態2の整流回路装置における制御装置の第3の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 5A is a diagram for explaining a control operation according to a third operation example of the control device in the rectifier circuit device of the second embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図5Bは、本発明に係る実施の形態2の整流回路装置における制御装置の第4の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 5B is a diagram for explaining the control operation according to the fourth operation example of the control device in the rectifier circuit device of the second embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図6Aは、本発明に係る実施の形態3の整流回路装置における制御装置の第5の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 6A is a diagram for explaining the control operation according to the fifth operation example of the control device in the rectifier circuit device of the embodiment 3 of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図6Bは、本発明に係る実施の形態3の整流回路装置における制御装置の第6の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 6B is a diagram for explaining the control operation according to the sixth operation example of the control device in the rectifier circuit device of the embodiment 3 of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図7Aは、本発明に係る実施の形態4の整流回路装置における制御装置の第7の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 7A is a diagram for explaining a control operation according to a seventh operation example of the control device in the rectifier circuit device of the fourth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図7Bは、本発明に係る実施の形態4の整流回路装置における制御装置の第8の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 7B is a diagram for explaining the control operation according to the eighth operation example of the control device in the rectifier circuit device of the fourth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図8Aは、本発明に係る実施の形態5の整流回路装置における制御装置の第9の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 8A is a diagram for explaining the control operation according to the ninth operation example of the control device in the rectifier circuit device of the fifth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification; FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図8Bは、本発明に係る実施の形態5の整流回路装置における制御装置の第10の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 8B is a diagram for explaining the control operation according to the tenth operation example of the control device in the rectifier circuit device of the fifth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図9Aは、本発明に係る実施の形態6の整流回路装置における制御装置の第11の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 9A is a diagram for explaining a control operation according to an eleventh operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図9Bは、本発明に係る実施の形態6の整流回路装置における制御装置の第12の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 9B is a diagram for explaining the control operation according to the twelfth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図10Aは、本発明に係る実施の形態6の整流回路装置における制御装置の第13の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 10A is a diagram for illustrating a control operation according to a thirteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図10Bは、本発明に係る実施の形態6の整流回路装置における制御装置の第14の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 10B is a diagram for explaining the control operation according to the fourteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図10Cは、本発明に係る実施の形態6の整流回路装置における制御装置の第15の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 10C is a diagram for illustrating the control operation according to the fifteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図10Dは、本発明に係る実施の形態6の整流回路装置における制御装置の第16の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流と、を示す信号波形図である。FIG. 10D is a diagram for explaining the control operation according to the sixteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled and (c) an AC current after actual control. 図11は、本発明に係る実施の形態7の整流回路装置の構成を示す回路図である。FIG. 11 is a circuit diagram showing a configuration of a rectifier circuit device according to a seventh embodiment of the present invention. 図12は、本発明に係る実施の形態8の整流回路装置の構成を示す回路図である。FIG. 12 is a circuit diagram showing a configuration of a rectifier circuit device according to an eighth embodiment of the present invention. 図13は、本発明に係る実施の形態9の整流回路装置の構成を示す回路図である。FIG. 13 is a circuit diagram showing a configuration of a rectifier circuit device according to a ninth embodiment of the present invention. 図14Aは、本発明に係る実施の形態1~9の整流回路装置における電圧レベル比較器の2値化処理の第1の動作例を説明するための図であって、(a)AC電圧としきい値電圧(Vth)との関係と、(b)電圧レベル比較器からの2値信号と、を示す信号波形図である。FIG. 14A is a diagram for explaining a first operation example of the binarization processing of the voltage level comparator in the rectifier circuit device according to the first to ninth embodiments of the present invention, in which It is a signal waveform diagram which shows the relationship with a threshold voltage (Vth), and the binary signal from (b) voltage level comparator. 図14Bは、本発明に係る実施の形態1~9の整流回路装置における電圧レベル比較器の2値化処理の第2の動作例を説明するための図であって、(a)AC電圧としきい値電圧(Vth)との関係と、(b)電圧レベル比較器からの2値信号と、を示す信号波形図である。FIG. 14B is a diagram for explaining a second operation example of the binarization processing of the voltage level comparator in the rectifier circuit device according to the first to ninth embodiments of the present invention; It is a signal waveform diagram which shows the relationship with a threshold voltage (Vth), and the binary signal from (b) voltage level comparator. 図15は、本発明に係る実施の形態10の整流回路装置における制御回路の詳細構成を示すブロック図である。FIG. 15 is a block diagram showing a detailed configuration of a control circuit in a rectifier circuit device according to a tenth embodiment of the present invention. 図16は、図15の整流回路装置におけるローパスフィルタ演算器(以下、「LPF演算器」という)の詳細構成を示すブロック図である。FIG. 16 is a block diagram showing a detailed configuration of a low pass filter computing unit (hereinafter referred to as “LPF computing unit”) in the rectifier circuit device of FIG. 図17は、図15の整流回路装置の動作を示す図であって、(a)交流電源からのAC電流(Iac)と、(b)DC電圧(Vdc)と、(c)AD変換器のAD変換値(Vad)(上記DC電圧Vdcを点線で示す。)と、を示す信号波形図である。FIG. 17 is a diagram showing the operation of the rectifier circuit device of FIG. 15, and (a) AC current (Iac) from AC power supply, (b) DC voltage (Vdc), (c) AD converter FIG. 7 is a signal waveform diagram showing an AD conversion value (Vad) (the DC voltage Vdc is indicated by a dotted line). 従来の整流回路装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the conventional rectifier circuit apparatus. 図18の従来の整流回路装置における制御部の詳細構成を示すブロック図である。It is a block diagram which shows the detailed structure of the control part in the conventional rectifier circuit apparatus of FIG.
 以下、本発明に係る整流回路装置の制御装置および整流回路装置の各態様について説明する。以下の各態様の説明において、括弧内の符号等は後述する各実施の形態における関連する要素の符号等を表すものであるが、本発明を各実施の形態の構成に限定するものではない。
 本発明の第1の態様に係る整流回路装置の制御装置は、
 半導体スイッチをチョッピング動作させることにより、単相交流電源からの交流電圧、或いは該交流電圧を整流した脈動電圧を、リアクタを介して短絡又は開放して、前記単相交流電源から直流電圧に整流して、負荷に電力を供給する整流回路装置の制御装置であって、
 前記制御装置は、
 前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成部(201,202)と、
 前記単相交流電源から流れる交流電流を検出する交流電流検出部(103)と、
 前記直流電圧を検出する直流電圧検出部(110)と、
 前記検出された交流電流(Iac)の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第1の制御部(208,209,210,211)と、
 前記検出された直流電圧(Vdc)が実質的に所定の目標直流電圧(Vdc)となるように前記目標電流波形の振幅を制御する第2の制御部(206,207)と、
 前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅(θwON)、若しくは前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅(θwOFF)が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第3の制御部(203,204,205,212)と、を備えている。
Hereinafter, each aspect of the control device of the rectifier circuit device according to the present invention and the rectifier circuit device will be described. In the following description of each aspect, reference numerals and the like in parentheses represent reference numerals and the like of related elements in the respective embodiments to be described later, but the present invention is not limited to the configurations of the respective embodiments.
The control device for a rectifier circuit device according to the first aspect of the present invention is
The chopping operation of the semiconductor switch shorts or opens the alternating voltage from the single phase alternating current power supply or the pulsating voltage obtained by rectifying the alternating current voltage through the reactor to rectify the single phase alternating current power supply into the direct current voltage. Control device of the rectifier circuit device for supplying power to the load,
The controller is
A waveform forming unit (201, 202) for forming a target current waveform having the same frequency as the waveform of the AC voltage;
An alternating current detection unit (103) for detecting an alternating current flowing from the single-phase alternating current power supply;
A DC voltage detection unit (110) for detecting the DC voltage;
A first control unit (208, 209, 210, 211) for controlling the chopping operation of the semiconductor switch so that the waveform of the detected alternating current (Iac) substantially becomes the target current waveform;
A second control unit (206, 207) for controlling the amplitude of the target current waveform such that the detected DC voltage (Vdc) substantially becomes a predetermined target DC voltage (Vdc * );
The predetermined value is set such that the chopping operation phase width (θw ON ) in which the semiconductor switch is in the chopping operation state or the chopping pause phase width (θw OFF ) in which the semiconductor switch is in the chopping pause state becomes substantially a predetermined phase width. And a third control unit (203, 204, 205, 212) for controlling the target DC voltage of
 本発明の第2の態様に係る整流回路装置の制御装置は、前記の第1の態様における前記所定の位相幅が、電源半周期に対して0度から180度の範囲で、負荷の状況、若しくは外部からの指令に応じて変更して設定されるように構成されている。 In the control apparatus for a rectifier circuit device according to the second aspect of the present invention, the load state is such that the predetermined phase width in the first aspect is in the range of 0 degrees to 180 degrees with respect to a power supply half cycle Alternatively, it is configured to be changed and set in accordance with an external command.
 本発明の第3の態様に係る整流回路装置の制御装置は、前記の第2の態様における前記負荷の状況が、前記交流電流の値、前記交流電流に基づいて計算される入力電力、または前記整流回路装置の出力電力で示されるよう構成されている。 In the control apparatus for a rectifier circuit device according to a third aspect of the present invention, the load status in the second aspect is the value of the alternating current, the input power calculated based on the alternating current, or It is configured as indicated by the output power of the rectifier circuit device.
 本発明の第4の態様に係る整流回路装置の制御装置において、前記の第1の態様から第3の態様におけるいずれかの態様の前記第3の制御部は、前記交流電圧の極性が固定されている期間内において検出されるチョッピング休止位相幅若しくはチョッピング動作位相幅の瞬時値、または予め設定されている回数による平均値が、実質的に所定の位相幅となるように前記所定の目標直流電圧を制御するよう構成されている。 In the control device for a rectifier circuit device according to the fourth aspect of the present invention, the polarity of the alternating voltage is fixed in the third control unit according to any one of the first to third aspects. The predetermined target DC voltage so that the chopping pause phase width or the instantaneous value of the chopping operation phase width detected within the period, or the average value by the number of times set in advance, substantially becomes the predetermined phase width Are configured to control the
 本発明の第5の態様に係る整流回路装置の制御装置において、前記の第1の態様から第3の態様におけるいずれかの態様の前記第3の制御部は、所定の期間における最も低い前記直流電圧時を含む、前記交流電圧の極性が固定されている期間内において検出されたチョッピング休止位相幅、若しくはチョッピング動作位相幅が、実質的に所定の位相幅となるように前記所定の目標直流電圧を制御するよう構成されている。 In the control device for a rectifier circuit device according to a fifth aspect of the present invention, the third control unit according to any one of the first to third aspects is characterized in that the direct current in the predetermined period is lowest. The predetermined target DC voltage so that the chopping pause phase width or chopping operation phase width detected within a period in which the polarity of the AC voltage is fixed, including voltage time, is substantially equal to the predetermined phase width. Are configured to control the
 本発明の第6の態様に係る整流回路装置の制御装置において、前記の第1の態様から第3の態様におけるいずれかの態様の前記第3の制御部は、所定の期間における最も大きい前記交流電流時を含む、前記交流電圧の極性が固定されている期間内において検出されたチョッピング休止位相幅、若しくはチョッピング動作位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御するよう構成されている。 In the control device for a rectifier circuit device according to a sixth aspect of the present invention, the third control unit according to any one of the first to third aspects is the largest alternating current in a predetermined period. The predetermined target DC voltage is set so that the chopping pause phase width or chopping operation phase width detected within a period in which the polarity of the AC voltage is fixed, including current, is substantially equal to the predetermined phase width. It is configured to control.
 本発明の第7の態様に係る整流回路装置の制御装置において、前記の第1の態様から第6の態様におけるいずれかの態様の前記第3の制御部は、前記交流電圧の極性が固定されている期間内において、複数の前記チョッピング動作位相幅、若しくは複数の前記チョッピング休止位相幅が存在するときに、当該期間内のいずれかの位相幅、若しくは合計の位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御するよう構成されている。 In the control device for a rectifier circuit device according to the seventh aspect of the present invention, the polarity of the alternating voltage is fixed in the third control unit according to any one of the first to sixth aspects. When a plurality of chopping operation phase widths or a plurality of chopping pause phase widths exist in a period, any phase width in the period or a total phase width is substantially a predetermined phase. The predetermined target DC voltage is controlled to have a width.
 本発明の第8の態様に係る整流回路装置の制御装置において、前記の第1の態様から第7の態様におけるいずれかの態様の前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、(a)当該期間の開始点から、所定の中間点までは、時間経過とともに、少なくとも増加し、若しくは少なくとも増加し、かつ、一部期間で一定であるように実質的に単調増加し、(b)前記中間点から終了点までは、時間経過とともに、少なくとも減少し、若しくは少なくとも減少し、かつ、一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定している。 In the control device for a rectifier circuit device according to an eighth aspect of the present invention, the target current waveform according to any one of the first to seventh aspects has an instantaneous absolute value of the target current waveform (A) Within a period in which the polarity of the AC voltage is fixed, (a) From the start point of the period to a predetermined midpoint, at least increase or at least increase with time, and a partial period And (b) from the midpoint to the end point at least decrease or at least decrease with time and substantially constant so as to be constant over a period of time. After monotonically decreasing, it is set to have a period which becomes zero.
 本発明の第9の態様に係る整流回路装置の制御装置において、前記の第1の態様から第7の態様におけるいずれかの態様の前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、(a)当該期間の開始点から、所定の第1の中間点までは、時間経過とともに、ゼロとなる期間を有し、(b)前記第1の中間点から所定の第2の中間点までは、少なくとも増加し、若しくは少なくとも増加し、かつ、一部期間で一定であるように実質的に単調増加し、(c)前記第2の中間点から終了点までは、時間経過とともに、少なくとも減少し、若しくは少なくとも減少し、かつ、一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定している。 In the control apparatus for a rectifier circuit device according to a ninth aspect of the present invention, the target current waveform according to any one of the first to seventh aspects has an instantaneous absolute value of the target current waveform (A) Within a period in which the polarity of the alternating voltage is fixed, (a) from the start point of the period to a predetermined first intermediate point has a period which becomes zero with the passage of time, (b) From the first midpoint to the predetermined second midpoint, at least increasing, or at least increasing, and substantially monotonically increasing so as to be constant over a period of time, and (c) the second From the middle point to the end point is set to have a period that decreases at least or at least decreases with time and substantially monotonically decreases and then becomes zero so as to be constant in part of the period doing.
 本発明の第10の態様に係る整流回路装置の制御装置は、前記の第1の態様から第9の態様におけるいずれかの態様において、前記交流電圧を所定のしきい値電圧と比較することにより2値信号を発生する位相検出部(109)をさらに備え、
 前記波形形成部は、前記2値信号に基づいて前記交流電圧の周期および位相を検出し、当該検出された交流電圧の周期および位相に基づいて、前記交流電圧の波形と同一周波数の目標電流波形を形成し、
 前記第3の制御部は、前記2値信号に基づいて、前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、若しくは前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅を検出するよう構成されている。
The control device for a rectifier circuit device according to a tenth aspect of the present invention is the control method according to any one of the first to ninth aspects, wherein the AC voltage is compared with a predetermined threshold voltage. It further comprises a phase detection unit (109) that generates a binary signal,
The waveform forming unit detects a cycle and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the cycle and the phase of the detected AC voltage. Form
The third control unit is configured to detect a chopping operation phase width in which the semiconductor switch is in the chopping operation state or a chopping pause phase width in which the semiconductor switch is in the chopping suspension state based on the binary signal. ing.
 本発明の第11の態様に係る整流回路装置の制御装置は、前記の第1の態様から第10の態様におけるいずれかの態様において、前記制御装置はさらに、前記直流電圧検出部と前記第2の制御部との間に設けられ、前記検出された直流電圧をデジタル電圧にAD変換するAD変換部(230)と、前記AD変換部と前記第2の制御部との間に設けられ、前記デジタル電圧に対して低域フィルタ演算を行った後、当該演算結果の電圧を前記第2の制御部に前記検出された直流電圧として出力する演算部(231)と、を備えている。 In the control device for a rectifier circuit device according to an eleventh aspect of the present invention, in any one of the first to tenth aspects, the control device further includes: the DC voltage detection unit; An AD conversion unit (230) for AD converting the detected DC voltage to a digital voltage, and between the AD conversion unit and the second control unit, And a calculation unit (231) for outputting the voltage of the calculation result as the detected direct current voltage to the second control unit after the low-pass filter calculation is performed on the digital voltage.
 本発明の第12の態様に係る整流回路装置の制御装置は、前記の第11の態様における前記AD変換部のサンプリング周波数が、前記単相交流電源の周波数よりも十分に高くなるように設定されている。 The control device of a rectifier circuit device according to a twelfth aspect of the present invention is set such that the sampling frequency of the AD converter in the eleventh aspect is sufficiently higher than the frequency of the single-phase AC power supply. ing.
 本発明の第13の態様に係る整流回路装置の制御装置において、前記の第11の態様又は第12の態様における前記低域通過フィルタ演算は、直前の演算結果に「(2n-1)/(2n)」なる係数(nは整数である)を乗算した後、入力されたデジタル電圧と加算し、当該加算結果の値を次の演算結果として用いて実行される。 In the control device for a rectifier circuit device according to the thirteenth aspect of the present invention, the low-pass filter computation in the eleventh aspect or the twelfth aspect further includes “(2 n −1) / After multiplying by a factor (2 n ) (where n is an integer), it is added to the input digital voltage and executed using the value of the addition result as the next calculation result.
 本発明の第14の態様に係る整流回路装置は、前記の第1の態様乃至第13の態様におけるいずれか一つの態様の整流回路装置の制御装置を備えている。 A rectifier circuit device according to a fourteenth aspect of the present invention includes the control device of the rectifier circuit device according to any one of the first to thirteenth aspects.
 上記各態様の構成によれば、直流電圧の検出精度に誤差があっても、直流電圧が相対的に適正な値に調整されて、入力電圧波形と同様の電流波形になり、かつ負荷の状況、或いは外部からの指令に応じて所望の位相幅を変更することや、負荷の変動状況によらず所望の位相幅と比較するチョッピング動作位相幅、若しくはチョッピング休止位相幅を的確に計測することで常に回路損失が少なく、かつ高調波電流が少ない整流動作を実現することができる。 According to the configuration of each of the above aspects, even if there is an error in the detection accuracy of the DC voltage, the DC voltage is adjusted to a relatively appropriate value, and the current waveform becomes the same as the input voltage waveform, and the load condition Or, by changing the desired phase width according to an external command, or by accurately measuring the chopping operation phase width or chopping pause phase width to be compared with the desired phase width regardless of the load fluctuation state. It is always possible to realize a rectification operation with low circuit loss and low harmonic current.
 また、交流電源の周波数よりも十分に高いサンプリング周波数で、直流電圧をAD変換部により、デジタル信号に変換して検出し、得られたデジタル信号を前記周期毎に低域フィルタ演算(LPF演算)を実行して、デジタル信号に分解能以下の微小情報を補間するように追加し、微小情報を補間したデジタル信号を直流電圧情報として、チョッピングが実際になされている位相幅が所望の値になるように、微小情報を補間したデジタル信号を調整している。直流電圧の平滑電圧に含まれている電源周波数成分に揺らぎがあり、デジタル情報の分解能が粗い場合でも、揺らぎによりデジタル信号が分散されるため、平均的には高い分解能と等価なデジタル信号を得ることができる。これによって、粗い分解能のAD変換手段を用いても、直流電圧の平均値を高精度に調節することができ、常に損失が少なく、かつ、高調波電流が少ない整流動作が実現される。 Also, with a sampling frequency sufficiently higher than the frequency of the AC power supply, the DC voltage is converted into a digital signal by the AD conversion unit and detected, and the obtained digital signal is subjected to low pass filter calculation (LPF calculation) for each period. To add minute information below the resolution to the digital signal so that it interpolates, and using the digital signal interpolated from the small information as direct current voltage information, the phase width for which chopping is actually made becomes the desired value. In addition, the digital signal which has interpolated the minute information is adjusted. Even if there is fluctuation in the power supply frequency component contained in the smoothed voltage of the DC voltage and the resolution of the digital information is coarse, the digital signal is dispersed due to the fluctuation, so a digital signal equivalent to high resolution is obtained on average be able to. As a result, even if coarse resolution AD conversion means are used, the average value of the DC voltage can be adjusted with high accuracy, and a rectification operation with less loss and less harmonic current can be realized.
 以下、本発明の整流回路装置および制御回路に係る実施の形態について、添付の図面を参照しながら説明する。なお、本発明の整流回路装置および制御回路は、以下の実施の形態に記載した整流回路装置および制御回路の構成に限定されるものではなく、以下の実施の形態において説明する技術的思想と同等の技術的思想に基づいて構成されるものを含む。また、以下の各実施の形態において、同様の機能を有する構成要素については同一の符号を付して説明する。 Hereinafter, embodiments of a rectifier circuit device and a control circuit of the present invention will be described with reference to the attached drawings. The rectifier circuit device and control circuit of the present invention are not limited to the configurations of the rectifier circuit device and control circuit described in the following embodiments, and are equivalent to the technical idea described in the following embodiments. Including those based on the technical ideas of Further, in each of the following embodiments, components having the same functions will be described with the same reference numerals.
 (実施の形態1)
 図1は本発明に係る実施の形態1の整流回路装置の構成を示す回路図である。図1において、単相の交流電源1の両出力端子を、リアクタ102を介して半導体スイッチ104により短絡することにより、1つのループが構成される。交流電流検出部である電流検出器103は、そのループの電流を検出し、検出された電流値Iacを示す信号を制御回路100に出力する。半導体スイッチ104をオン状態にすると、リアクタ102の電流は増加する。一方、半導体スイッチ104をオフ状態にすると、リアクタ102に流れていた電流はダイオードブリッジ回路105にて整流されて、その整流された電流は平滑コンデンサ106および負荷4に流れ、負荷4を駆動する。負荷4に印加される平滑コンデンサ106の両端のDC電圧Vdcは、DC電圧検出器110により検出され、DC電圧検出器110は検出されたDC電圧Vdcを示す信号を制御回路100に出力する。
Embodiment 1
FIG. 1 is a circuit diagram showing a configuration of a rectifier circuit device according to a first embodiment of the present invention. In FIG. 1, a single loop is configured by shorting both output terminals of single-phase AC power supply 1 with semiconductor switch 104 via reactor 102. The current detector 103, which is an alternating current detection unit, detects the current of the loop, and outputs a signal indicating the detected current value Iac to the control circuit 100. When the semiconductor switch 104 is turned on, the current of the reactor 102 is increased. On the other hand, when the semiconductor switch 104 is turned off, the current flowing to the reactor 102 is rectified by the diode bridge circuit 105, and the rectified current flows to the smoothing capacitor 106 and the load 4 to drive the load 4. The DC voltage Vdc across the smoothing capacitor 106 applied to the load 4 is detected by the DC voltage detector 110, and the DC voltage detector 110 outputs a signal indicating the detected DC voltage Vdc to the control circuit 100.
 また、交流電源1から入力された交流電圧の位相検出部である電圧レベル比較器109は、交流電源1のAC電圧レベルを所定のしきい値電圧と比較することにより、当該しきい値電圧以上であるか否かを示す2値信号Scomを発生して制御回路100に出力する。制御回路100は、2値信号Scomの周期および位相に基づいて、交流電源1から出力されるAC電圧の位相を検知する。制御回路100は、検知されたAC電圧の位相に基づいて、AC電圧と実質的に同一の周波数であって、AC電圧と相似形状を有する目標電流波形を生成し、電流検出器103により検出された電流値Iacが前記生成した目標電流波形の相似形状に漸近するように半導体スイッチ104をチョッピング動作させるように制御する。 The voltage level comparator 109, which is a phase detection unit of the AC voltage input from the AC power supply 1, compares the AC voltage level of the AC power supply 1 with a predetermined threshold voltage to obtain the threshold voltage or more. Is generated and output to the control circuit 100. The control circuit 100 detects the phase of the AC voltage output from the AC power supply 1 based on the period and the phase of the binary signal Scom. The control circuit 100 generates a target current waveform having substantially the same frequency as the AC voltage and having a similar shape to the AC voltage based on the phase of the detected AC voltage, and is detected by the current detector 103. The semiconductor switch 104 is controlled to chopping so that the current value Iac approaches the similar shape of the generated target current waveform.
 さらに、制御回路100は、DC電圧検出器110により検出されたDC電圧Vdcが、制御回路100内で設定された所望の電圧になるように、その偏差に応じて、生成する目標電流波形の相似比率を調整する。ここで、制御回路100は、実際のDC電圧Vdcが所望のDC電圧より低ければ、目標電流波形の相似比率を増大させて、大きな電流になるように制御し、実際のDC電圧Vdcが所望のDC電圧よりも高ければ、小さな電流になるように制御する。また、制御回路100は、半導体スイッチ104のチョッピング状態に基づいて、半導体スイッチ104をパルス幅変調(以下、「PWM」という。)駆動している位相幅を検出し、その位相幅と所望の値との偏差を検出し、当該偏差に応じて前記所望のDC電圧値を調整する。 Furthermore, control circuit 100 is similar to the target current waveform to be generated according to the deviation so that DC voltage Vdc detected by DC voltage detector 110 becomes the desired voltage set in control circuit 100. Adjust the ratio. Here, if the actual DC voltage Vdc is lower than the desired DC voltage, the control circuit 100 increases the similarity ratio of the target current waveform to control so as to be a large current, and the actual DC voltage Vdc is desired. If it is higher than the DC voltage, control is made to be a small current. Further, the control circuit 100 detects a phase width driving the semiconductor switch 104 by pulse width modulation (hereinafter referred to as "PWM") based on the chopping state of the semiconductor switch 104, and the phase width and a desired value. And the desired DC voltage value is adjusted according to the deviation.
 図2Aは図1の制御回路100の詳細構成を示すブロック図である。図2Aの制御回路100において、当該制御システムとしての最終制御目標は、チョッピング駆動がなされているチョッピング動作位相幅θwONを目標位相幅設定器203からの所望の位相幅θwON *に制御することである。まず、AC電圧位相検出器201は、交流電源1の電圧レベルを所定のしきい値電圧Vthと比較することにより2値化した2値信号Scomに基づいて、AC位相を検出し、検出したAC位相を示す信号を目標電流波形形成器202およびチョッピング位相幅検出器212に出力する。なお、AC電圧位相検出器201の具体的な動作の詳細は後述する。次いで、目標電流波形形成器202は、前記AC位相を示す信号に基づいて、詳細を後述する所定の目標電流波形を発生して、乗算器208に出力する。 FIG. 2A is a block diagram showing the detailed configuration of the control circuit 100 of FIG. In the control circuit 100 of FIG. 2A, the final control target as the control system is to control the chopping operation phase width θw ON in which chopping driving is performed to a desired phase width θw ON * from the target phase width setter 203. It is. First, the AC voltage phase detector 201 detects an AC phase based on a binary signal Scom binarized by comparing the voltage level of the AC power supply 1 with a predetermined threshold voltage Vth, and detects AC. A signal indicating the phase is output to the target current waveform shaper 202 and the chopping phase width detector 212. The details of the specific operation of the AC voltage phase detector 201 will be described later. Next, based on the signal indicating the AC phase, the target current waveform former 202 generates a predetermined target current waveform, which will be described in detail later, and outputs it to the multiplier 208.
 なお、本発明に係る実施の形態1においては、制御回路100におけるAC電圧位相検出器201と目標電流波形形成器202により、交流電圧の波形と同一周波数の目標電流波形を形成する波形形成部が構成されている。 In the first embodiment according to the present invention, a waveform forming unit that forms a target current waveform having the same frequency as the waveform of AC voltage by AC voltage phase detector 201 and target current waveform shaper 202 in control circuit 100 is provided. It is configured.
 チョッピング位相幅検出器212は、Iac補償演算器210からPWM変調器211に出力される半導体スイッチ104に対するチョッピング駆動信号Schの原信号に基づいて、AC電圧位相検出器201からの信号が示すAC電圧の位相を基準として、チョッピング状態である位相幅(以下、「チョッピング動作位相幅」又は、単に「チョッピング位相幅」という。)θwONを検出して、チョッピング位相幅θwONを示す信号を減算器204に出力する。一方、目標位相幅設定器203は、電流検出部である電流検出器103により検出された実際の電流値Iacから予め設定された関係に従い所望のチョッピング位相幅θwON *を示す信号を減算器204に出力する。 The chopping phase width detector 212 is an AC voltage indicated by the signal from the AC voltage phase detector 201 based on the original signal of the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation operator 210 to the PWM modulator 211. Phase width in the chopping state (hereinafter referred to as “chopping operation phase width” or simply “chopping phase width”) θw ON is detected, and a signal indicating the chopping phase width θw ON is subtracted from the phase of the phase Output to 204. On the other hand, the target phase width setting unit 203 subtracts a signal indicating a desired chopping phase width θw ON * according to a preset relationship from the actual current value Iac detected by the current detector 103 which is a current detection unit. Output to
 ここで、図3Aは、目標位相幅設定器203から出力される所望のチョッピング位相幅θwON *と、目標位相幅設定器203に入力される電流検出器103により検出された実際の電流値Iacとの関係の一例を示したものである。 Here, FIG. 3A shows the desired chopping phase width θw ON * output from the target phase width setter 203 and the actual current value Iac detected by the current detector 103 input to the target phase width setter 203. And an example of the relationship with
 図3Aに示すように、実際の電流値Iacの増加に従い所望のチョッピング位相幅θwON *が増加する特性としている。このような特性とすることにより、低入力では高調波電流自体の大きさが小さいため損失低減を重視する一方で、高入力では高調波電流の低減を重視した特性を持たせることができる。その結果、損失低減と高調波電流の抑制を狙った特性を持たせることができる。 As shown in FIG. 3A, the desired chopping phase width θw ON * increases as the actual current value Iac increases. With such characteristics, it is possible to give a characteristic that emphasizes reduction of the harmonic current at high input while emphasizing loss reduction since the magnitude of the harmonic current itself is small at low input. As a result, it is possible to provide characteristics aiming for loss reduction and suppression of harmonic current.
 なお、図3Aに示す特性では、前後を平坦にし、その間を滑らかな直線で繋いだものとしているが、チョッピング位相幅θwON *と電流値Iacとの関係を示す特性としては、図3Aに示した特性に限定されるものではない。 In the characteristics shown in FIG. 3A, the front and back are made flat, and between them is assumed to be connected by a smooth straight line, but as characteristics showing the relationship between the chopping phase width θw ON * and the current value Iac, it is shown in FIG. It is not limited to the following characteristics.
 また、図3Aの特性図において、横軸を実際の電流値Iacとして説明しているが、電流値Iacに基づいて計算される入力電力、若しくは負荷4に流れる電流を検出する電流検出器112の出力と直流電圧検出部であるDC電圧検出器110の出力から得られる整流回路装置の出力電力を用いても同様の結果が得られる。 Further, in the characteristic diagram of FIG. 3A, the horizontal axis is described as the actual current value Iac, but the input power calculated based on the current value Iac or the current detector 112 for detecting the current flowing to the load 4 Similar results can be obtained using the output and the output power of the rectifier circuit device obtained from the output of the DC voltage detector 110 which is the DC voltage detector.
 減算器204は、いわゆる位相比較器であり、実際のチョッピング位相幅θwONから所望のチョッピング位相幅θwON *を減算することにより、その位相幅の偏差を演算して当該偏差を示す信号を位相幅補償演算器205に出力する。位相幅補償演算器205は、PWM駆動状態の位相幅を安定に保つための所定の補償演算を行うことにより、当該整流回路装置により出力すべきDC電圧の指令電圧Vdc*を発生して、当該指令電圧Vdc*を示す信号を減算器206に出力する。一方、直流電圧検出部であるDC電圧検出器110により検出された実際の出力DC電圧Vdcを示す信号は減算器206に入力される。 The subtractor 204 is a so-called phase comparator, which subtracts the desired chopping phase width θw ON * from the actual chopping phase width θw ON to calculate the deviation of the phase width and phase the signal indicating the deviation It is output to the width compensation computing unit 205. The phase width compensation computing unit 205 generates a command voltage Vdc * of the DC voltage to be output by the rectifier circuit device by performing a predetermined compensation operation to keep the phase width of the PWM drive state stable. A signal indicating command voltage Vdc * is output to subtractor 206. On the other hand, a signal indicating the actual output DC voltage Vdc detected by the DC voltage detector 110 which is a DC voltage detection unit is input to the subtractor 206.
 減算器206は、DC電圧の指令電圧Vdc*から実際の出力DC電圧Vdcを減算することにより、電圧偏差を演算し、電圧偏差を示す信号を発生してVdc補償演算器207に出力する。Vdc補償演算器207は、実際のDC電圧Vdcが指令電圧Vdc*と実質的に一致し、かつ、安定になるための補償演算を実行することにより、補償演算後の電圧偏差を示す信号を乗算器208に出力する。乗算器208は、目標電流波形形成器202からの目標電流波形に対して補償演算後の電圧偏差を乗算し、乗算結果である瞬時の電流指令値Iac*を形成して、減算器209に出力する。乗算器208の動作では、実際の電圧Vdcが指令電圧Vdc*よりも低いとき、目標電流波形の振幅を増大させる一方、実際の電圧Vdcが指令電圧Vdc*よりも高いとき、目標電流波形の振幅を減少させる。 The subtractor 206 subtracts the actual output DC voltage Vdc from the command voltage Vdc * of the DC voltage to calculate a voltage deviation, generates a signal indicating the voltage deviation, and outputs the signal to the Vdc compensation computing unit 207. The Vdc compensation computing unit 207 multiplies the signal indicating the voltage deviation after the compensation operation by executing the compensation operation for the actual DC voltage Vdc to substantially coincide with the command voltage Vdc * and become stable. Output to the signal generator 208. The multiplier 208 multiplies the target current waveform from the target current waveform former 202 by the voltage deviation after the compensation operation, forms an instantaneous current command value Iac * which is the multiplication result, and outputs the current command value Iac * to the subtractor 209 Do. In the operation of the multiplier 208, the amplitude of the target current waveform is increased when the actual voltage Vdc is lower than the command voltage Vdc *, while the amplitude of the target current waveform is increased when the actual voltage Vdc is higher than the command voltage Vdc *. Reduce
 減算器209は、瞬時の電流指令値Iac*から、電流検出器103により検出された実際の電流値Iacを減算することにより、減算結果である電流偏差を示す信号をIac補償演算器210に出力する。Iac補償演算器210は、交流電源1から入力される電流が電流指令値Iac*に安定、かつ、速やかに実質的に一致するように所定の補償演算を行って、補償演算後の電流偏差を示す信号をPWM変調器211およびチョッピング位相幅検出器212に出力する。PWM変調器211は、入力される信号が示す補償演算後の電流偏差に対してPWM変調することにより、半導体スイッチ104をオンオフするためのチョッピング駆動信号Schを形成して、半導体スイッチ104に出力する。一方、チョッピング位相幅検出器212は、前述のように、Iac補償演算器210からPWM変調器211に出力される半導体スイッチ104に対するチョッピング駆動信号Schの原信号に基づいて、AC電圧位相検出器201からの信号が示すAC電圧の位相を基準として、チョッピング位相幅θwONを検出して、そのチョッピング位相幅θwONを示す信号を減算器204に出力する。これにより、チョッピング位相幅の制御ループが構成される。 The subtractor 209 subtracts the actual current value Iac detected by the current detector 103 from the instantaneous current command value Iac * to output a signal indicating a current deviation as a subtraction result to the Iac compensation computing unit 210. Do. The Iac compensation operation unit 210 performs a predetermined compensation operation so that the current input from the AC power supply 1 stably and promptly substantially matches the current command value Iac * , and the current deviation after the compensation operation is calculated. The signal shown is output to the PWM modulator 211 and the chopping phase width detector 212. The PWM modulator 211 generates a chopping drive signal Sch for turning on / off the semiconductor switch 104 by performing PWM modulation on the current deviation after the compensation operation indicated by the input signal, and outputs the chopping drive signal Sch to the semiconductor switch 104. . On the other hand, as described above, the chopping phase width detector 212 generates the AC voltage phase detector 201 based on the original signal of the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation operation unit 210 to the PWM modulator 211. The chopping phase width θw ON is detected on the basis of the phase of the AC voltage indicated by the signal from the signal D.2 and a signal indicating the chopping phase width θw ON is output to the subtractor 204. This constitutes a control loop of chopping phase width.
 以上のように構成された、半導体スイッチ104をチョッピング駆動制御する制御回路100においては、図2Aの減算器204よりも右側のループ(204から205,206,207,208,209,210,212を介して204に戻るループをいう。)において、チョッピング位相幅検出器212により検出されたチョッピング位相幅が目標位相幅設定器203により設定された目標位相幅に実質的に一致するようにDC電圧Vdcが制御される。また、図2Aの減算器206よりも右側のループ(206から207,208,209,210,211,104,110を介して206に戻るループをいう。)において、DC電圧検出器110により検出されたDC電圧Vdcが位相幅補償演算器205により示される所望のDC電圧Vdc*と実質的に一致するように目標電流の振幅が制御されてチョッピング駆動制御される。さらに、図2Aの減算器209よりも右側のループ(209から210,211,104,103を介して209に戻るループをいう。)において、電流検出器103により検出された電流Iacが目標電流波形形成器202により形成された目標電流波形に基づいて発生された目標電流Iac*に実質的に一致するようにチョッピング駆動制御される。 In the control circuit 100 configured to chopping drive control of the semiconductor switch 104 configured as described above, the loops (204 to 205, 206, 207, 208, 209, 210, and 212 on the right side of the subtractor 204 in FIG. DC) voltage Vdc so that the chopping phase width detected by the chopping phase width detector 212 substantially matches the target phase width set by the target phase width setter 203). Is controlled. Also, it is detected by the DC voltage detector 110 in a loop on the right side of the subtractor 206 in FIG. 2A (that is, a loop that returns to 206 via 206 to 207, 208, 209, 210, 211, 104, 110). The amplitude of the target current is controlled to perform chopping drive control so that the DC voltage Vdc substantially matches the desired DC voltage Vdc * indicated by the phase width compensation computing unit 205. Furthermore, in the loop on the right side of the subtractor 209 in FIG. 2A (the loop from 209 to 210, 211, 104, and 103 to return to 209), the current Iac detected by the current detector 103 is the target current waveform The chopping drive is controlled so as to substantially match the target current Iac * generated based on the target current waveform formed by the former 202.
 図4Aは、実施の形態1における制御装置の第1の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。また、図4Bは、実施の形態1における制御装置の第2の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。 FIG. 4A is a diagram for explaining a control operation according to a first operation example of the control device in the embodiment 1, wherein (a) relationship between AC voltage and DC voltage after rectification; (b) It is a signal waveform diagram which shows the target current waveform which should be controlled, and (c) AC current after actually controlling. FIG. 4B is a diagram for explaining the control operation according to the second operation example of the control device in the first embodiment, and (a) relationship between AC voltage and DC voltage after rectification; b) A signal waveform diagram showing a target current waveform to be controlled and (c) an AC current after actual control.
 図4Aの第1の動作例は、出力されるDC電圧が比較的低く、半導体スイッチ104に対するチョッピング位相幅(例えば、最小の位相幅)θwONが所望の位相幅θwON *よりも小さくなっている場合である。このときには、AC電圧がDC電圧より高い位相期間が増加するので、交流電源1からリアクタ102とダイオードブリッジ回路105を経由してDC側へと流れ込む電流が増加する。このため、AC電流の波形が先鋭になり、AC電流の高調波成分が増加する。 In the first operation example of FIG. 4A, the DC voltage to be output is relatively low, and the chopping phase width (for example, the minimum phase width) θw ON for the semiconductor switch 104 is smaller than the desired phase width θw ON * It is the case. At this time, since the phase period in which the AC voltage is higher than the DC voltage increases, the current flowing from the AC power supply 1 to the DC side via the reactor 102 and the diode bridge circuit 105 increases. Therefore, the waveform of the AC current is sharpened, and the harmonic component of the AC current is increased.
 一方、図4Bの第2の動作例は、出力されるDC電圧が比較的高く、半導体スイッチ104に対するチョッピング位相幅(例えば、最大の位相幅)θwONが所望の位相幅θwON *よりも大きくなっている場合である。このときには、AC電圧がDC電圧より高い位相期間が第1の動作例に比較して減少するので、交流電源1からリアクタ102とダイオードブリッジ回路105を経由してDC側へと流れ込む電流も減少し、AC電流の高調波成分が減少する。しかし、図4Bの第2の動作例は、図4Aの第1の動作例での波形に比べて、半導体スイッチ104に対するチョッピングが行われている期間が増加しているため、回路の損失が増加してしまう。 On the other hand, in the second operation example of FIG. 4B, the output DC voltage is relatively high, and the chopping phase width (for example, maximum phase width) θw ON for the semiconductor switch 104 is larger than the desired phase width θw ON * This is the case. At this time, since the phase period in which the AC voltage is higher than the DC voltage decreases in comparison with the first operation example, the current flowing from the AC power supply 1 to the DC side via the reactor 102 and the diode bridge circuit 105 also decreases. , The harmonic component of the AC current is reduced. However, in the second operation example of FIG. 4B, the period during which the semiconductor switch 104 is chopping is increased as compared to the waveform in the first operation example of FIG. Resulting in.
 ここで、交流電源1からのAC電圧にひずみが含まれていると、AC電圧の半周期の間にチョッピングがなされている区間が複数回数出現することがある。その場合には、チョッピング位相幅検出器212が、AC電圧の位相の0度又は180度に近いチョッピング位相幅を制御用チョッピング位相幅として選択して、当該チョッピング制御を行ってもよい。また、チョッピング位相幅検出器212は、AC電圧の位相の0度又は180度の代わりに、AC電流又はAC電圧の極性を判定している基準位相に近いほうの位相幅を制御用チョッピング位相幅として選択して、当該チョッピング制御を行ってもよい。さらに、チョッピング位相幅検出器212は、前記複数個得られたチョッピング位相幅を加算して、加算結果の位相幅を制御用チョッピング位相幅として当該チョッピング制御を行ってもよい。 Here, if distortion is included in the AC voltage from the AC power supply 1, a section in which chopping is performed may appear a plurality of times during a half cycle of the AC voltage. In that case, the chopping phase width detector 212 may select the chopping phase width close to 0 degree or 180 degrees of the phase of the AC voltage as the control chopping phase width to perform the chopping control. Also, the chopping phase width detector 212 controls the phase width closer to the reference phase for determining the polarity of the AC current or the AC voltage instead of 0 degree or 180 degrees of the phase of the AC voltage. May be selected to perform the chopping control. Furthermore, the chopping phase width detector 212 may perform the chopping control by adding the plurality of obtained chopping phase widths and using the phase width of the addition result as the control chopping phase width.
 本発明に係る実施の形態1の構成において、整流回路装置における制御装置としては、制御回路100とともに、交流電流検出部である電流検出器103と、直流電流検出部である電流検出器112と、直流電圧検出部であるDC電圧検出器110と、電圧レベル比較器109と、を含むものである。 In the configuration of the first embodiment according to the present invention, the control device in the rectifier circuit device includes, together with the control circuit 100, a current detector 103 which is an alternating current detection unit, and a current detector 112 which is a direct current detection unit. It includes a DC voltage detector 110 which is a DC voltage detection unit, and a voltage level comparator 109.
 また、実施の形態1における制御回路100は、波形成形部と、第1の制御部、第2の制御部、および第3の制御部に機能的に分けられる。 Further, the control circuit 100 in the first embodiment is functionally divided into a waveform shaping unit, a first control unit, a second control unit, and a third control unit.
 第1の制御部は、検出された交流電流Iacの波形が実質的に目標電流波形となるように半導体スイッチ104のチョッピング動作を制御するものである。第1の制御部は、図2Aに示す実施の形態1の構成においては、乗算器208、減算器209、Iac補償演算器210、およびPWM変調器211により構成される。 The first control unit controls the chopping operation of the semiconductor switch 104 so that the waveform of the detected alternating current Iac substantially becomes the target current waveform. In the configuration of the first embodiment shown in FIG. 2A, the first control unit is composed of a multiplier 208, a subtractor 209, an Iac compensation operation unit 210, and a PWM modulator 211.
 第2の制御部は、検出された直流電圧Vdcが実質的に所定の目標直流電圧Vdcとなるように目標電流波形の振幅を制御するものである。第2の制御部は、実施の形態1の構成においては、減算器206、Vdc補償演算器207により構成される。 The second control unit controls the amplitude of the target current waveform so that the detected DC voltage Vdc substantially becomes a predetermined target DC voltage Vdc * . In the configuration of the first embodiment, the second control unit is configured of a subtractor 206 and a Vdc compensation computing unit 207.
 第3の制御部は、半導体スイッチ104がチョッピング動作状態であるチョッピング動作位相幅、若しくは半導体スイッチ104がチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように所定の目標直流電圧Vdcを制御するものである。第3の制御部は、実施の形態1の構成においては、目標位相幅設定器203、減算器204、位相幅補償演算器205、およびチョッピング位相幅検出器212により構成される。 The third control unit sets a predetermined target such that the chopping operation phase width in which the semiconductor switch 104 is in the chopping operation state or the chopping pause phase width in which the semiconductor switch 104 is in the chopping pause state is substantially the predetermined phase width. The DC voltage Vdc * is controlled. In the configuration of the first embodiment, the third control unit is configured of the target phase width setting unit 203, the subtractor 204, the phase width compensation computing unit 205, and the chopping phase width detector 212.
 なお、実施の形態1において、目標位相幅設定器203は電流検出器103により検出された実際の電流値Iacから予め設定された関係に従い所望のチョッピング位相幅θwON *を求める構成であるが、他の構成により対応することも可能である。例えば、目標位相幅設定器203が、交流電圧の極性が固定されている期間内の電流検出器103で得た最大電流(瞬時値)を順次記憶し、予め設定されている回数の中から最も大きな電流を抽出し、位相幅設定用電流Iacpとし、実際の電流Iacの代わりに用いてもよい。または、目標位相幅設定器203においては、予め設定されている回数において記憶した最大電流(瞬時値)を用いた平均値を位相幅設定用電流Iacpとし、実際の電流Iacの代わりに用いてもよい。 In the first embodiment, the target phase width setting unit 203 is configured to obtain a desired chopping phase width θw ON * according to a preset relationship from the actual current value Iac detected by the current detector 103. It is also possible to cope with other configurations. For example, the target phase width setting unit 203 sequentially stores the maximum current (instantaneous value) obtained by the current detector 103 within the period in which the polarity of the AC voltage is fixed, and the most among the preset number. A large current may be extracted and used as the phase width setting current Iacp, and may be used instead of the actual current Iac. Alternatively, in the target phase width setting unit 203, the average value using the maximum current (instantaneous value) stored in the preset number of times may be used as the phase width setting current Iacp and used instead of the actual current Iac. Good.
 或いは、目標位相幅設定器203が、実際の電流Iacではなく、実際の電流Iacに基づいて計算される入力電力、若しくはDC電圧検出器110と電流検出器112とより計算される整流回路装置の出力電力を用いてもよい。 Alternatively, in the rectifier circuit device, the target phase width setter 203 is calculated based on the input power calculated based on the actual current Iac, not the actual current Iac, or the DC voltage detector 110 and the current detector 112. Output power may be used.
 また、負荷4がモータを含むインバータである場合は、モータへの回転数指令により所望のチョッピング位相幅θwON *が切り替わるように、外部より指示信号(図示しない)を与える方法でもよい。或いは、特定の条件において高力率や高いDC電圧を望むなどの整流回路装置を含むシステム全体の要求から所望のチョッピング位相幅θwON *が切り替わるように、外部より指示信号(図示しない)を与える方法でもよい。この方法の場合には、所望のチョッピング位相幅θwON *を180度として全域スイッチングとしてもよい。さらに、これらの方法を複合した方法でもよい。 When the load 4 is an inverter including a motor, an instruction signal (not shown) may be given from the outside so that a desired chopping phase width θw ON * is switched by a rotation speed command to the motor. Alternatively, an instruction signal (not shown) is externally provided so that the desired chopping phase width θw ON * is switched from the requirement of the entire system including the rectifier circuit device such as requiring a high power factor or a high DC voltage under a specific condition. It may be a method. In this method, the desired chopping phase width θw ON * may be 180 degrees to perform the entire area switching. Furthermore, a method combining these methods may be used.
 実施の形態1におけるチョッピング位相幅検出器212においては、Iac補償演算器210からPWM変調器211に出力される半導体スイッチ104に対するチョッピング駆動信号Schの原信号に基づいて、AC電圧位相検出器201からの信号が示すAC電圧の位相を基準として、チョッピング動作位相幅θwONを検出する構成で説明したが、本発明としては、例えば、以下に説明する図2B、図2C図2D、又は図2Eに示すような構成でも同様の作用効果を奏するものである。 In the chopping phase width detector 212 according to the first embodiment, the AC voltage phase detector 201 is used based on the original signal of the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation operator 210 to the PWM modulator 211. The chopping operation phase width .theta.w ON is detected based on the phase of the AC voltage indicated by the signal C. However, as the present invention, for example, FIG. 2B, FIG. 2C, FIG. 2D or FIG. The same effects can be obtained even with the configuration as shown.
 図2Bに示した構成においては、チョッピング駆動信号Schが入力される波形成形器111を設けて、波形成形器111がチョッピング駆動信号Schをスイッチングが連続する部分とスイッチングが停止する部分の二値信号に成形して、その二値信号をチョッピング位相幅検出器212に出力する構成である。チョッピング位相幅検出器212においては、AC電圧位相検出器201からの信号が示すAC電圧の位相を基準として、二値信号のスイッチングが連続する部分に相当する部分からチョッピング位相幅を抽出し、抽出したチョッピング位相幅をチョッピング動作位相幅θwONとしている。 In the configuration shown in FIG. 2B, a waveform shaper 111 to which a chopping drive signal Sch is input is provided, and a binary signal of a portion in which the waveform shaper 111 continuously switches the chopping drive signal Sch and a portion in which the switching is stopped. And outputs the binary signal to the chopping phase width detector 212. The chopping phase width detector 212 extracts the chopping phase width from a portion corresponding to a portion in which switching of the binary signal is continuous based on the phase of the AC voltage indicated by the signal from the AC voltage phase detector 201 and extracts the chopping phase width. The chopping phase width is set to the chopping operation phase width θw ON .
 上記のように図2Bに示した構成においても、前述の図2Aに示した構成と同様の作用効果を有する。 The configuration shown in FIG. 2B as described above also has the same effects as the configuration shown in FIG. 2A described above.
 また、図2Cに示した構成においては、チョッピング位相幅検出器212は極性が固定されている周期の間におけるチョッピング位相幅と測定期間中に電流検出器103から出力される実際の電流値Iacの最大値とを関連づけて記憶し、連続した複数の測定結果から、実際の電流値Iacが最大であるチョッピング位相幅を抽出し、抽出したチョッピング位相幅をチョッピング動作位相幅θwONとしてもよい。 Further, in the configuration shown in FIG. 2C, the chopping phase width detector 212 detects the chopping phase width during the period in which the polarity is fixed and the actual current value Iac output from the current detector 103 during the measurement period. The chopping phase width at which the actual current value Iac is maximum may be extracted from a plurality of continuous measurement results in association with the maximum value, and the extracted chopping phase width may be set as the chopping operation phase width θw ON .
 実際の電流値Iacの最大値を関連づけて記憶し用いるのは、電源高調波レベルが入力電流に比例するため、電源高調波レベルが最も大きくなる電流波形に着目してチョッピング位相幅を制御することにより、電源高調波を目標レベル以下に制御するためである。 The reason why the maximum value of the actual current value Iac is linked and stored is that the chopping phase width is controlled focusing on the current waveform where the power supply harmonic level becomes the largest since the power supply harmonic level is proportional to the input current Thus, the power supply harmonics are controlled to the target level or less.
 また、チョッピング位相幅検出器212において、連続した複数の測定結果から抽出するのは、負荷4が脈動を持つ特性の場合に、1回1回のチョッピング位相幅の測定値が異なるためである。 In addition, the reason why the chopping phase width detector 212 extracts from a plurality of continuous measurement results is that the measurement value of the chopping phase width once is different when the load 4 has a characteristic with pulsation.
 さらに、図2Dに示した構成においては、チョッピング位相幅検出器212は、極性が固定されている周期の間におけるチョッピング位相幅と測定期間中にDC電圧検出器110から出力されるDC電圧Vdcの最小値とを関連づけて記憶し、連続した複数の測定結果から、DC電圧Vdcが最小であるチョッピング位相幅を抽出し、抽出したチョッピング位相幅をチョッピング動作位相幅θwONとしている。 Furthermore, in the configuration shown in FIG. 2D, the chopping phase width detector 212 detects the chopping phase width during the period in which the polarity is fixed and the DC voltage Vdc output from the DC voltage detector 110 during the measurement period. The chopping phase width having the minimum DC voltage Vdc is extracted from a plurality of continuous measurement results in association with the minimum value, and the extracted chopping phase width is set as the chopping operation phase width θw ON .
 電源高調波のレベルは入力電流に比例する。この関係をDC電圧Vdcで置き換えると、負荷が最も大きくなる箇所ではそれだけDC電圧Vdcの電圧低下が大きくなることとなる。したがって、図2Dに示した構成においては、DC電圧Vdcの最小値と関連づけて記憶して、電源高調波レベルが最も大きくなる電流波形に着目し、チョッピング位相幅制御することにより、電源高調波を目標レベル以下に制御することができる。 The level of power supply harmonics is proportional to the input current. If this relationship is replaced with the DC voltage Vdc, the voltage drop of the DC voltage Vdc becomes large at the place where the load is the largest. Therefore, in the configuration shown in FIG. 2D, power harmonics are stored by being correlated with the minimum value of DC voltage Vdc, focusing on the current waveform where the power supply harmonic level is maximized, and chopping phase width control. It can be controlled below the target level.
 なお、連続した複数の測定結果から抽出するのは、負荷4が脈動を持つ特性の場合に、1回1回のチョッピング位相幅の測定値が異なるためである。 The reason why extraction is performed from a plurality of continuous measurement results is that, in the case where the load 4 has a characteristic with pulsation, the measurement values of the chopping phase width once are different.
 以上のように構成した場合、負荷4が脈動を持つ特性においても、図2Aに示した構成と同様の作用効果を有する。 When it comprises as mentioned above, also in the characteristic in which the load 4 has a pulsation, it has an effect similar to the structure shown to FIG. 2A.
 或いは、図2Eに示した構成においては、チョッピング位相幅検出器212は、極性が固定されている周期の間におけるPWM変調器211の出力であるパルス数を計測し、計測したパルス数にチョッピング周期を乗算することにより、チョッピング位相幅を計算し、その計算結果をチョッピング動作位相幅θwONとしてもよい。図2Eに示した構成においては、実際に半導体スイッチを駆動しているパルス数からチョッピング位相幅を制御することにより、電源高調波を目標レベル以下に制御することができる。 Alternatively, in the configuration shown in FIG. 2E, the chopping phase width detector 212 measures the number of pulses which is the output of the PWM modulator 211 during the period in which the polarity is fixed, and chopping period is measured The chopping phase width may be calculated by multiplying the chopping phase width by the chopping operation phase width θw ON . In the configuration shown in FIG. 2E, the power supply harmonic can be controlled to a target level or less by controlling the chopping phase width from the number of pulses actually driving the semiconductor switch.
 (実施の形態2)
 以下、本発明に係る実施の形態2の整流回路装置およびその整流回路装置における制御装置について説明する。
Second Embodiment
Hereinafter, a rectifier circuit device according to a second embodiment of the present invention and a control device in the rectifier circuit device will be described.
 前述の実施の形態1の整流回路装置では、チョッピングしている位相幅θwONを検出し、その位相幅θwONを用いてDC電圧指令Vdc*を調整しているが、本発明に係る実施の形態2の整流回路装置では、チョッピングが休止状態になっている位相幅(以下、「チョッピング休止位相幅」という。)θwOFFを検出し、そのチョッピング休止位相幅θwOFFを用いてDC電圧指令Vdc*を調整することにより、同様の作用効果を得るものである。 In the rectifier circuit device according to the first embodiment described above, the chopping phase width θw ON is detected and the DC voltage command Vdc * is adjusted using the phase width θw ON . In the rectifier circuit device of mode 2, the phase width (hereinafter referred to as “chopping pause phase width”) θw OFF in which chopping is in the pause state is detected, and the DC voltage command Vdc is detected using the chopping pause phase width θw OFF. Similar effects can be obtained by adjusting * .
 したがって、本発明に係る実施の形態2の整流回路装置および制御装置の構成としては、前述の実施の形態1において説明した図1および図2Aの構成と実質的に同じ構成を有するものであり、実施の形態2においては実施の形態1における符号と同じ符号を用いて説明する。 Therefore, the configurations of the rectifier circuit device and the control device of the second embodiment according to the present invention are substantially the same as the configurations of FIG. 1 and FIG. 2A described in the first embodiment, The second embodiment will be described using the same reference numerals as the reference numerals in the first embodiment.
 ただし、目標位相幅設定器203から出力される所望のチョッピング位相幅θwOFF *と、目標位相幅設定器203に入力される電流検出器103により検出された実際の電流値Iacとの関係は実施の形態1とは異なる。目標位相幅設定器203から出力される所望のチョッピング位相幅θwOFF *と、目標位相幅設定器203に入力される電流検出器103により検出された実際の電流値Iacとの関係の一例を図3Bに示す。図3Bは、目標位相幅設定器203から出力される所望のチョッピング位相幅θwOFF *と、目標位相幅設定器203に入力される電流検出器103により検出された実際の電流値Iacとの関係の一例を示したものである。 However, the relationship between the desired chopping phase width θw OFF * output from the target phase width setter 203 and the actual current value Iac detected by the current detector 103 input to the target phase width setter 203 is implemented. It is different from Form 1. The figure shows an example of the relationship between the desired chopping phase width θw OFF * output from the target phase width setter 203 and the actual current value Iac detected by the current detector 103 input to the target phase width setter 203. Shown in 3B. FIG. 3B shows the relationship between the desired chopping phase width θw OFF * output from the target phase width setter 203 and the actual current value Iac detected by the current detector 103 input to the target phase width setter 203. An example is shown.
 図3Bに示す特性は、電流検出器103により検出された実際の電流値Iacの増加に従い、所望のチョッピング位相幅θwOFF *が減少する特性である。このような特性とすることにより、低入力では高調波電流自体の大きさが小さいため損失低減を重視する一方で、高入力では高調波電流の低減を重視した特性を持たせることができる。その結果、損失低減と高調波電流の抑制を狙った特性を持たせることができる。 The characteristic shown in FIG. 3B is a characteristic in which the desired chopping phase width θw OFF * decreases as the actual current value Iac detected by the current detector 103 increases. With such characteristics, it is possible to give a characteristic that emphasizes reduction of the harmonic current at high input while emphasizing loss reduction since the magnitude of the harmonic current itself is small at low input. As a result, it is possible to provide characteristics aiming for loss reduction and suppression of harmonic current.
 なお、図3Bに示す特性では、前後を平坦にし、その間を滑らかな直線で繋いだものとしているが、チョッピング位相幅θwOFF *と電流値Iacとの関係を示す特性はこの形に限定されるものではない。 In the characteristic shown in FIG. 3B, the front and back are made flat, and between them is assumed to be connected by a smooth straight line, the characteristic showing the relationship between the chopping phase width θw OFF * and the current value Iac is limited to this shape It is not a thing.
 また、図3Bの特性図において、横軸を実際の電流値Iacとして説明しているが、電流値Iacに基づいて計算される入力電力、若しくは負荷4に流れる電流を検出する電流検出器112の出力とDC電圧検出器110の出力から得られる整流回路装置の出力電力を用いても同様の結果が得られる。 Further, in the characteristic diagram of FIG. 3B, the horizontal axis is described as the actual current value Iac, but the input power calculated based on the current value Iac or the current detector 112 for detecting the current flowing to the load 4 Similar results are obtained using the output and the output power of the rectifier circuit device obtained from the output and the output of the DC voltage detector 110.
 図5Aは、本発明に係る実施の形態2の整流回路装置における制御装置の第3の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。また、図5Bは、本発明に係る実施の形態2の整流回路装置における制御装置の第4の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。 FIG. 5A is a diagram for explaining a control operation according to a third operation example of the control device in the rectifier circuit device of the second embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control. FIG. 5B is a diagram for explaining a control operation according to a fourth operation example of the control device in the rectifier circuit device of the second embodiment of the present invention, and (a) after the rectification with the AC voltage. It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
 図5Aの第3の動作例では、出力されるDC電圧が比較的低く、半導体スイッチ104がチョッピング動作されないチョッピング休止位相幅(例えば、最大の位相幅)θwOFFが大きくなっている場合である。一方、図5Bの第4の動作例では、出力されるDC電圧が第3の動作例に比較して高く、半導体スイッチ104がチョッピングされないチョッピング休止位相幅(例えば、最小の位相幅)θwOFFが第3の動作例に比較して小さくなっている場合である。チョッピング休止位相幅θwOFFはチョッピング動作位相幅θwONと相補的であるため、同様の作用効果を得ることができる。 In the third operation example of FIG. 5A, the output DC voltage is relatively low, and the chopping pause phase width (for example, maximum phase width) θw OFF in which the semiconductor switch 104 is not chopping operated is large. On the other hand, in the fourth operation example of FIG. 5B, the chopping pause phase width (for example, minimum phase width) θw OFF in which the output DC voltage is higher than in the third operation example and the semiconductor switch 104 is not chopping This is a case where the size is smaller than that of the third operation example. Since the chopping pause phase width θw OFF is complementary to the chopping operation phase width θw ON , the same function and effect can be obtained.
 また、交流電源1からのAC電圧にひずみが含まれていると、AC電圧の半周期の間にチョッピングがなされている区間が複数回数出現することがある。このような場合には、チョッピング位相幅検出器212は、AC電圧の位相の90度に近いオフ期間のチョッピング休止位相幅θwOFFを制御用チョッピング位相幅として選択して当該チョッピング制御を行ってもよい。さらに、チョッピング位相幅検出器212は、上記複数個得られたチョッピング休止位相幅を加算し、加算結果の位相幅を制御用チョッピング位相幅として当該チョッピング制御を行ってもよい。 In addition, when distortion is included in the AC voltage from the AC power supply 1, a section in which chopping is performed may appear a plurality of times during a half cycle of the AC voltage. In such a case, the chopping phase width detector 212 selects the chopping pause phase width θw OFF of the off period close to 90 degrees of the phase of the AC voltage as the chopping phase width for control and performs the chopping control. Good. Furthermore, the chopping phase width detector 212 may perform the chopping control by adding the plurality of chopping pause phase widths obtained above and using the phase width of the addition result as the control chopping phase width.
 なお、図5Aおよび図5Bの特性図では、AC電圧の半周期分のみの波形を示しているが、図4Aおよび図4Bや従来技術などからも明らかなように、残りの半周期も絶対値(瞬時絶対値)としては同様の波形になるので省略する。 Although the characteristic diagrams of FIGS. 5A and 5B show waveforms of only half cycles of the AC voltage, as is apparent from FIGS. 4A and 4B and the prior art, the remaining half cycles also have absolute values. The waveform is the same as (instantaneous absolute value), and thus omitted.
 なお、実施の形態2においては、目標位相幅設定器203が電流検出器103により検出された実際の電流値Iacから、予め設定された関係に従い、所望のチョッピング休止位相幅θwOFF *を求める構成であるが、他の構成により対応することも可能である。例えば、目標位相幅設定器203が、交流電圧の極性が固定されている期間内の電流検出器103で得た最大電流を順次記憶し、予め設定されている回数の中から最も大きな電流を抽出し、位相幅設定用電流Iacpとし、実際の電流Iacの代わりに用いてもよい。または、目標位相幅設定器203が、記憶した最大電流を用いた平均値を位相幅設定用電流Iacpとして、実際の電流Iacの代わりに用いてもよい。 In the second embodiment, the desired phase width setting unit 203 obtains the desired chopping pause phase width θw OFF * from the actual current value Iac detected by the current detector 103 according to a preset relationship. However, other configurations are also possible. For example, the target phase width setting unit 203 sequentially stores the maximum current obtained by the current detector 103 within the period in which the polarity of the AC voltage is fixed, and extracts the largest current from the preset number of times. The phase width setting current Iacp may be used instead of the actual current Iac. Alternatively, the target phase width setting unit 203 may use an average value using the stored maximum current as the phase width setting current Iacp instead of the actual current Iac.
 或いは、目標位相幅設定器203が、実際の電流Iacではなく、実際の電流Iacに基づいて計算される入力電力、若しくはDC電圧検出器110と電流検出器112とより計算される整流回路装置の出力電力を用いてもよい。 Alternatively, in the rectifier circuit device, the target phase width setter 203 is calculated based on the input power calculated based on the actual current Iac, not the actual current Iac, or the DC voltage detector 110 and the current detector 112. Output power may be used.
 また、負荷4がモータを含むインバータである場合には、モータへの回転数指令により所望のチョッピング休止位相幅θwOFF *が切り替わるように外部より指示信号(図示しない)を与える方法でもよい。或いは、特定の条件において高力率や高いDC電圧を望むなどの整流回路装置を含むシステム全体の要求から所望のチョッピング休止位相幅θwOFF *が切り替わるように、外部より指示信号(図示しない)を与える方法でもよい。この場合は、所望のチョッピング休止位相幅θwOFF *を0度として全域スイッチングとしてもよい。さらの、これらの方法を複合した方法でもよい。 When the load 4 is an inverter including a motor, an instruction signal (not shown) may be given from the outside so that the desired chopping pause phase width θw OFF * is switched by a rotation speed command to the motor. Alternatively, an instruction signal (not shown) is externally supplied so that the desired chopping pause phase width θw OFF * is switched from the requirement of the entire system including a rectifier circuit device such as a high power factor or a high DC voltage desired in a specific condition. It may be a method of giving. In this case, the desired chopping pause phase width θw OFF * may be set to 0 degrees to perform the entire region switching. Furthermore, a combined method of these methods may be used.
 実施の形態2におけるチョッピング位相幅検出器212においては、Iac補償演算器210からPWM変調器211に出力される半導体スイッチ104に対するチョッピング駆動信号Schの原信号に基づいて、AC電圧位相検出器201からの信号が示すAC電圧の位相を基準として、チョッピング休止位相幅θwOFFを検出する構成で説明したが、本発明としては、例えば、前述の実施の形態1において説明した図2B、図2C、図2D、又は図2Eに示すような構成でも同様の作用効果を奏するものである。 In the chopping phase width detector 212 according to the second embodiment, the AC voltage phase detector 201 is used based on the original signal of the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation operation unit 210 to the PWM modulator 211. The chopping pause phase width θw OFF is detected on the basis of the phase of the AC voltage indicated by the signal of FIG. 2B, but the present invention is described with reference to FIGS. 2B, 2C, and 2 described in the first embodiment, for example. The same function and effect can be obtained with the configuration as shown in 2D or FIG. 2E.
 図2Bに示した構成を適用した場合においては、チョッピング駆動信号Schが入力される波形成形器111を設けて、波形成形器111がチョッピング駆動信号Schをスイッチングが連続する部分とスイッチングが停止する部分の二値信号に成形して、その二値信号をチョッピング位相幅検出器212に出力する構成である。チョッピング位相幅検出器212においては、AC電圧位相検出器201からの信号が示すAC電圧の位相を基準として、二値信号のスイッチングが休止する部分に相当する部分からチョッピング休止位相幅を抽出し、抽出したチョッピング休止位相幅をチョッピング休止位相幅θwOFFとしてもよい。 In the case where the configuration shown in FIG. 2B is applied, a waveform shaper 111 to which the chopping drive signal Sch is input is provided, and a portion where the waveform shaper 111 continuously switches the chopping drive signal Sch and a portion where the switching stops The binary signal is formed into a binary signal, and the binary signal is output to the chopping phase width detector 212. The chopping phase width detector 212 extracts the chopping pause phase width from a portion corresponding to a portion where switching of the binary signal is paused based on the phase of the AC voltage indicated by the signal from the AC voltage phase detector 201, The extracted chopping pause phase width may be set as the chopping pause phase width θw OFF .
 以上のように、実施の形態2の整流回路装置が図2Bに示した構成を有する場合でも、前述の図2Aに示した構成と同様の作用効果を有する。 As described above, even when the rectifier circuit device of the second embodiment has the configuration shown in FIG. 2B, it has the same function and effect as the configuration shown in FIG. 2A described above.
 また、前述の図2Cに示した構成を適用した場合においては、チョッピング位相幅検出器212は極性が固定されている周期の間におけるチョッピング休止位相幅と測定期間中に電流検出器103から出力される実際の電流値Iacの最大値(瞬時値)とを関連づけて記憶し、連続した複数の測定結果から、実際の電流値Iacが最大であるチョッピング休止位相幅を抽出し、抽出したチョッピング休止位相幅をチョッピング休止位相幅θwOFFとしてもよい。 Further, when the configuration shown in FIG. 2C described above is applied, the chopping phase width detector 212 is outputted from the current detector 103 during the chopping pause phase width during the period in which the polarity is fixed and during the measurement period. Chopping pause phase width in which the actual current value Iac is maximum is extracted from the continuous plural measurement results in association with the maximum value (instantaneous value) of the actual current value Iac. The width may be a chopping pause phase width θw OFF .
 実際の電流値Iacの最大値(瞬時値)を関連づけて記憶し用いるのは、電源高調波レベルが入力電流に比例するため、電源高調波レベルが最も大きくなる電流波形に着目してチョッピング位相幅を制御することにより、電源高調波を目標レベル以下に制御するためである。 The maximum value (instantaneous value) of the actual current value Iac is linked and stored for use because the power supply harmonic level is proportional to the input current, and focusing on the current waveform where the power supply harmonic level becomes the largest, the chopping phase width To control the power supply harmonics below the target level.
 また、チョッピング位相幅検出器212において、連続した複数の測定結果から抽出するのは、負荷4が脈動を持つ特性の場合に、1回1回のチョッピング位相幅の測定値が異なるためである。 In addition, the reason why the chopping phase width detector 212 extracts from a plurality of continuous measurement results is that the measurement value of the chopping phase width once is different when the load 4 has a characteristic with pulsation.
 さらに、図2Dに示した構成を適用した場合においては、チョッピング位相幅検出器212は、極性が固定されている周期の間におけるチョッピング休止位相幅と測定期間中にDC電圧検出器110から出力されるDC電圧Vdcの最小値とを関連づけて記憶し、連続した複数の測定結果から、DC電圧Vdcが最小であるチョッピング休止位相幅を抽出し、抽出したチョッピング休止位相幅をチョッピング休止位相幅θwOFFとしている。 Further, in the case where the configuration shown in FIG. 2D is applied, the chopping phase width detector 212 is outputted from the DC voltage detector 110 during the chopping pause phase width during the period in which the polarity is fixed and the measurement period. Chopping pause phase width with the minimum DC voltage Vdc is extracted from a plurality of continuous measurement results in association with the minimum value of the DC voltage Vdc, and the extracted chopping pause phase width is the chopping pause phase width θw OFF And
 電源高調波のレベルは入力電流に比例する。この関係をDC電圧Vdcで置き換えると、最も負荷が大きくなる箇所ではそれだけDC電圧Vdcの電圧低下が大きくなることとなる。したがって、図2Dに示した構成において、DC電圧Vdcの最小値と関連づけて記憶して、電源高調波レベルが最も大きくなる電流波形に着目し、チョッピング位相幅制御することにより、電源高調波を目標レベル以下に制御することができる。 The level of power supply harmonics is proportional to the input current. If this relationship is replaced with the DC voltage Vdc, the voltage drop of the DC voltage Vdc becomes large at the place where the load is the largest. Therefore, in the configuration shown in FIG. 2D, the power harmonics are targeted by storing them in association with the minimum value of DC voltage Vdc, focusing on the current waveform where the power harmonics level becomes the largest, and controlling the chopping phase width. It can be controlled below the level.
 なお、連続した複数の測定結果から抽出するのは、負荷4が脈動を持つ特性の場合に、1回1回のチョッピング位相幅の測定値が異なるためである。 The reason why extraction is performed from a plurality of continuous measurement results is that, in the case where the load 4 has a characteristic with pulsation, the measurement values of the chopping phase width once are different.
 上記のように実施の形態2の整流回路装置が図2B~2Dに示した構成を有する場合には、負荷4が脈動を持つ特性であっても、図2Aに示した構成と同様に優れた作用効果を有する。 As described above, when the rectifier circuit device according to the second embodiment has the configuration shown in FIGS. 2B to 2D, even if the load 4 has a characteristic with pulsation, it is excellent as in the configuration shown in FIG. 2A. It has an effect.
 (実施の形態3)
 以下、本発明に係る実施の形態3の整流回路装置およびその整流回路装置における制御装置について説明する。
Third Embodiment
Hereinafter, a rectifier circuit device according to a third embodiment of the present invention and a control device in the rectifier circuit device will be described.
 本発明に係る実施の形態3の整流回路装置は、前述の実施の形態1の整流回路装置おける制御方法を簡素化したものである。実施の形態3の整流回路装置におけるチョッピング位相幅検出器212は、0度又は180度からチョッピングが休止状態になるまでのAC電圧の極性(符号)が変化せず固定されている区間(正の区間又は負の区間)での前半の位相幅θ1wON(チョッピング位相幅)を検出して、その位相幅θ1wONを用いて当該チョッピング制御を行う。 The rectifier circuit device of the third embodiment according to the present invention is a simplification of the control method of the rectifier circuit device of the first embodiment described above. Chopping phase width detector 212 in the rectifier circuit device according to the third embodiment is a section (positive value) in which the polarity (sign) of AC voltage does not change and is fixed from 0 degrees or 180 degrees until chopping is stopped. The phase width θ1w ON (chopping phase width) of the first half in the section or negative section) is detected, and the chopping control is performed using the phase width θ1w ON .
 したがって、本発明に係る実施の形態3の整流回路装置および制御装置の構成としては、前述の実施の形態1において説明した図1および図2Aの構成と実質的に同じ構成を有するものであり、実施の形態3においては実施の形態1における符号と同じ符号を用いて説明する。 Therefore, the configurations of the rectifier circuit device and the control device of the third embodiment according to the present invention are substantially the same as the configurations of FIG. 1 and FIG. 2A described in the first embodiment, The third embodiment will be described using the same reference numerals as in the first embodiment.
 図6Aは、本発明に係る実施の形態3の整流回路装置における制御装置の第5の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。また、図6Bは、本発明に係る実施の形態3の整流回路装置における制御装置の第6の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。 FIG. 6A is a diagram for explaining the control operation according to the fifth operation example of the control device in the rectifier circuit device of the embodiment 3 of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control. FIG. 6B is a diagram for explaining the control operation according to the sixth operation example of the control device in the rectifier circuit device of the third embodiment of the present invention, and (a) after rectification with AC voltage; It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
 図6Aの第5の動作例では、出力されるDC電圧が比較的低く、半導体スイッチ104がチョッピングされる位相幅θ1wONが比較的小さくなっている場合である。一方、図6Bの第6の動作例では、出力されるDC電圧が第5の動作例に比較して高く、半導体スイッチ104がチョッピングされる位相幅θ1wONが第5の動作例に比較して大きくなっている場合である。 In the fifth operation example of FIG. 6A, the output DC voltage is relatively low, and the phase width θ1w ON at which the semiconductor switch 104 is chopped is relatively small. On the other hand, in the sixth operation example of FIG. 6B, the output DC voltage is higher than that in the fifth operation example, and the phase width θ1w ON at which the semiconductor switch 104 is chopped is higher than that in the fifth operation example. It is the case of getting bigger.
 実施の形態3の整流回路装置では、図6Aおよび図6Bに示した動作例におけるAC電圧の半周期の区間において、前半のチョッピングがなされている位相幅θ1wONは、前述の図4Aおよび図4Bに示した傾向と同様の傾向があるため、実施の形態1と同様の作用効果を得ることができる。 In the rectifier circuit device of the third embodiment, the phase width θ1w ON where chopping of the first half is performed in the half cycle period of the AC voltage in the operation example shown in FIGS. 6A and 6B corresponds to FIG. 4A and FIG. Since there is a tendency similar to the tendency shown in, it is possible to obtain the same effect as that of the first embodiment.
 (実施の形態4)
 以下、本発明に係る実施の形態4の整流回路装置およびその整流回路装置における制御装置について説明する。
Embodiment 4
Hereinafter, a rectifier circuit device of a fourth embodiment according to the present invention and a control device in the rectifier circuit device will be described.
 本発明に係る実施の形態4の整流回路装置は、前述の実施の形態3の整流回路装置と同様に、実施の形態1の整流回路装置おける制御方法を簡素化したものである。実施の形態4の整流回路装置におけるチョッピング位相幅検出器212は、0度又は180度からチョッピングが休止状態になるまでのAC電圧の極性(符号)が変化せず固定されている区間(正の区間又は負の区間)での後半の位相幅θ2wONを検出して当該チョッピング制御を行う。 The rectifier circuit device of the fourth embodiment according to the present invention is a simplification of the control method in the rectifier circuit device of the first embodiment, similarly to the rectifier circuit device of the third embodiment described above. The chopping phase width detector 212 in the rectifier circuit device according to the fourth embodiment is a section (positive value) in which the polarity (sign) of the AC voltage does not change and is fixed from 0 degrees or 180 degrees until chopping stops. The chopping control is performed by detecting the second half phase width θ2w ON in the section or the negative section).
 したがって、本発明に係る実施の形態4の整流回路装置および制御装置の構成としては、前述の実施の形態1において説明した図1および図2Aの構成と実質的に同じ構成を有するものであり、実施の形態4においては実施の形態1における符号と同じ符号を用いて説明する。 Therefore, the configuration of the rectifier circuit device and the control device of the fourth embodiment according to the present invention is substantially the same as the configuration of FIG. 1 and FIG. 2A described in the first embodiment, The fourth embodiment will be described using the same reference numerals as the reference numerals in the first embodiment.
 図7Aは、本発明に係る実施の形態4の整流回路装置における制御装置の第7の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。また、図7Bは、本発明に係る実施の形態4の整流回路装置における制御装置の第8の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。 FIG. 7A is a diagram for explaining a control operation according to a seventh operation example of the control device in the rectifier circuit device of the fourth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control. FIG. 7B is a view for explaining the control operation according to the eighth operation example of the control device in the rectifier circuit device of the fourth embodiment of the present invention, and (a) after rectification with AC voltage; It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
 図7Aの第7の動作例では、出力されるDC電圧が比較的低く、半導体スイッチ104がチョッピングされる位相幅θ2wON(チョッピング位相幅)が比較的小さくなっている場合である。一方、図7Bの第8の動作例では、出力されるDC電圧が第7の動作例に比較して高く、半導体スイッチ104がチョッピングされる位相幅θ2wONが第7の動作例に比較して大きくなっている場合である。 In the seventh operation example of FIG. 7A, the output DC voltage is relatively low, and the phase width θ2w ON (chopping phase width) at which the semiconductor switch 104 is chopping is relatively small. On the other hand, in the eighth operation example of FIG. 7B, the output DC voltage is higher than that in the seventh operation example, and the phase width θ2w ON at which the semiconductor switch 104 is chopped is higher than that in the seventh operation example. It is the case of getting bigger.
 実施の形態4の整流回路装置では、図7Aおよび図7Bに示した動作例における交流電源1の半周期の区間において、後半のチョッピングがなされている位相幅θ2wONは、前述の図4Aおよび図4Bに示した傾向と同様の傾向があるため、実施の形態1と同様の作用効果を得ることができる。 In the rectifier circuit device of the fourth embodiment, the phase width θ2w ON in which chopping in the second half is performed in the half cycle section of the AC power supply 1 in the operation example shown in FIGS. 7A and 7B corresponds to FIG. Since there is a tendency similar to the tendency shown in 4B, the same function and effect as those of Embodiment 1 can be obtained.
 (実施の形態5)
 以下、本発明に係る実施の形態5の整流回路装置およびその整流回路装置における制御装置について説明する。
Fifth Embodiment
Hereinafter, a rectifier circuit device of a fifth embodiment according to the present invention and a control device in the rectifier circuit device will be described.
 本発明に係る実施の形態5の整流回路装置は、前述の実施の形態3の整流回路装置におけるチョッピング位相幅θw1ONと、実施の形態4の整流回路装置におけるチョッピング位相幅θw2ONとの合計の位相幅(θw1ON+θw2ON)をチョッピング位相幅検出器212により検出して、当該合計の位相幅(θw1ON+θw2ON)が所望の位相幅になるようにDC電圧を制御する構成である。 Rectifier circuit device of Embodiment 5 according to the present invention, the chopping phase width Shitadaburyu1 ON in the rectifier circuit device of the third embodiment described above, the sum of the chopping phase width Shitadaburyu2 ON in the rectifier circuit of the fourth embodiment The phase width (θw1 ON + θw2 ON ) is detected by the chopping phase width detector 212, and the DC voltage is controlled so that the total phase width (θw1 ON + θw2 ON ) becomes a desired phase width.
 図8Aは、本発明に係る実施の形態5の整流回路装置における制御装置の第9の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。また、図8Bは、本発明に係る実施の形態5の整流回路装置における制御装置の第10の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。 FIG. 8A is a diagram for explaining the control operation according to the ninth operation example of the control device in the rectifier circuit device of the fifth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification; FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control. FIG. 8B is a diagram for explaining a control operation according to a tenth operation example of the control device in the rectifier circuit device of the fifth embodiment of the present invention, and (a) after the rectification with the AC voltage; It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
 図8Aの第9の動作例では、出力されるDC電圧が比較的低く、半導体スイッチ104がチョッピングされる前半のチョッピング位相幅θ1wON、および後半のチョッピング位相幅θ2wONが比較的小さくなっている場合である。一方、図8Bの第10の動作例では、出力されるDC電圧が第9の動作例に比較して高く、半導体スイッチ104がチョッピングされる前半のチョッピング位相幅θ1wON、および後半のチョッピング位相幅θ2wONが第9の動作例に比較して大きくなっている場合である。 In a ninth operation example in FIG. 8A, DC voltage output is relatively low, the chopping phase width Shita1w ON of the first half of the semiconductor switch 104 is chopped, and the second half of the chopping phase width Shita2w ON is relatively small That's the case. On the other hand, in the tenth operation example of FIG. 8B, the output DC voltage is high compared to the ninth operation example, and the first half chopping phase width θ1w ON where the semiconductor switch 104 is chopping, and the second half chopping phase width In this case, θ2w ON is larger than that in the ninth operation example.
 実施の形態5の整流回路装置では、図8Aおよび図8Bに示した動作例における交流電源1の半周期の区間において、前半のチョッピング位相幅θ1wON、および後半のチョッピング位相幅θ2wONは、前述の図4Aおよび図4Bに示した傾向と同様の傾向があるため、実施の形態1から実施の形態4と同様の作用効果を得ることができる。 The rectifier circuit device of the fifth embodiment, the half cycle of the period of the AC power supply 1 in the operation example shown in FIGS. 8A and 8B, the first half of the chopping phase width Shita1w ON, and the second half of the chopping phase width Shita2w ON is above Since there is a tendency similar to the tendency shown in FIGS. 4A and 4B, the same function and effect as those of Embodiment 1 to Embodiment 4 can be obtained.
 (実施の形態6)
 以下、本発明に係る実施の形態6の整流回路装置およびその整流回路装置における制御装置について説明する。
Sixth Embodiment
Hereinafter, a rectifier circuit device according to a sixth embodiment of the present invention and a control device in the rectifier circuit device will be described.
 図9Aは、本発明に係る実施の形態6の整流回路装置における制御装置の第11の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。また、図9Bは、本発明に係る実施の形態6の整流回路装置における制御装置の第12の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。 FIG. 9A is a diagram for explaining a control operation according to an eleventh operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control. FIG. 9B is a diagram for explaining the control operation according to a twelfth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) after rectification with AC voltage; It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
 実施の形態6の整流回路装置における制御装置は、目標電流波形が正弦波以外の波形であって、例えば三角波とすることにより、さらに回路損失を低減することができることを特徴としている。特に、負荷が軽いときには、波形歪みが増加しても、高調波電流そのものは少ないため、さらに回路損失を低減することが可能である。 The control device in the rectifier circuit device of the sixth embodiment is characterized in that the circuit loss can be further reduced by setting the target current waveform to a waveform other than a sine wave, for example, a triangular wave. In particular, when the load is light, even if the waveform distortion increases, the harmonic current itself is small, so it is possible to further reduce the circuit loss.
 図9Aの第11の動作例は、出力されるDC電圧が比較的低く、半導体スイッチ104がチョッピングされる位相幅θwONが所望の位相幅θwON *よりも小さくなっている場合である。このときにも、AC電圧がDC電圧より高い位相期間が増加するため、交流電源1からリアクタ102とダイオードブリッジ回路105を経由してDC側へと流れ込む電流が増加する。このため、AC電流の波形が先鋭になり、AC電流の高調波成分が増加する。 The eleventh operation example of FIG. 9A is a case where the output DC voltage is relatively low, and the phase width θw ON at which the semiconductor switch 104 is chopped is smaller than the desired phase width θw ON * . Also at this time, since the phase period in which the AC voltage is higher than the DC voltage increases, the current flowing from the AC power supply 1 to the DC side via the reactor 102 and the diode bridge circuit 105 increases. Therefore, the waveform of the AC current is sharpened, and the harmonic component of the AC current is increased.
 一方、図9Bの第12の動作例は、出力されるDC電圧が第11の動作例に比較して高く、半導体スイッチ104がチョッピングされる位相幅θwONが所望の位相幅θwON *よりも大きくなっている場合である。このときには、AC電圧がDC電圧より高い位相期間が減少するため、交流電源1からリアクタ102とダイオードブリッジ回路105を経由してDC側へと流れ込むAC電流が減少し、AC電流の高調波成分が減少する。しかし、図9Bの第12の動作例では、図4Aおよび図4Bと同様に、図9Aの第11の動作例の波形に比べて、半導体スイッチ104のチョッピングが行われている期間(位相幅)が増加しているため、回路の損失が増加してしまう。 On the other hand, in the twelfth operation example of FIG. 9B, the output DC voltage is higher than in the eleventh operation example, and the phase width θw ON at which the semiconductor switch 104 is chopped is higher than the desired phase width θw ON * It is the case of getting bigger. At this time, since the phase period in which the AC voltage is higher than the DC voltage decreases, the AC current flowing from the AC power supply 1 to the DC side via the reactor 102 and the diode bridge circuit 105 decreases, and harmonic components of the AC current Decrease. However, in the twelfth operation example of FIG. 9B, as in FIGS. 4A and 4B, a period (phase width) in which the chopping of the semiconductor switch 104 is performed as compared with the waveform of the eleventh operation example of FIG. The loss of the circuit will increase because
 実施の形態6においては、好ましくは、図9Aおよび図9Bに示すように、目標電流波形の瞬時の絶対値は、時間経過とともに、AC電圧の0度(開始点)から180度(終了点)までの期間の前半の期間において、一定の傾きで単調増加した後、所定の中間点(90度よりも小さい角度)から一定の傾きで単調減少し、その後終了点までゼロになる区間を有する三角波形を用いる。 In Embodiment 6, preferably, as shown in FIGS. 9A and 9B, the absolute value of the instantaneous value of the target current waveform is 0 degrees (start point) to 180 degrees (end point) of the AC voltage with the passage of time. In the first half of the period up to the end of the period, after a monotonously increasing with a constant slope, it is monotonically decreasing with a constant slope from a predetermined midpoint (an angle smaller than 90 degrees) Use a waveform.
 なお、図9Aおよび図9Bにおいて、AC電圧の半周期で1つのチョッピング位相幅θwONが図示されているため、AC電圧の1周期で2つのチョッピング休止位相幅が図示されていることになる。したがって、前述のように、2つのチョッピング休止位相幅のいずれかの位相幅、若しくは合計の位相幅に基づいてチョッピング制御してもよい。或いは、前述の実施の形態2で説明したように、AC電圧の半周期からチョッピング位相幅θwONを減算してチョッピング休止位相幅θwOFFを求める。或いは、直接にチョッピング休止位相幅θwOFFを求めて、この求めたチョッピング休止位相幅θwOFFに基づいて制御を行ってもよい。 9A and 9B, since one chopping phase width θw ON is illustrated in a half cycle of the AC voltage, two chopping pause phase widths are illustrated in one cycle of the AC voltage. Therefore, as described above, chopping control may be performed based on the phase width of any of the two chopping pause phase widths, or the total phase width. Alternatively, as described in the second embodiment, the chopping phase width θw ON is subtracted from the half cycle of the AC voltage to obtain the chopping pause phase width θw OFF . Alternatively, control may be performed based on the obtained chopping pause phase width θw OFF by directly obtaining the chopping pause phase width θw OFF .
 (実施の形態6の変形例)
 以下、本発明に係る実施の形態6の整流回路装置および制御装置の変形例について図10A~図10Dを参照して説明する。本発明に係る実施の形態6の変形例においては、図9Aおよび図9Bに示した目標電流波形とは異なる別の形状を有するものである。
(Modification of Embodiment 6)
Hereinafter, modifications of the rectifier circuit device and the control device according to the sixth embodiment of the present invention will be described with reference to FIGS. 10A to 10D. The modification of the sixth embodiment according to the present invention has another shape different from the target current waveform shown in FIGS. 9A and 9B.
 図10Aは、本発明に係る実施の形態6の整流回路装置における制御装置の第13の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。また、図10Bは、本発明に係る実施の形態6の整流回路装置における制御装置の第14の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。さらに、図10Cは、本発明に係る実施の形態6の整流回路装置における制御装置の第15の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。また、図10Dは、本発明に係る実施の形態6の整流回路装置における制御装置の第16の動作例に係る制御動作を説明するための図であって、(a)AC電圧と整流後のDC電圧との関係と、(b)制御すべき目標電流波形と、(c)実際に制御した後のAC電流とを示す信号波形図である。 FIG. 10A is a diagram for illustrating a control operation according to a thirteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) AC voltage and DC voltage after rectification FIG. 7 is a signal waveform diagram showing the relationship of (b) a target current waveform to be controlled, and (c) an AC current after actual control. FIG. 10B is a diagram for explaining the control operation according to the fourteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control. Furthermore, FIG. 10C is a diagram for explaining a control operation according to a fifteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) after rectification with AC voltage. It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control. Further, FIG. 10D is a diagram for explaining a control operation according to a sixteenth operation example of the control device in the rectifier circuit device of the sixth embodiment of the present invention, and (a) after the rectification with the AC voltage. It is a signal waveform diagram which shows the relationship with DC voltage, (b) target current waveform to be controlled, and (c) AC current after actual control.
 図10Aの第13の動作例における目標電流波形は、図9Aの第11の動作例における目標電流波形と比較して、時間経過とともに単調減少する区間の代わりに、後半の90度を超える所定の位相(例えば、110度)の中間点Tmで瞬時にゼロにする区間(ゼロで一定の区間)を有するように構成した三角波形である。 As compared with the target current waveform in the eleventh operation example of FIG. 9A, the target current waveform in the thirteenth operation example of FIG. 10A is a predetermined value exceeding 90 degrees in the latter half, instead of a monotonically decreasing section with time. It is a triangular waveform configured to have a section (zero and constant section) which is instantaneously zeroed at the midpoint Tm of the phase (for example, 110 degrees).
 また、図10Bの第14の動作例における目標電流波形は、図10Aの第13の動作例における目標電流波形と比較して、時間経過とともに単調増加する区間を正弦波状に増加させており、後半の90度を超える所定の位相(例えば、110度)の中間点Tmで瞬時にゼロになる区間(ゼロで一定の区間)を有する波形である。 Further, the target current waveform in the fourteenth operation example of FIG. 10B is sinusoidally increased in a monotonously increasing section with time as compared with the target current waveform in the thirteenth operation example of FIG. The waveform has a section (zero and constant section) which is instantaneously zero at a midpoint Tm of a predetermined phase (for example, 110 degrees) exceeding 90 degrees.
 さらに、図10Cの第15の動作例における目標電流波形は、図10Bの第14の動作例における目標電流波形において制約条件を設けて、前半部の正弦波波形において90度より手前の中間点Tmの位相(例えば、70度)で瞬時にゼロにした波形である。 Furthermore, the target current waveform in the fifteenth operation example of FIG. 10C provides a constraint condition in the target current waveform in the fourteenth operation example of FIG. 10B, and the midpoint Tm before 90 degrees in the first half sine wave waveform. The waveform is instantaneously zeroed at a phase of (for example, 70 degrees).
 また、図10Dの第16の動作例における目標電流波形は、図10Cの第15の動作例における目標電流波形において、時間経過とともに、0度から第1の中間点Tm1までの所定期間ゼロ(ゼロで一定の区間)とし、その後、第2の中間点Tm2まで単調増加させるように構成した波形である。 Further, the target current waveform in the sixteenth operation example of FIG. 10D is zero (zero) for a predetermined period from 0 degrees to the first midpoint Tm1 over time in the target current waveform in the fifteenth operation example of FIG. And a constant interval), and thereafter, it is a waveform configured to monotonously increase up to the second midpoint Tm2.
 図10Cおよび図10Dの動作例では、90度よりも手前で目標電流をゼロにしているが、ゼロにする位相よりも手前で半導体スイッチ104のチョッピング動作から、チョッピングが休止になる期間になるような負荷で使用すればよい。しかも、本動作例は、DC電圧がAC電圧の最高瞬時電圧よりも低いため、90度近傍では、交流電源1からリアクタ102とダイオードブリッジ回路105を経由して電流が流れ込む。このため、目標電流がゼロになってもAC電流がしばらくは流れ続け、高調波成分の少ない電流が高効率で実現できる。 In the operation example of FIG. 10C and FIG. 10D, the target current is set to zero before 90 degrees, but the chopping operation of the semiconductor switch 104 is before chopping operation before the phase to be zeroed. You can use it with a heavy load. Moreover, in this operation example, since the DC voltage is lower than the maximum instantaneous voltage of the AC voltage, current flows from the AC power supply 1 via the reactor 102 and the diode bridge circuit 105 in the vicinity of 90 degrees. Therefore, even if the target current is zero, the AC current continues to flow for a while, and a current with few harmonic components can be realized with high efficiency.
 以上の各実施の形態において、目標電流波形の単調増加又は単調減少において、一定である期間を含んでもよく、すなわち、実質的に単調増加又は実質的に単調減少させてもよい。ここで、「実質的に単調増加」とは、目標電流波形の位相θ1<θ2であるときに、f(θ1)≦f(θ2)の関係にある広義の単調増加をいい、言い換えれば、時間経過とともに、少なくとも増加し、若しくは少なくとも増加しかつ一部期間で一定であるように、実質的に単調増加することをいう。また、「実質的に単調減少」とは、目標電流波形の位相θ1<θ2であるときに、f(θ1)≧f(θ2)の関係にある広義の単調減少をいい、言い換えれば、時間経過とともに、少なくとも減少し、若しくは少なくとも減少しかつ一部期間で一定であるように、実質的に単調減少することをいう。 In each of the above embodiments, the monotonous increase or decrease of the target current waveform may include a fixed period, that is, it may be substantially monotonically increased or substantially monotonically decreased. Here, “substantially monotonically increasing” refers to a monotonous increase in a broad sense having a relationship of f (θ1) ≦ f (θ2) when the phase θ1 <θ2 of the target current waveform. Over time, substantially monotonically increasing so as to at least increase or at least increase and be constant over a period. Also, “substantially monotonically decreasing” refers to a monotonous decrease in a broad sense in which f (θ1) ≧ f (θ2) when the phase θ1 <θ2 of the target current waveform. And substantially monotonically decreasing so as to at least decrease or at least decrease and be constant over a period of time.
 (実施の形態7)
 以下、本発明に係る実施の形態7の整流回路装置およびその整流回路装置における制御装置について説明する。
Seventh Embodiment
Hereinafter, a rectifier circuit device according to a seventh embodiment of the present invention and a control device in the rectifier circuit device will be described.
 図11は、本発明に係る実施の形態7の整流回路装置の構成を示す回路図である。実施の形態7の整流回路装置は、交流電源1からのAC電圧を、リアクタ602を介して、半導体スイッチ604a、604bおよびダイオード605a、605b、605c、605dで構成されたブリッジ回路で整流して、平滑コンデンサ106を介して負荷4を駆動する構成を有する。 FIG. 11 is a circuit diagram showing a configuration of a rectifier circuit device according to a seventh embodiment of the present invention. In the rectifier circuit device of the seventh embodiment, the AC voltage from AC power supply 1 is rectified by a bridge circuit constituted of semiconductor switches 604a and 604b and diodes 605a, 605b, 605c and 605d via reactor 602, The load 4 is driven via the smoothing capacitor 106.
 実施の形態7の整流回路装置におけるチョッピング制御方法は、前述の図1に示した実施の形態1の整流回路装置における制御装置と同様であり、2つの半導体スイッチ604a、604bに対してチョッピング駆動信号Schを用いて同時に駆動する。 The chopping control method in the rectifier circuit device of the seventh embodiment is the same as that of the control device in the rectifier circuit device of the first embodiment shown in FIG. 1 described above, and chopping drive signals for two semiconductor switches 604a and 604b. It drives simultaneously using Sch.
 実施の形態7の整流回路装置におけるチョッピング駆動信号Schについては、前述の実施の形態1において図2A~図2Eを用いて説明した構成と同様の構成により形成することができる。また、実施の形態7の整流回路装置においても、前述の各実施の形態において説明したチョッピング制御を行うことにより、同様の作用効果を奏することができる。 The chopping drive signal Sch in the rectifier circuit device of the seventh embodiment can be formed with the same configuration as that described with reference to FIGS. 2A to 2E in the first embodiment. Also in the rectifier circuit device of the seventh embodiment, similar effects can be obtained by performing the chopping control described in each of the above-described embodiments.
 (実施の形態8)
 以下、本発明に係る実施の形態8の整流回路装置およびその整流回路装置における制御装置について説明する。
Eighth Embodiment
Hereinafter, a rectifier circuit device according to an eighth embodiment of the present invention and a control device in the rectifier circuit device will be described.
 図12は、本発明に係る実施の形態8の整流回路装置の構成を示す回路図である。実施の形態8に係る整流回路装置は、交流電源1からのAC電圧を、リアクタ702を介して、半導体スイッチ704a、704bおよびダイオード705a、705b、705c、705dで構成されたブリッジ回路で整流して、平滑コンデンサ106を介して負荷4を駆動する構成を有する。 FIG. 12 is a circuit diagram showing a configuration of a rectifier circuit device according to an eighth embodiment of the present invention. The rectifier circuit device according to the eighth embodiment rectifies AC voltage from AC power supply 1 with a bridge circuit configured of semiconductor switches 704a and 704b and diodes 705a, 705b, 705c and 705d via reactor 702. , Drive the load 4 via the smoothing capacitor 106.
 実施の形態8の整流回路装置におけるチョッピング制御方法は、交流電源1からのAC電圧の極性に応じて、2つのチョッピング駆動信号Sch1,Sch2を用いて、いずれか一方の半導体スイッチ704a又は704bのみをチョッピング動作させるものである。例えば、AC電圧の極性がリアクタ702に接続されている側が高い期間であれば、チョッピング駆動信号Sch2を用いて半導体スイッチ704bをチョッピング動作させ、AC電圧の極性がリアクタ702に接続されている側が低い期間であれば、チョッピング駆動信号Sch1を用いて半導体スイッチ704aをチョッピング動作させる。 According to the chopping control method in the rectifier circuit device of the eighth embodiment, only one of the semiconductor switches 704a or 704b is selected using two chopping drive signals Sch1 and Sch2 according to the polarity of the AC voltage from AC power supply 1. It is what makes chopping work. For example, if the period in which the polarity of the AC voltage is connected to the reactor 702 is high, the chopping drive signal Sch2 is used to chopping the semiconductor switch 704b and the polarity of the AC voltage is connected to the reactor 702 is low If it is a period, the chopping drive signal Sch1 is used to chopping the semiconductor switch 704a.
 なお、実施の形態8の整流回路装置においては、半導体スイッチ704aと704bを同時にオンさせると、負荷4へのDC出力電圧を短絡することになるため、AC電圧の極性が反転する近傍では、半導体スイッチ704aと704bのどちらもオン状態とならないように設定する必要がある場合がある。このように設定した場合には、前述の図4Aおよび図4Bにおいては、チョッピング動作が休止状態に変化する位相が、0度および180度近傍でも発生し得ることになる。ただし、この場合は、DC出力電圧の短絡防止として、意図的にチョッピング動作を休止しているため、本発明の実施の形態8の整流回路装置においては、0度および180度近傍ではチョッピング動作が休止状態に変化した位相としての取り扱いをしないことにより、容易に実現することができる。 In the rectifier circuit device according to the eighth embodiment, when the semiconductor switches 704 a and 704 b are simultaneously turned on, the DC output voltage to the load 4 is short-circuited. It may be necessary to set so that neither switch 704a nor 704b will be in an ON state. When set in this manner, in FIGS. 4A and 4B described above, the phase in which the chopping operation changes to the pause state can occur even near 0 degrees and 180 degrees. However, in this case, the chopping operation is intentionally stopped to prevent a short circuit of the DC output voltage, so in the rectifier circuit device according to the eighth embodiment of the present invention, the chopping operation is performed near 0 degrees and 180 degrees. This can be easily realized by not handling the phase changed to the resting state.
 実施の形態8の整流回路装置におけるチョッピング駆動信号Sch1,Sch2については、前述の実施の形態1において図2A~図2Eを用いて説明した構成と同様の構成により形成することができる。また、実施の形態8の整流回路装置においても、前述の各実施の形態において説明したチョッピング制御をそれぞれの半導体スイッチに対して行うことにより、同様の作用効果を奏することができる。 The chopping drive signals Sch1 and Sch2 in the rectifier circuit device of the eighth embodiment can be formed with the same configuration as that described with reference to FIGS. 2A to 2E in the first embodiment described above. Also in the rectifier circuit device of the eighth embodiment, the same operation and effect can be achieved by performing the chopping control described in each of the above-described embodiments for each semiconductor switch.
 (実施の形態9)
 以下、本発明に係る実施の形態9の整流回路装置およびその整流回路装置における制御装置について説明する。
(Embodiment 9)
Hereinafter, a rectifier circuit device according to a ninth embodiment of the present invention and a control device in the rectifier circuit device will be described.
 図13は、本発明に係る実施の形態9の整流回路装置の構成を示す回路図である。実施の形態9の整流回路装置は、交流電源1の両出力端子を整流ブリッジ105とリアクタ102を介して半導体スイッチ104がオン状態のとき、リアクタ102に電流を充電し、半導体スイッチ104がオフ状態になったときに、ダイオード304により平滑用コンデンサ106と負荷4を駆動する構成である。 FIG. 13 is a circuit diagram showing a configuration of a rectifier circuit device according to a ninth embodiment of the present invention. In the rectifier circuit device according to the ninth embodiment, when the semiconductor switch 104 is on via the rectifier bridge 105 and the reactor 102 at both output terminals of the AC power supply 1, the reactor 102 is charged with current, and the semiconductor switch 104 is off. When it becomes, the smoothing capacitor 106 and the load 4 are driven by the diode 304.
 実施の形態9の整流回路装置におけるチョッピング駆動信号Schについては、前述の実施の形態1において図2A~図2Eを用いて説明した構成と同様の構成により成形することができる。また、実施の形態9の整流回路装置においても、前述の各実施の形態において説明したチョッピング制御をそれぞれの半導体スイッチに対して行うことにより、同様の作用効果を奏することができる。 The chopping drive signal Sch in the rectifier circuit device of the ninth embodiment can be formed with the same configuration as the configuration described using FIG. 2A to FIG. 2E in the first embodiment described above. Also in the rectifier circuit device of the ninth embodiment, similar effects can be obtained by performing the chopping control described in each of the above-described embodiments for each semiconductor switch.
 以下、本発明に係る実施の形態1~9の整流回路装置において用いる電圧レベル比較器109の2値化処理について、図14Aおよび図14Bを参照して説明する。 The binarization processing of the voltage level comparator 109 used in the rectifier circuit device according to the first to ninth embodiments of the present invention will be described below with reference to FIGS. 14A and 14B.
 図14Aは、本発明に係る実施の形態1~9の整流回路装置における電圧レベル比較器109の2値化処理の第1の動作例を説明するための波形図である。図14Aの波形図においては、(a)AC電圧としきい値電圧Vthとの関係と、(b)電圧レベル比較器109からの2値信号とを示している。また、図14Bは、本発明に係る実施の形態1~9の整流回路装置における電圧レベル比較器109の2値化処理の第2の動作例を説明するための波形図である。図14Bの波形図においては、(a)AC電圧としきい値電圧Vthとの関係と、(b)電圧レベル比較器109からの2値信号とを示している。 FIG. 14A is a waveform diagram for describing a first operation example of the binarization processing of the voltage level comparator 109 in the rectifier circuit device according to the first to ninth embodiments of the present invention. The waveform diagram of FIG. 14A shows (a) the relationship between the AC voltage and the threshold voltage Vth and (b) the binary signal from the voltage level comparator 109. FIG. 14B is a waveform diagram for describing a second operation example of the binarization processing of the voltage level comparator 109 in the rectifier circuit device according to the first to ninth embodiments of the present invention. The waveform chart of FIG. 14B shows (a) the relationship between the AC voltage and the threshold voltage Vth and (b) the binary signal from the voltage level comparator 109.
 図14Aおよび図14Bは、AC電圧が一定のレベル以上か否かの情報から電圧位相を検出する方法を示している。この情報は、AC電圧の瞬時電圧がしきい値を超えているか否かを2値信号として得るものである。すなわち、電圧レベル比較器109は、AC電圧をしきい値電圧Vthと比較し、AC電圧がしきい値電圧Vth以上のときハイレベル信号を出力する一方、AC電圧がしきい値電圧Vth未満のときローレベル信号を出力する。 FIGS. 14A and 14B show a method of detecting a voltage phase from information on whether the AC voltage is equal to or higher than a certain level. This information is used to obtain, as a binary signal, whether the instantaneous voltage of the AC voltage exceeds a threshold. That is, the voltage level comparator 109 compares the AC voltage with the threshold voltage Vth, and outputs a high level signal when the AC voltage is higher than the threshold voltage Vth, while the AC voltage is lower than the threshold voltage Vth. When low level signal is output.
 ここで、しきい値電圧Vthが変動しても2値信号の周期は電源周波数と同一であり、2値信号のハイレベル側又はローレベル側の中点を求めれば、AC電圧位相の90度又は270度の時間を知ることができる。また、AC電圧位相の90度と270度の中点は180度および0度の位相になる。このようにして得られた情報を、PLLなどを用いて逓倍すれば、瞬時瞬時の位相を正確に知ることができる。 Here, even if the threshold voltage Vth fluctuates, the cycle of the binary signal is the same as the power supply frequency, and if the middle point of the high level side or the low level side of the binary signal is determined, the AC voltage phase is 90 degrees. Or you can know the time of 270 degrees. Also, the midpoint of the AC voltage phase of 90 degrees and 270 degrees is 180 degrees and 0 degrees of phase. If the information obtained in this manner is multiplied using a PLL or the like, it is possible to accurately know the instantaneous phase.
 例えば、360逓倍すれば、1つのパルスが1度相当になり、このパルスを計数すれば、単位が度の位相情報を得ることができる。そして、得られた位相情報で、その瞬時瞬時の目標電流波形を呼び出せばよい。その他のレベル比較から得られた2値情報を用いて位相を検出する方法については、例えば、本発明者が開示した特許文献4にも提案されており、特に限定されるものではない。 For example, if it is multiplied by 360, one pulse corresponds to one degree, and if this pulse is counted, phase information whose unit is degree can be obtained. Then, based on the obtained phase information, the instantaneous target current waveform may be recalled. About the method of detecting a phase using the binary information obtained from other level comparisons, for example, it is proposed also to patent documents 4 which the present inventor indicated, and it is not limited in particular.
 上記のように、本発明に係る実施の形態1~9の整流回路装置においては、DC電圧の検出精度に誤差があっても、チョッピング動作を行っている位相幅が、所望の位相幅になるようにDC電圧を相対的に調整している。このため、本発明に係る実施の形態1~9の整流回路装置においては、同様の電流波形となり、常に回路損失が少なく、かつ高調波電流が少ない整流動作を実現することができる。 As described above, in the rectifier circuit devices according to the first to ninth embodiments of the present invention, even if there is an error in the DC voltage detection accuracy, the phase width during chopping operation becomes a desired phase width. To adjust the DC voltage relatively. Therefore, in the rectifier circuit devices of Embodiments 1 to 9 according to the present invention, the same current waveform is obtained, and it is possible to realize the rectification operation with less circuit loss and less harmonic current.
 (実施の形態10)
 以下、本発明に係る実施の形態10の整流回路装置およびその整流回路装置のための制御回路について説明する。
Tenth Embodiment
The rectifier circuit device according to the tenth embodiment of the present invention and the control circuit for the rectifier circuit device will be described below.
 図15は、本発明に係る実施の形態10の整流回路装置における制御回路100の詳細構成を示すブロック図である。実施の形態10の整流回路装置における制御回路100は、前述の図2Aに示した実施の形態1の整流回路装置における制御回路100と比較して、DC電圧検出器110と減算器206との間に、AD変換部であるAD変換器230と、および演算部であるローパスフィルタ演算器(以下、「LPF演算器」という。)231と、を挿入した構成である。実施の形態10の整流回路装置は、デジタル演算で実施する場合に特に有効な実施の形態を提供するものである。以下、図2Aに示した制御回路100との相違点について説明する。 FIG. 15 is a block diagram showing a detailed configuration of the control circuit 100 in the rectifier circuit device of the tenth embodiment according to the present invention. The control circuit 100 in the rectifier circuit device of the tenth embodiment is between the DC voltage detector 110 and the subtractor 206 in comparison with the control circuit 100 in the rectifier circuit device of the first embodiment shown in FIG. 2A described above. , And an AD converter 230 which is an AD conversion unit, and a low pass filter operation unit (hereinafter referred to as “LPF operation unit”) 231 which is an operation unit. The rectifier circuit device of the tenth embodiment provides an embodiment that is particularly effective when implemented by digital operation. Hereinafter, differences from the control circuit 100 shown in FIG. 2A will be described.
 図15において、DC電圧検出器110により検出されたDC電圧Vdcを示すアナログ信号は、交流電源1の周波数よりも十分に高いサンプリング周波数でAD変換するAD変換器230により、AD変換値Vadを示すデジタル信号に変換される。AD変換器230からのAD変換値Vadは、低域通過フィルタ特性を有する演算(詳細後述)を行うLPF演算器231に入力されて、LPF演算される。LPF演算器231における演算結果を示す信号(LPF演算値Vdca)は減算器206に出力される。実施の形態10の整流回路装置においては、例えば、交流電源1の周波数が60Hzであり、サンプリング周波数が600kHzである。 In FIG. 15, an analog signal indicating the DC voltage Vdc detected by the DC voltage detector 110 indicates an AD conversion value Vad by the AD converter 230 that AD converts at a sampling frequency sufficiently higher than the frequency of the AC power supply 1. It is converted to a digital signal. The AD conversion value Vad from the AD converter 230 is input to the LPF computing unit 231 that performs computation (details will be described later) having low-pass filter characteristics, and is subjected to LPF computation. A signal (LPF calculation value Vdca) indicating the calculation result in the LPF calculator 231 is output to the subtractor 206. In the rectifier circuit device of the tenth embodiment, for example, the frequency of the AC power supply 1 is 60 Hz, and the sampling frequency is 600 kHz.
 図16は、図15に示した制御回路100におけるLPF演算器231の詳細構成を示すブロック図である。図16において、AD変換器230からのAD変換値Vadを示す信号は、LPF演算器231における加算器253に入力される。加算器253は、入力されるAD変換値Vadを示す信号と、定数乗算器251からの信号とを加算して、加算結果であるLPF演算値Vdcaを示す信号を減算器206に出力するとともに、1つのクロック時間だけ遅延する遅延器252を介して定数乗算器251に出力する。定数乗算器251は、入力される信号に対して所定の定数(2-1)/(2)を乗算して、その乗算結果を示す信号を加算器253に出力する。 FIG. 16 is a block diagram showing a detailed configuration of the LPF computing unit 231 in the control circuit 100 shown in FIG. In FIG. 16, the signal indicating the AD conversion value Vad from the AD converter 230 is input to the adder 253 in the LPF computing unit 231. The adder 253 adds the signal indicating the AD conversion value Vad to be input and the signal from the constant multiplier 251, and outputs a signal indicating the LPF operation value Vdca which is the addition result to the subtractor 206. The signal is output to the constant multiplier 251 via the delay unit 252 delayed by one clock time. The constant multiplier 251 multiplies the input signal by a predetermined constant (2 n -1) / (2 n ), and outputs a signal indicating the multiplication result to the adder 253.
 図16に示すLPF演算器231による演算を、入力をX(j)、出力をY(j)とし、時系列の漸化式で表現すると、次式(1)のようになる。 Assuming that the operation by the LPF computing unit 231 shown in FIG. 16 is X (j) as an input and Y (j) as an output, and expressed as a time-series recurrence formula, the following equation (1) is obtained.
Y(j+1)←[(2-1)/(2)]×Y(j)+X(j)・・・(1) Y (j + 1) ← [(2 n -1) / (2 n )] × Y (j) + X (j) (1)
 このLPF演算処理は、演算周期の「2」倍の時定数を有する一次型の低域通過フィルタであり、かつ、振幅が「2」倍になる。したがって、このLPF演算処理を実行することにより、AD変換値Vadに小数点以下のnビットの情報が追加される。 This LPF calculation processing is a linear low-pass filter having a time constant of “2 n ” times the calculation cycle, and the amplitude is “2 n ” times. Therefore, by executing this LPF calculation process, n bits of information after the decimal point are added to the AD conversion value Vad.
 図17は、図15に示した整流回路装置における制御回路100の動作を示す信号波形図である。図17の信号波形図において、(a)交流電源1からのAC電流Iac、(b)DC電圧Vdc、および(c)AD変換器230のAD変換値Vadを示す。なお、図17における(c)においては、DC電圧Vdcを点線で示す。すなわち、図17は、単相ACの整流回路で低域通過フィルタ処理を行うことにより、電圧検出精度を向上させることができる動作原理を示す。 FIG. 17 is a signal waveform diagram representing an operation of control circuit 100 in the rectifier circuit device shown in FIG. In the signal waveform diagram of FIG. 17, (a) AC current Iac from AC power supply 1, (b) DC voltage Vdc, and (c) AD conversion value Vad of AD converter 230 are shown. In (c) of FIG. 17, the DC voltage Vdc is indicated by a dotted line. That is, FIG. 17 shows an operation principle capable of improving voltage detection accuracy by performing low-pass filter processing with a single-phase AC rectifier circuit.
 単相交流電源1からのAC電圧にはゼロの区間があり、瞬時瞬時の電力が一定でないため、平滑コンデンサ106を用いても、DC電圧には電源周波数の2倍の周波数を有する変動が残る。この変動を少なくするには、平滑コンデンサ106のコンデンサ容量を無限に大きくする必要があり、現実的には不可能である。 Since the AC voltage from single-phase AC power supply 1 has a section of zero and the instantaneous power is not constant, DC voltage still has a fluctuation having a frequency twice the power supply frequency even if smoothing capacitor 106 is used. . In order to reduce this fluctuation, the capacity of the smoothing capacitor 106 needs to be increased infinitely, which is practically impossible.
 図17における(c)には、点線で示すDC電圧Vdcと、このDC電圧Vdcを交流電源1の周波数よりも十分に高いサンプリング周波数でAD変換した場合のAD変換値Vadとを示す。ここで、十分に高いサンプリング周波数とは、交流電源1の周波数に比べて2倍以上の周波数をいう。瞬時瞬時のDC電圧Vdcに応じて、得られるAD変換値Vad(デジタル値)はK,K+1,K+2,K+3,…の値をとる。ここで、AD変換値Vadに対して低域通過フィルタ演算を行うと、図17の場合には、(K+1)と(K+2)の間の値に収束する。さらに、図16で示したように、低域通過フィルタ演算として2倍する機能を含んでいるため、{(K+1)×2}と{(K+2)×2}との間の値(整数値)が得られる。つまり、AD変換器230の分解能に対して、小数点以下のnビットの情報が追加されて、分解能が改善されたことになる。なお、DC電圧Vdcに電源周波数の2倍の周波数を有する変動が全く無く、図17における(c)の平均値のような場合には、AD変換値Vadは常に(K+1)になり、LPF演算をしても、分解能を改善することはできない。すなわち、このLPF演算の手法(低域通過フィルタ処理)は、単相ACの整流回路装置により、その効果を発揮することができる。 (C) in FIG. 17 shows a DC voltage Vdc indicated by a dotted line and an AD conversion value Vad when the DC voltage Vdc is AD converted at a sampling frequency sufficiently higher than the frequency of the AC power supply 1. Here, a sufficiently high sampling frequency means a frequency twice or more that of the AC power supply 1. According to the instantaneous DC voltage Vdc, the obtained AD conversion value Vad (digital value) takes values of K, K + 1, K + 2, K + 3,. Here, when the low-pass filter calculation is performed on the AD conversion value Vad, in the case of FIG. 17, the value converges to a value between (K + 1) and (K + 2). Furthermore, as shown in FIG. 16, since it includes a function of multiplying by 2 n as a low-pass filter operation, a value between {(K + 1) × 2 n } and {(K + 2) × 2 n } Integer value is obtained. That is, n bits of information after the decimal point is added to the resolution of the AD converter 230 to improve the resolution. In the case where there is no fluctuation in the DC voltage Vdc having a frequency twice as high as the power supply frequency, such as the average value of (c) in FIG. 17, the AD conversion value Vad always becomes (K + 1) However, the resolution can not be improved. That is, the method (low-pass filter processing) of the LPF calculation can exhibit its effect by the single-phase AC rectifier circuit device.
 (実施の形態10の変形例および補足説明)
 前述の図2Aに示した実施の形態1の整流回路装置における減算器206において、指令電圧Vdc*にもAD変換器230と同等の分解能を有する必要がある。指令電圧Vdc*は情報のみであるため、上記の実施の形態10と同様に分解能を高めておくことは、容易に実現することができる。
(Modified example and supplementary description of the tenth embodiment)
In the subtractor 206 in the rectifier circuit device of the first embodiment shown in FIG. 2A described above, the command voltage Vdc * also needs to have the same resolution as that of the AD converter 230. Since command voltage Vdc * is only information, it is possible to easily realize an increase in resolution as in the above-described tenth embodiment.
 また、LPF演算では2の累乗を用いる事例で説明したが、定数乗算器251の定数を0から1の間の値に設定すれば、同様にLPF演算を実現することができる。また、図17の動作原理から明らかなように、LPF演算が図16で示した構成以外の手法でも同様の効果を得ることができる。 Also, although the LPF operation has been described as an example using a power of 2, if the constant of the constant multiplier 251 is set to a value between 0 and 1, the LPF operation can be realized similarly. Further, as is clear from the operation principle of FIG. 17, similar effects can be obtained by methods other than the configuration shown in FIG.
 実施の形態10の整流回路装置の構成においては、AD変換器230の分解能が粗い場合でも、きめ細かい電圧情報を得ることができるため、DC電圧Vdcを高精度に調節することができ、常に回路損失が少なく、かつ、高調波電流が少ない整流動作を実現することができる。 In the configuration of the rectifier circuit device of the tenth embodiment, fine voltage information can be obtained even when the resolution of AD converter 230 is coarse, so that DC voltage Vdc can be adjusted with high precision, and circuit loss can always be achieved. Can realize a rectification operation with a small number of harmonic currents and a small number of harmonic currents.
 また、実施の形態10の整流回路装置における電圧検出精度を向上させる手法は、これまで説明した実施の形態1~9に組み合わせて実施することが可能である。 Further, the method for improving the voltage detection accuracy in the rectifier circuit device of the tenth embodiment can be implemented in combination with the first to ninth embodiments described above.
 なお、本発明に係る各実施の形態において、実質的にというのは、おおよそ、或いは平均的にという意味で用いている。 In each of the embodiments according to the present invention, the term "substantially" is used to mean approximately or on average.
 本発明の整流回路装置の制御回路および整流回路装置においては、上記各実施の形態により明らかなように、直流電圧の検出精度に誤差があっても、直流電圧が相対的に適正な値に調整されて、同様の電流波形になり、かつ負荷の状況、或いは外部からの指令に応じて所望の位相幅を変更することができる。また、本発明によれば、負荷の変動状況によらず所望の位相幅と比較するチョッピング動作位相幅、或いはチョッピング休止位相幅を的確に計測することにより、常に回路損失が少なく、かつ高調波電流が少ない整流動作を実現することができる。 In the control circuit and the rectifier circuit device of the rectifier circuit device according to the present invention, as apparent from the above embodiments, even if there is an error in the detection accuracy of the DC voltage, the DC voltage is adjusted to a relatively appropriate value. Thus, the same current waveform can be obtained, and the desired phase width can be changed in accordance with the load condition or an external command. Further, according to the present invention, circuit loss is always reduced and harmonic current is constantly measured by accurately measuring the chopping operation phase width or chopping pause phase width to be compared with the desired phase width regardless of the load fluctuation state. Can realize a rectification operation with less
 また、本発明においては、交流電源の周波数よりも十分に高いサンプリング周波数で、直流電圧をAD変換部により、デジタル信号に変換して検出し、得られたデジタル信号を周期毎にLPF演算を実行して、デジタル信号に分解能以下の微小情報を補間するように追加している。さらに、本発明においては、微小情報を補間したデジタル信号を直流電圧情報として、チョッピングが実際になされている位相幅が所望の値になるように、微小情報を補間したデジタル信号を調整している。直流電圧の平滑電圧に含まれている電源周波数成分には揺らぎがあり、デジタル情報の分解能が粗い場合でも、揺らぎによりデジタル信号が分散されるため、本発明によれば、平均的には高い分解能と等価なデジタル信号を得ることができる。これによって、本発明においては、粗い分解能のAD変換手段を用いても、直流電圧の平均値を高精度に調節することができ、常に損失が少なく、かつ、高調波電流が少ない整流動作を実現することができる。したがって、本発明に係る整流回路装置は、接続された負荷の状況に応じて所望の位相幅を変更することで常に損失が少なく、かつ高調波電流が少ない整流動作を実現することができる。 Further, in the present invention, the DC voltage is converted into a digital signal by the A / D conversion unit and detected at a sampling frequency sufficiently higher than the frequency of the AC power supply, and the obtained digital signal is subjected to LPF calculation for each cycle. Then, it is added to the digital signal so as to interpolate minute information below the resolution. Furthermore, in the present invention, a digital signal obtained by interpolating minute information is used as DC voltage information, and the digital signal obtained by interpolating the minute information is adjusted so that the phase width actually being chopping becomes a desired value. . According to the present invention, according to the present invention, the power supply frequency component contained in the smoothed voltage of the DC voltage has fluctuations, and even if the resolution of the digital information is coarse, the digital signals are dispersed by the fluctuations. It is possible to obtain a digital signal equivalent to By this, in the present invention, even if coarse resolution AD conversion means are used, the average value of DC voltage can be adjusted with high accuracy, and a rectification operation with less loss and less harmonic current is always realized. can do. Therefore, the rectifier circuit device according to the present invention can realize the rectification operation with less loss and less harmonic current by changing the desired phase width according to the state of the connected load.
 なお、本発明における全ての実施の形態に共通することとして、チョッピングが休止状態からチョッピング状態に変化する際に、回路の揺らぎやノイズにより、一瞬だけ休止状態に再度変化する場合がある。このような場合については、本発明でのチョッピングが休止状態に変化した位相としての取り扱いをしないことにより、本発明の整流回路装置および制御回路の構成を容易に実現することができる。 As common to all the embodiments in the present invention, when chopping changes from the paused state to the chopping state, it may change to the paused state only for a moment due to the fluctuation or noise of the circuit. In such a case, the configuration of the rectifier circuit device and the control circuit of the present invention can be easily realized by not treating the chopping in the present invention as a phase changed to the inactive state.
 さらに、本発明に係る実施の形態においては、AC電圧位相検出器201においてAC電圧の位相を検出し、その検出された位相を基準としてチョッピング位相幅を検出する構成で説明したが、本発明はこのような構成に限定されるものではない。例えば、本発明における構成としては、交流電源の周波数が固定されている場合には、交流電源のゼロクロスなどの情報に基づいて、チョッピング位相幅を検出してもよい。また、チョッピング位相幅を検出するときに、チョッピング手法の一例であるPWM制御を実現するキャリア信号のパルス数で計数することにより、チョッピング位相幅の時間を計測してもよい。 Furthermore, in the embodiment according to the present invention, the AC voltage phase detector 201 detects the phase of the AC voltage, and the chopping phase width is detected based on the detected phase. It is not limited to such a configuration. For example, as the configuration in the present invention, when the frequency of the AC power supply is fixed, the chopping phase width may be detected based on information such as the zero cross of the AC power supply. In addition, when detecting the chopping phase width, the time of the chopping phase width may be measured by counting by the number of pulses of the carrier signal for realizing the PWM control which is an example of the chopping method.
 本発明をある程度の詳細さをもって各実施の形態において説明したが、これらの実施の形態の開示内容は構成の細部において変化してしかるべきものであり、各実施の形態における要素の組合せや順序の変化は請求された本発明の範囲および思想を逸脱することなく実現し得るものである。 Although the present invention has been described in the embodiments with a certain degree of detail, the disclosed contents of these embodiments should be changed in the details of the configuration, and the combination and order of the elements in the embodiments can be appropriately changed. Changes can be made without departing from the scope and spirit of the claimed invention.
 本発明に係る整流回路装置は、高調波電流の抑制と回路損失の低減を両立することが可能となるため、圧縮機により冷媒を圧縮することによりヒートポンプを構成し、冷房、暖房、あるいは食品などの冷凍を行うもの等の各種用途に幅広く適用できる。 The rectifier circuit device according to the present invention can achieve both suppression of harmonic current and reduction of circuit loss. Therefore, a heat pump is configured by compressing a refrigerant with a compressor, and cooling, heating, food, etc. It can be widely applied to various applications such as those that perform refrigeration.
 1 交流電源
 4 負荷
 100 制御回路
 102,602,702 リアクタ
 103,112 電流検出器
 104,604a,604b,704a,704b 半導体スイッチ
 105 ダイオードブリッジ回路
 106 平滑コンデンサ
 109 電圧レベル比較器
 110 DC電圧検出器
 111 波形成形器
 201 AC電圧位相検出器
 202 目標電流波形形成器
 203 目標位相幅設定器
 204,206,209 減算器
 205 位相幅補償演算器
 207 Vdc補償演算器
 208 乗算器
 210 Iac補償演算器
 211 PWM変調器
 212 チョッピング位相幅検出器
 230 AD変換器
 231 ローパスフィルタ演算器(LPF演算器)
 251 定数乗算器
 252 遅延器
 253 加算器
 605a~605d,705a~705d ダイオード
Reference Signs List 1 AC power supply 4 load 100 control circuit 102, 602, 702 reactor 103, 112 current detector 104, 604a, 604b, 704a, 704b semiconductor switch 105 diode bridge circuit 106 smoothing capacitor 109 voltage level comparator 110 DC voltage detector 111 waveform Shaper 201 AC voltage phase detector 202 Target current waveform shaper 203 Target phase width setter 204, 206, 209 Subtractor 205 Phase width compensation computing unit 207 Vdc compensation computing unit 208 Multiplier 210 Iac compensation computing unit 211 PWM modulator 212 Chopping phase width detector 230 AD converter 231 low pass filter calculator (LPF calculator)
251 constant multiplier 252 delay device 253 adder 605a to 605d, 705a to 705d diode

Claims (14)

  1.  半導体スイッチをチョッピング動作させることにより、単相交流電源からの交流電圧、或いは該交流電圧を整流した脈動電圧を、リアクタを介して短絡又は開放して、前記単相交流電源から直流電圧に整流して、負荷に電力を供給する整流回路装置の制御装置であって、
     前記制御装置は、
     前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成部と、
     前記単相交流電源から流れる交流電流を検出する交流電流検出部と、
     前記直流電圧を検出する直流電圧検出部と、
     前記検出された交流電流の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第1の制御部と、
     前記検出された直流電圧が実質的に所定の目標直流電圧となるように前記目標電流波形の振幅を制御する第2の制御部と、
     前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、若しくは前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第3の制御部と、
    を備えたことを特徴とする整流回路装置の制御装置。
    The chopping operation of the semiconductor switch shorts or opens the alternating voltage from the single phase alternating current power supply or the pulsating voltage obtained by rectifying the alternating current voltage through the reactor to rectify the single phase alternating current power supply into the direct current voltage. Control device of the rectifier circuit device for supplying power to the load,
    The controller is
    A waveform forming unit that forms a target current waveform having the same frequency as the waveform of the AC voltage;
    An alternating current detection unit that detects an alternating current flowing from the single-phase alternating current power supply;
    A DC voltage detection unit that detects the DC voltage;
    A first control unit configured to control a chopping operation of the semiconductor switch such that a waveform of the detected alternating current substantially becomes the target current waveform;
    A second control unit configured to control an amplitude of the target current waveform such that the detected DC voltage substantially becomes a predetermined target DC voltage;
    The predetermined target DC voltage is controlled such that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping pause phase width in which the semiconductor switch is in a chopping pause state is substantially a predetermined phase width. 3 controls,
    A control device for a rectifier circuit device, comprising:
  2.  前記所定の位相幅は、電源半周期に対して0度から180度の範囲で、負荷の状況、若しくは外部からの指令に応じて変更して設定されるよう構成された請求項1記載の整流回路装置の制御装置。 The rectifier according to claim 1, wherein the predetermined phase width is changed and set in a range of 0 degree to 180 degrees with respect to a power supply half cycle according to a load condition or an external command. Control device of circuit device.
  3.  前記負荷の状況は、前記交流電流の値、前記交流電流に基づいて計算される入力電力、または前記整流回路装置の出力電力で示されるよう構成された請求項2記載の整流回路装置の制御装置。 The control device for a rectifier circuit device according to claim 2, wherein the status of the load is configured to be indicated by the value of the AC current, the input power calculated based on the AC current, or the output power of the rectifier circuit device. .
  4.  前記第3の制御部は、前記交流電圧の極性が固定されている期間内において検出されるチョッピング休止位相幅若しくはチョッピング動作位相幅の瞬時値、または予め設定されている回数による平均値が、実質的に所定の位相幅となるように前記所定の目標直流電圧を制御するよう構成された請求項1乃至3のいずれか一項に記載の整流回路装置の制御装置。 In the third control unit, an instantaneous value of the chopping pause phase width or chopping operation phase width detected within a period in which the polarity of the alternating voltage is fixed, or an average value by a preset number of times is substantially The control device of the rectifier circuit device according to any one of claims 1 to 3, configured to control the predetermined target DC voltage so that the predetermined phase width is achieved.
  5.  前記第3の制御部は、所定の期間における最も低い前記直流電圧時を含む、前記交流電圧の極性が固定されている期間内において検出されたチョッピング休止位相幅、若しくはチョッピング動作位相幅が、実質的に所定の位相幅となるように前記所定の目標直流電圧を制御するよう構成された請求項1乃至3のいずれか一項に記載の整流回路装置の制御装置。 In the third control unit, the chopping pause phase width or chopping operation phase width detected in a period in which the polarity of the AC voltage is fixed, including the lowest DC voltage in a predetermined period, is substantially The control device of the rectifier circuit device according to any one of claims 1 to 3, configured to control the predetermined target DC voltage so that the predetermined phase width is achieved.
  6.  前記第3の制御部は、所定の期間における最も大きい前記交流電流時を含む、前記交流電圧の極性が固定されている期間内において検出されたチョッピング休止位相幅、若しくはチョッピング動作位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御するよう構成された請求項1乃至3のいずれか一項に記載の整流回路装置の制御装置。 The third control unit is configured such that a chopping pause phase width or chopping operation phase width detected within a period in which the polarity of the AC voltage is fixed, including the largest AC current in a predetermined period, is substantially The control device for a rectifier circuit device according to any one of claims 1 to 3, configured to control the predetermined target DC voltage so as to have a predetermined phase width.
  7.  前記第3の制御部は、前記交流電圧の極性が固定されている期間内において、複数の前記チョッピング動作位相幅、若しくは複数の前記チョッピング休止位相幅が存在するときに、当該期間内のいずれかの位相幅、若しくは合計の位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御するよう構成された請求項1乃至6のいずれか一項に記載の整流回路装置の制御装置。 When a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths exist in a period in which the polarity of the alternating voltage is fixed, the third control unit is in any of the periods. The rectifier circuit device according to any one of claims 1 to 6, which is configured to control the predetermined target DC voltage so that the phase width of or the total phase width is substantially equal to the predetermined phase width. Control device.
  8.  前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、(a)当該期間の開始点から、所定の中間点までは、時間経過とともに、少なくとも増加し、若しくは少なくとも増加し、かつ、一部期間で一定であるように実質的に単調増加し、(b)前記中間点から終了点までは、時間経過とともに、少なくとも減少し、若しくは少なくとも減少し、かつ、一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定された請求項1乃至7のいずれか一項に記載の整流回路装置の制御装置。 In the target current waveform, in the period in which the instantaneous absolute value of the target current waveform is fixed in the polarity of the AC voltage, (a) time elapses from the start point of the period to the predetermined middle point And at least increase, or at least increase, and substantially monotonously increase so as to be constant over a period, and (b) at least decrease from the midpoint to the end over time, or The rectifier circuit device according to any one of claims 1 to 7, wherein it is set to have a period which becomes at least decreasing and then substantially monotonically decreasing so as to be constant for part of the period and then becomes zero. Control device.
  9.  前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、(a)当該期間の開始点から、所定の第1の中間点までは、時間経過とともに、ゼロとなる期間を有し、(b)前記第1の中間点から所定の第2の中間点までは、少なくとも増加し、若しくは少なくとも増加し、かつ、一部期間で一定であるように実質的に単調増加し、(c)前記第2の中間点から終了点までは、時間経過とともに、少なくとも減少し、若しくは少なくとも減少し、かつ、一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定された請求項1乃至7のいずれか一項に記載の整流回路装置の制御装置。 The target current waveform is (a) from the start point of the period to a predetermined first intermediate point within a period in which the absolute value of the instantaneous value of the target current waveform is fixed in polarity of the AC voltage. (B) at least increasing or at least increasing from the first intermediate point to a predetermined second intermediate point, and constant over a period of time, (C) substantially substantially monotonically increasing, and (c) at least decreasing or at least decreasing with the passage of time from the second intermediate point to the end point, and being constant for a part period The control device of the rectifier circuit device according to any one of claims 1 to 7, wherein the control device is set to have a period which becomes zero after being monotonically decreased.
  10.  前記交流電圧を所定のしきい値電圧と比較することにより2値信号を発生する位相検出部をさらに備え、
     前記波形形成部は、前記2値信号に基づいて前記交流電圧の周期および位相を検出し、当該検出された交流電圧の周期および位相に基づいて、前記交流電圧の波形と同一周波数の目標電流波形を形成し、
     前記第3の制御部は、前記2値信号に基づいて、前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、若しくは前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅を検出するよう構成された請求項1乃至9のいずれか一項に記載の整流回路装置の制御装置。
    It further comprises a phase detection unit that generates a binary signal by comparing the AC voltage with a predetermined threshold voltage,
    The waveform forming unit detects a cycle and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the cycle and the phase of the detected AC voltage. Form
    The third control unit is configured to detect a chopping operation phase width in which the semiconductor switch is in the chopping operation state or a chopping pause phase width in which the semiconductor switch is in the chopping suspension state based on the binary signal. A control device of a rectifier circuit device according to any one of claims 1 to 9.
  11.  前記制御装置はさらに、前記直流電圧検出部と前記第2の制御部との間に設けられ、前記検出された直流電圧をデジタル電圧にAD変換するAD変換部と、前記AD変換部と前記第2の制御部との間に設けられ、前記デジタル電圧に対して低域フィルタ演算を行った後、当該演算結果の電圧を前記第2の制御部に前記検出された直流電圧として出力する演算部とを備えた請求項1乃至10のいずれか一項に記載の整流回路装置の制御装置。 The control device is further provided between the direct current voltage detection unit and the second control unit, and includes an AD conversion unit that AD-converts the detected direct current voltage into a digital voltage, the AD conversion unit, and An arithmetic unit which is provided between the second control unit and the second control unit, and after performing low-pass filter operation on the digital voltage, outputs the voltage of the operation result to the second control unit as the detected DC voltage The control apparatus of the rectifier circuit apparatus as described in any one of the Claims 1 thru | or 10 provided with these.
  12.  前記AD変換部のサンプリング周波数は、前記単相交流電源の周波数よりも十分に高くなるように設定された請求項11記載の整流回路装置の制御装置。 The control device of a rectifier circuit device according to claim 11, wherein a sampling frequency of the AD conversion unit is set to be sufficiently higher than a frequency of the single phase AC power supply.
  13.  前記低域通過フィルタ演算は、直前の演算結果に「(2n-1)/(2n)」なる係数(nは整数である)を乗算した後、入力されたデジタル電圧と加算し、当該加算結果の値を次の演算結果として用いて実行されるよう構成された請求項11又は12記載の整流回路装置の制御装置。 The low-pass filter calculation multiplies the immediately preceding calculation result by a coefficient (“ n ” is an integer) “(2 n −1) / (2 n )”, and then adds the result to the input digital voltage The control device of the rectifier circuit device according to claim 11 or 12, configured to be executed using the value of the addition result as the next calculation result.
  14.  請求項1乃至13のいずれか一項に記載の整流回路装置の制御装置を備えたことを特徴とする整流回路装置。 A rectifier circuit device comprising the control device of the rectifier circuit device according to any one of claims 1 to 13.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016010283A (en) * 2014-06-26 2016-01-18 パナソニックIpマネジメント株式会社 Rectification circuit device and control circuit for the same
JP2016154434A (en) * 2015-02-18 2016-08-25 パナソニックIpマネジメント株式会社 Motor drive unit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6906148B2 (en) * 2019-01-11 2021-07-21 パナソニックIpマネジメント株式会社 Rectifier circuit device
JP6890237B2 (en) * 2019-04-05 2021-06-18 パナソニックIpマネジメント株式会社 Rectifier circuit device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008141901A (en) * 2006-12-05 2008-06-19 Matsushita Electric Ind Co Ltd Dc power supply unit
WO2012004927A1 (en) * 2010-07-08 2012-01-12 パナソニック株式会社 Rectifier circuit device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013021882A (en) * 2011-07-14 2013-01-31 Panasonic Corp Dc power supply

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008141901A (en) * 2006-12-05 2008-06-19 Matsushita Electric Ind Co Ltd Dc power supply unit
WO2012004927A1 (en) * 2010-07-08 2012-01-12 パナソニック株式会社 Rectifier circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016010283A (en) * 2014-06-26 2016-01-18 パナソニックIpマネジメント株式会社 Rectification circuit device and control circuit for the same
JP2016154434A (en) * 2015-02-18 2016-08-25 パナソニックIpマネジメント株式会社 Motor drive unit

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